Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"A few fixes all over the place:
radeon is probably the biggest standout, it's a fix for screen
corruption or hung black outputs so I thought it was worth pulling in.
Otherwise some amdgpu power control fixes, some misc vmwgfx fixes, one
etnaviv fix, one virtio-gpu fix, two DP MST fixes, and a single TTM
fix"
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm/vmwgfx: Fix order of operation
drm/vmwgfx: use vmw_cmd_dx_cid_check for query commands.
drm/vmwgfx: Enable SVGA_3D_CMD_DX_SET_PREDICATION
drm/amdgpu: disable vm interrupts with vm_fault_stop=2
drm/amdgpu: print a message if ATPX dGPU power control is missing
Revert "drm/amdgpu: disable runtime pm on PX laptops without dGPU power control"
drm/radeon: fix vertical bars appear on monitor (v2)
drm/ttm: fix kref count mess in ttm_bo_move_to_lru_tail
drm/virtio: send vblank event after crtc updates
drm/dp/mst: Restore primary hub guid on resume
drm/dp/mst: Get validated port ref in drm_dp_update_payload_part1()
drm/etnaviv: don't move linear memory window on 3D cores without MC2.0
+277
-48
+7
-4
drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
+7
-4
drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
···
63
63
return amdgpu_atpx_priv.atpx_detected;
64
64
}
65
65
66
-
bool amdgpu_has_atpx_dgpu_power_cntl(void) {
67
-
return amdgpu_atpx_priv.atpx.functions.power_cntl;
68
-
}
69
-
70
66
/**
71
67
* amdgpu_atpx_call - call an ATPX method
72
68
*
···
142
146
*/
143
147
static int amdgpu_atpx_validate(struct amdgpu_atpx *atpx)
144
148
{
149
+
/* make sure required functions are enabled */
150
+
/* dGPU power control is required */
151
+
if (atpx->functions.power_cntl == false) {
152
+
printk("ATPX dGPU power cntl not present, forcing\n");
153
+
atpx->functions.power_cntl = true;
154
+
}
155
+
145
156
if (atpx->functions.px_params) {
146
157
union acpi_object *info;
147
158
struct atpx_px_params output;
+1
-7
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+1
-7
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
···
62
62
"LAST",
63
63
};
64
64
65
-
#if defined(CONFIG_VGA_SWITCHEROO)
66
-
bool amdgpu_has_atpx_dgpu_power_cntl(void);
67
-
#else
68
-
static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
69
-
#endif
70
-
71
65
bool amdgpu_device_is_px(struct drm_device *dev)
72
66
{
73
67
struct amdgpu_device *adev = dev->dev_private;
···
1479
1485
1480
1486
if (amdgpu_runtime_pm == 1)
1481
1487
runtime = true;
1482
-
if (amdgpu_device_is_px(ddev) && amdgpu_has_atpx_dgpu_power_cntl())
1488
+
if (amdgpu_device_is_px(ddev))
1483
1489
runtime = true;
1484
1490
vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime);
1485
1491
if (runtime)
+4
-1
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+4
-1
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
···
910
910
{
911
911
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
912
912
913
-
return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
913
+
if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
914
+
return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
915
+
else
916
+
return 0;
914
917
}
915
918
916
919
static int gmc_v7_0_sw_init(void *handle)
+4
-1
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+4
-1
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
···
870
870
{
871
871
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
872
872
873
-
return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
873
+
if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
874
+
return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
875
+
else
876
+
return 0;
874
877
}
875
878
876
879
#define mmMC_SEQ_MISC0_FIJI 0xA71
+20
drivers/gpu/drm/drm_dp_mst_topology.c
+20
drivers/gpu/drm/drm_dp_mst_topology.c
···
1796
1796
req_payload.start_slot = cur_slots;
1797
1797
if (mgr->proposed_vcpis[i]) {
1798
1798
port = container_of(mgr->proposed_vcpis[i], struct drm_dp_mst_port, vcpi);
1799
+
port = drm_dp_get_validated_port_ref(mgr, port);
1800
+
if (!port) {
1801
+
mutex_unlock(&mgr->payload_lock);
1802
+
return -EINVAL;
1803
+
}
1799
1804
req_payload.num_slots = mgr->proposed_vcpis[i]->num_slots;
1800
1805
req_payload.vcpi = mgr->proposed_vcpis[i]->vcpi;
1801
1806
} else {
···
1828
1823
mgr->payloads[i].payload_state = req_payload.payload_state;
1829
1824
}
1830
1825
cur_slots += req_payload.num_slots;
1826
+
1827
+
if (port)
1828
+
drm_dp_put_port(port);
1831
1829
}
1832
1830
1833
1831
for (i = 0; i < mgr->max_payloads; i++) {
···
2136
2128
2137
2129
if (mgr->mst_primary) {
2138
2130
int sret;
2131
+
u8 guid[16];
2132
+
2139
2133
sret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, mgr->dpcd, DP_RECEIVER_CAP_SIZE);
2140
2134
if (sret != DP_RECEIVER_CAP_SIZE) {
2141
2135
DRM_DEBUG_KMS("dpcd read failed - undocked during suspend?\n");
···
2152
2142
ret = -1;
2153
2143
goto out_unlock;
2154
2144
}
2145
+
2146
+
/* Some hubs forget their guids after they resume */
2147
+
sret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16);
2148
+
if (sret != 16) {
2149
+
DRM_DEBUG_KMS("dpcd read failed - undocked during suspend?\n");
2150
+
ret = -1;
2151
+
goto out_unlock;
2152
+
}
2153
+
drm_dp_check_mstb_guid(mgr->mst_primary, guid);
2154
+
2155
2155
ret = 0;
2156
2156
} else
2157
2157
ret = -1;
+153
-1
drivers/gpu/drm/radeon/evergreen.c
+153
-1
drivers/gpu/drm/radeon/evergreen.c
···
2608
2608
WREG32(VM_CONTEXT1_CNTL, 0);
2609
2609
}
2610
2610
2611
+
static const unsigned ni_dig_offsets[] =
2612
+
{
2613
+
NI_DIG0_REGISTER_OFFSET,
2614
+
NI_DIG1_REGISTER_OFFSET,
2615
+
NI_DIG2_REGISTER_OFFSET,
2616
+
NI_DIG3_REGISTER_OFFSET,
2617
+
NI_DIG4_REGISTER_OFFSET,
2618
+
NI_DIG5_REGISTER_OFFSET
2619
+
};
2620
+
2621
+
static const unsigned ni_tx_offsets[] =
2622
+
{
2623
+
NI_DCIO_UNIPHY0_UNIPHY_TX_CONTROL1,
2624
+
NI_DCIO_UNIPHY1_UNIPHY_TX_CONTROL1,
2625
+
NI_DCIO_UNIPHY2_UNIPHY_TX_CONTROL1,
2626
+
NI_DCIO_UNIPHY3_UNIPHY_TX_CONTROL1,
2627
+
NI_DCIO_UNIPHY4_UNIPHY_TX_CONTROL1,
2628
+
NI_DCIO_UNIPHY5_UNIPHY_TX_CONTROL1
2629
+
};
2630
+
2631
+
static const unsigned evergreen_dp_offsets[] =
2632
+
{
2633
+
EVERGREEN_DP0_REGISTER_OFFSET,
2634
+
EVERGREEN_DP1_REGISTER_OFFSET,
2635
+
EVERGREEN_DP2_REGISTER_OFFSET,
2636
+
EVERGREEN_DP3_REGISTER_OFFSET,
2637
+
EVERGREEN_DP4_REGISTER_OFFSET,
2638
+
EVERGREEN_DP5_REGISTER_OFFSET
2639
+
};
2640
+
2641
+
2642
+
/*
2643
+
* Assumption is that EVERGREEN_CRTC_MASTER_EN enable for requested crtc
2644
+
* We go from crtc to connector and it is not relible since it
2645
+
* should be an opposite direction .If crtc is enable then
2646
+
* find the dig_fe which selects this crtc and insure that it enable.
2647
+
* if such dig_fe is found then find dig_be which selects found dig_be and
2648
+
* insure that it enable and in DP_SST mode.
2649
+
* if UNIPHY_PLL_CONTROL1.enable then we should disconnect timing
2650
+
* from dp symbols clocks .
2651
+
*/
2652
+
static bool evergreen_is_dp_sst_stream_enabled(struct radeon_device *rdev,
2653
+
unsigned crtc_id, unsigned *ret_dig_fe)
2654
+
{
2655
+
unsigned i;
2656
+
unsigned dig_fe;
2657
+
unsigned dig_be;
2658
+
unsigned dig_en_be;
2659
+
unsigned uniphy_pll;
2660
+
unsigned digs_fe_selected;
2661
+
unsigned dig_be_mode;
2662
+
unsigned dig_fe_mask;
2663
+
bool is_enabled = false;
2664
+
bool found_crtc = false;
2665
+
2666
+
/* loop through all running dig_fe to find selected crtc */
2667
+
for (i = 0; i < ARRAY_SIZE(ni_dig_offsets); i++) {
2668
+
dig_fe = RREG32(NI_DIG_FE_CNTL + ni_dig_offsets[i]);
2669
+
if (dig_fe & NI_DIG_FE_CNTL_SYMCLK_FE_ON &&
2670
+
crtc_id == NI_DIG_FE_CNTL_SOURCE_SELECT(dig_fe)) {
2671
+
/* found running pipe */
2672
+
found_crtc = true;
2673
+
dig_fe_mask = 1 << i;
2674
+
dig_fe = i;
2675
+
break;
2676
+
}
2677
+
}
2678
+
2679
+
if (found_crtc) {
2680
+
/* loop through all running dig_be to find selected dig_fe */
2681
+
for (i = 0; i < ARRAY_SIZE(ni_dig_offsets); i++) {
2682
+
dig_be = RREG32(NI_DIG_BE_CNTL + ni_dig_offsets[i]);
2683
+
/* if dig_fe_selected by dig_be? */
2684
+
digs_fe_selected = NI_DIG_BE_CNTL_FE_SOURCE_SELECT(dig_be);
2685
+
dig_be_mode = NI_DIG_FE_CNTL_MODE(dig_be);
2686
+
if (dig_fe_mask & digs_fe_selected &&
2687
+
/* if dig_be in sst mode? */
2688
+
dig_be_mode == NI_DIG_BE_DPSST) {
2689
+
dig_en_be = RREG32(NI_DIG_BE_EN_CNTL +
2690
+
ni_dig_offsets[i]);
2691
+
uniphy_pll = RREG32(NI_DCIO_UNIPHY0_PLL_CONTROL1 +
2692
+
ni_tx_offsets[i]);
2693
+
/* dig_be enable and tx is running */
2694
+
if (dig_en_be & NI_DIG_BE_EN_CNTL_ENABLE &&
2695
+
dig_en_be & NI_DIG_BE_EN_CNTL_SYMBCLK_ON &&
2696
+
uniphy_pll & NI_DCIO_UNIPHY0_PLL_CONTROL1_ENABLE) {
2697
+
is_enabled = true;
2698
+
*ret_dig_fe = dig_fe;
2699
+
break;
2700
+
}
2701
+
}
2702
+
}
2703
+
}
2704
+
2705
+
return is_enabled;
2706
+
}
2707
+
2708
+
/*
2709
+
* Blank dig when in dp sst mode
2710
+
* Dig ignores crtc timing
2711
+
*/
2712
+
static void evergreen_blank_dp_output(struct radeon_device *rdev,
2713
+
unsigned dig_fe)
2714
+
{
2715
+
unsigned stream_ctrl;
2716
+
unsigned fifo_ctrl;
2717
+
unsigned counter = 0;
2718
+
2719
+
if (dig_fe >= ARRAY_SIZE(evergreen_dp_offsets)) {
2720
+
DRM_ERROR("invalid dig_fe %d\n", dig_fe);
2721
+
return;
2722
+
}
2723
+
2724
+
stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL +
2725
+
evergreen_dp_offsets[dig_fe]);
2726
+
if (!(stream_ctrl & EVERGREEN_DP_VID_STREAM_CNTL_ENABLE)) {
2727
+
DRM_ERROR("dig %d , should be enable\n", dig_fe);
2728
+
return;
2729
+
}
2730
+
2731
+
stream_ctrl &=~EVERGREEN_DP_VID_STREAM_CNTL_ENABLE;
2732
+
WREG32(EVERGREEN_DP_VID_STREAM_CNTL +
2733
+
evergreen_dp_offsets[dig_fe], stream_ctrl);
2734
+
2735
+
stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL +
2736
+
evergreen_dp_offsets[dig_fe]);
2737
+
while (counter < 32 && stream_ctrl & EVERGREEN_DP_VID_STREAM_STATUS) {
2738
+
msleep(1);
2739
+
counter++;
2740
+
stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL +
2741
+
evergreen_dp_offsets[dig_fe]);
2742
+
}
2743
+
if (counter >= 32 )
2744
+
DRM_ERROR("counter exceeds %d\n", counter);
2745
+
2746
+
fifo_ctrl = RREG32(EVERGREEN_DP_STEER_FIFO + evergreen_dp_offsets[dig_fe]);
2747
+
fifo_ctrl |= EVERGREEN_DP_STEER_FIFO_RESET;
2748
+
WREG32(EVERGREEN_DP_STEER_FIFO + evergreen_dp_offsets[dig_fe], fifo_ctrl);
2749
+
2750
+
}
2751
+
2611
2752
void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
2612
2753
{
2613
2754
u32 crtc_enabled, tmp, frame_count, blackout;
2614
2755
int i, j;
2756
+
unsigned dig_fe;
2615
2757
2616
2758
if (!ASIC_IS_NODCE(rdev)) {
2617
2759
save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
···
2793
2651
break;
2794
2652
udelay(1);
2795
2653
}
2796
-
2654
+
/*we should disable dig if it drives dp sst*/
2655
+
/*but we are in radeon_device_init and the topology is unknown*/
2656
+
/*and it is available after radeon_modeset_init*/
2657
+
/*the following method radeon_atom_encoder_dpms_dig*/
2658
+
/*does the job if we initialize it properly*/
2659
+
/*for now we do it this manually*/
2660
+
/**/
2661
+
if (ASIC_IS_DCE5(rdev) &&
2662
+
evergreen_is_dp_sst_stream_enabled(rdev, i ,&dig_fe))
2663
+
evergreen_blank_dp_output(rdev, dig_fe);
2664
+
/*we could remove 6 lines below*/
2797
2665
/* XXX this is a hack to avoid strange behavior with EFI on certain systems */
2798
2666
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
2799
2667
tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
+46
drivers/gpu/drm/radeon/evergreen_reg.h
+46
drivers/gpu/drm/radeon/evergreen_reg.h
···
250
250
251
251
/* HDMI blocks at 0x7030, 0x7c30, 0x10830, 0x11430, 0x12030, 0x12c30 */
252
252
#define EVERGREEN_HDMI_BASE 0x7030
253
+
/*DIG block*/
254
+
#define NI_DIG0_REGISTER_OFFSET (0x7000 - 0x7000)
255
+
#define NI_DIG1_REGISTER_OFFSET (0x7C00 - 0x7000)
256
+
#define NI_DIG2_REGISTER_OFFSET (0x10800 - 0x7000)
257
+
#define NI_DIG3_REGISTER_OFFSET (0x11400 - 0x7000)
258
+
#define NI_DIG4_REGISTER_OFFSET (0x12000 - 0x7000)
259
+
#define NI_DIG5_REGISTER_OFFSET (0x12C00 - 0x7000)
260
+
261
+
262
+
#define NI_DIG_FE_CNTL 0x7000
263
+
# define NI_DIG_FE_CNTL_SOURCE_SELECT(x) ((x) & 0x3)
264
+
# define NI_DIG_FE_CNTL_SYMCLK_FE_ON (1<<24)
265
+
266
+
267
+
#define NI_DIG_BE_CNTL 0x7140
268
+
# define NI_DIG_BE_CNTL_FE_SOURCE_SELECT(x) (((x) >> 8 ) & 0x3F)
269
+
# define NI_DIG_FE_CNTL_MODE(x) (((x) >> 16) & 0x7 )
270
+
271
+
#define NI_DIG_BE_EN_CNTL 0x7144
272
+
# define NI_DIG_BE_EN_CNTL_ENABLE (1 << 0)
273
+
# define NI_DIG_BE_EN_CNTL_SYMBCLK_ON (1 << 8)
274
+
# define NI_DIG_BE_DPSST 0
253
275
254
276
/* Display Port block */
277
+
#define EVERGREEN_DP0_REGISTER_OFFSET (0x730C - 0x730C)
278
+
#define EVERGREEN_DP1_REGISTER_OFFSET (0x7F0C - 0x730C)
279
+
#define EVERGREEN_DP2_REGISTER_OFFSET (0x10B0C - 0x730C)
280
+
#define EVERGREEN_DP3_REGISTER_OFFSET (0x1170C - 0x730C)
281
+
#define EVERGREEN_DP4_REGISTER_OFFSET (0x1230C - 0x730C)
282
+
#define EVERGREEN_DP5_REGISTER_OFFSET (0x12F0C - 0x730C)
283
+
284
+
285
+
#define EVERGREEN_DP_VID_STREAM_CNTL 0x730C
286
+
# define EVERGREEN_DP_VID_STREAM_CNTL_ENABLE (1 << 0)
287
+
# define EVERGREEN_DP_VID_STREAM_STATUS (1 <<16)
288
+
#define EVERGREEN_DP_STEER_FIFO 0x7310
289
+
# define EVERGREEN_DP_STEER_FIFO_RESET (1 << 0)
255
290
#define EVERGREEN_DP_SEC_CNTL 0x7280
256
291
# define EVERGREEN_DP_SEC_STREAM_ENABLE (1 << 0)
257
292
# define EVERGREEN_DP_SEC_ASP_ENABLE (1 << 4)
···
300
265
#define EVERGREEN_DP_SEC_AUD_N 0x7294
301
266
# define EVERGREEN_DP_SEC_N_BASE_MULTIPLE(x) (((x) & 0xf) << 24)
302
267
# define EVERGREEN_DP_SEC_SS_EN (1 << 28)
268
+
269
+
/*DCIO_UNIPHY block*/
270
+
#define NI_DCIO_UNIPHY0_UNIPHY_TX_CONTROL1 (0x6600 -0x6600)
271
+
#define NI_DCIO_UNIPHY1_UNIPHY_TX_CONTROL1 (0x6640 -0x6600)
272
+
#define NI_DCIO_UNIPHY2_UNIPHY_TX_CONTROL1 (0x6680 - 0x6600)
273
+
#define NI_DCIO_UNIPHY3_UNIPHY_TX_CONTROL1 (0x66C0 - 0x6600)
274
+
#define NI_DCIO_UNIPHY4_UNIPHY_TX_CONTROL1 (0x6700 - 0x6600)
275
+
#define NI_DCIO_UNIPHY5_UNIPHY_TX_CONTROL1 (0x6740 - 0x6600)
276
+
277
+
#define NI_DCIO_UNIPHY0_PLL_CONTROL1 0x6618
278
+
# define NI_DCIO_UNIPHY0_PLL_CONTROL1_ENABLE (1 << 0)
303
279
304
280
#endif
+4
-13
drivers/gpu/drm/ttm/ttm_bo.c
+4
-13
drivers/gpu/drm/ttm/ttm_bo.c
···
230
230
231
231
void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo)
232
232
{
233
-
struct ttm_bo_device *bdev = bo->bdev;
234
-
struct ttm_mem_type_manager *man;
233
+
int put_count = 0;
235
234
236
235
lockdep_assert_held(&bo->resv->lock.base);
237
236
238
-
if (bo->mem.placement & TTM_PL_FLAG_NO_EVICT) {
239
-
list_del_init(&bo->swap);
240
-
list_del_init(&bo->lru);
241
-
242
-
} else {
243
-
if (bo->ttm && !(bo->ttm->page_flags & TTM_PAGE_FLAG_SG))
244
-
list_move_tail(&bo->swap, &bo->glob->swap_lru);
245
-
246
-
man = &bdev->man[bo->mem.mem_type];
247
-
list_move_tail(&bo->lru, &man->lru);
248
-
}
237
+
put_count = ttm_bo_del_from_lru(bo);
238
+
ttm_bo_list_ref_sub(bo, put_count, true);
239
+
ttm_bo_add_to_lru(bo);
249
240
}
250
241
EXPORT_SYMBOL(ttm_bo_move_to_lru_tail);
251
242
+12
drivers/gpu/drm/virtio/virtgpu_display.c
+12
drivers/gpu/drm/virtio/virtgpu_display.c
···
267
267
return 0;
268
268
}
269
269
270
+
static void virtio_gpu_crtc_atomic_flush(struct drm_crtc *crtc,
271
+
struct drm_crtc_state *old_state)
272
+
{
273
+
unsigned long flags;
274
+
275
+
spin_lock_irqsave(&crtc->dev->event_lock, flags);
276
+
if (crtc->state->event)
277
+
drm_crtc_send_vblank_event(crtc, crtc->state->event);
278
+
spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
279
+
}
280
+
270
281
static const struct drm_crtc_helper_funcs virtio_gpu_crtc_helper_funcs = {
271
282
.enable = virtio_gpu_crtc_enable,
272
283
.disable = virtio_gpu_crtc_disable,
273
284
.mode_set_nofb = virtio_gpu_crtc_mode_set_nofb,
274
285
.atomic_check = virtio_gpu_crtc_atomic_check,
286
+
.atomic_flush = virtio_gpu_crtc_atomic_flush,
275
287
};
276
288
277
289
static void virtio_gpu_enc_mode_set(struct drm_encoder *encoder,
+5
-5
drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
+5
-5
drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
···
3293
3293
&vmw_cmd_dx_cid_check, true, false, true),
3294
3294
VMW_CMD_DEF(SVGA_3D_CMD_DX_DEFINE_QUERY, &vmw_cmd_dx_define_query,
3295
3295
true, false, true),
3296
-
VMW_CMD_DEF(SVGA_3D_CMD_DX_DESTROY_QUERY, &vmw_cmd_ok,
3296
+
VMW_CMD_DEF(SVGA_3D_CMD_DX_DESTROY_QUERY, &vmw_cmd_dx_cid_check,
3297
3297
true, false, true),
3298
3298
VMW_CMD_DEF(SVGA_3D_CMD_DX_BIND_QUERY, &vmw_cmd_dx_bind_query,
3299
3299
true, false, true),
3300
3300
VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_QUERY_OFFSET,
3301
-
&vmw_cmd_ok, true, false, true),
3302
-
VMW_CMD_DEF(SVGA_3D_CMD_DX_BEGIN_QUERY, &vmw_cmd_ok,
3301
+
&vmw_cmd_dx_cid_check, true, false, true),
3302
+
VMW_CMD_DEF(SVGA_3D_CMD_DX_BEGIN_QUERY, &vmw_cmd_dx_cid_check,
3303
3303
true, false, true),
3304
-
VMW_CMD_DEF(SVGA_3D_CMD_DX_END_QUERY, &vmw_cmd_ok,
3304
+
VMW_CMD_DEF(SVGA_3D_CMD_DX_END_QUERY, &vmw_cmd_dx_cid_check,
3305
3305
true, false, true),
3306
3306
VMW_CMD_DEF(SVGA_3D_CMD_DX_READBACK_QUERY, &vmw_cmd_invalid,
3307
3307
true, false, true),
3308
-
VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_PREDICATION, &vmw_cmd_invalid,
3308
+
VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_PREDICATION, &vmw_cmd_dx_cid_check,
3309
3309
true, false, true),
3310
3310
VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_VIEWPORTS, &vmw_cmd_dx_cid_check,
3311
3311
true, false, true),
+3
-3
drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
+3
-3
drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
···
573
573
mode = old_mode;
574
574
old_mode = NULL;
575
575
} else if (!vmw_kms_validate_mode_vram(vmw_priv,
576
-
mode->hdisplay *
577
-
(var->bits_per_pixel + 7) / 8,
578
-
mode->vdisplay)) {
576
+
mode->hdisplay *
577
+
DIV_ROUND_UP(var->bits_per_pixel, 8),
578
+
mode->vdisplay)) {
579
579
drm_mode_destroy(vmw_priv->dev, mode);
580
580
return -EINVAL;
581
581
}