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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'parisc-for-6.6-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux
Pull parisc fixes from Helge Deller:
- fix random faults in mmap'd memory on pre PA8800 processors
- fix boot crash with nr_cpus=1 on kernel command line
* tag 'parisc-for-6.6-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux:
parisc: Restore __ldcw_align for PA-RISC 2.0 processors
parisc: Fix crash with nr_cpus=1 option
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-23
+20
-17
arch/parisc/include/asm/ldcw.h
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-17
arch/parisc/include/asm/ldcw.h
···
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#ifndef __PARISC_LDCW_H
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#define __PARISC_LDCW_H
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#ifndef CONFIG_PA20
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/* Because kmalloc only guarantees 8-byte alignment for kmalloc'd data,
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and GCC only guarantees 8-byte alignment for stack locals, we can't
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be assured of 16-byte alignment for atomic lock data even if we
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specify "__attribute ((aligned(16)))" in the type declaration. So,
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we use a struct containing an array of four ints for the atomic lock
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type and dynamically select the 16-byte aligned int from the array
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for the semaphore. */
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for the semaphore. */
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/* From: "Jim Hull" <jim.hull of hp.com>
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I've attached a summary of the change, but basically, for PA 2.0, as
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long as the ",CO" (coherent operation) completer is implemented, then the
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16-byte alignment requirement for ldcw and ldcd is relaxed, and instead
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they only require "natural" alignment (4-byte for ldcw, 8-byte for
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ldcd).
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Although the cache control hint is accepted by all PA 2.0 processors,
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it is only implemented on PA8800/PA8900 CPUs. Prior PA8X00 CPUs still
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require 16-byte alignment. If the address is unaligned, the operation
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of the instruction is undefined. The ldcw instruction does not generate
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unaligned data reference traps so misaligned accesses are not detected.
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This hid the problem for years. So, restore the 16-byte alignment dropped
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by Kyle McMartin in "Remove __ldcw_align for PA-RISC 2.0 processors". */
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#define __PA_LDCW_ALIGNMENT 16
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#define __PA_LDCW_ALIGN_ORDER 4
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#define __ldcw_align(a) ({ \
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unsigned long __ret = (unsigned long) &(a)->lock[0]; \
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__ret = (__ret + __PA_LDCW_ALIGNMENT - 1) \
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& ~(__PA_LDCW_ALIGNMENT - 1); \
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(volatile unsigned int *) __ret; \
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})
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#define __LDCW "ldcw"
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#else /*CONFIG_PA20*/
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/* From: "Jim Hull" <jim.hull of hp.com>
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I've attached a summary of the change, but basically, for PA 2.0, as
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long as the ",CO" (coherent operation) completer is specified, then the
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16-byte alignment requirement for ldcw and ldcd is relaxed, and instead
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they only require "natural" alignment (4-byte for ldcw, 8-byte for
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ldcd). */
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#define __PA_LDCW_ALIGNMENT 4
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#define __PA_LDCW_ALIGN_ORDER 2
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#define __ldcw_align(a) (&(a)->slock)
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#ifdef CONFIG_PA20
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#define __LDCW "ldcw,co"
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#endif /*!CONFIG_PA20*/
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#else
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#define __LDCW "ldcw"
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#endif
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/* LDCW, the only atomic read-write operation PA-RISC has. *sigh*.
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We don't explicitly expose that "*a" may be written as reload
-5
arch/parisc/include/asm/spinlock_types.h
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arch/parisc/include/asm/spinlock_types.h
···
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#ifndef __ASSEMBLY__
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typedef struct {
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#ifdef CONFIG_PA20
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volatile unsigned int slock;
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# define __ARCH_SPIN_LOCK_UNLOCKED { __ARCH_SPIN_LOCK_UNLOCKED_VAL }
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#else
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volatile unsigned int lock[4];
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# define __ARCH_SPIN_LOCK_UNLOCKED \
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{ { __ARCH_SPIN_LOCK_UNLOCKED_VAL, __ARCH_SPIN_LOCK_UNLOCKED_VAL, \
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__ARCH_SPIN_LOCK_UNLOCKED_VAL, __ARCH_SPIN_LOCK_UNLOCKED_VAL } }
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#endif
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} arch_spinlock_t;
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+3
-1
arch/parisc/kernel/smp.c
+3
-1
arch/parisc/kernel/smp.c
···
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if (cpu_online(cpu))
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return 0;
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if (num_online_cpus() < setup_max_cpus && smp_boot_one_cpu(cpu, tidle))
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if (num_online_cpus() < nr_cpu_ids &&
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num_online_cpus() < setup_max_cpus &&
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smp_boot_one_cpu(cpu, tidle))
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return -EIO;
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return cpu_online(cpu) ? 0 : -EIO;