powerpc/e500: Always use 64 bits PTE · tjh.dev/kernel@b9e7e3e

+1 -3

arch/powerpc/include/asm/nohash/32/pgtable.h

··· 120 120 121 121 #if defined(CONFIG_44x) 122 122 #include <asm/nohash/32/pte-44x.h> 123 - #elif defined(CONFIG_PPC_85xx) && defined(CONFIG_PTE_64BIT) 124 - #include <asm/nohash/pte-e500.h> 125 123 #elif defined(CONFIG_PPC_85xx) 126 - #include <asm/nohash/32/pte-85xx.h> 124 + #include <asm/nohash/pte-e500.h> 127 125 #elif defined(CONFIG_PPC_8xx) 128 126 #include <asm/nohash/32/pte-8xx.h> 129 127 #endif

-59

arch/powerpc/include/asm/nohash/32/pte-85xx.h

··· 1 - /* SPDX-License-Identifier: GPL-2.0 */ 2 - #ifndef _ASM_POWERPC_NOHASH_32_PTE_85xx_H 3 - #define _ASM_POWERPC_NOHASH_32_PTE_85xx_H 4 - #ifdef __KERNEL__ 5 - 6 - /* PTE bit definitions for Freescale BookE SW loaded TLB MMU based 7 - * processors 8 - * 9 - MMU Assist Register 3: 10 - 11 - 32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63 12 - RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR 13 - 14 - - PRESENT *must* be in the bottom two bits because swap PTEs use 15 - the top 30 bits. 16 - 17 - */ 18 - 19 - /* Definitions for FSL Book-E Cores */ 20 - #define _PAGE_READ 0x00001 /* H: Read permission (SR) */ 21 - #define _PAGE_PRESENT 0x00002 /* S: PTE contains a translation */ 22 - #define _PAGE_WRITE 0x00004 /* S: Write permission (SW) */ 23 - #define _PAGE_DIRTY 0x00008 /* S: Page dirty */ 24 - #define _PAGE_EXEC 0x00010 /* H: SX permission */ 25 - #define _PAGE_ACCESSED 0x00020 /* S: Page referenced */ 26 - 27 - #define _PAGE_ENDIAN 0x00040 /* H: E bit */ 28 - #define _PAGE_GUARDED 0x00080 /* H: G bit */ 29 - #define _PAGE_COHERENT 0x00100 /* H: M bit */ 30 - #define _PAGE_NO_CACHE 0x00200 /* H: I bit */ 31 - #define _PAGE_WRITETHRU 0x00400 /* H: W bit */ 32 - #define _PAGE_SPECIAL 0x00800 /* S: Special page */ 33 - 34 - #define _PMD_PRESENT 0 35 - #define _PMD_PRESENT_MASK (PAGE_MASK) 36 - #define _PMD_BAD (~PAGE_MASK) 37 - #define _PMD_USER 0 38 - 39 - #define _PTE_NONE_MASK 0 40 - 41 - #define PTE_WIMGE_SHIFT (6) 42 - 43 - /* 44 - * We define 2 sets of base prot bits, one for basic pages (ie, 45 - * cacheable kernel and user pages) and one for non cacheable 46 - * pages. We always set _PAGE_COHERENT when SMP is enabled or 47 - * the processor might need it for DMA coherency. 48 - */ 49 - #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) 50 - #if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC) 51 - #define _PAGE_BASE (_PAGE_BASE_NC | _PAGE_COHERENT) 52 - #else 53 - #define _PAGE_BASE (_PAGE_BASE_NC) 54 - #endif 55 - 56 - #include <asm/pgtable-masks.h> 57 - 58 - #endif /* __KERNEL__ */ 59 - #endif /* _ASM_POWERPC_NOHASH_32_PTE_FSL_85xx_H */

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arch/powerpc/include/asm/pgtable-types.h

··· 49 49 #endif /* CONFIG_PPC64 */ 50 50 51 51 /* PGD level */ 52 - #if defined(CONFIG_PPC_85xx) && defined(CONFIG_PTE_64BIT) 52 + #if defined(CONFIG_PPC_85xx) 53 53 typedef struct { unsigned long long pgd; } pgd_t; 54 54 55 55 static inline unsigned long long pgd_val(pgd_t x)

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arch/powerpc/kernel/head_85xx.S

··· 305 305 * r12 is pointer to the pte 306 306 * r10 is the pshift from the PGD, if we're a hugepage 307 307 */ 308 - #ifdef CONFIG_PTE_64BIT 309 308 #ifdef CONFIG_HUGETLB_PAGE 310 309 #define FIND_PTE \ 311 310 rlwinm r12, r13, 14, 18, 28; /* Compute pgdir/pmd offset */ \ ··· 328 329 rlwimi r12, r13, 23, 20, 28; /* Compute pte address */ \ 329 330 lwz r11, 4(r12); /* Get pte entry */ 330 331 #endif /* HUGEPAGE */ 331 - #else /* !PTE_64BIT */ 332 - #define FIND_PTE \ 333 - rlwimi r11, r13, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \ 334 - lwz r11, 0(r11); /* Get L1 entry */ \ 335 - rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \ 336 - beq 2f; /* Bail if no table */ \ 337 - rlwimi r12, r13, 22, 20, 29; /* Compute PTE address */ \ 338 - lwz r11, 0(r12); /* Get Linux PTE */ 339 - #endif 340 332 341 333 /* 342 334 * Interrupt vector entry code ··· 463 473 4: 464 474 FIND_PTE 465 475 466 - #ifdef CONFIG_PTE_64BIT 467 476 li r13,_PAGE_PRESENT|_PAGE_BAP_SR 468 477 oris r13,r13,_PAGE_ACCESSED@h 469 - #else 470 - li r13,_PAGE_PRESENT|_PAGE_READ|_PAGE_ACCESSED 471 - #endif 472 478 andc. r13,r13,r11 /* Check permission */ 473 479 474 - #ifdef CONFIG_PTE_64BIT 475 480 #ifdef CONFIG_SMP 476 481 subf r13,r11,r12 /* create false data dep */ 477 482 lwzx r13,r11,r13 /* Get upper pte bits */ 478 483 #else 479 484 lwz r13,0(r12) /* Get upper pte bits */ 480 - #endif 481 485 #endif 482 486 483 487 bne 2f /* Bail if permission/valid mismatch */ ··· 536 552 537 553 FIND_PTE 538 554 /* Make up the required permissions for kernel code */ 539 - #ifdef CONFIG_PTE_64BIT 540 555 li r13,_PAGE_PRESENT | _PAGE_BAP_SX 541 556 oris r13,r13,_PAGE_ACCESSED@h 542 - #else 543 - li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC 544 - #endif 545 557 b 4f 546 558 547 559 /* Get the PGD for the current thread */ ··· 553 573 554 574 FIND_PTE 555 575 /* Make up the required permissions for user code */ 556 - #ifdef CONFIG_PTE_64BIT 557 576 li r13,_PAGE_PRESENT | _PAGE_BAP_UX 558 577 oris r13,r13,_PAGE_ACCESSED@h 559 - #else 560 - li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC 561 - #endif 562 578 563 579 4: 564 580 andc. r13,r13,r11 /* Check permission */ 565 581 566 - #ifdef CONFIG_PTE_64BIT 567 582 #ifdef CONFIG_SMP 568 583 subf r13,r11,r12 /* create false data dep */ 569 584 lwzx r13,r11,r13 /* Get upper pte bits */ 570 585 #else 571 586 lwz r13,0(r12) /* Get upper pte bits */ 572 - #endif 573 587 #endif 574 588 575 589 bne 2f /* Bail if permission mismatch */ ··· 657 683 * r10 - tsize encoding (if HUGETLB_PAGE) or available to use 658 684 * r11 - TLB (info from Linux PTE) 659 685 * r12 - available to use 660 - * r13 - upper bits of PTE (if PTE_64BIT) or available to use 686 + * r13 - upper bits of PTE 661 687 * CR5 - results of addr >= PAGE_OFFSET 662 688 * MAS0, MAS1 - loaded with proper value when we get here 663 689 * MAS2, MAS3 - will need additional info from Linux PTE ··· 725 751 * here we (properly should) assume have the appropriate value. 726 752 */ 727 753 finish_tlb_load_cont: 728 - #ifdef CONFIG_PTE_64BIT 729 754 rlwinm r12, r11, 32-2, 26, 31 /* Move in perm bits */ 730 755 andi. r10, r11, _PAGE_DIRTY 731 756 bne 1f ··· 737 764 srwi r10, r13, 12 /* grab RPN[12:31] */ 738 765 mtspr SPRN_MAS7, r10 739 766 END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS) 740 - #else 741 - li r10, (_PAGE_EXEC | _PAGE_READ) 742 - mr r13, r11 743 - rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */ 744 - and r12, r11, r10 745 - mcrf cr0, cr5 /* Test for user page */ 746 - slwi r10, r12, 1 747 - or r10, r10, r12 748 - rlwinm r10, r10, 0, ~_PAGE_EXEC /* Clear SX on user pages */ 749 - isellt r12, r10, r12 750 - rlwimi r13, r12, 0, 20, 31 /* Get RPN from PTE, merge w/ perms */ 751 - mtspr SPRN_MAS3, r13 752 - #endif 753 767 754 768 mfspr r12, SPRN_MAS2 755 - #ifdef CONFIG_PTE_64BIT 756 769 rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */ 757 - #else 758 - rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */ 759 - #endif 760 770 #ifdef CONFIG_HUGETLB_PAGE 761 771 beq 6, 3f /* don't mask if page isn't huge */ 762 772 li r13, 1

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arch/powerpc/platforms/Kconfig.cputype

··· 276 276 config PPC_E500 277 277 select FSL_EMB_PERFMON 278 278 bool 279 - select ARCH_SUPPORTS_HUGETLBFS if PHYS_64BIT || PPC64 279 + select ARCH_SUPPORTS_HUGETLBFS 280 280 select PPC_SMP_MUXED_IPI 281 281 select PPC_DOORBELL 282 282 select PPC_KUEP ··· 337 337 config PTE_64BIT 338 338 bool 339 339 depends on 44x || PPC_E500 || PPC_86xx 340 - default y if PHYS_64BIT 340 + default y if PPC_E500 || PHYS_64BIT 341 341 342 342 config PHYS_64BIT 343 343 bool 'Large physical address support' if PPC_E500 || PPC_86xx

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