Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2020-03-06' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie:
"Weekly fixes round, looks like a few people woke up, got a bunch of
fixes across the drivers. Bit bigger than I'd like but they all seem
fine and hopefully it quiets down now.
sun4i, kirin, mediatek and exynos on the ARM side. virtio-gpu and core
have some mmap fixes, and there is a dma-buf leak. one ttm fence leak
is also fixed.
Otherwise it's mostly amdgpu and i915.
One of the i915 fixes is for a very long latency I was seeing (using
latencytop) running gnome-shell locally when using firefox and eating
nearly all my RAM, it really helps with desktop responsiveness esp
when firefox is chewing a lot.
dma-buf:
- fix memory leak
core:
- shmem object mmap fix.
ttm:
- Fix fence leak in ttm_buffer_object_transfer().
amdgpu:
- Gfx reset fix for gfx9, 10
- Fix for gfx10
- DP MST fix
- DCC fix
- Renoir power fixes
- Navi power fix
i915:
- Break up long lists of object reclaim with cond_resched()
- PSR probe fix
- TGL workarounds
- Selftest return value fix
- Drop timeline mutex while waiting for retirement
- Wait for OA configuration completion before writes to OA buffer
virtio:
- Fix resource id creation race in virtio.
- mmap fixes
sun4i:
- Fixes for sun4i VI layer format support.
kirin:
- kirin: Revert "Fix for hikey620 display offset problem"
exynos:
- fix a kernel oops problem in case that driver is loaded as module.
- fix a regulator warning issue when I2C DDC adapter cannot be gathered.
- print out an error message only in error case excepting -EPROBE_DEFER.
mediatek:
- overlay, cursor and gce fixes"
`
* tag 'drm-fixes-2020-03-06' of git://anongit.freedesktop.org/drm/drm: (38 commits)
drm/amdgpu/display: navi1x copy dcn watermark clock settings to smu resume from s3 (v2)
drm/amd/powerplay: map mclk to fclk for COMBINATIONAL_BYPASS case
drm/amd/powerplay: fix pre-check condition for setting clock range
drm/amd/display: fix dcc swath size calculations on dcn1
drm/amd/display: Clear link settings on MST disable connector
drm/amdgpu: disable 3D pipe 1 on Navi1x
drm/amdgpu: clean wptr on wb when gpu recovery
drm: kirin: Revert "Fix for hikey620 display offset problem"
drm/i915/gt: Drop the timeline->mutex as we wait for retirement
drm/i915/perf: Reintroduce wait on OA configuration completion
drm/sun4i: Fix DE2 VI layer format support
drm/sun4i: Add separate DE3 VI layer formats
drm/sun4i: de2/de3: Remove unsupported VI layer formats
drm/i915/selftests: Fix return in assert_mmap_offset()
drm/i915: Protect i915_request_await_start from early waits
drm/i915/tgl: Add Wa_1608008084
drm/i915/tgl: Add Wa_22010178259:tgl
drm/i915: Program MBUS with rmw during initialization
drm/i915/psr: Force PSR probe only after full initialization
drm/i915/gem: Break up long lists of object reclaim
...
+526
-218
+1
drivers/dma-buf/dma-buf.c
+1
drivers/dma-buf/dma-buf.c
+50
-44
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+50
-44
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
···
52
52
* 1. Primary ring
53
53
* 2. Async ring
54
54
*/
55
-
#define GFX10_NUM_GFX_RINGS 2
55
+
#define GFX10_NUM_GFX_RINGS_NV1X 1
56
56
#define GFX10_MEC_HPD_SIZE 2048
57
57
58
58
#define F32_CE_PROGRAM_RAM_SIZE 65536
···
1304
1304
case CHIP_NAVI14:
1305
1305
case CHIP_NAVI12:
1306
1306
adev->gfx.me.num_me = 1;
1307
-
adev->gfx.me.num_pipe_per_me = 2;
1307
+
adev->gfx.me.num_pipe_per_me = 1;
1308
1308
adev->gfx.me.num_queue_per_pipe = 1;
1309
1309
adev->gfx.mec.num_mec = 2;
1310
1310
adev->gfx.mec.num_pipe_per_mec = 4;
···
2710
2710
amdgpu_ring_commit(ring);
2711
2711
2712
2712
/* submit cs packet to copy state 0 to next available state */
2713
-
ring = &adev->gfx.gfx_ring[1];
2714
-
r = amdgpu_ring_alloc(ring, 2);
2715
-
if (r) {
2716
-
DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2717
-
return r;
2713
+
if (adev->gfx.num_gfx_rings > 1) {
2714
+
/* maximum supported gfx ring is 2 */
2715
+
ring = &adev->gfx.gfx_ring[1];
2716
+
r = amdgpu_ring_alloc(ring, 2);
2717
+
if (r) {
2718
+
DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2719
+
return r;
2720
+
}
2721
+
2722
+
amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2723
+
amdgpu_ring_write(ring, 0);
2724
+
2725
+
amdgpu_ring_commit(ring);
2718
2726
}
2719
-
2720
-
amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2721
-
amdgpu_ring_write(ring, 0);
2722
-
2723
-
amdgpu_ring_commit(ring);
2724
-
2725
2727
return 0;
2726
2728
}
2727
2729
···
2820
2818
mutex_unlock(&adev->srbm_mutex);
2821
2819
2822
2820
/* Init gfx ring 1 for pipe 1 */
2823
-
mutex_lock(&adev->srbm_mutex);
2824
-
gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
2825
-
ring = &adev->gfx.gfx_ring[1];
2826
-
rb_bufsz = order_base_2(ring->ring_size / 8);
2827
-
tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
2828
-
tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
2829
-
WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
2830
-
/* Initialize the ring buffer's write pointers */
2831
-
ring->wptr = 0;
2832
-
WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
2833
-
WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
2834
-
/* Set the wb address wether it's enabled or not */
2835
-
rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2836
-
WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2837
-
WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
2838
-
CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2839
-
wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2840
-
WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
2841
-
lower_32_bits(wptr_gpu_addr));
2842
-
WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
2843
-
upper_32_bits(wptr_gpu_addr));
2821
+
if (adev->gfx.num_gfx_rings > 1) {
2822
+
mutex_lock(&adev->srbm_mutex);
2823
+
gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
2824
+
/* maximum supported gfx ring is 2 */
2825
+
ring = &adev->gfx.gfx_ring[1];
2826
+
rb_bufsz = order_base_2(ring->ring_size / 8);
2827
+
tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
2828
+
tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
2829
+
WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
2830
+
/* Initialize the ring buffer's write pointers */
2831
+
ring->wptr = 0;
2832
+
WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
2833
+
WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
2834
+
/* Set the wb address wether it's enabled or not */
2835
+
rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2836
+
WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2837
+
WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
2838
+
CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2839
+
wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2840
+
WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
2841
+
lower_32_bits(wptr_gpu_addr));
2842
+
WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
2843
+
upper_32_bits(wptr_gpu_addr));
2844
2844
2845
-
mdelay(1);
2846
-
WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
2845
+
mdelay(1);
2846
+
WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
2847
2847
2848
-
rb_addr = ring->gpu_addr >> 8;
2849
-
WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
2850
-
WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
2851
-
WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
2848
+
rb_addr = ring->gpu_addr >> 8;
2849
+
WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
2850
+
WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
2851
+
WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
2852
2852
2853
-
gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
2854
-
mutex_unlock(&adev->srbm_mutex);
2855
-
2853
+
gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
2854
+
mutex_unlock(&adev->srbm_mutex);
2855
+
}
2856
2856
/* Switch to pipe 0 */
2857
2857
mutex_lock(&adev->srbm_mutex);
2858
2858
gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
···
3517
3513
3518
3514
/* reset ring buffer */
3519
3515
ring->wptr = 0;
3516
+
atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
3520
3517
amdgpu_ring_clear_ring(ring);
3521
3518
} else {
3522
3519
amdgpu_ring_clear_ring(ring);
···
3971
3966
{
3972
3967
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3973
3968
3974
-
adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS;
3969
+
adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
3970
+
3975
3971
adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
3976
3972
3977
3973
gfx_v10_0_set_kiq_pm4_funcs(adev);
+1
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+1
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+69
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+69
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
1422
1422
drm_kms_helper_hotplug_event(dev);
1423
1423
}
1424
1424
1425
+
static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
1426
+
{
1427
+
struct smu_context *smu = &adev->smu;
1428
+
int ret = 0;
1429
+
1430
+
if (!is_support_sw_smu(adev))
1431
+
return 0;
1432
+
1433
+
/* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
1434
+
* on window driver dc implementation.
1435
+
* For Navi1x, clock settings of dcn watermarks are fixed. the settings
1436
+
* should be passed to smu during boot up and resume from s3.
1437
+
* boot up: dc calculate dcn watermark clock settings within dc_create,
1438
+
* dcn20_resource_construct
1439
+
* then call pplib functions below to pass the settings to smu:
1440
+
* smu_set_watermarks_for_clock_ranges
1441
+
* smu_set_watermarks_table
1442
+
* navi10_set_watermarks_table
1443
+
* smu_write_watermarks_table
1444
+
*
1445
+
* For Renoir, clock settings of dcn watermark are also fixed values.
1446
+
* dc has implemented different flow for window driver:
1447
+
* dc_hardware_init / dc_set_power_state
1448
+
* dcn10_init_hw
1449
+
* notify_wm_ranges
1450
+
* set_wm_ranges
1451
+
* -- Linux
1452
+
* smu_set_watermarks_for_clock_ranges
1453
+
* renoir_set_watermarks_table
1454
+
* smu_write_watermarks_table
1455
+
*
1456
+
* For Linux,
1457
+
* dc_hardware_init -> amdgpu_dm_init
1458
+
* dc_set_power_state --> dm_resume
1459
+
*
1460
+
* therefore, this function apply to navi10/12/14 but not Renoir
1461
+
* *
1462
+
*/
1463
+
switch(adev->asic_type) {
1464
+
case CHIP_NAVI10:
1465
+
case CHIP_NAVI14:
1466
+
case CHIP_NAVI12:
1467
+
break;
1468
+
default:
1469
+
return 0;
1470
+
}
1471
+
1472
+
mutex_lock(&smu->mutex);
1473
+
1474
+
/* pass data to smu controller */
1475
+
if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1476
+
!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1477
+
ret = smu_write_watermarks_table(smu);
1478
+
1479
+
if (ret) {
1480
+
mutex_unlock(&smu->mutex);
1481
+
DRM_ERROR("Failed to update WMTABLE!\n");
1482
+
return ret;
1483
+
}
1484
+
smu->watermarks_bitmap |= WATERMARKS_LOADED;
1485
+
}
1486
+
1487
+
mutex_unlock(&smu->mutex);
1488
+
1489
+
return 0;
1490
+
}
1491
+
1425
1492
/**
1426
1493
* dm_hw_init() - Initialize DC device
1427
1494
* @handle: The base driver device containing the amdgpu_dm device.
···
1766
1699
dm->cached_state = NULL;
1767
1700
1768
1701
amdgpu_dm_irq_resume_late(adev);
1702
+
1703
+
amdgpu_dm_smu_write_watermarks_table(adev);
1769
1704
1770
1705
return 0;
1771
1706
}
+1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+2
-2
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+2
-2
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
···
840
840
841
841
hubbub1_get_blk256_size(&blk256_width, &blk256_height, bpe);
842
842
843
-
swath_bytes_horz_wc = height * blk256_height * bpe;
844
-
swath_bytes_vert_wc = width * blk256_width * bpe;
843
+
swath_bytes_horz_wc = width * blk256_height * bpe;
844
+
swath_bytes_vert_wc = height * blk256_width * bpe;
845
845
846
846
*req128_horz_wc = (2 * swath_bytes_horz_wc <= detile_buf_size) ?
847
847
false : /* full 256B request */
+1
-1
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+1
-1
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+3
-3
drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+3
-3
drivers/gpu/drm/amd/powerplay/renoir_ppt.c
···
111
111
CLK_MAP(GFXCLK, CLOCK_GFXCLK),
112
112
CLK_MAP(SCLK, CLOCK_GFXCLK),
113
113
CLK_MAP(SOCCLK, CLOCK_SOCCLK),
114
-
CLK_MAP(UCLK, CLOCK_UMCCLK),
115
-
CLK_MAP(MCLK, CLOCK_UMCCLK),
114
+
CLK_MAP(UCLK, CLOCK_FCLK),
115
+
CLK_MAP(MCLK, CLOCK_FCLK),
116
116
};
117
117
118
118
static struct smu_12_0_cmn2aisc_mapping renoir_table_map[SMU_TABLE_COUNT] = {
···
280
280
break;
281
281
case SMU_MCLK:
282
282
count = NUM_MEMCLK_DPM_LEVELS;
283
-
cur_value = metrics.ClockFrequency[CLOCK_UMCCLK];
283
+
cur_value = metrics.ClockFrequency[CLOCK_FCLK];
284
284
break;
285
285
case SMU_DCEFCLK:
286
286
count = NUM_DCFCLK_DPM_LEVELS;
-3
drivers/gpu/drm/amd/powerplay/smu_v12_0.c
-3
drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+1
-2
drivers/gpu/drm/bridge/analogix/analogix-anx6345.c
+1
-2
drivers/gpu/drm/bridge/analogix/analogix-anx6345.c
+11
-5
drivers/gpu/drm/drm_gem_shmem_helper.c
+11
-5
drivers/gpu/drm/drm_gem_shmem_helper.c
···
254
254
if (ret)
255
255
goto err_zero_use;
256
256
257
-
if (obj->import_attach)
257
+
if (obj->import_attach) {
258
258
shmem->vaddr = dma_buf_vmap(obj->import_attach->dmabuf);
259
-
else
259
+
} else {
260
+
pgprot_t prot = PAGE_KERNEL;
261
+
262
+
if (!shmem->map_cached)
263
+
prot = pgprot_writecombine(prot);
260
264
shmem->vaddr = vmap(shmem->pages, obj->size >> PAGE_SHIFT,
261
-
VM_MAP, pgprot_writecombine(PAGE_KERNEL));
265
+
VM_MAP, prot);
266
+
}
262
267
263
268
if (!shmem->vaddr) {
264
269
DRM_DEBUG_KMS("Failed to vmap pages\n");
···
545
540
}
546
541
547
542
vma->vm_flags |= VM_MIXEDMAP | VM_DONTEXPAND;
548
-
vma->vm_page_prot = pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
549
-
vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot);
543
+
vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
544
+
if (!shmem->map_cached)
545
+
vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
550
546
vma->vm_ops = &drm_gem_shmem_vm_ops;
551
547
552
548
return 0;
+7
-5
drivers/gpu/drm/exynos/exynos_drm_dsi.c
+7
-5
drivers/gpu/drm/exynos/exynos_drm_dsi.c
···
1773
1773
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies),
1774
1774
dsi->supplies);
1775
1775
if (ret) {
1776
-
dev_info(dev, "failed to get regulators: %d\n", ret);
1777
-
return -EPROBE_DEFER;
1776
+
if (ret != -EPROBE_DEFER)
1777
+
dev_info(dev, "failed to get regulators: %d\n", ret);
1778
+
return ret;
1778
1779
}
1779
1780
1780
1781
dsi->clks = devm_kcalloc(dev,
···
1788
1787
dsi->clks[i] = devm_clk_get(dev, clk_names[i]);
1789
1788
if (IS_ERR(dsi->clks[i])) {
1790
1789
if (strcmp(clk_names[i], "sclk_mipi") == 0) {
1791
-
strcpy(clk_names[i], OLD_SCLK_MIPI_CLK_NAME);
1792
-
i--;
1793
-
continue;
1790
+
dsi->clks[i] = devm_clk_get(dev,
1791
+
OLD_SCLK_MIPI_CLK_NAME);
1792
+
if (!IS_ERR(dsi->clks[i]))
1793
+
continue;
1794
1794
}
1795
1795
1796
1796
dev_info(dev, "failed to get the clock: %s\n",
+12
-10
drivers/gpu/drm/exynos/exynos_hdmi.c
+12
-10
drivers/gpu/drm/exynos/exynos_hdmi.c
···
1805
1805
1806
1806
hdata->reg_hdmi_en = devm_regulator_get_optional(dev, "hdmi-en");
1807
1807
1808
-
if (PTR_ERR(hdata->reg_hdmi_en) != -ENODEV) {
1808
+
if (PTR_ERR(hdata->reg_hdmi_en) != -ENODEV)
1809
1809
if (IS_ERR(hdata->reg_hdmi_en))
1810
1810
return PTR_ERR(hdata->reg_hdmi_en);
1811
-
1812
-
ret = regulator_enable(hdata->reg_hdmi_en);
1813
-
if (ret) {
1814
-
DRM_DEV_ERROR(dev,
1815
-
"failed to enable hdmi-en regulator\n");
1816
-
return ret;
1817
-
}
1818
-
}
1819
1811
1820
1812
return hdmi_bridge_init(hdata);
1821
1813
}
···
2015
2023
}
2016
2024
}
2017
2025
2026
+
if (!IS_ERR(hdata->reg_hdmi_en)) {
2027
+
ret = regulator_enable(hdata->reg_hdmi_en);
2028
+
if (ret) {
2029
+
DRM_DEV_ERROR(dev,
2030
+
"failed to enable hdmi-en regulator\n");
2031
+
goto err_hdmiphy;
2032
+
}
2033
+
}
2034
+
2018
2035
pm_runtime_enable(dev);
2019
2036
2020
2037
audio_infoframe = &hdata->audio.infoframe;
···
2048
2047
2049
2048
err_rpm_disable:
2050
2049
pm_runtime_disable(dev);
2051
-
2050
+
if (!IS_ERR(hdata->reg_hdmi_en))
2051
+
regulator_disable(hdata->reg_hdmi_en);
2052
2052
err_hdmiphy:
2053
2053
if (hdata->hdmiphy_port)
2054
2054
put_device(&hdata->hdmiphy_port->dev);
-1
drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h
-1
drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h
-20
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
-20
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
···
46
46
struct clk *media_noc_clk;
47
47
struct clk *ade_pix_clk;
48
48
struct reset_control *reset;
49
-
struct work_struct display_reset_wq;
50
49
bool power_on;
51
50
int irq;
52
51
···
135
136
*/
136
137
ade_update_bits(base + ADE_CTRL, FRM_END_START_OFST,
137
138
FRM_END_START_MASK, REG_EFFECTIVE_IN_ADEEN_FRMEND);
138
-
ade_update_bits(base + LDI_INT_EN, UNDERFLOW_INT_EN_OFST, MASK(1), 1);
139
139
}
140
140
141
141
static bool ade_crtc_mode_fixup(struct drm_crtc *crtc,
···
302
304
MASK(1), 0);
303
305
}
304
306
305
-
static void drm_underflow_wq(struct work_struct *work)
306
-
{
307
-
struct ade_hw_ctx *ctx = container_of(work, struct ade_hw_ctx,
308
-
display_reset_wq);
309
-
struct drm_device *drm_dev = ctx->crtc->dev;
310
-
struct drm_atomic_state *state;
311
-
312
-
state = drm_atomic_helper_suspend(drm_dev);
313
-
drm_atomic_helper_resume(drm_dev, state);
314
-
}
315
-
316
307
static irqreturn_t ade_irq_handler(int irq, void *data)
317
308
{
318
309
struct ade_hw_ctx *ctx = data;
···
317
330
ade_update_bits(base + LDI_INT_CLR, FRAME_END_INT_EN_OFST,
318
331
MASK(1), 1);
319
332
drm_crtc_handle_vblank(crtc);
320
-
}
321
-
if (status & BIT(UNDERFLOW_INT_EN_OFST)) {
322
-
ade_update_bits(base + LDI_INT_CLR, UNDERFLOW_INT_EN_OFST,
323
-
MASK(1), 1);
324
-
DRM_ERROR("LDI underflow!");
325
-
schedule_work(&ctx->display_reset_wq);
326
333
}
327
334
328
335
return IRQ_HANDLED;
···
900
919
if (ret)
901
920
return ERR_PTR(-EIO);
902
921
903
-
INIT_WORK(&ctx->display_reset_wq, drm_underflow_wq);
904
922
ctx->crtc = crtc;
905
923
906
924
return ctx;
+24
-5
drivers/gpu/drm/i915/display/intel_display_power.c
+24
-5
drivers/gpu/drm/i915/display/intel_display_power.c
···
4466
4466
4467
4467
static void icl_mbus_init(struct drm_i915_private *dev_priv)
4468
4468
{
4469
-
u32 val;
4469
+
u32 mask, val;
4470
4470
4471
-
val = MBUS_ABOX_BT_CREDIT_POOL1(16) |
4472
-
MBUS_ABOX_BT_CREDIT_POOL2(16) |
4473
-
MBUS_ABOX_B_CREDIT(1) |
4474
-
MBUS_ABOX_BW_CREDIT(1);
4471
+
mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK |
4472
+
MBUS_ABOX_BT_CREDIT_POOL2_MASK |
4473
+
MBUS_ABOX_B_CREDIT_MASK |
4474
+
MBUS_ABOX_BW_CREDIT_MASK;
4475
4475
4476
+
val = I915_READ(MBUS_ABOX_CTL);
4477
+
val &= ~mask;
4478
+
val |= MBUS_ABOX_BT_CREDIT_POOL1(16) |
4479
+
MBUS_ABOX_BT_CREDIT_POOL2(16) |
4480
+
MBUS_ABOX_B_CREDIT(1) |
4481
+
MBUS_ABOX_BW_CREDIT(1);
4476
4482
I915_WRITE(MBUS_ABOX_CTL, val);
4477
4483
}
4478
4484
···
4974
4968
I915_WRITE(BW_BUDDY1_CTL, BW_BUDDY_DISABLE);
4975
4969
I915_WRITE(BW_BUDDY2_CTL, BW_BUDDY_DISABLE);
4976
4970
} else {
4971
+
u32 val;
4972
+
4977
4973
I915_WRITE(BW_BUDDY1_PAGE_MASK, table[i].page_mask);
4978
4974
I915_WRITE(BW_BUDDY2_PAGE_MASK, table[i].page_mask);
4975
+
4976
+
/* Wa_22010178259:tgl */
4977
+
val = I915_READ(BW_BUDDY1_CTL);
4978
+
val &= ~BW_BUDDY_TLB_REQ_TIMER_MASK;
4979
+
val |= REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8);
4980
+
I915_WRITE(BW_BUDDY1_CTL, val);
4981
+
4982
+
val = I915_READ(BW_BUDDY2_CTL);
4983
+
val &= ~BW_BUDDY_TLB_REQ_TIMER_MASK;
4984
+
val |= REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8);
4985
+
I915_WRITE(BW_BUDDY2_CTL, val);
4979
4986
}
4980
4987
}
4981
4988
+21
-4
drivers/gpu/drm/i915/display/intel_psr.c
+21
-4
drivers/gpu/drm/i915/display/intel_psr.c
···
852
852
{
853
853
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
854
854
855
-
if (!crtc_state->has_psr)
855
+
if (!CAN_PSR(dev_priv) || dev_priv->psr.dp != intel_dp)
856
856
return;
857
857
858
-
if (WARN_ON(!CAN_PSR(dev_priv)))
858
+
dev_priv->psr.force_mode_changed = false;
859
+
860
+
if (!crtc_state->has_psr)
859
861
return;
860
862
861
863
WARN_ON(dev_priv->drrs.dp);
···
1010
1008
1011
1009
if (!CAN_PSR(dev_priv) || READ_ONCE(psr->dp) != intel_dp)
1012
1010
return;
1011
+
1012
+
dev_priv->psr.force_mode_changed = false;
1013
1013
1014
1014
mutex_lock(&dev_priv->psr.lock);
1015
1015
···
1538
1534
struct drm_crtc_state *crtc_state;
1539
1535
1540
1536
if (!CAN_PSR(dev_priv) || !new_state->crtc ||
1541
-
dev_priv->psr.initially_probed)
1537
+
!dev_priv->psr.force_mode_changed)
1542
1538
return;
1543
1539
1544
1540
intel_connector = to_intel_connector(connector);
···
1549
1545
crtc_state = drm_atomic_get_new_crtc_state(new_state->state,
1550
1546
new_state->crtc);
1551
1547
crtc_state->mode_changed = true;
1552
-
dev_priv->psr.initially_probed = true;
1548
+
}
1549
+
1550
+
void intel_psr_set_force_mode_changed(struct intel_dp *intel_dp)
1551
+
{
1552
+
struct drm_i915_private *dev_priv;
1553
+
1554
+
if (!intel_dp)
1555
+
return;
1556
+
1557
+
dev_priv = dp_to_i915(intel_dp);
1558
+
if (!CAN_PSR(dev_priv) || intel_dp != dev_priv->psr.dp)
1559
+
return;
1560
+
1561
+
dev_priv->psr.force_mode_changed = true;
1553
1562
}
+1
drivers/gpu/drm/i915/display/intel_psr.h
+1
drivers/gpu/drm/i915/display/intel_psr.h
+1
drivers/gpu/drm/i915/gem/i915_gem_object.c
+1
drivers/gpu/drm/i915/gem/i915_gem_object.c
+1
-1
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+1
-1
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+11
-3
drivers/gpu/drm/i915/gt/intel_gt_requests.c
+11
-3
drivers/gpu/drm/i915/gt/intel_gt_requests.c
···
147
147
148
148
fence = i915_active_fence_get(&tl->last_request);
149
149
if (fence) {
150
+
mutex_unlock(&tl->mutex);
151
+
150
152
timeout = dma_fence_wait_timeout(fence,
151
153
interruptible,
152
154
timeout);
153
155
dma_fence_put(fence);
156
+
157
+
/* Retirement is best effort */
158
+
if (!mutex_trylock(&tl->mutex)) {
159
+
active_count++;
160
+
goto out_active;
161
+
}
154
162
}
155
163
}
156
164
157
165
if (!retire_requests(tl) || flush_submission(gt))
158
166
active_count++;
167
+
mutex_unlock(&tl->mutex);
159
168
160
-
spin_lock(&timelines->lock);
169
+
out_active: spin_lock(&timelines->lock);
161
170
162
-
/* Resume iteration after dropping lock */
171
+
/* Resume list iteration after reacquiring spinlock */
163
172
list_safe_reset_next(tl, tn, link);
164
173
if (atomic_dec_and_test(&tl->active_count))
165
174
list_del(&tl->link);
166
175
167
-
mutex_unlock(&tl->mutex);
168
176
169
177
/* Defer the final release to after the spinlock */
170
178
if (refcount_dec_and_test(&tl->kref.refcount)) {
+7
-12
drivers/gpu/drm/i915/gt/intel_workarounds.c
+7
-12
drivers/gpu/drm/i915/gt/intel_workarounds.c
···
575
575
static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
576
576
struct i915_wa_list *wal)
577
577
{
578
-
u32 val;
579
-
580
578
/* Wa_1409142259:tgl */
581
579
WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
582
580
GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
583
581
584
-
/* Wa_1604555607:tgl */
585
-
val = intel_uncore_read(engine->uncore, FF_MODE2);
586
-
val &= ~FF_MODE2_TDS_TIMER_MASK;
587
-
val |= FF_MODE2_TDS_TIMER_128;
588
582
/*
589
-
* FIXME: FF_MODE2 register is not readable till TGL B0. We can
590
-
* enable verification of WA from the later steppings, which enables
591
-
* the read of FF_MODE2.
583
+
* Wa_1604555607:gen12 and Wa_1608008084:gen12
584
+
* FF_MODE2 register will return the wrong value when read. The default
585
+
* value for this register is zero for all fields and there are no bit
586
+
* masks. So instead of doing a RMW we should just write the TDS timer
587
+
* value for Wa_1604555607.
592
588
*/
593
-
wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
594
-
IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
595
-
FF_MODE2_TDS_TIMER_MASK);
589
+
wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK,
590
+
FF_MODE2_TDS_TIMER_128, 0);
596
591
}
597
592
598
593
static void
+3
drivers/gpu/drm/i915/i915_drv.c
+3
drivers/gpu/drm/i915/i915_drv.c
···
56
56
#include "display/intel_hotplug.h"
57
57
#include "display/intel_overlay.h"
58
58
#include "display/intel_pipe_crc.h"
59
+
#include "display/intel_psr.h"
59
60
#include "display/intel_sprite.h"
60
61
#include "display/intel_vga.h"
61
62
···
330
329
intel_hpd_init(i915);
331
330
332
331
intel_init_ipc(i915);
332
+
333
+
intel_psr_set_force_mode_changed(i915->psr.dp);
333
334
334
335
return 0;
335
336
+1
-1
drivers/gpu/drm/i915/i915_drv.h
+1
-1
drivers/gpu/drm/i915/i915_drv.h
+41
-17
drivers/gpu/drm/i915/i915_perf.c
+41
-17
drivers/gpu/drm/i915/i915_perf.c
···
1954
1954
return i915_vma_get(oa_bo->vma);
1955
1955
}
1956
1956
1957
-
static int emit_oa_config(struct i915_perf_stream *stream,
1958
-
struct i915_oa_config *oa_config,
1959
-
struct intel_context *ce)
1957
+
static struct i915_request *
1958
+
emit_oa_config(struct i915_perf_stream *stream,
1959
+
struct i915_oa_config *oa_config,
1960
+
struct intel_context *ce)
1960
1961
{
1961
1962
struct i915_request *rq;
1962
1963
struct i915_vma *vma;
···
1965
1964
1966
1965
vma = get_oa_vma(stream, oa_config);
1967
1966
if (IS_ERR(vma))
1968
-
return PTR_ERR(vma);
1967
+
return ERR_CAST(vma);
1969
1968
1970
1969
err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
1971
1970
if (err)
···
1990
1989
err = rq->engine->emit_bb_start(rq,
1991
1990
vma->node.start, 0,
1992
1991
I915_DISPATCH_SECURE);
1992
+
if (err)
1993
+
goto err_add_request;
1994
+
1995
+
i915_request_get(rq);
1993
1996
err_add_request:
1994
1997
i915_request_add(rq);
1995
1998
err_vma_unpin:
1996
1999
i915_vma_unpin(vma);
1997
2000
err_vma_put:
1998
2001
i915_vma_put(vma);
1999
-
return err;
2002
+
return err ? ERR_PTR(err) : rq;
2000
2003
}
2001
2004
2002
2005
static struct intel_context *oa_context(struct i915_perf_stream *stream)
···
2008
2003
return stream->pinned_ctx ?: stream->engine->kernel_context;
2009
2004
}
2010
2005
2011
-
static int hsw_enable_metric_set(struct i915_perf_stream *stream)
2006
+
static struct i915_request *
2007
+
hsw_enable_metric_set(struct i915_perf_stream *stream)
2012
2008
{
2013
2009
struct intel_uncore *uncore = stream->uncore;
2014
2010
···
2412
2406
return oa_configure_all_contexts(stream, regs, ARRAY_SIZE(regs));
2413
2407
}
2414
2408
2415
-
static int gen8_enable_metric_set(struct i915_perf_stream *stream)
2409
+
static struct i915_request *
2410
+
gen8_enable_metric_set(struct i915_perf_stream *stream)
2416
2411
{
2417
2412
struct intel_uncore *uncore = stream->uncore;
2418
2413
struct i915_oa_config *oa_config = stream->oa_config;
···
2455
2448
*/
2456
2449
ret = lrc_configure_all_contexts(stream, oa_config);
2457
2450
if (ret)
2458
-
return ret;
2451
+
return ERR_PTR(ret);
2459
2452
2460
2453
return emit_oa_config(stream, oa_config, oa_context(stream));
2461
2454
}
···
2467
2460
0 : GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS);
2468
2461
}
2469
2462
2470
-
static int gen12_enable_metric_set(struct i915_perf_stream *stream)
2463
+
static struct i915_request *
2464
+
gen12_enable_metric_set(struct i915_perf_stream *stream)
2471
2465
{
2472
2466
struct intel_uncore *uncore = stream->uncore;
2473
2467
struct i915_oa_config *oa_config = stream->oa_config;
···
2499
2491
*/
2500
2492
ret = gen12_configure_all_contexts(stream, oa_config);
2501
2493
if (ret)
2502
-
return ret;
2494
+
return ERR_PTR(ret);
2503
2495
2504
2496
/*
2505
2497
* For Gen12, performance counters are context
···
2509
2501
if (stream->ctx) {
2510
2502
ret = gen12_configure_oar_context(stream, true);
2511
2503
if (ret)
2512
-
return ret;
2504
+
return ERR_PTR(ret);
2513
2505
}
2514
2506
2515
2507
return emit_oa_config(stream, oa_config, oa_context(stream));
···
2704
2696
.read = i915_oa_read,
2705
2697
};
2706
2698
2699
+
static int i915_perf_stream_enable_sync(struct i915_perf_stream *stream)
2700
+
{
2701
+
struct i915_request *rq;
2702
+
2703
+
rq = stream->perf->ops.enable_metric_set(stream);
2704
+
if (IS_ERR(rq))
2705
+
return PTR_ERR(rq);
2706
+
2707
+
i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT);
2708
+
i915_request_put(rq);
2709
+
2710
+
return 0;
2711
+
}
2712
+
2707
2713
/**
2708
2714
* i915_oa_stream_init - validate combined props for OA stream and init
2709
2715
* @stream: An i915 perf stream
···
2851
2829
stream->ops = &i915_oa_stream_ops;
2852
2830
perf->exclusive_stream = stream;
2853
2831
2854
-
ret = perf->ops.enable_metric_set(stream);
2832
+
ret = i915_perf_stream_enable_sync(stream);
2855
2833
if (ret) {
2856
2834
DRM_DEBUG("Unable to enable metric set\n");
2857
2835
goto err_enable;
···
3169
3147
return -EINVAL;
3170
3148
3171
3149
if (config != stream->oa_config) {
3172
-
int err;
3150
+
struct i915_request *rq;
3173
3151
3174
3152
/*
3175
3153
* If OA is bound to a specific context, emit the
···
3180
3158
* When set globally, we use a low priority kernel context,
3181
3159
* so it will effectively take effect when idle.
3182
3160
*/
3183
-
err = emit_oa_config(stream, config, oa_context(stream));
3184
-
if (err == 0)
3161
+
rq = emit_oa_config(stream, config, oa_context(stream));
3162
+
if (!IS_ERR(rq)) {
3185
3163
config = xchg(&stream->oa_config, config);
3186
-
else
3187
-
ret = err;
3164
+
i915_request_put(rq);
3165
+
} else {
3166
+
ret = PTR_ERR(rq);
3167
+
}
3188
3168
}
3189
3169
3190
3170
i915_oa_config_put(config);
+2
-1
drivers/gpu/drm/i915/i915_perf_types.h
+2
-1
drivers/gpu/drm/i915/i915_perf_types.h
···
339
339
* counter reports being sampled. May apply system constraints such as
340
340
* disabling EU clock gating as required.
341
341
*/
342
-
int (*enable_metric_set)(struct i915_perf_stream *stream);
342
+
struct i915_request *
343
+
(*enable_metric_set)(struct i915_perf_stream *stream);
343
344
344
345
/**
345
346
* @disable_metric_set: Remove system constraints associated with using
+1
drivers/gpu/drm/i915/i915_reg.h
+1
drivers/gpu/drm/i915/i915_reg.h
···
7757
7757
#define BW_BUDDY1_CTL _MMIO(0x45140)
7758
7758
#define BW_BUDDY2_CTL _MMIO(0x45150)
7759
7759
#define BW_BUDDY_DISABLE REG_BIT(31)
7760
+
#define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16)
7760
7761
7761
7762
#define BW_BUDDY1_PAGE_MASK _MMIO(0x45144)
7762
7763
#define BW_BUDDY2_PAGE_MASK _MMIO(0x45154)
+28
-13
drivers/gpu/drm/i915/i915_request.c
+28
-13
drivers/gpu/drm/i915/i915_request.c
···
275
275
spin_unlock_irq(&rq->lock);
276
276
277
277
remove_from_client(rq);
278
-
list_del(&rq->link);
278
+
list_del_rcu(&rq->link);
279
279
280
280
intel_context_exit(rq->context);
281
281
intel_context_unpin(rq->context);
···
721
721
rq->infix = rq->ring->emit; /* end of header; start of user payload */
722
722
723
723
intel_context_mark_active(ce);
724
+
list_add_tail_rcu(&rq->link, &tl->requests);
725
+
724
726
return rq;
725
727
726
728
err_unwind:
···
779
777
GEM_BUG_ON(i915_request_timeline(rq) ==
780
778
rcu_access_pointer(signal->timeline));
781
779
780
+
if (i915_request_started(signal))
781
+
return 0;
782
+
782
783
fence = NULL;
783
784
rcu_read_lock();
784
785
spin_lock_irq(&signal->lock);
785
-
if (!i915_request_started(signal) &&
786
-
!list_is_first(&signal->link,
787
-
&rcu_dereference(signal->timeline)->requests)) {
788
-
struct i915_request *prev = list_prev_entry(signal, link);
786
+
do {
787
+
struct list_head *pos = READ_ONCE(signal->link.prev);
788
+
struct i915_request *prev;
789
+
790
+
/* Confirm signal has not been retired, the link is valid */
791
+
if (unlikely(i915_request_started(signal)))
792
+
break;
793
+
794
+
/* Is signal the earliest request on its timeline? */
795
+
if (pos == &rcu_dereference(signal->timeline)->requests)
796
+
break;
789
797
790
798
/*
791
799
* Peek at the request before us in the timeline. That
···
803
791
* after acquiring a reference to it, confirm that it is
804
792
* still part of the signaler's timeline.
805
793
*/
806
-
if (i915_request_get_rcu(prev)) {
807
-
if (list_next_entry(prev, link) == signal)
808
-
fence = &prev->fence;
809
-
else
810
-
i915_request_put(prev);
794
+
prev = list_entry(pos, typeof(*prev), link);
795
+
if (!i915_request_get_rcu(prev))
796
+
break;
797
+
798
+
/* After the strong barrier, confirm prev is still attached */
799
+
if (unlikely(READ_ONCE(prev->link.next) != &signal->link)) {
800
+
i915_request_put(prev);
801
+
break;
811
802
}
812
-
}
803
+
804
+
fence = &prev->fence;
805
+
} while (0);
813
806
spin_unlock_irq(&signal->lock);
814
807
rcu_read_unlock();
815
808
if (!fence)
···
1258
1241
&rq->dep,
1259
1242
0);
1260
1243
}
1261
-
1262
-
list_add_tail(&rq->link, &timeline->requests);
1263
1244
1264
1245
/*
1265
1246
* Make sure that no request gazumped us - if it was allocated after
+20
-10
drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+20
-10
drivers/gpu/drm/mediatek/mtk_drm_crtc.c
···
486
486
}
487
487
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
488
488
if (mtk_crtc->cmdq_client) {
489
+
mbox_flush(mtk_crtc->cmdq_client->chan, 2000);
489
490
cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);
490
491
cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
491
492
cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event);
···
637
636
638
637
static int mtk_drm_crtc_init(struct drm_device *drm,
639
638
struct mtk_drm_crtc *mtk_crtc,
640
-
struct drm_plane *primary,
641
-
struct drm_plane *cursor, unsigned int pipe)
639
+
unsigned int pipe)
642
640
{
643
-
int ret;
641
+
struct drm_plane *primary = NULL;
642
+
struct drm_plane *cursor = NULL;
643
+
int i, ret;
644
+
645
+
for (i = 0; i < mtk_crtc->layer_nr; i++) {
646
+
if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY)
647
+
primary = &mtk_crtc->planes[i];
648
+
else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR)
649
+
cursor = &mtk_crtc->planes[i];
650
+
}
644
651
645
652
ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor,
646
653
&mtk_crtc_funcs, NULL);
···
698
689
}
699
690
700
691
static inline
701
-
enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx)
692
+
enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx,
693
+
unsigned int num_planes)
702
694
{
703
695
if (plane_idx == 0)
704
696
return DRM_PLANE_TYPE_PRIMARY;
705
-
else if (plane_idx == 1)
697
+
else if (plane_idx == (num_planes - 1))
706
698
return DRM_PLANE_TYPE_CURSOR;
707
699
else
708
700
return DRM_PLANE_TYPE_OVERLAY;
···
722
712
ret = mtk_plane_init(drm_dev,
723
713
&mtk_crtc->planes[mtk_crtc->layer_nr],
724
714
BIT(pipe),
725
-
mtk_drm_crtc_plane_type(mtk_crtc->layer_nr),
715
+
mtk_drm_crtc_plane_type(mtk_crtc->layer_nr,
716
+
num_planes),
726
717
mtk_ddp_comp_supported_rotations(comp));
727
718
if (ret)
728
719
return ret;
···
818
807
return ret;
819
808
}
820
809
821
-
ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, &mtk_crtc->planes[0],
822
-
mtk_crtc->layer_nr > 1 ? &mtk_crtc->planes[1] :
823
-
NULL, pipe);
810
+
ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe);
824
811
if (ret < 0)
825
812
return ret;
826
813
···
837
828
drm_crtc_index(&mtk_crtc->base));
838
829
mtk_crtc->cmdq_client = NULL;
839
830
}
840
-
ret = of_property_read_u32_index(dev->of_node, "mediatek,gce-events",
831
+
ret = of_property_read_u32_index(priv->mutex_node,
832
+
"mediatek,gce-events",
841
833
drm_crtc_index(&mtk_crtc->base),
842
834
&mtk_crtc->cmdq_event);
843
835
if (ret)
+1
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+1
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+7
drivers/gpu/drm/mediatek/mtk_drm_plane.c
+7
drivers/gpu/drm/mediatek/mtk_drm_plane.c
···
80
80
struct drm_plane_state *state)
81
81
{
82
82
struct drm_crtc_state *crtc_state;
83
+
int ret;
83
84
84
85
if (plane != state->crtc->cursor)
85
86
return -EINVAL;
···
90
89
91
90
if (!plane->state->fb)
92
91
return -EINVAL;
92
+
93
+
ret = mtk_drm_crtc_plane_check(state->crtc, plane,
94
+
to_mtk_plane_state(state));
95
+
if (ret)
96
+
return ret;
93
97
94
98
if (state->state)
95
99
crtc_state = drm_atomic_get_existing_crtc_state(state->state,
···
121
115
plane->state->src_y = new_state->src_y;
122
116
plane->state->src_h = new_state->src_h;
123
117
plane->state->src_w = new_state->src_w;
118
+
swap(plane->state->fb, new_state->fb);
124
119
state->pending.async_dirty = true;
125
120
126
121
mtk_drm_crtc_async_update(new_state->crtc, plane, new_state);
+19
-25
drivers/gpu/drm/panfrost/panfrost_mmu.c
+19
-25
drivers/gpu/drm/panfrost/panfrost_mmu.c
···
601
601
source_id = (fault_status >> 16);
602
602
603
603
/* Page fault only */
604
-
if ((status & mask) == BIT(i)) {
605
-
WARN_ON(exception_type < 0xC1 || exception_type > 0xC4);
606
-
604
+
ret = -1;
605
+
if ((status & mask) == BIT(i) && (exception_type & 0xF8) == 0xC0)
607
606
ret = panfrost_mmu_map_fault_addr(pfdev, i, addr);
608
-
if (!ret) {
609
-
mmu_write(pfdev, MMU_INT_CLEAR, BIT(i));
610
-
status &= ~mask;
611
-
continue;
612
-
}
613
-
}
614
607
615
-
/* terminal fault, print info about the fault */
616
-
dev_err(pfdev->dev,
617
-
"Unhandled Page fault in AS%d at VA 0x%016llX\n"
618
-
"Reason: %s\n"
619
-
"raw fault status: 0x%X\n"
620
-
"decoded fault status: %s\n"
621
-
"exception type 0x%X: %s\n"
622
-
"access type 0x%X: %s\n"
623
-
"source id 0x%X\n",
624
-
i, addr,
625
-
"TODO",
626
-
fault_status,
627
-
(fault_status & (1 << 10) ? "DECODER FAULT" : "SLAVE FAULT"),
628
-
exception_type, panfrost_exception_name(pfdev, exception_type),
629
-
access_type, access_type_name(pfdev, fault_status),
630
-
source_id);
608
+
if (ret)
609
+
/* terminal fault, print info about the fault */
610
+
dev_err(pfdev->dev,
611
+
"Unhandled Page fault in AS%d at VA 0x%016llX\n"
612
+
"Reason: %s\n"
613
+
"raw fault status: 0x%X\n"
614
+
"decoded fault status: %s\n"
615
+
"exception type 0x%X: %s\n"
616
+
"access type 0x%X: %s\n"
617
+
"source id 0x%X\n",
618
+
i, addr,
619
+
"TODO",
620
+
fault_status,
621
+
(fault_status & (1 << 10) ? "DECODER FAULT" : "SLAVE FAULT"),
622
+
exception_type, panfrost_exception_name(pfdev, exception_type),
623
+
access_type, access_type_name(pfdev, fault_status),
624
+
source_id);
631
625
632
626
mmu_write(pfdev, MMU_INT_CLEAR, mask);
633
627
+92
-12
drivers/gpu/drm/sun4i/sun8i_mixer.c
+92
-12
drivers/gpu/drm/sun4i/sun8i_mixer.c
···
107
107
.csc = SUN8I_CSC_MODE_OFF,
108
108
},
109
109
{
110
+
/* for DE2 VI layer which ignores alpha */
111
+
.drm_fmt = DRM_FORMAT_XRGB4444,
112
+
.de2_fmt = SUN8I_MIXER_FBFMT_ARGB4444,
113
+
.rgb = true,
114
+
.csc = SUN8I_CSC_MODE_OFF,
115
+
},
116
+
{
110
117
.drm_fmt = DRM_FORMAT_ABGR4444,
118
+
.de2_fmt = SUN8I_MIXER_FBFMT_ABGR4444,
119
+
.rgb = true,
120
+
.csc = SUN8I_CSC_MODE_OFF,
121
+
},
122
+
{
123
+
/* for DE2 VI layer which ignores alpha */
124
+
.drm_fmt = DRM_FORMAT_XBGR4444,
111
125
.de2_fmt = SUN8I_MIXER_FBFMT_ABGR4444,
112
126
.rgb = true,
113
127
.csc = SUN8I_CSC_MODE_OFF,
···
133
119
.csc = SUN8I_CSC_MODE_OFF,
134
120
},
135
121
{
122
+
/* for DE2 VI layer which ignores alpha */
123
+
.drm_fmt = DRM_FORMAT_RGBX4444,
124
+
.de2_fmt = SUN8I_MIXER_FBFMT_RGBA4444,
125
+
.rgb = true,
126
+
.csc = SUN8I_CSC_MODE_OFF,
127
+
},
128
+
{
136
129
.drm_fmt = DRM_FORMAT_BGRA4444,
130
+
.de2_fmt = SUN8I_MIXER_FBFMT_BGRA4444,
131
+
.rgb = true,
132
+
.csc = SUN8I_CSC_MODE_OFF,
133
+
},
134
+
{
135
+
/* for DE2 VI layer which ignores alpha */
136
+
.drm_fmt = DRM_FORMAT_BGRX4444,
137
137
.de2_fmt = SUN8I_MIXER_FBFMT_BGRA4444,
138
138
.rgb = true,
139
139
.csc = SUN8I_CSC_MODE_OFF,
···
159
131
.csc = SUN8I_CSC_MODE_OFF,
160
132
},
161
133
{
134
+
/* for DE2 VI layer which ignores alpha */
135
+
.drm_fmt = DRM_FORMAT_XRGB1555,
136
+
.de2_fmt = SUN8I_MIXER_FBFMT_ARGB1555,
137
+
.rgb = true,
138
+
.csc = SUN8I_CSC_MODE_OFF,
139
+
},
140
+
{
162
141
.drm_fmt = DRM_FORMAT_ABGR1555,
142
+
.de2_fmt = SUN8I_MIXER_FBFMT_ABGR1555,
143
+
.rgb = true,
144
+
.csc = SUN8I_CSC_MODE_OFF,
145
+
},
146
+
{
147
+
/* for DE2 VI layer which ignores alpha */
148
+
.drm_fmt = DRM_FORMAT_XBGR1555,
163
149
.de2_fmt = SUN8I_MIXER_FBFMT_ABGR1555,
164
150
.rgb = true,
165
151
.csc = SUN8I_CSC_MODE_OFF,
···
185
143
.csc = SUN8I_CSC_MODE_OFF,
186
144
},
187
145
{
146
+
/* for DE2 VI layer which ignores alpha */
147
+
.drm_fmt = DRM_FORMAT_RGBX5551,
148
+
.de2_fmt = SUN8I_MIXER_FBFMT_RGBA5551,
149
+
.rgb = true,
150
+
.csc = SUN8I_CSC_MODE_OFF,
151
+
},
152
+
{
188
153
.drm_fmt = DRM_FORMAT_BGRA5551,
189
154
.de2_fmt = SUN8I_MIXER_FBFMT_BGRA5551,
155
+
.rgb = true,
156
+
.csc = SUN8I_CSC_MODE_OFF,
157
+
},
158
+
{
159
+
/* for DE2 VI layer which ignores alpha */
160
+
.drm_fmt = DRM_FORMAT_BGRX5551,
161
+
.de2_fmt = SUN8I_MIXER_FBFMT_BGRA5551,
162
+
.rgb = true,
163
+
.csc = SUN8I_CSC_MODE_OFF,
164
+
},
165
+
{
166
+
.drm_fmt = DRM_FORMAT_ARGB2101010,
167
+
.de2_fmt = SUN8I_MIXER_FBFMT_ARGB2101010,
168
+
.rgb = true,
169
+
.csc = SUN8I_CSC_MODE_OFF,
170
+
},
171
+
{
172
+
.drm_fmt = DRM_FORMAT_ABGR2101010,
173
+
.de2_fmt = SUN8I_MIXER_FBFMT_ABGR2101010,
174
+
.rgb = true,
175
+
.csc = SUN8I_CSC_MODE_OFF,
176
+
},
177
+
{
178
+
.drm_fmt = DRM_FORMAT_RGBA1010102,
179
+
.de2_fmt = SUN8I_MIXER_FBFMT_RGBA1010102,
180
+
.rgb = true,
181
+
.csc = SUN8I_CSC_MODE_OFF,
182
+
},
183
+
{
184
+
.drm_fmt = DRM_FORMAT_BGRA1010102,
185
+
.de2_fmt = SUN8I_MIXER_FBFMT_BGRA1010102,
190
186
.rgb = true,
191
187
.csc = SUN8I_CSC_MODE_OFF,
192
188
},
···
277
197
.csc = SUN8I_CSC_MODE_YUV2RGB,
278
198
},
279
199
{
280
-
.drm_fmt = DRM_FORMAT_YUV444,
281
-
.de2_fmt = SUN8I_MIXER_FBFMT_RGB888,
282
-
.rgb = true,
283
-
.csc = SUN8I_CSC_MODE_YUV2RGB,
284
-
},
285
-
{
286
200
.drm_fmt = DRM_FORMAT_YUV422,
287
201
.de2_fmt = SUN8I_MIXER_FBFMT_YUV422,
288
202
.rgb = false,
···
295
221
.csc = SUN8I_CSC_MODE_YUV2RGB,
296
222
},
297
223
{
298
-
.drm_fmt = DRM_FORMAT_YVU444,
299
-
.de2_fmt = SUN8I_MIXER_FBFMT_RGB888,
300
-
.rgb = true,
301
-
.csc = SUN8I_CSC_MODE_YVU2RGB,
302
-
},
303
-
{
304
224
.drm_fmt = DRM_FORMAT_YVU422,
305
225
.de2_fmt = SUN8I_MIXER_FBFMT_YUV422,
306
226
.rgb = false,
···
311
243
.de2_fmt = SUN8I_MIXER_FBFMT_YUV411,
312
244
.rgb = false,
313
245
.csc = SUN8I_CSC_MODE_YVU2RGB,
246
+
},
247
+
{
248
+
.drm_fmt = DRM_FORMAT_P010,
249
+
.de2_fmt = SUN8I_MIXER_FBFMT_P010_YUV,
250
+
.rgb = false,
251
+
.csc = SUN8I_CSC_MODE_YUV2RGB,
252
+
},
253
+
{
254
+
.drm_fmt = DRM_FORMAT_P210,
255
+
.de2_fmt = SUN8I_MIXER_FBFMT_P210_YUV,
256
+
.rgb = false,
257
+
.csc = SUN8I_CSC_MODE_YUV2RGB,
314
258
},
315
259
};
316
260
+11
drivers/gpu/drm/sun4i/sun8i_mixer.h
+11
drivers/gpu/drm/sun4i/sun8i_mixer.h
···
93
93
#define SUN8I_MIXER_FBFMT_ABGR1555 17
94
94
#define SUN8I_MIXER_FBFMT_RGBA5551 18
95
95
#define SUN8I_MIXER_FBFMT_BGRA5551 19
96
+
#define SUN8I_MIXER_FBFMT_ARGB2101010 20
97
+
#define SUN8I_MIXER_FBFMT_ABGR2101010 21
98
+
#define SUN8I_MIXER_FBFMT_RGBA1010102 22
99
+
#define SUN8I_MIXER_FBFMT_BGRA1010102 23
96
100
97
101
#define SUN8I_MIXER_FBFMT_YUYV 0
98
102
#define SUN8I_MIXER_FBFMT_UYVY 1
···
113
109
/* format 12 is semi-planar YUV411 UVUV */
114
110
/* format 13 is semi-planar YUV411 VUVU */
115
111
#define SUN8I_MIXER_FBFMT_YUV411 14
112
+
/* format 15 doesn't exist */
113
+
/* format 16 is P010 YVU */
114
+
#define SUN8I_MIXER_FBFMT_P010_YUV 17
115
+
/* format 18 is P210 YVU */
116
+
#define SUN8I_MIXER_FBFMT_P210_YUV 19
117
+
/* format 20 is packed YVU444 10-bit */
118
+
/* format 21 is packed YUV444 10-bit */
116
119
117
120
/*
118
121
* Sub-engines listed bellow are unused for now. The EN registers are here only
+66
-16
drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+66
-16
drivers/gpu/drm/sun4i/sun8i_vi_layer.c
···
398
398
};
399
399
400
400
/*
401
-
* While all RGB formats are supported, VI planes don't support
402
-
* alpha blending, so there is no point having formats with alpha
403
-
* channel if their opaque analog exist.
401
+
* While DE2 VI layer supports same RGB formats as UI layer, alpha
402
+
* channel is ignored. This structure lists all unique variants
403
+
* where alpha channel is replaced with "don't care" (X) channel.
404
404
*/
405
405
static const u32 sun8i_vi_layer_formats[] = {
406
-
DRM_FORMAT_ABGR1555,
407
-
DRM_FORMAT_ABGR4444,
408
-
DRM_FORMAT_ARGB1555,
409
-
DRM_FORMAT_ARGB4444,
410
406
DRM_FORMAT_BGR565,
411
407
DRM_FORMAT_BGR888,
412
-
DRM_FORMAT_BGRA5551,
413
-
DRM_FORMAT_BGRA4444,
408
+
DRM_FORMAT_BGRX4444,
409
+
DRM_FORMAT_BGRX5551,
414
410
DRM_FORMAT_BGRX8888,
415
411
DRM_FORMAT_RGB565,
416
412
DRM_FORMAT_RGB888,
417
-
DRM_FORMAT_RGBA4444,
418
-
DRM_FORMAT_RGBA5551,
413
+
DRM_FORMAT_RGBX4444,
414
+
DRM_FORMAT_RGBX5551,
419
415
DRM_FORMAT_RGBX8888,
416
+
DRM_FORMAT_XBGR1555,
417
+
DRM_FORMAT_XBGR4444,
420
418
DRM_FORMAT_XBGR8888,
419
+
DRM_FORMAT_XRGB1555,
420
+
DRM_FORMAT_XRGB4444,
421
421
DRM_FORMAT_XRGB8888,
422
422
423
423
DRM_FORMAT_NV16,
···
431
431
DRM_FORMAT_YUV411,
432
432
DRM_FORMAT_YUV420,
433
433
DRM_FORMAT_YUV422,
434
-
DRM_FORMAT_YUV444,
435
434
DRM_FORMAT_YVU411,
436
435
DRM_FORMAT_YVU420,
437
436
DRM_FORMAT_YVU422,
438
-
DRM_FORMAT_YVU444,
437
+
};
438
+
439
+
static const u32 sun8i_vi_layer_de3_formats[] = {
440
+
DRM_FORMAT_ABGR1555,
441
+
DRM_FORMAT_ABGR2101010,
442
+
DRM_FORMAT_ABGR4444,
443
+
DRM_FORMAT_ABGR8888,
444
+
DRM_FORMAT_ARGB1555,
445
+
DRM_FORMAT_ARGB2101010,
446
+
DRM_FORMAT_ARGB4444,
447
+
DRM_FORMAT_ARGB8888,
448
+
DRM_FORMAT_BGR565,
449
+
DRM_FORMAT_BGR888,
450
+
DRM_FORMAT_BGRA1010102,
451
+
DRM_FORMAT_BGRA5551,
452
+
DRM_FORMAT_BGRA4444,
453
+
DRM_FORMAT_BGRA8888,
454
+
DRM_FORMAT_BGRX8888,
455
+
DRM_FORMAT_RGB565,
456
+
DRM_FORMAT_RGB888,
457
+
DRM_FORMAT_RGBA1010102,
458
+
DRM_FORMAT_RGBA4444,
459
+
DRM_FORMAT_RGBA5551,
460
+
DRM_FORMAT_RGBA8888,
461
+
DRM_FORMAT_RGBX8888,
462
+
DRM_FORMAT_XBGR8888,
463
+
DRM_FORMAT_XRGB8888,
464
+
465
+
DRM_FORMAT_NV16,
466
+
DRM_FORMAT_NV12,
467
+
DRM_FORMAT_NV21,
468
+
DRM_FORMAT_NV61,
469
+
DRM_FORMAT_P010,
470
+
DRM_FORMAT_P210,
471
+
DRM_FORMAT_UYVY,
472
+
DRM_FORMAT_VYUY,
473
+
DRM_FORMAT_YUYV,
474
+
DRM_FORMAT_YVYU,
475
+
DRM_FORMAT_YUV411,
476
+
DRM_FORMAT_YUV420,
477
+
DRM_FORMAT_YUV422,
478
+
DRM_FORMAT_YVU411,
479
+
DRM_FORMAT_YVU420,
480
+
DRM_FORMAT_YVU422,
439
481
};
440
482
441
483
struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
···
485
443
int index)
486
444
{
487
445
u32 supported_encodings, supported_ranges;
446
+
unsigned int plane_cnt, format_count;
488
447
struct sun8i_vi_layer *layer;
489
-
unsigned int plane_cnt;
448
+
const u32 *formats;
490
449
int ret;
491
450
492
451
layer = devm_kzalloc(drm->dev, sizeof(*layer), GFP_KERNEL);
493
452
if (!layer)
494
453
return ERR_PTR(-ENOMEM);
495
454
455
+
if (mixer->cfg->is_de3) {
456
+
formats = sun8i_vi_layer_de3_formats;
457
+
format_count = ARRAY_SIZE(sun8i_vi_layer_de3_formats);
458
+
} else {
459
+
formats = sun8i_vi_layer_formats;
460
+
format_count = ARRAY_SIZE(sun8i_vi_layer_formats);
461
+
}
462
+
496
463
/* possible crtcs are set later */
497
464
ret = drm_universal_plane_init(drm, &layer->plane, 0,
498
465
&sun8i_vi_layer_funcs,
499
-
sun8i_vi_layer_formats,
500
-
ARRAY_SIZE(sun8i_vi_layer_formats),
466
+
formats, format_count,
501
467
NULL, DRM_PLANE_TYPE_OVERLAY, NULL);
502
468
if (ret) {
503
469
dev_err(drm->dev, "Couldn't initialize layer\n");
+1
drivers/gpu/drm/ttm/ttm_bo_util.c
+1
drivers/gpu/drm/ttm/ttm_bo_util.c
+3
-2
drivers/gpu/drm/virtio/virtgpu_object.c
+3
-2
drivers/gpu/drm/virtio/virtgpu_object.c
···
42
42
* "f91a9dd35715 Fix unlinking resources from hash
43
43
* table." (Feb 2019) fixes the bug.
44
44
*/
45
-
static int handle;
46
-
handle++;
45
+
static atomic_t seqno = ATOMIC_INIT(0);
46
+
int handle = atomic_inc_return(&seqno);
47
47
*resid = handle + 1;
48
48
} else {
49
49
int handle = ida_alloc(&vgdev->resource_ida, GFP_KERNEL);
···
99
99
return NULL;
100
100
101
101
bo->base.base.funcs = &virtio_gpu_gem_funcs;
102
+
bo->base.map_cached = true;
102
103
return &bo->base.base;
103
104
}
104
105
+5
include/drm/drm_gem_shmem_helper.h
+5
include/drm/drm_gem_shmem_helper.h