tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'pinctrl-v3.15-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij:
"Here is a small set of pin control fixes for the v3.15 series. All
are individual driver fixes and quite self-contained. One of them
tagged for stable.

- Signedness bug in the TB10x

- GPIO inversion fix for the AS3722

- Clear pending pin interrups enabled in the bootloader in the
pinctrl-single driver

- Minor pin definition fixes for the PFC/Renesas driver"

* tag 'pinctrl-v3.15-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
sh-pfc: r8a7791: Fix definition of MOD_SEL3
sh-pfc: r8a7790: Fix definition of IPSR5
pinctrl: single: Clear pin interrupts enabled by bootloader
pinctrl: as3722: fix handling of GPIO invert bit
pinctrl/TB10x: Fix signedness bug

Linus Torvalds ba6728f5 60b88f39

+27 -11
+11 -6
drivers/pinctrl/pinctrl-as3722.c
··· 64 64 }; 65 65 66 66 struct as3722_gpio_pin_control { 67 - bool enable_gpio_invert; 68 67 unsigned mode_prop; 69 68 int io_function; 70 69 }; ··· 319 320 return mode; 320 321 } 321 322 322 - if (as_pci->gpio_control[offset].enable_gpio_invert) 323 - mode |= AS3722_GPIO_INV; 324 - 325 - return as3722_write(as3722, AS3722_GPIOn_CONTROL_REG(offset), mode); 323 + return as3722_update_bits(as3722, AS3722_GPIOn_CONTROL_REG(offset), 324 + AS3722_GPIO_MODE_MASK, mode); 326 325 } 327 326 328 327 static const struct pinmux_ops as3722_pinmux_ops = { ··· 493 496 { 494 497 struct as3722_pctrl_info *as_pci = to_as_pci(chip); 495 498 struct as3722 *as3722 = as_pci->as3722; 496 - int en_invert = as_pci->gpio_control[offset].enable_gpio_invert; 499 + int en_invert; 497 500 u32 val; 498 501 int ret; 502 + 503 + ret = as3722_read(as3722, AS3722_GPIOn_CONTROL_REG(offset), &val); 504 + if (ret < 0) { 505 + dev_err(as_pci->dev, 506 + "GPIO_CONTROL%d_REG read failed: %d\n", offset, ret); 507 + return; 508 + } 509 + en_invert = !!(val & AS3722_GPIO_INV); 499 510 500 511 if (value) 501 512 val = (en_invert) ? 0 : AS3722_GPIOn_SIGNAL(offset);
+13
drivers/pinctrl/pinctrl-single.c
··· 810 810 static int pcs_add_pin(struct pcs_device *pcs, unsigned offset, 811 811 unsigned pin_pos) 812 812 { 813 + struct pcs_soc_data *pcs_soc = &pcs->socdata; 813 814 struct pinctrl_pin_desc *pin; 814 815 struct pcs_name *pn; 815 816 int i; ··· 820 819 dev_err(pcs->dev, "too many pins, max %i\n", 821 820 pcs->desc.npins); 822 821 return -ENOMEM; 822 + } 823 + 824 + if (pcs_soc->irq_enable_mask) { 825 + unsigned val; 826 + 827 + val = pcs->read(pcs->base + offset); 828 + if (val & pcs_soc->irq_enable_mask) { 829 + dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n", 830 + (unsigned long)pcs->res->start + offset, val); 831 + val &= ~pcs_soc->irq_enable_mask; 832 + pcs->write(val, pcs->base + offset); 833 + } 823 834 } 824 835 825 836 pin = &pcs->pins.pa[i];
+1 -2
drivers/pinctrl/pinctrl-tb10x.c
··· 629 629 */ 630 630 for (i = 0; i < state->pinfuncgrpcnt; i++) { 631 631 const struct tb10x_pinfuncgrp *pfg = &state->pingroups[i]; 632 - unsigned int port = pfg->port; 633 632 unsigned int mode = pfg->mode; 634 - int j; 633 + int j, port = pfg->port; 635 634 636 635 /* 637 636 * Skip pin groups which are always mapped and don't need
+1 -2
drivers/pinctrl/sh-pfc/pfc-r8a7790.c
··· 4794 4794 FN_MSIOF0_SCK_B, 0, 4795 4795 /* IP5_23_21 [3] */ 4796 4796 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, 4797 - FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, 4798 - FN_IERX_C, 0, 4797 + FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C, 4799 4798 /* IP5_20_18 [3] */ 4800 4799 FN_WE0_N, FN_IECLK, FN_CAN_CLK, 4801 4800 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
+1 -1
drivers/pinctrl/sh-pfc/pfc-r8a7791.c
··· 5288 5288 /* SEL_SCIF3 [2] */ 5289 5289 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, 5290 5290 /* SEL_IEB [2] */ 5291 - FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 5291 + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, 5292 5292 /* SEL_MMC [1] */ 5293 5293 FN_SEL_MMC_0, FN_SEL_MMC_1, 5294 5294 /* SEL_SCIF5 [1] */