drm/amd/pp: Add hwmgr_sw_init/fini functioins

+83 -285

drivers/gpu/drm/amd/powerplay/amd_powerplay.c

··· 31 31 #include "amdgpu.h" 32 32 #include "hwmgr.h" 33 33 34 - #define PP_DPM_DISABLED 0xCCCC 35 - 36 34 static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id, 37 35 enum amd_pm_state_type *user_state); 38 36 39 37 static const struct amd_pm_funcs pp_dpm_funcs; 40 - 41 - static inline int pp_check(struct pp_hwmgr *hwmgr) 42 - { 43 - if (hwmgr == NULL || hwmgr->smumgr_funcs == NULL) 44 - return -EINVAL; 45 - 46 - if (hwmgr->pm_en == 0 || hwmgr->hwmgr_func == NULL) 47 - return PP_DPM_DISABLED; 48 - 49 - return 0; 50 - } 51 38 52 39 static int amd_powerplay_create(struct amdgpu_device *adev) 53 40 { ··· 60 73 } 61 74 62 75 63 - static int amd_powerplay_destroy(struct amdgpu_device *adev) 76 + static void amd_powerplay_destroy(struct amdgpu_device *adev) 64 77 { 65 78 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 66 79 ··· 69 82 70 83 kfree(hwmgr); 71 84 hwmgr = NULL; 72 - 73 - return 0; 74 85 } 75 86 76 87 static int pp_early_init(void *handle) ··· 94 109 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 95 110 int ret = 0; 96 111 97 - ret = pp_check(hwmgr); 112 + ret = hwmgr_sw_init(hwmgr); 98 113 99 - if (ret >= 0) { 100 - if (hwmgr->smumgr_funcs->smu_init == NULL) 101 - return -EINVAL; 102 - 103 - ret = hwmgr->smumgr_funcs->smu_init(hwmgr); 104 - 105 - phm_register_irq_handlers(hwmgr); 106 - 107 - pr_debug("amdgpu: powerplay sw initialized\n"); 108 - } 114 + pr_debug("powerplay sw init %s\n", ret ? "failed" : "successfully"); 109 115 110 116 return ret; 111 117 } ··· 105 129 { 106 130 struct amdgpu_device *adev = handle; 107 131 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 108 - int ret = 0; 109 132 110 - ret = pp_check(hwmgr); 111 - if (ret >= 0) { 112 - if (hwmgr->smumgr_funcs->smu_fini != NULL) 113 - hwmgr->smumgr_funcs->smu_fini(hwmgr); 114 - } 133 + hwmgr_sw_fini(hwmgr); 115 134 116 135 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) 117 136 amdgpu_ucode_fini_bo(adev); ··· 123 152 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) 124 153 amdgpu_ucode_init_bo(adev); 125 154 126 - ret = pp_check(hwmgr); 155 + ret = hwmgr_hw_init(hwmgr); 127 156 128 - if (ret >= 0) { 129 - if (hwmgr->smumgr_funcs->start_smu == NULL) 130 - return -EINVAL; 157 + if (ret) 158 + pr_err("powerplay hw init failed\n"); 131 159 132 - if (hwmgr->smumgr_funcs->start_smu(hwmgr)) { 133 - pr_err("smc start failed\n"); 134 - hwmgr->smumgr_funcs->smu_fini(hwmgr); 135 - return -EINVAL; 136 - } 137 - if (ret == PP_DPM_DISABLED) 138 - goto exit; 139 - ret = hwmgr_hw_init(hwmgr); 140 - if (ret) 141 - goto exit; 142 - } 143 160 return ret; 144 - exit: 145 - hwmgr->pm_en = 0; 146 - cgs_notify_dpm_enabled(hwmgr->device, false); 147 - return 0; 148 - 149 161 } 150 162 151 163 static int pp_hw_fini(void *handle) 152 164 { 153 165 struct amdgpu_device *adev = handle; 154 166 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 155 - int ret = 0; 156 167 157 - ret = pp_check(hwmgr); 158 - if (ret == 0) 159 - hwmgr_hw_fini(hwmgr); 168 + hwmgr_hw_fini(hwmgr); 160 169 161 170 return 0; 162 171 } ··· 145 194 { 146 195 struct amdgpu_device *adev = handle; 147 196 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 148 - int ret = 0; 149 197 150 - ret = pp_check(hwmgr); 151 - 152 - if (ret == 0) 198 + if (hwmgr && hwmgr->pm_en) 153 199 pp_dpm_dispatch_tasks(hwmgr, 154 200 AMD_PP_TASK_COMPLETE_INIT, NULL); 155 201 ··· 181 233 { 182 234 struct amdgpu_device *adev = handle; 183 235 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 184 - int ret = 0; 185 236 186 - ret = pp_check(hwmgr); 187 - 188 - if (ret) 189 - return ret; 237 + if (!hwmgr || !hwmgr->pm_en) 238 + return 0; 190 239 191 240 if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) { 192 241 pr_info("%s was not implemented.\n", __func__); ··· 199 254 { 200 255 struct amdgpu_device *adev = handle; 201 256 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 202 - int ret = 0; 203 257 204 - ret = pp_check(hwmgr); 205 - if (ret == 0) 206 - hwmgr_hw_suspend(hwmgr); 207 - return 0; 258 + return hwmgr_suspend(hwmgr); 208 259 } 209 260 210 261 static int pp_resume(void *handle) 211 262 { 212 263 struct amdgpu_device *adev = handle; 213 264 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 214 - int ret; 215 265 216 - ret = pp_check(hwmgr); 217 - 218 - if (ret < 0) 219 - return ret; 220 - 221 - if (hwmgr->smumgr_funcs->start_smu == NULL) 222 - return -EINVAL; 223 - 224 - if (hwmgr->smumgr_funcs->start_smu(hwmgr)) { 225 - pr_err("smc start failed\n"); 226 - hwmgr->smumgr_funcs->smu_fini(hwmgr); 227 - return -EINVAL; 228 - } 229 - 230 - if (ret == PP_DPM_DISABLED) 231 - return 0; 232 - 233 - return hwmgr_hw_resume(hwmgr); 266 + return hwmgr_resume(hwmgr); 234 267 } 235 268 236 269 static int pp_set_clockgating_state(void *handle, ··· 257 334 static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id) 258 335 { 259 336 struct pp_hwmgr *hwmgr = handle; 260 - int ret = 0; 261 337 262 - ret = pp_check(hwmgr); 263 - 264 - if (ret) 265 - return ret; 338 + if (!hwmgr || !hwmgr->pm_en) 339 + return -EINVAL; 266 340 267 341 if (hwmgr->hwmgr_func->update_clock_gatings == NULL) { 268 342 pr_info("%s was not implemented.\n", __func__); ··· 309 389 enum amd_dpm_forced_level level) 310 390 { 311 391 struct pp_hwmgr *hwmgr = handle; 312 - int ret = 0; 313 392 314 - ret = pp_check(hwmgr); 315 - 316 - if (ret) 317 - return ret; 393 + if (!hwmgr || !hwmgr->pm_en) 394 + return -EINVAL; 318 395 319 396 if (level == hwmgr->dpm_level) 320 397 return 0; ··· 329 412 void *handle) 330 413 { 331 414 struct pp_hwmgr *hwmgr = handle; 332 - int ret = 0; 333 415 enum amd_dpm_forced_level level; 334 416 335 - ret = pp_check(hwmgr); 336 - 337 - if (ret) 338 - return ret; 417 + if (!hwmgr || !hwmgr->pm_en) 418 + return -EINVAL; 339 419 340 420 mutex_lock(&hwmgr->smu_lock); 341 421 level = hwmgr->dpm_level; ··· 343 429 static uint32_t pp_dpm_get_sclk(void *handle, bool low) 344 430 { 345 431 struct pp_hwmgr *hwmgr = handle; 346 - int ret = 0; 347 432 uint32_t clk = 0; 348 433 349 - ret = pp_check(hwmgr); 350 - 351 - if (ret) 352 - return ret; 434 + if (!hwmgr || !hwmgr->pm_en) 435 + return 0; 353 436 354 437 if (hwmgr->hwmgr_func->get_sclk == NULL) { 355 438 pr_info("%s was not implemented.\n", __func__); ··· 361 450 static uint32_t pp_dpm_get_mclk(void *handle, bool low) 362 451 { 363 452 struct pp_hwmgr *hwmgr = handle; 364 - int ret = 0; 365 453 uint32_t clk = 0; 366 454 367 - ret = pp_check(hwmgr); 368 - 369 - if (ret) 370 - return ret; 455 + if (!hwmgr || !hwmgr->pm_en) 456 + return 0; 371 457 372 458 if (hwmgr->hwmgr_func->get_mclk == NULL) { 373 459 pr_info("%s was not implemented.\n", __func__); ··· 379 471 static void pp_dpm_powergate_vce(void *handle, bool gate) 380 472 { 381 473 struct pp_hwmgr *hwmgr = handle; 382 - int ret = 0; 383 474 384 - ret = pp_check(hwmgr); 385 - 386 - if (ret) 475 + if (!hwmgr || !hwmgr->pm_en) 387 476 return; 388 477 389 478 if (hwmgr->hwmgr_func->powergate_vce == NULL) { ··· 395 490 static void pp_dpm_powergate_uvd(void *handle, bool gate) 396 491 { 397 492 struct pp_hwmgr *hwmgr = handle; 398 - int ret = 0; 399 493 400 - ret = pp_check(hwmgr); 401 - 402 - if (ret) 494 + if (!hwmgr || !hwmgr->pm_en) 403 495 return; 404 496 405 497 if (hwmgr->hwmgr_func->powergate_uvd == NULL) { ··· 414 512 int ret = 0; 415 513 struct pp_hwmgr *hwmgr = handle; 416 514 417 - ret = pp_check(hwmgr); 418 - 419 - if (ret) 420 - return ret; 515 + if (!hwmgr || !hwmgr->pm_en) 516 + return -EINVAL; 421 517 422 518 mutex_lock(&hwmgr->smu_lock); 423 519 ret = hwmgr_handle_task(hwmgr, task_id, user_state); ··· 428 528 { 429 529 struct pp_hwmgr *hwmgr = handle; 430 530 struct pp_power_state *state; 431 - int ret = 0; 432 531 enum amd_pm_state_type pm_type; 433 532 434 - ret = pp_check(hwmgr); 435 - 436 - if (ret) 437 - return ret; 438 - 439 - if (hwmgr->current_ps == NULL) 533 + if (!hwmgr || !hwmgr->pm_en || !hwmgr->current_ps) 440 534 return -EINVAL; 441 535 442 536 mutex_lock(&hwmgr->smu_lock); ··· 462 568 static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode) 463 569 { 464 570 struct pp_hwmgr *hwmgr = handle; 465 - int ret = 0; 466 571 467 - ret = pp_check(hwmgr); 468 - 469 - if (ret) 572 + if (!hwmgr || !hwmgr->pm_en) 470 573 return; 471 574 472 575 if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) { ··· 478 587 static uint32_t pp_dpm_get_fan_control_mode(void *handle) 479 588 { 480 589 struct pp_hwmgr *hwmgr = handle; 481 - int ret = 0; 482 590 uint32_t mode = 0; 483 591 484 - ret = pp_check(hwmgr); 485 - 486 - if (ret) 487 - return ret; 592 + if (!hwmgr || !hwmgr->pm_en) 593 + return 0; 488 594 489 595 if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) { 490 596 pr_info("%s was not implemented.\n", __func__); ··· 498 610 struct pp_hwmgr *hwmgr = handle; 499 611 int ret = 0; 500 612 501 - ret = pp_check(hwmgr); 502 - 503 - if (ret) 504 - return ret; 613 + if (!hwmgr || !hwmgr->pm_en) 614 + return -EINVAL; 505 615 506 616 if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) { 507 617 pr_info("%s was not implemented.\n", __func__); ··· 516 630 struct pp_hwmgr *hwmgr = handle; 517 631 int ret = 0; 518 632 519 - ret = pp_check(hwmgr); 520 - 521 - if (ret) 522 - return ret; 633 + if (!hwmgr || !hwmgr->pm_en) 634 + return -EINVAL; 523 635 524 636 if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) { 525 637 pr_info("%s was not implemented.\n", __func__); ··· 535 651 struct pp_hwmgr *hwmgr = handle; 536 652 int ret = 0; 537 653 538 - ret = pp_check(hwmgr); 539 - 540 - if (ret) 541 - return ret; 654 + if (!hwmgr || !hwmgr->pm_en) 655 + return -EINVAL; 542 656 543 657 if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL) 544 658 return -EINVAL; ··· 552 670 { 553 671 struct pp_hwmgr *hwmgr = handle; 554 672 int i; 555 - int ret = 0; 556 673 557 674 memset(data, 0, sizeof(*data)); 558 675 559 - ret = pp_check(hwmgr); 560 - 561 - if (ret) 562 - return ret; 563 - 564 - if (hwmgr->ps == NULL) 676 + if (!hwmgr || !hwmgr->pm_en ||!hwmgr->ps) 565 677 return -EINVAL; 566 678 567 679 mutex_lock(&hwmgr->smu_lock); ··· 589 713 static int pp_dpm_get_pp_table(void *handle, char **table) 590 714 { 591 715 struct pp_hwmgr *hwmgr = handle; 592 - int ret = 0; 593 716 int size = 0; 594 717 595 - ret = pp_check(hwmgr); 596 - 597 - if (ret) 598 - return ret; 599 - 600 - if (!hwmgr->soft_pp_table) 718 + if (!hwmgr || !hwmgr->pm_en ||!hwmgr->soft_pp_table) 601 719 return -EINVAL; 602 720 603 721 mutex_lock(&hwmgr->smu_lock); ··· 605 735 { 606 736 struct pp_hwmgr *hwmgr = handle; 607 737 int ret; 608 - 609 - ret = pp_check(hwmgr); 610 - if (ret) 611 - return ret; 612 738 613 739 ret = hwmgr_hw_fini(hwmgr); 614 740 if (ret) ··· 622 756 struct pp_hwmgr *hwmgr = handle; 623 757 int ret = 0; 624 758 625 - ret = pp_check(hwmgr); 626 - 627 - if (ret) 628 - return ret; 759 + if (!hwmgr || !hwmgr->pm_en) 760 + return -EINVAL; 629 761 630 762 mutex_lock(&hwmgr->smu_lock); 631 763 if (!hwmgr->hardcode_pp_table) { ··· 660 796 struct pp_hwmgr *hwmgr = handle; 661 797 int ret = 0; 662 798 663 - ret = pp_check(hwmgr); 664 - 665 - if (ret) 666 - return ret; 799 + if (!hwmgr || !hwmgr->pm_en) 800 + return -EINVAL; 667 801 668 802 if (hwmgr->hwmgr_func->force_clock_level == NULL) { 669 803 pr_info("%s was not implemented.\n", __func__); ··· 682 820 struct pp_hwmgr *hwmgr = handle; 683 821 int ret = 0; 684 822 685 - ret = pp_check(hwmgr); 686 - 687 - if (ret) 688 - return ret; 823 + if (!hwmgr || !hwmgr->pm_en) 824 + return -EINVAL; 689 825 690 826 if (hwmgr->hwmgr_func->print_clock_levels == NULL) { 691 827 pr_info("%s was not implemented.\n", __func__); ··· 700 840 struct pp_hwmgr *hwmgr = handle; 701 841 int ret = 0; 702 842 703 - ret = pp_check(hwmgr); 704 - 705 - if (ret) 706 - return ret; 843 + if (!hwmgr || !hwmgr->pm_en) 844 + return -EINVAL; 707 845 708 846 if (hwmgr->hwmgr_func->get_sclk_od == NULL) { 709 847 pr_info("%s was not implemented.\n", __func__); ··· 718 860 struct pp_hwmgr *hwmgr = handle; 719 861 int ret = 0; 720 862 721 - ret = pp_check(hwmgr); 722 - 723 - if (ret) 724 - return ret; 863 + if (!hwmgr || !hwmgr->pm_en) 864 + return -EINVAL; 725 865 726 866 if (hwmgr->hwmgr_func->set_sclk_od == NULL) { 727 867 pr_info("%s was not implemented.\n", __func__); ··· 737 881 struct pp_hwmgr *hwmgr = handle; 738 882 int ret = 0; 739 883 740 - ret = pp_check(hwmgr); 741 - 742 - if (ret) 743 - return ret; 884 + if (!hwmgr || !hwmgr->pm_en) 885 + return -EINVAL; 744 886 745 887 if (hwmgr->hwmgr_func->get_mclk_od == NULL) { 746 888 pr_info("%s was not implemented.\n", __func__); ··· 755 901 struct pp_hwmgr *hwmgr = handle; 756 902 int ret = 0; 757 903 758 - ret = pp_check(hwmgr); 759 - 760 - if (ret) 761 - return ret; 904 + if (!hwmgr || !hwmgr->pm_en) 905 + return -EINVAL; 762 906 763 907 if (hwmgr->hwmgr_func->set_mclk_od == NULL) { 764 908 pr_info("%s was not implemented.\n", __func__); ··· 774 922 struct pp_hwmgr *hwmgr = handle; 775 923 int ret = 0; 776 924 777 - ret = pp_check(hwmgr); 778 - if (ret) 779 - return ret; 780 - 781 - if (value == NULL) 925 + if (!hwmgr || !hwmgr->pm_en || !value) 782 926 return -EINVAL; 783 927 784 928 switch (idx) { ··· 796 948 pp_dpm_get_vce_clock_state(void *handle, unsigned idx) 797 949 { 798 950 struct pp_hwmgr *hwmgr = handle; 799 - int ret = 0; 800 951 801 - ret = pp_check(hwmgr); 802 - 803 - if (ret) 952 + if (!hwmgr || !hwmgr->pm_en) 804 953 return NULL; 805 954 806 - if (hwmgr && idx < hwmgr->num_vce_state_tables) 955 + if (idx < hwmgr->num_vce_state_tables) 807 956 return &hwmgr->vce_states[idx]; 808 957 return NULL; 809 958 } ··· 809 964 { 810 965 struct pp_hwmgr *hwmgr = handle; 811 966 812 - if (!buf || pp_check(hwmgr)) 967 + if (!hwmgr || !hwmgr->pm_en || !buf) 813 968 return -EINVAL; 814 969 815 970 if (hwmgr->hwmgr_func->get_power_profile_mode == NULL) { ··· 825 980 struct pp_hwmgr *hwmgr = handle; 826 981 int ret = -EINVAL; 827 982 828 - if (pp_check(hwmgr)) 829 - return -EINVAL; 983 + if (!hwmgr || !hwmgr->pm_en) 984 + return ret; 830 985 831 986 if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) { 832 987 pr_info("%s was not implemented.\n", __func__); 833 - return -EINVAL; 988 + return ret; 834 989 } 835 990 mutex_lock(&hwmgr->smu_lock); 836 991 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) ··· 843 998 { 844 999 struct pp_hwmgr *hwmgr = handle; 845 1000 846 - if (pp_check(hwmgr)) 1001 + if (!hwmgr || !hwmgr->pm_en) 847 1002 return -EINVAL; 848 1003 849 1004 if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) { ··· 861 1016 long workload; 862 1017 uint32_t index; 863 1018 864 - if (pp_check(hwmgr)) 1019 + if (!hwmgr || !hwmgr->pm_en) 865 1020 return -EINVAL; 866 1021 867 1022 if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) { ··· 903 1058 struct pp_hwmgr *hwmgr = handle; 904 1059 int ret = 0; 905 1060 906 - ret = pp_check(hwmgr); 907 - 908 - if (ret) 909 - return ret; 1061 + if (!hwmgr || !hwmgr->pm_en) 1062 + return -EINVAL; 910 1063 911 1064 if (hwmgr->hwmgr_func->notify_cac_buffer_info == NULL) { 912 1065 pr_info("%s was not implemented.\n", __func__); ··· 925 1082 static int pp_set_power_limit(void *handle, uint32_t limit) 926 1083 { 927 1084 struct pp_hwmgr *hwmgr = handle; 928 - int ret = 0; 929 1085 930 - ret = pp_check(hwmgr); 931 - 932 - if (ret) 933 - return ret; 1086 + if (!hwmgr || !hwmgr->pm_en) 1087 + return -EINVAL; 934 1088 935 1089 if (hwmgr->hwmgr_func->set_power_limit == NULL) { 936 1090 pr_info("%s was not implemented.\n", __func__); ··· 944 1104 hwmgr->hwmgr_func->set_power_limit(hwmgr, limit); 945 1105 hwmgr->power_limit = limit; 946 1106 mutex_unlock(&hwmgr->smu_lock); 947 - return ret; 1107 + return 0; 948 1108 } 949 1109 950 1110 static int pp_get_power_limit(void *handle, uint32_t *limit, bool default_limit) 951 1111 { 952 1112 struct pp_hwmgr *hwmgr = handle; 953 - int ret = 0; 954 1113 955 - ret = pp_check(hwmgr); 956 - 957 - if (ret) 958 - return ret; 959 - 960 - if (limit == NULL) 1114 + if (!hwmgr || !hwmgr->pm_en ||!limit) 961 1115 return -EINVAL; 962 1116 963 1117 mutex_lock(&hwmgr->smu_lock); ··· 963 1129 964 1130 mutex_unlock(&hwmgr->smu_lock); 965 1131 966 - return ret; 1132 + return 0; 967 1133 } 968 1134 969 1135 static int pp_display_configuration_change(void *handle, 970 1136 const struct amd_pp_display_configuration *display_config) 971 1137 { 972 1138 struct pp_hwmgr *hwmgr = handle; 973 - int ret = 0; 974 1139 975 - ret = pp_check(hwmgr); 976 - 977 - if (ret) 978 - return ret; 1140 + if (!hwmgr || !hwmgr->pm_en) 1141 + return -EINVAL; 979 1142 980 1143 mutex_lock(&hwmgr->smu_lock); 981 1144 phm_store_dal_configuration_data(hwmgr, display_config); ··· 986 1155 struct pp_hwmgr *hwmgr = handle; 987 1156 int ret = 0; 988 1157 989 - ret = pp_check(hwmgr); 990 - 991 - if (ret) 992 - return ret; 993 - 994 - if (output == NULL) 1158 + if (!hwmgr || !hwmgr->pm_en ||!output) 995 1159 return -EINVAL; 996 1160 997 1161 mutex_lock(&hwmgr->smu_lock); ··· 1003 1177 struct pp_hwmgr *hwmgr = handle; 1004 1178 int ret = 0; 1005 1179 1006 - ret = pp_check(hwmgr); 1007 - 1008 - if (ret) 1009 - return ret; 1180 + if (!hwmgr || !hwmgr->pm_en) 1181 + return -EINVAL; 1010 1182 1011 1183 mutex_lock(&hwmgr->smu_lock); 1012 1184 ··· 1049 1225 struct pp_hwmgr *hwmgr = handle; 1050 1226 int ret = 0; 1051 1227 1052 - ret = pp_check(hwmgr); 1053 - 1054 - if (ret) 1055 - return ret; 1228 + if (!hwmgr || !hwmgr->pm_en) 1229 + return -EINVAL; 1056 1230 1057 1231 if (clocks == NULL) 1058 1232 return -EINVAL; ··· 1068 1246 struct pp_hwmgr *hwmgr = handle; 1069 1247 int ret = 0; 1070 1248 1071 - ret = pp_check(hwmgr); 1072 - if (ret) 1073 - return ret; 1074 - 1075 - if (!clocks) 1249 + if (!hwmgr || !hwmgr->pm_en ||!clocks) 1076 1250 return -EINVAL; 1077 1251 1078 1252 mutex_lock(&hwmgr->smu_lock); ··· 1084 1266 struct pp_hwmgr *hwmgr = handle; 1085 1267 int ret = 0; 1086 1268 1087 - ret = pp_check(hwmgr); 1088 - if (ret) 1089 - return ret; 1090 - 1091 - if (!clocks) 1269 + if (!hwmgr || !hwmgr->pm_en ||!clocks) 1092 1270 return -EINVAL; 1093 1271 1094 1272 mutex_lock(&hwmgr->smu_lock); ··· 1101 1287 struct pp_hwmgr *hwmgr = handle; 1102 1288 int ret = 0; 1103 1289 1104 - ret = pp_check(hwmgr); 1105 - if (ret) 1106 - return ret; 1107 - 1108 - if (!wm_with_clock_ranges) 1290 + if (!hwmgr || !hwmgr->pm_en ||!wm_with_clock_ranges) 1109 1291 return -EINVAL; 1110 1292 1111 1293 mutex_lock(&hwmgr->smu_lock); ··· 1118 1308 struct pp_hwmgr *hwmgr = handle; 1119 1309 int ret = 0; 1120 1310 1121 - ret = pp_check(hwmgr); 1122 - if (ret) 1123 - return ret; 1124 - 1125 - if (!clock) 1311 + if (!hwmgr || !hwmgr->pm_en ||!clock) 1126 1312 return -EINVAL; 1127 1313 1128 1314 mutex_lock(&hwmgr->smu_lock); ··· 1134 1328 struct pp_hwmgr *hwmgr = handle; 1135 1329 int ret = 0; 1136 1330 1137 - ret = pp_check(hwmgr); 1138 - 1139 - if (ret) 1140 - return ret; 1141 - 1142 - if (clocks == NULL) 1331 + if (!hwmgr || !hwmgr->pm_en ||!clocks) 1143 1332 return -EINVAL; 1144 1333 1145 1334 mutex_lock(&hwmgr->smu_lock); ··· 1149 1348 static int pp_set_mmhub_powergating_by_smu(void *handle) 1150 1349 { 1151 1350 struct pp_hwmgr *hwmgr = handle; 1152 - int ret = 0; 1153 1351 1154 - ret = pp_check(hwmgr); 1155 - 1156 - if (ret) 1157 - return ret; 1352 + if (!hwmgr || !hwmgr->pm_en) 1353 + return -EINVAL; 1158 1354 1159 1355 if (hwmgr->hwmgr_func->set_mmhub_powergating_by_smu == NULL) { 1160 1356 pr_info("%s was not implemented.\n", __func__);

+2 -12

drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c

··· 75 75 76 76 int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr) 77 77 { 78 - int ret = 1; 79 - bool enabled; 78 + int ret = -EINVAL;; 80 79 PHM_FUNC_CHECK(hwmgr); 81 80 82 81 if (smum_is_dpm_running(hwmgr)) { ··· 86 87 if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable) 87 88 ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr); 88 89 89 - enabled = ret == 0; 90 - 91 - cgs_notify_dpm_enabled(hwmgr->device, enabled); 92 - 93 90 return ret; 94 91 } 95 92 96 93 int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr) 97 94 { 98 - int ret = -1; 99 - bool enabled; 95 + int ret = -EINVAL; 100 96 101 97 PHM_FUNC_CHECK(hwmgr); 102 98 ··· 102 108 103 109 if (hwmgr->hwmgr_func->dynamic_state_management_disable) 104 110 ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr); 105 - 106 - enabled = ret == 0 ? false : true; 107 - 108 - cgs_notify_dpm_enabled(hwmgr->device, enabled); 109 111 110 112 return ret; 111 113 }

+57 -17

drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c

··· 76 76 77 77 int hwmgr_early_init(struct pp_hwmgr *hwmgr) 78 78 { 79 - if (hwmgr == NULL) 79 + if (!hwmgr) 80 80 return -EINVAL; 81 81 82 82 hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT; ··· 170 170 return 0; 171 171 } 172 172 173 + int hwmgr_sw_init(struct pp_hwmgr *hwmgr) 174 + { 175 + if (!hwmgr|| !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->smu_init) 176 + return -EINVAL; 177 + 178 + phm_register_irq_handlers(hwmgr); 179 + 180 + return hwmgr->smumgr_funcs->smu_init(hwmgr); 181 + } 182 + 183 + 184 + int hwmgr_sw_fini(struct pp_hwmgr *hwmgr) 185 + { 186 + if (hwmgr && hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->smu_fini) 187 + hwmgr->smumgr_funcs->smu_fini(hwmgr); 188 + 189 + return 0; 190 + } 191 + 173 192 int hwmgr_hw_init(struct pp_hwmgr *hwmgr) 174 193 { 175 194 int ret = 0; 176 195 177 - if (hwmgr == NULL) 196 + if (!hwmgr || !hwmgr->smumgr_funcs) 178 197 return -EINVAL; 179 198 180 - if (hwmgr->pptable_func == NULL || 181 - hwmgr->pptable_func->pptable_init == NULL || 182 - hwmgr->hwmgr_func->backend_init == NULL) 183 - return -EINVAL; 199 + if (hwmgr->smumgr_funcs->start_smu) { 200 + ret = hwmgr->smumgr_funcs->start_smu(hwmgr); 201 + if (ret) { 202 + pr_err("smc start failed\n"); 203 + return -EINVAL; 204 + } 205 + } 206 + 207 + if (!hwmgr->pm_en) 208 + return 0; 209 + 210 + if (!hwmgr->pptable_func || 211 + !hwmgr->pptable_func->pptable_init || 212 + !hwmgr->hwmgr_func->backend_init) { 213 + hwmgr->pm_en = false; 214 + ((struct amdgpu_device *)hwmgr->adev)->pm.dpm_enabled = false; 215 + pr_info("dpm not supported \n"); 216 + return 0; 217 + } 184 218 185 219 ret = hwmgr->pptable_func->pptable_init(hwmgr); 186 220 if (ret) ··· 248 214 if (hwmgr->pptable_func->pptable_fini) 249 215 hwmgr->pptable_func->pptable_fini(hwmgr); 250 216 err: 251 - pr_err("amdgpu: powerplay initialization failed\n"); 252 217 return ret; 253 218 } 254 219 255 220 int hwmgr_hw_fini(struct pp_hwmgr *hwmgr) 256 221 { 257 - if (hwmgr == NULL) 258 - return -EINVAL; 222 + if (!hwmgr || !hwmgr->pm_en) 223 + return 0; 259 224 260 225 phm_stop_thermal_controller(hwmgr); 261 226 psm_set_boot_states(hwmgr); ··· 269 236 return psm_fini_power_state_table(hwmgr); 270 237 } 271 238 272 - int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr) 239 + int hwmgr_suspend(struct pp_hwmgr *hwmgr) 273 240 { 274 241 int ret = 0; 275 242 276 - if (hwmgr == NULL) 277 - return -EINVAL; 243 + if (!hwmgr || !hwmgr->pm_en) 244 + return 0; 278 245 279 246 phm_disable_smc_firmware_ctf(hwmgr); 280 247 ret = psm_set_boot_states(hwmgr); ··· 288 255 return ret; 289 256 } 290 257 291 - int hwmgr_hw_resume(struct pp_hwmgr *hwmgr) 258 + int hwmgr_resume(struct pp_hwmgr *hwmgr) 292 259 { 293 260 int ret = 0; 294 261 295 - if (hwmgr == NULL) 262 + if (!hwmgr) 296 263 return -EINVAL; 264 + 265 + if (hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->start_smu) { 266 + if (hwmgr->smumgr_funcs->start_smu(hwmgr)) { 267 + pr_err("smc start failed\n"); 268 + return -EINVAL; 269 + } 270 + } 271 + 272 + if (!hwmgr->pm_en) 273 + return 0; 297 274 298 275 ret = phm_setup_asic(hwmgr); 299 276 if (ret) ··· 313 270 if (ret) 314 271 return ret; 315 272 ret = phm_start_thermal_controller(hwmgr); 316 - if (ret) 317 - return ret; 318 - 319 273 ret |= psm_set_performance_states(hwmgr); 320 274 if (ret) 321 275 return ret;

+5 -2

drivers/gpu/drm/amd/powerplay/inc/hwmgr.h

··· 782 782 }; 783 783 784 784 int hwmgr_early_init(struct pp_hwmgr *hwmgr); 785 + int hwmgr_sw_init(struct pp_hwmgr *hwmgr); 786 + int hwmgr_sw_fini(struct pp_hwmgr *hwmgr); 785 787 int hwmgr_hw_init(struct pp_hwmgr *hwmgr); 786 788 int hwmgr_hw_fini(struct pp_hwmgr *hwmgr); 787 - int hwmgr_hw_suspend(struct pp_hwmgr *hwmgr); 788 - int hwmgr_hw_resume(struct pp_hwmgr *hwmgr); 789 + int hwmgr_suspend(struct pp_hwmgr *hwmgr); 790 + int hwmgr_resume(struct pp_hwmgr *hwmgr); 791 + 789 792 int hwmgr_handle_task(struct pp_hwmgr *hwmgr, 790 793 enum amd_pp_task task_id, 791 794 enum amd_pm_state_type *user_state);

Configure Feed

Configure Feed