clk: qcom: gcc-sm8150: De-register gcc_cpuss_ahb_clk_src

The branch clocks of gcc_cpuss_ahb_clk_src are marked critical
and hence these clocks vote on XO blocking the suspend.
De-register these clocks and its source as there is no rate
setting happening on them.

Fixes: 4433594bbe5d ("clk: qcom: gcc: Add global clock controller driver for SC8180x")
Cc: stable@vger.kernel.org
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20240812-gcc-sc8180x-fixes-v2-5-8b3eaa5fb856@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Satya Priya Kakitapalli and committed by

Bjorn Andersson 2 years ago bab0c7a0 b8acaf2d

-63

1 changed file

expand all

drivers

clk

qcom

gcc-sc8180x.c

-63

drivers/clk/qcom/gcc-sc8180x.c

··· 277 277 { .hw = &gpll0_out_even.clkr.hw }, 278 278 }; 279 279 280 - static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { 281 - F(19200000, P_BI_TCXO, 1, 0, 0), 282 - F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), 283 - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), 284 - { } 285 - }; 286 - 287 - static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { 288 - .cmd_rcgr = 0x48014, 289 - .mnd_width = 0, 290 - .hid_width = 5, 291 - .parent_map = gcc_parent_map_0, 292 - .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, 293 - .clkr.hw.init = &(struct clk_init_data){ 294 - .name = "gcc_cpuss_ahb_clk_src", 295 - .parent_data = gcc_parents_0, 296 - .num_parents = ARRAY_SIZE(gcc_parents_0), 297 - .flags = CLK_SET_RATE_PARENT, 298 - .ops = &clk_rcg2_ops, 299 - }, 300 - }; 301 - 302 280 static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = { 303 281 F(19200000, P_BI_TCXO, 1, 0, 0), 304 282 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), ··· 1629 1651 }, 1630 1652 .num_parents = 1, 1631 1653 .flags = CLK_SET_RATE_PARENT, 1632 - .ops = &clk_branch2_ops, 1633 - }, 1634 - }, 1635 - }; 1636 - 1637 - /* For CPUSS functionality the AHB clock needs to be left enabled */ 1638 - static struct clk_branch gcc_cpuss_ahb_clk = { 1639 - .halt_reg = 0x48000, 1640 - .halt_check = BRANCH_HALT_VOTED, 1641 - .clkr = { 1642 - .enable_reg = 0x52004, 1643 - .enable_mask = BIT(21), 1644 - .hw.init = &(struct clk_init_data){ 1645 - .name = "gcc_cpuss_ahb_clk", 1646 - .parent_hws = (const struct clk_hw *[]){ 1647 - &gcc_cpuss_ahb_clk_src.clkr.hw 1648 - }, 1649 - .num_parents = 1, 1650 - .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 1651 1654 .ops = &clk_branch2_ops, 1652 1655 }, 1653 1656 }, ··· 3166 3207 }, 3167 3208 }; 3168 3209 3169 - /* For CPUSS functionality the SYS NOC clock needs to be left enabled */ 3170 - static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { 3171 - .halt_reg = 0x4819c, 3172 - .halt_check = BRANCH_HALT_VOTED, 3173 - .clkr = { 3174 - .enable_reg = 0x52004, 3175 - .enable_mask = BIT(0), 3176 - .hw.init = &(struct clk_init_data){ 3177 - .name = "gcc_sys_noc_cpuss_ahb_clk", 3178 - .parent_hws = (const struct clk_hw *[]){ 3179 - &gcc_cpuss_ahb_clk_src.clkr.hw 3180 - }, 3181 - .num_parents = 1, 3182 - .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 3183 - .ops = &clk_branch2_ops, 3184 - }, 3185 - }, 3186 - }; 3187 - 3188 3210 static struct clk_branch gcc_tsif_ahb_clk = { 3189 3211 .halt_reg = 0x36004, 3190 3212 .halt_check = BRANCH_HALT, ··· 4281 4341 [GCC_CFG_NOC_USB3_MP_AXI_CLK] = &gcc_cfg_noc_usb3_mp_axi_clk.clkr, 4282 4342 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 4283 4343 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, 4284 - [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, 4285 - [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, 4286 4344 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr, 4287 4345 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, 4288 4346 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, ··· 4417 4479 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 4418 4480 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 4419 4481 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, 4420 - [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, 4421 4482 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, 4422 4483 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr, 4423 4484 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,

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