Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ASoC: rt1320: Add RT1320 SDCA vendor-specific driver
This is the initial amplifier driver for rt1320.
--
add class id 1
Signed-off-by: Shuming Fan <shumingf@realtek.com>
v2: add Capture DAI for AEC feedback
v3: add some comments for blind writes/patch_code/calling sdw_slave_read_prop
v4: add comments for different class id
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://msgid.link/r/20240521084625.453554-1-shumingf@realtek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
authored by
Shuming Fan
and committed by
Mark Brown
bad0a07a
1613e604
+2363
+7
sound/soc/codecs/Kconfig
+7
sound/soc/codecs/Kconfig
···
222
222
imply SND_SOC_RT1308_SDW
223
223
imply SND_SOC_RT1316_SDW
224
224
imply SND_SOC_RT1318_SDW
225
+
imply SND_SOC_RT1320_SDW
225
226
imply SND_SOC_RT9120
226
227
imply SND_SOC_RTQ9128
227
228
imply SND_SOC_SDW_MOCKUP
···
1575
1574
tristate "Realtek RT1318 Codec - SDW"
1576
1575
depends on SOUNDWIRE
1577
1576
select REGMAP_SOUNDWIRE
1577
+
1578
+
config SND_SOC_RT1320_SDW
1579
+
tristate "Realtek RT1320 Codec - SDW"
1580
+
depends on SOUNDWIRE
1581
+
select REGMAP_SOUNDWIRE
1582
+
select REGMAP_SOUNDWIRE_MBQ
1578
1583
1579
1584
config SND_SOC_RT5514
1580
1585
tristate
+2
sound/soc/codecs/Makefile
+2
sound/soc/codecs/Makefile
···
222
222
snd-soc-rt1308-sdw-y := rt1308-sdw.o
223
223
snd-soc-rt1316-sdw-y := rt1316-sdw.o
224
224
snd-soc-rt1318-sdw-y := rt1318-sdw.o
225
+
snd-soc-rt1320-sdw-y := rt1320-sdw.o
225
226
snd-soc-rt274-y := rt274.o
226
227
snd-soc-rt286-y := rt286.o
227
228
snd-soc-rt298-y := rt298.o
···
615
614
obj-$(CONFIG_SND_SOC_RT1308_SDW) += snd-soc-rt1308-sdw.o
616
615
obj-$(CONFIG_SND_SOC_RT1316_SDW) += snd-soc-rt1316-sdw.o
617
616
obj-$(CONFIG_SND_SOC_RT1318_SDW) += snd-soc-rt1318-sdw.o
617
+
obj-$(CONFIG_SND_SOC_RT1320_SDW) += snd-soc-rt1320-sdw.o
618
618
obj-$(CONFIG_SND_SOC_RT274) += snd-soc-rt274.o
619
619
obj-$(CONFIG_SND_SOC_RT286) += snd-soc-rt286.o
620
620
obj-$(CONFIG_SND_SOC_RT298) += snd-soc-rt298.o
+2260
sound/soc/codecs/rt1320-sdw.c
+2260
sound/soc/codecs/rt1320-sdw.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
//
3
+
// rt1320-sdw.c -- rt1320 SDCA ALSA SoC amplifier audio driver
4
+
//
5
+
// Copyright(c) 2024 Realtek Semiconductor Corp.
6
+
//
7
+
//
8
+
#include <linux/delay.h>
9
+
#include <linux/device.h>
10
+
#include <linux/pm_runtime.h>
11
+
#include <linux/mod_devicetable.h>
12
+
#include <linux/module.h>
13
+
#include <linux/regmap.h>
14
+
#include <linux/dmi.h>
15
+
#include <linux/firmware.h>
16
+
#include <sound/core.h>
17
+
#include <sound/pcm.h>
18
+
#include <sound/pcm_params.h>
19
+
#include <sound/soc-dapm.h>
20
+
#include <sound/initval.h>
21
+
#include <sound/tlv.h>
22
+
#include <sound/sdw.h>
23
+
#include "rt1320-sdw.h"
24
+
25
+
/*
26
+
* The 'blind writes' is an SDCA term to deal with platform-specific initialization.
27
+
* It might include vendor-specific or SDCA control registers.
28
+
*/
29
+
static const struct reg_sequence rt1320_blind_write[] = {
30
+
{ 0xc003, 0xe0 },
31
+
{ 0xc01b, 0xfc },
32
+
{ 0xc5c3, 0xf2 },
33
+
{ 0xc5c2, 0x00 },
34
+
{ 0xc5c6, 0x10 },
35
+
{ 0xc5c4, 0x12 },
36
+
{ 0xc5c8, 0x03 },
37
+
{ 0xc5d8, 0x0a },
38
+
{ 0xc5f7, 0x22 },
39
+
{ 0xc5f6, 0x22 },
40
+
{ 0xc5d0, 0x0f },
41
+
{ 0xc5d1, 0x89 },
42
+
{ 0xc057, 0x51 },
43
+
{ 0xc054, 0x35 },
44
+
{ 0xc053, 0x55 },
45
+
{ 0xc052, 0x55 },
46
+
{ 0xc051, 0x13 },
47
+
{ 0xc050, 0x15 },
48
+
{ 0xc060, 0x77 },
49
+
{ 0xc061, 0x55 },
50
+
{ 0xc063, 0x55 },
51
+
{ 0xc065, 0xa5 },
52
+
{ 0xc06b, 0x0a },
53
+
{ 0xca05, 0xd6 },
54
+
{ 0xca25, 0xd6 },
55
+
{ 0xcd00, 0x05 },
56
+
{ 0xc604, 0x40 },
57
+
{ 0xc609, 0x40 },
58
+
{ 0xc046, 0xff },
59
+
{ 0xc045, 0xff },
60
+
{ 0xc044, 0xff },
61
+
{ 0xc043, 0xff },
62
+
{ 0xc042, 0xff },
63
+
{ 0xc041, 0xff },
64
+
{ 0xc040, 0xff },
65
+
{ 0xcc10, 0x01 },
66
+
{ 0xc700, 0xf0 },
67
+
{ 0xc701, 0x13 },
68
+
{ 0xc901, 0x04 },
69
+
{ 0xc900, 0x73 },
70
+
{ 0xde03, 0x05 },
71
+
{ 0xdd0b, 0x0d },
72
+
{ 0xdd0a, 0xff },
73
+
{ 0xdd09, 0x0d },
74
+
{ 0xdd08, 0xff },
75
+
{ 0xc570, 0x08 },
76
+
{ 0xe803, 0xbe },
77
+
{ 0xc003, 0xc0 },
78
+
{ 0xc081, 0xfe },
79
+
{ 0xce31, 0x0d },
80
+
{ 0xce30, 0xae },
81
+
{ 0xce37, 0x0b },
82
+
{ 0xce36, 0xd2 },
83
+
{ 0xce39, 0x04 },
84
+
{ 0xce38, 0x80 },
85
+
{ 0xce3f, 0x00 },
86
+
{ 0xce3e, 0x00 },
87
+
{ 0xd470, 0x8b },
88
+
{ 0xd471, 0x18 },
89
+
{ 0xc019, 0x10 },
90
+
{ 0xd487, 0x3f },
91
+
{ 0xd486, 0xc3 },
92
+
};
93
+
94
+
/*
95
+
* The 'patch code' is written to the patch code area.
96
+
* The patch code area is used for SDCA register expansion flexibility.
97
+
*/
98
+
static const struct reg_sequence rt1320_patch_code_write[] = {
99
+
{ 0x10007000, 0x37 },
100
+
{ 0x10007001, 0x77 },
101
+
{ 0x10007002, 0x00 },
102
+
{ 0x10007003, 0x10 },
103
+
{ 0x10007004, 0xb7 },
104
+
{ 0x10007005, 0xe7 },
105
+
{ 0x10007006, 0x00 },
106
+
{ 0x10007007, 0x10 },
107
+
{ 0x10007008, 0x13 },
108
+
{ 0x10007009, 0x07 },
109
+
{ 0x1000700a, 0x07 },
110
+
{ 0x1000700b, 0x40 },
111
+
{ 0x1000700c, 0x23 },
112
+
{ 0x1000700d, 0xae },
113
+
{ 0x1000700e, 0xe7 },
114
+
{ 0x1000700f, 0xda },
115
+
{ 0x10007010, 0x37 },
116
+
{ 0x10007011, 0x77 },
117
+
{ 0x10007012, 0x00 },
118
+
{ 0x10007013, 0x10 },
119
+
{ 0x10007014, 0x13 },
120
+
{ 0x10007015, 0x07 },
121
+
{ 0x10007016, 0x47 },
122
+
{ 0x10007017, 0x61 },
123
+
{ 0x10007018, 0x23 },
124
+
{ 0x10007019, 0xa4 },
125
+
{ 0x1000701a, 0xe7 },
126
+
{ 0x1000701b, 0xde },
127
+
{ 0x1000701c, 0x37 },
128
+
{ 0x1000701d, 0x77 },
129
+
{ 0x1000701e, 0x00 },
130
+
{ 0x1000701f, 0x10 },
131
+
{ 0x10007020, 0x13 },
132
+
{ 0x10007021, 0x07 },
133
+
{ 0x10007022, 0x07 },
134
+
{ 0x10007023, 0x52 },
135
+
{ 0x10007024, 0x23 },
136
+
{ 0x10007025, 0xae },
137
+
{ 0x10007026, 0xe7 },
138
+
{ 0x10007027, 0xde },
139
+
{ 0x10007028, 0x37 },
140
+
{ 0x10007029, 0x77 },
141
+
{ 0x1000702a, 0x00 },
142
+
{ 0x1000702b, 0x10 },
143
+
{ 0x1000702c, 0x13 },
144
+
{ 0x1000702d, 0x07 },
145
+
{ 0x1000702e, 0x47 },
146
+
{ 0x1000702f, 0x54 },
147
+
{ 0x10007030, 0x23 },
148
+
{ 0x10007031, 0xaa },
149
+
{ 0x10007032, 0xe7 },
150
+
{ 0x10007033, 0xe4 },
151
+
{ 0x10007034, 0x37 },
152
+
{ 0x10007035, 0x87 },
153
+
{ 0x10007036, 0x00 },
154
+
{ 0x10007037, 0x10 },
155
+
{ 0x10007038, 0x13 },
156
+
{ 0x10007039, 0x07 },
157
+
{ 0x1000703a, 0x47 },
158
+
{ 0x1000703b, 0x81 },
159
+
{ 0x1000703c, 0x23 },
160
+
{ 0x1000703d, 0xa2 },
161
+
{ 0x1000703e, 0xe7 },
162
+
{ 0x1000703f, 0xe8 },
163
+
{ 0x10007040, 0x23 },
164
+
{ 0x10007041, 0xa4 },
165
+
{ 0x10007042, 0xe7 },
166
+
{ 0x10007043, 0xe8 },
167
+
{ 0x10007044, 0x37 },
168
+
{ 0x10007045, 0x77 },
169
+
{ 0x10007046, 0x00 },
170
+
{ 0x10007047, 0x10 },
171
+
{ 0x10007048, 0x13 },
172
+
{ 0x10007049, 0x07 },
173
+
{ 0x1000704a, 0x07 },
174
+
{ 0x1000704b, 0x59 },
175
+
{ 0x1000704c, 0x23 },
176
+
{ 0x1000704d, 0xa8 },
177
+
{ 0x1000704e, 0xe7 },
178
+
{ 0x1000704f, 0xea },
179
+
{ 0x10007050, 0x37 },
180
+
{ 0x10007051, 0x77 },
181
+
{ 0x10007052, 0x00 },
182
+
{ 0x10007053, 0x10 },
183
+
{ 0x10007054, 0x13 },
184
+
{ 0x10007055, 0x07 },
185
+
{ 0x10007056, 0x07 },
186
+
{ 0x10007057, 0x78 },
187
+
{ 0x10007058, 0x23 },
188
+
{ 0x10007059, 0xa6 },
189
+
{ 0x1000705a, 0xe7 },
190
+
{ 0x1000705b, 0xec },
191
+
{ 0x1000705c, 0x67 },
192
+
{ 0x1000705d, 0x80 },
193
+
{ 0x1000705e, 0x00 },
194
+
{ 0x1000705f, 0x00 },
195
+
{ 0x10007400, 0x37 },
196
+
{ 0x10007401, 0xd7 },
197
+
{ 0x10007402, 0x00 },
198
+
{ 0x10007403, 0x00 },
199
+
{ 0x10007404, 0x83 },
200
+
{ 0x10007405, 0x27 },
201
+
{ 0x10007406, 0x47 },
202
+
{ 0x10007407, 0x56 },
203
+
{ 0x10007408, 0xb7 },
204
+
{ 0x10007409, 0x06 },
205
+
{ 0x1000740a, 0x00 },
206
+
{ 0x1000740b, 0x02 },
207
+
{ 0x1000740c, 0xb3 },
208
+
{ 0x1000740d, 0xf7 },
209
+
{ 0x1000740e, 0xd7 },
210
+
{ 0x1000740f, 0x00 },
211
+
{ 0x10007410, 0x63 },
212
+
{ 0x10007411, 0x8a },
213
+
{ 0x10007412, 0x07 },
214
+
{ 0x10007413, 0x00 },
215
+
{ 0x10007414, 0x93 },
216
+
{ 0x10007415, 0x06 },
217
+
{ 0x10007416, 0x10 },
218
+
{ 0x10007417, 0x00 },
219
+
{ 0x10007418, 0x23 },
220
+
{ 0x10007419, 0x83 },
221
+
{ 0x1000741a, 0xd1 },
222
+
{ 0x1000741b, 0x44 },
223
+
{ 0x1000741c, 0x93 },
224
+
{ 0x1000741d, 0x07 },
225
+
{ 0x1000741e, 0xf0 },
226
+
{ 0x1000741f, 0xff },
227
+
{ 0x10007420, 0x23 },
228
+
{ 0x10007421, 0x22 },
229
+
{ 0x10007422, 0xf7 },
230
+
{ 0x10007423, 0x56 },
231
+
{ 0x10007424, 0x37 },
232
+
{ 0x10007425, 0xd7 },
233
+
{ 0x10007426, 0x00 },
234
+
{ 0x10007427, 0x00 },
235
+
{ 0x10007428, 0x83 },
236
+
{ 0x10007429, 0x27 },
237
+
{ 0x1000742a, 0x47 },
238
+
{ 0x1000742b, 0x58 },
239
+
{ 0x1000742c, 0x93 },
240
+
{ 0x1000742d, 0xf7 },
241
+
{ 0x1000742e, 0x17 },
242
+
{ 0x1000742f, 0x00 },
243
+
{ 0x10007430, 0x63 },
244
+
{ 0x10007431, 0x86 },
245
+
{ 0x10007432, 0x07 },
246
+
{ 0x10007433, 0x00 },
247
+
{ 0x10007434, 0x93 },
248
+
{ 0x10007435, 0x07 },
249
+
{ 0x10007436, 0x10 },
250
+
{ 0x10007437, 0x00 },
251
+
{ 0x10007438, 0x23 },
252
+
{ 0x10007439, 0x22 },
253
+
{ 0x1000743a, 0xf7 },
254
+
{ 0x1000743b, 0x58 },
255
+
{ 0x1000743c, 0xb7 },
256
+
{ 0x1000743d, 0xd7 },
257
+
{ 0x1000743e, 0x00 },
258
+
{ 0x1000743f, 0x00 },
259
+
{ 0x10007440, 0x03 },
260
+
{ 0x10007441, 0xa7 },
261
+
{ 0x10007442, 0x47 },
262
+
{ 0x10007443, 0x58 },
263
+
{ 0x10007444, 0xb7 },
264
+
{ 0x10007445, 0x07 },
265
+
{ 0x10007446, 0x00 },
266
+
{ 0x10007447, 0x04 },
267
+
{ 0x10007448, 0x33 },
268
+
{ 0x10007449, 0x77 },
269
+
{ 0x1000744a, 0xf7 },
270
+
{ 0x1000744b, 0x00 },
271
+
{ 0x1000744c, 0x93 },
272
+
{ 0x1000744d, 0x07 },
273
+
{ 0x1000744e, 0x00 },
274
+
{ 0x1000744f, 0x00 },
275
+
{ 0x10007450, 0x63 },
276
+
{ 0x10007451, 0x0e },
277
+
{ 0x10007452, 0x07 },
278
+
{ 0x10007453, 0x04 },
279
+
{ 0x10007454, 0x37 },
280
+
{ 0x10007455, 0x07 },
281
+
{ 0x10007456, 0x00 },
282
+
{ 0x10007457, 0x11 },
283
+
{ 0x10007458, 0x03 },
284
+
{ 0x10007459, 0x47 },
285
+
{ 0x1000745a, 0x87 },
286
+
{ 0x1000745b, 0x0e },
287
+
{ 0x1000745c, 0x93 },
288
+
{ 0x1000745d, 0x06 },
289
+
{ 0x1000745e, 0x40 },
290
+
{ 0x1000745f, 0x00 },
291
+
{ 0x10007460, 0x13 },
292
+
{ 0x10007461, 0x77 },
293
+
{ 0x10007462, 0xf7 },
294
+
{ 0x10007463, 0x0f },
295
+
{ 0x10007464, 0x63 },
296
+
{ 0x10007465, 0x02 },
297
+
{ 0x10007466, 0xd7 },
298
+
{ 0x10007467, 0x0a },
299
+
{ 0x10007468, 0x93 },
300
+
{ 0x10007469, 0x06 },
301
+
{ 0x1000746a, 0x70 },
302
+
{ 0x1000746b, 0x00 },
303
+
{ 0x1000746c, 0x63 },
304
+
{ 0x1000746d, 0x10 },
305
+
{ 0x1000746e, 0xd7 },
306
+
{ 0x1000746f, 0x04 },
307
+
{ 0x10007470, 0x93 },
308
+
{ 0x10007471, 0x07 },
309
+
{ 0x10007472, 0x60 },
310
+
{ 0x10007473, 0x06 },
311
+
{ 0x10007474, 0x37 },
312
+
{ 0x10007475, 0xd7 },
313
+
{ 0x10007476, 0x00 },
314
+
{ 0x10007477, 0x00 },
315
+
{ 0x10007478, 0x83 },
316
+
{ 0x10007479, 0x46 },
317
+
{ 0x1000747a, 0x77 },
318
+
{ 0x1000747b, 0xa6 },
319
+
{ 0x1000747c, 0x93 },
320
+
{ 0x1000747d, 0xe6 },
321
+
{ 0x1000747e, 0x06 },
322
+
{ 0x1000747f, 0xf8 },
323
+
{ 0x10007480, 0x93 },
324
+
{ 0x10007481, 0xf6 },
325
+
{ 0x10007482, 0xf6 },
326
+
{ 0x10007483, 0x0f },
327
+
{ 0x10007484, 0xa3 },
328
+
{ 0x10007485, 0x03 },
329
+
{ 0x10007486, 0xd7 },
330
+
{ 0x10007487, 0xa6 },
331
+
{ 0x10007488, 0x83 },
332
+
{ 0x10007489, 0x46 },
333
+
{ 0x1000748a, 0x77 },
334
+
{ 0x1000748b, 0xa8 },
335
+
{ 0x1000748c, 0x93 },
336
+
{ 0x1000748d, 0xe6 },
337
+
{ 0x1000748e, 0x06 },
338
+
{ 0x1000748f, 0xf8 },
339
+
{ 0x10007490, 0x93 },
340
+
{ 0x10007491, 0xf6 },
341
+
{ 0x10007492, 0xf6 },
342
+
{ 0x10007493, 0x0f },
343
+
{ 0x10007494, 0xa3 },
344
+
{ 0x10007495, 0x03 },
345
+
{ 0x10007496, 0xd7 },
346
+
{ 0x10007497, 0xa8 },
347
+
{ 0x10007498, 0xb7 },
348
+
{ 0x10007499, 0xc6 },
349
+
{ 0x1000749a, 0x00 },
350
+
{ 0x1000749b, 0x00 },
351
+
{ 0x1000749c, 0x23 },
352
+
{ 0x1000749d, 0x84 },
353
+
{ 0x1000749e, 0xf6 },
354
+
{ 0x1000749f, 0x06 },
355
+
{ 0x100074a0, 0xa3 },
356
+
{ 0x100074a1, 0x84 },
357
+
{ 0x100074a2, 0xf6 },
358
+
{ 0x100074a3, 0x06 },
359
+
{ 0x100074a4, 0xb7 },
360
+
{ 0x100074a5, 0x06 },
361
+
{ 0x100074a6, 0x00 },
362
+
{ 0x100074a7, 0x04 },
363
+
{ 0x100074a8, 0x23 },
364
+
{ 0x100074a9, 0x22 },
365
+
{ 0x100074aa, 0xd7 },
366
+
{ 0x100074ab, 0x58 },
367
+
{ 0x100074ac, 0x37 },
368
+
{ 0x100074ad, 0xd7 },
369
+
{ 0x100074ae, 0x00 },
370
+
{ 0x100074af, 0x00 },
371
+
{ 0x100074b0, 0x03 },
372
+
{ 0x100074b1, 0x27 },
373
+
{ 0x100074b2, 0x47 },
374
+
{ 0x100074b3, 0x58 },
375
+
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796
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797
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798
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799
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800
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801
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802
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803
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804
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805
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806
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807
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808
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809
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810
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811
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812
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813
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814
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815
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816
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817
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818
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819
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820
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821
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822
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823
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824
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825
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826
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827
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{ 0x10007678, 0x93 },
828
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829
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830
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831
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832
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833
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834
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835
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836
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837
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838
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839
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840
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841
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842
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843
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844
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845
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846
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847
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848
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849
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850
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851
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852
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853
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854
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855
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856
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857
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858
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859
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860
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861
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862
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863
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864
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865
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866
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867
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868
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869
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870
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871
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872
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873
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874
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875
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876
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877
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878
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879
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880
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881
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882
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883
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884
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885
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886
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887
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888
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889
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890
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891
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892
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893
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894
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895
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896
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897
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898
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899
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900
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901
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902
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903
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904
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905
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906
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907
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908
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909
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910
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911
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912
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913
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914
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915
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916
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917
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918
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919
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920
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921
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922
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923
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924
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925
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926
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927
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928
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929
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930
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931
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932
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933
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934
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935
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936
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937
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938
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939
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940
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941
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942
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943
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944
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945
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946
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947
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948
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949
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{ 0x100076f2, 0xf7 },
950
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951
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{ 0x100076f4, 0x93 },
952
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953
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954
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955
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956
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957
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958
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959
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960
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961
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962
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963
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964
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965
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966
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967
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968
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969
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970
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{ 0x10007707, 0x54 },
971
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972
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{ 0x10007709, 0xa8 },
973
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{ 0x1000770a, 0x01 },
974
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975
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976
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{ 0x1000770d, 0xd7 },
977
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{ 0x1000770e, 0x00 },
978
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{ 0x1000770f, 0x10 },
979
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{ 0x10007710, 0x03 },
980
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{ 0x10007711, 0xc7 },
981
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{ 0x10007712, 0x07 },
982
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{ 0x10007713, 0xd9 },
983
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{ 0x10007714, 0x93 },
984
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{ 0x10007715, 0x06 },
985
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{ 0x10007716, 0x10 },
986
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{ 0x10007717, 0x00 },
987
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988
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989
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{ 0x1000771a, 0xf7 },
990
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{ 0x1000771b, 0x0f },
991
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{ 0x1000771c, 0x63 },
992
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{ 0x1000771d, 0x1a },
993
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{ 0x1000771e, 0xd7 },
994
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{ 0x1000771f, 0x04 },
995
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{ 0x10007720, 0x03 },
996
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{ 0x10007721, 0xc7 },
997
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{ 0x10007722, 0x27 },
998
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{ 0x10007723, 0xd9 },
999
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{ 0x10007724, 0x13 },
1000
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{ 0x10007725, 0x07 },
1001
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{ 0x10007726, 0x17 },
1002
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{ 0x10007727, 0x00 },
1003
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{ 0x10007728, 0x13 },
1004
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{ 0x10007729, 0x77 },
1005
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{ 0x1000772a, 0xf7 },
1006
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{ 0x1000772b, 0x0f },
1007
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{ 0x1000772c, 0x23 },
1008
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{ 0x1000772d, 0x89 },
1009
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{ 0x1000772e, 0xe7 },
1010
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{ 0x1000772f, 0xd8 },
1011
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{ 0x10007730, 0x83 },
1012
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{ 0x10007731, 0xc6 },
1013
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{ 0x10007732, 0x27 },
1014
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{ 0x10007733, 0xd9 },
1015
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{ 0x10007734, 0x03 },
1016
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{ 0x10007735, 0xc7 },
1017
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{ 0x10007736, 0x17 },
1018
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{ 0x10007737, 0xd9 },
1019
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{ 0x10007738, 0x93 },
1020
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{ 0x10007739, 0xf6 },
1021
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{ 0x1000773a, 0xf6 },
1022
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{ 0x1000773b, 0x0f },
1023
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{ 0x1000773c, 0x13 },
1024
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{ 0x1000773d, 0x77 },
1025
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{ 0x1000773e, 0xf7 },
1026
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{ 0x1000773f, 0x0f },
1027
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{ 0x10007740, 0x63 },
1028
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{ 0x10007741, 0xe8 },
1029
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{ 0x10007742, 0xe6 },
1030
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{ 0x10007743, 0x02 },
1031
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{ 0x10007744, 0xb7 },
1032
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{ 0x10007745, 0xd6 },
1033
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{ 0x10007746, 0x00 },
1034
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{ 0x10007747, 0x00 },
1035
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{ 0x10007748, 0x03 },
1036
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{ 0x10007749, 0xc7 },
1037
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{ 0x1000774a, 0xa6 },
1038
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{ 0x1000774b, 0xe1 },
1039
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{ 0x1000774c, 0x13 },
1040
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{ 0x1000774d, 0x67 },
1041
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{ 0x1000774e, 0x07 },
1042
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{ 0x1000774f, 0xf8 },
1043
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{ 0x10007750, 0x13 },
1044
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{ 0x10007751, 0x77 },
1045
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{ 0x10007752, 0xf7 },
1046
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{ 0x10007753, 0x0f },
1047
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{ 0x10007754, 0x23 },
1048
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{ 0x10007755, 0x8d },
1049
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{ 0x10007756, 0xe6 },
1050
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{ 0x10007757, 0xe0 },
1051
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{ 0x10007758, 0x03 },
1052
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{ 0x10007759, 0xc7 },
1053
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{ 0x1000775a, 0x37 },
1054
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{ 0x1000775b, 0xd9 },
1055
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{ 0x1000775c, 0x13 },
1056
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{ 0x1000775d, 0x07 },
1057
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{ 0x1000775e, 0x17 },
1058
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{ 0x1000775f, 0x00 },
1059
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{ 0x10007760, 0x13 },
1060
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{ 0x10007761, 0x77 },
1061
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{ 0x10007762, 0xf7 },
1062
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{ 0x10007763, 0x0f },
1063
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{ 0x10007764, 0xa3 },
1064
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{ 0x10007765, 0x89 },
1065
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{ 0x10007766, 0xe7 },
1066
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{ 0x10007767, 0xd8 },
1067
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{ 0x10007768, 0x13 },
1068
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{ 0x10007769, 0x07 },
1069
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{ 0x1000776a, 0x20 },
1070
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{ 0x1000776b, 0x00 },
1071
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{ 0x1000776c, 0x23 },
1072
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{ 0x1000776d, 0x88 },
1073
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{ 0x1000776e, 0xe7 },
1074
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{ 0x1000776f, 0xd8 },
1075
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{ 0x10007770, 0x83 },
1076
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{ 0x10007771, 0x20 },
1077
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{ 0x10007772, 0xc1 },
1078
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{ 0x10007773, 0x00 },
1079
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{ 0x10007774, 0x03 },
1080
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{ 0x10007775, 0x24 },
1081
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{ 0x10007776, 0x81 },
1082
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{ 0x10007777, 0x00 },
1083
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{ 0x10007778, 0x13 },
1084
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{ 0x10007779, 0x01 },
1085
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{ 0x1000777a, 0x01 },
1086
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{ 0x1000777b, 0x01 },
1087
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{ 0x1000777c, 0x67 },
1088
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{ 0x1000777d, 0x80 },
1089
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{ 0x1000777e, 0x00 },
1090
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{ 0x1000777f, 0x00 },
1091
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{ 0x10007780, 0x03 },
1092
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{ 0x10007781, 0xc7 },
1093
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{ 0x10007782, 0xa1 },
1094
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{ 0x10007783, 0x40 },
1095
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{ 0x10007784, 0x93 },
1096
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{ 0x10007785, 0x06 },
1097
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{ 0x10007786, 0x10 },
1098
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{ 0x10007787, 0x00 },
1099
+
{ 0x10007788, 0x63 },
1100
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{ 0x10007789, 0x16 },
1101
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{ 0x1000778a, 0xd7 },
1102
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{ 0x1000778b, 0x00 },
1103
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{ 0x1000778c, 0xb7 },
1104
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{ 0x1000778d, 0xd6 },
1105
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{ 0x1000778e, 0x00 },
1106
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{ 0x1000778f, 0x10 },
1107
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{ 0x10007790, 0xa3 },
1108
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{ 0x10007791, 0x8a },
1109
+
{ 0x10007792, 0xe6 },
1110
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{ 0x10007793, 0xd8 },
1111
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{ 0x10007794, 0x83 },
1112
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{ 0x10007795, 0xc7 },
1113
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{ 0x10007796, 0xa1 },
1114
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{ 0x10007797, 0x40 },
1115
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{ 0x10007798, 0x63 },
1116
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{ 0x10007799, 0x9c },
1117
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{ 0x1000779a, 0x07 },
1118
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{ 0x1000779b, 0x06 },
1119
+
{ 0x1000779c, 0x13 },
1120
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{ 0x1000779d, 0x01 },
1121
+
{ 0x1000779e, 0x01 },
1122
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{ 0x1000779f, 0xff },
1123
+
{ 0x100077a0, 0x23 },
1124
+
{ 0x100077a1, 0x22 },
1125
+
{ 0x100077a2, 0x91 },
1126
+
{ 0x100077a3, 0x00 },
1127
+
{ 0x100077a4, 0x23 },
1128
+
{ 0x100077a5, 0x26 },
1129
+
{ 0x100077a6, 0x11 },
1130
+
{ 0x100077a7, 0x00 },
1131
+
{ 0x100077a8, 0x23 },
1132
+
{ 0x100077a9, 0x24 },
1133
+
{ 0x100077aa, 0x81 },
1134
+
{ 0x100077ab, 0x00 },
1135
+
{ 0x100077ac, 0xb7 },
1136
+
{ 0x100077ad, 0xc4 },
1137
+
{ 0x100077ae, 0x00 },
1138
+
{ 0x100077af, 0x00 },
1139
+
{ 0x100077b0, 0x83 },
1140
+
{ 0x100077b1, 0xc7 },
1141
+
{ 0x100077b2, 0x04 },
1142
+
{ 0x100077b3, 0x56 },
1143
+
{ 0x100077b4, 0x13 },
1144
+
{ 0x100077b5, 0x07 },
1145
+
{ 0x100077b6, 0x80 },
1146
+
{ 0x100077b7, 0x01 },
1147
+
{ 0x100077b8, 0x93 },
1148
+
{ 0x100077b9, 0xf7 },
1149
+
{ 0x100077ba, 0xf7 },
1150
+
{ 0x100077bb, 0x0f },
1151
+
{ 0x100077bc, 0x63 },
1152
+
{ 0x100077bd, 0x70 },
1153
+
{ 0x100077be, 0xf7 },
1154
+
{ 0x100077bf, 0x04 },
1155
+
{ 0x100077c0, 0x37 },
1156
+
{ 0x100077c1, 0xd4 },
1157
+
{ 0x100077c2, 0x00 },
1158
+
{ 0x100077c3, 0x10 },
1159
+
{ 0x100077c4, 0x83 },
1160
+
{ 0x100077c5, 0x47 },
1161
+
{ 0x100077c6, 0x54 },
1162
+
{ 0x100077c7, 0xd9 },
1163
+
{ 0x100077c8, 0x93 },
1164
+
{ 0x100077c9, 0xf7 },
1165
+
{ 0x100077ca, 0xf7 },
1166
+
{ 0x100077cb, 0x0f },
1167
+
{ 0x100077cc, 0x63 },
1168
+
{ 0x100077cd, 0x88 },
1169
+
{ 0x100077ce, 0x07 },
1170
+
{ 0x100077cf, 0x02 },
1171
+
{ 0x100077d0, 0x93 },
1172
+
{ 0x100077d1, 0x07 },
1173
+
{ 0x100077d2, 0x10 },
1174
+
{ 0x100077d3, 0x00 },
1175
+
{ 0x100077d4, 0x23 },
1176
+
{ 0x100077d5, 0x82 },
1177
+
{ 0x100077d6, 0xf4 },
1178
+
{ 0x100077d7, 0x58 },
1179
+
{ 0x100077d8, 0x03 },
1180
+
{ 0x100077d9, 0x45 },
1181
+
{ 0x100077da, 0x64 },
1182
+
{ 0x100077db, 0xd9 },
1183
+
{ 0x100077dc, 0xb7 },
1184
+
{ 0x100077dd, 0x15 },
1185
+
{ 0x100077de, 0x00 },
1186
+
{ 0x100077df, 0x00 },
1187
+
{ 0x100077e0, 0x93 },
1188
+
{ 0x100077e1, 0x85 },
1189
+
{ 0x100077e2, 0x85 },
1190
+
{ 0x100077e3, 0x38 },
1191
+
{ 0x100077e4, 0x13 },
1192
+
{ 0x100077e5, 0x75 },
1193
+
{ 0x100077e6, 0xf5 },
1194
+
{ 0x100077e7, 0x0f },
1195
+
{ 0x100077e8, 0xef },
1196
+
{ 0x100077e9, 0xe0 },
1197
+
{ 0x100077ea, 0x9f },
1198
+
{ 0x100077eb, 0xd0 },
1199
+
{ 0x100077ec, 0x93 },
1200
+
{ 0x100077ed, 0x55 },
1201
+
{ 0x100077ee, 0xf5 },
1202
+
{ 0x100077ef, 0x41 },
1203
+
{ 0x100077f0, 0xef },
1204
+
{ 0x100077f1, 0xe0 },
1205
+
{ 0x100077f2, 0x8f },
1206
+
{ 0x100077f3, 0xa3 },
1207
+
{ 0x100077f4, 0x23 },
1208
+
{ 0x100077f5, 0x82 },
1209
+
{ 0x100077f6, 0x04 },
1210
+
{ 0x100077f7, 0x58 },
1211
+
{ 0x100077f8, 0xa3 },
1212
+
{ 0x100077f9, 0x0a },
1213
+
{ 0x100077fa, 0x04 },
1214
+
{ 0x100077fb, 0xd8 },
1215
+
{ 0x100077fc, 0x83 },
1216
+
{ 0x100077fd, 0x20 },
1217
+
{ 0x100077fe, 0xc1 },
1218
+
{ 0x100077ff, 0x00 },
1219
+
{ 0x10007800, 0x03 },
1220
+
{ 0x10007801, 0x24 },
1221
+
{ 0x10007802, 0x81 },
1222
+
{ 0x10007803, 0x00 },
1223
+
{ 0x10007804, 0x83 },
1224
+
{ 0x10007805, 0x24 },
1225
+
{ 0x10007806, 0x41 },
1226
+
{ 0x10007807, 0x00 },
1227
+
{ 0x10007808, 0x13 },
1228
+
{ 0x10007809, 0x01 },
1229
+
{ 0x1000780a, 0x01 },
1230
+
{ 0x1000780b, 0x01 },
1231
+
{ 0x1000780c, 0x67 },
1232
+
{ 0x1000780d, 0x80 },
1233
+
{ 0x1000780e, 0x00 },
1234
+
{ 0x1000780f, 0x00 },
1235
+
{ 0x10007810, 0x67 },
1236
+
{ 0x10007811, 0x80 },
1237
+
{ 0x10007812, 0x00 },
1238
+
{ 0x10007813, 0x00 },
1239
+
{ 0x10007814, 0x13 },
1240
+
{ 0x10007815, 0x01 },
1241
+
{ 0x10007816, 0x01 },
1242
+
{ 0x10007817, 0xff },
1243
+
{ 0x10007818, 0x23 },
1244
+
{ 0x10007819, 0x26 },
1245
+
{ 0x1000781a, 0x11 },
1246
+
{ 0x1000781b, 0x00 },
1247
+
{ 0x1000781c, 0xef },
1248
+
{ 0x1000781d, 0xd0 },
1249
+
{ 0x1000781e, 0x8f },
1250
+
{ 0x1000781f, 0x86 },
1251
+
{ 0x10007820, 0x83 },
1252
+
{ 0x10007821, 0xc7 },
1253
+
{ 0x10007822, 0x11 },
1254
+
{ 0x10007823, 0x42 },
1255
+
{ 0x10007824, 0x63 },
1256
+
{ 0x10007825, 0x86 },
1257
+
{ 0x10007826, 0x07 },
1258
+
{ 0x10007827, 0x00 },
1259
+
{ 0x10007828, 0x03 },
1260
+
{ 0x10007829, 0xc7 },
1261
+
{ 0x1000782a, 0x01 },
1262
+
{ 0x1000782b, 0x42 },
1263
+
{ 0x1000782c, 0x63 },
1264
+
{ 0x1000782d, 0x10 },
1265
+
{ 0x1000782e, 0x07 },
1266
+
{ 0x1000782f, 0x02 },
1267
+
{ 0x10007830, 0x83 },
1268
+
{ 0x10007831, 0xc6 },
1269
+
{ 0x10007832, 0x21 },
1270
+
{ 0x10007833, 0x41 },
1271
+
{ 0x10007834, 0x13 },
1272
+
{ 0x10007835, 0x07 },
1273
+
{ 0x10007836, 0xf0 },
1274
+
{ 0x10007837, 0x01 },
1275
+
{ 0x10007838, 0x13 },
1276
+
{ 0x10007839, 0x05 },
1277
+
{ 0x1000783a, 0xf0 },
1278
+
{ 0x1000783b, 0x01 },
1279
+
{ 0x1000783c, 0x63 },
1280
+
{ 0x1000783d, 0x98 },
1281
+
{ 0x1000783e, 0xe6 },
1282
+
{ 0x1000783f, 0x02 },
1283
+
{ 0x10007840, 0x63 },
1284
+
{ 0x10007841, 0x8a },
1285
+
{ 0x10007842, 0x07 },
1286
+
{ 0x10007843, 0x02 },
1287
+
{ 0x10007844, 0x83 },
1288
+
{ 0x10007845, 0xc7 },
1289
+
{ 0x10007846, 0x01 },
1290
+
{ 0x10007847, 0x42 },
1291
+
{ 0x10007848, 0x63 },
1292
+
{ 0x10007849, 0x86 },
1293
+
{ 0x1000784a, 0x07 },
1294
+
{ 0x1000784b, 0x02 },
1295
+
{ 0x1000784c, 0x83 },
1296
+
{ 0x1000784d, 0xc7 },
1297
+
{ 0x1000784e, 0x31 },
1298
+
{ 0x1000784f, 0x42 },
1299
+
{ 0x10007850, 0x63 },
1300
+
{ 0x10007851, 0x86 },
1301
+
{ 0x10007852, 0x07 },
1302
+
{ 0x10007853, 0x00 },
1303
+
{ 0x10007854, 0x83 },
1304
+
{ 0x10007855, 0xc7 },
1305
+
{ 0x10007856, 0x21 },
1306
+
{ 0x10007857, 0x42 },
1307
+
{ 0x10007858, 0x63 },
1308
+
{ 0x10007859, 0x9e },
1309
+
{ 0x1000785a, 0x07 },
1310
+
{ 0x1000785b, 0x00 },
1311
+
{ 0x1000785c, 0x03 },
1312
+
{ 0x1000785d, 0xc7 },
1313
+
{ 0x1000785e, 0x21 },
1314
+
{ 0x1000785f, 0x41 },
1315
+
{ 0x10007860, 0x93 },
1316
+
{ 0x10007861, 0x07 },
1317
+
{ 0x10007862, 0xb0 },
1318
+
{ 0x10007863, 0x01 },
1319
+
{ 0x10007864, 0x63 },
1320
+
{ 0x10007865, 0x08 },
1321
+
{ 0x10007866, 0xf7 },
1322
+
{ 0x10007867, 0x00 },
1323
+
{ 0x10007868, 0x13 },
1324
+
{ 0x10007869, 0x05 },
1325
+
{ 0x1000786a, 0xb0 },
1326
+
{ 0x1000786b, 0x01 },
1327
+
{ 0x1000786c, 0xef },
1328
+
{ 0x1000786d, 0xd0 },
1329
+
{ 0x1000786e, 0x0f },
1330
+
{ 0x1000786f, 0xcf },
1331
+
{ 0x10007870, 0xef },
1332
+
{ 0x10007871, 0xd0 },
1333
+
{ 0x10007872, 0x8f },
1334
+
{ 0x10007873, 0xa4 },
1335
+
{ 0x10007874, 0x93 },
1336
+
{ 0x10007875, 0x06 },
1337
+
{ 0x10007876, 0x10 },
1338
+
{ 0x10007877, 0x00 },
1339
+
{ 0x10007878, 0xa3 },
1340
+
{ 0x10007879, 0x89 },
1341
+
{ 0x1000787a, 0xd1 },
1342
+
{ 0x1000787b, 0x40 },
1343
+
{ 0x1000787c, 0x37 },
1344
+
{ 0x1000787d, 0xd7 },
1345
+
{ 0x1000787e, 0x00 },
1346
+
{ 0x1000787f, 0x10 },
1347
+
{ 0x10007880, 0x83 },
1348
+
{ 0x10007881, 0x47 },
1349
+
{ 0x10007882, 0x07 },
1350
+
{ 0x10007883, 0xd9 },
1351
+
{ 0x10007884, 0x93 },
1352
+
{ 0x10007885, 0xf7 },
1353
+
{ 0x10007886, 0xf7 },
1354
+
{ 0x10007887, 0x0f },
1355
+
{ 0x10007888, 0x63 },
1356
+
{ 0x10007889, 0x90 },
1357
+
{ 0x1000788a, 0x07 },
1358
+
{ 0x1000788b, 0x02 },
1359
+
{ 0x1000788c, 0x37 },
1360
+
{ 0x1000788d, 0xc6 },
1361
+
{ 0x1000788e, 0x00 },
1362
+
{ 0x1000788f, 0x00 },
1363
+
{ 0x10007890, 0x83 },
1364
+
{ 0x10007891, 0x47 },
1365
+
{ 0x10007892, 0x26 },
1366
+
{ 0x10007893, 0x04 },
1367
+
{ 0x10007894, 0x93 },
1368
+
{ 0x10007895, 0xe7 },
1369
+
{ 0x10007896, 0x07 },
1370
+
{ 0x10007897, 0xf8 },
1371
+
{ 0x10007898, 0x93 },
1372
+
{ 0x10007899, 0xf7 },
1373
+
{ 0x1000789a, 0xf7 },
1374
+
{ 0x1000789b, 0x0f },
1375
+
{ 0x1000789c, 0x23 },
1376
+
{ 0x1000789d, 0x01 },
1377
+
{ 0x1000789e, 0xf6 },
1378
+
{ 0x1000789f, 0x04 },
1379
+
{ 0x100078a0, 0x23 },
1380
+
{ 0x100078a1, 0x08 },
1381
+
{ 0x100078a2, 0xd7 },
1382
+
{ 0x100078a3, 0xd8 },
1383
+
{ 0x100078a4, 0x23 },
1384
+
{ 0x100078a5, 0x09 },
1385
+
{ 0x100078a6, 0x07 },
1386
+
{ 0x100078a7, 0xd8 },
1387
+
{ 0x100078a8, 0x83 },
1388
+
{ 0x100078a9, 0x20 },
1389
+
{ 0x100078aa, 0xc1 },
1390
+
{ 0x100078ab, 0x00 },
1391
+
{ 0x100078ac, 0x13 },
1392
+
{ 0x100078ad, 0x01 },
1393
+
{ 0x100078ae, 0x01 },
1394
+
{ 0x100078af, 0x01 },
1395
+
{ 0x100078b0, 0x67 },
1396
+
{ 0x100078b1, 0x80 },
1397
+
{ 0x100078b2, 0x00 },
1398
+
{ 0x100078b3, 0x00 },
1399
+
{ 0x3fc2bfc7, 0x00 },
1400
+
{ 0x3fc2bfc6, 0x00 },
1401
+
{ 0x3fc2bfc5, 0x00 },
1402
+
{ 0x3fc2bfc4, 0x01 },
1403
+
{ 0x0000d486, 0x43 },
1404
+
{ 0x1000db00, 0x02 },
1405
+
{ 0x1000db01, 0x00 },
1406
+
{ 0x1000db02, 0x11 },
1407
+
{ 0x1000db03, 0x00 },
1408
+
{ 0x1000db04, 0x00 },
1409
+
{ 0x1000db05, 0x82 },
1410
+
{ 0x1000db06, 0x04 },
1411
+
{ 0x1000db07, 0xf1 },
1412
+
{ 0x1000db08, 0x00 },
1413
+
{ 0x1000db09, 0x00 },
1414
+
{ 0x1000db0a, 0x40 },
1415
+
{ 0x0000d540, 0x01 },
1416
+
};
1417
+
1418
+
static const struct reg_default rt1320_reg_defaults[] = {
1419
+
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 },
1420
+
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 },
1421
+
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0x00 },
1422
+
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 },
1423
+
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x0b },
1424
+
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 },
1425
+
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
1426
+
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
1427
+
};
1428
+
1429
+
static const struct reg_default rt1320_mbq_defaults[] = {
1430
+
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 },
1431
+
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 },
1432
+
};
1433
+
1434
+
static bool rt1320_readable_register(struct device *dev, unsigned int reg)
1435
+
{
1436
+
switch (reg) {
1437
+
case 0xc000 ... 0xc086:
1438
+
case 0xc400 ... 0xc409:
1439
+
case 0xc480 ... 0xc48f:
1440
+
case 0xc4c0 ... 0xc4c4:
1441
+
case 0xc4e0 ... 0xc4e7:
1442
+
case 0xc500:
1443
+
case 0xc560 ... 0xc56b:
1444
+
case 0xc570:
1445
+
case 0xc580 ... 0xc59a:
1446
+
case 0xc5b0 ... 0xc60f:
1447
+
case 0xc640 ... 0xc64f:
1448
+
case 0xc670:
1449
+
case 0xc680 ... 0xc683:
1450
+
case 0xc700 ... 0xc76f:
1451
+
case 0xc800 ... 0xc801:
1452
+
case 0xc820:
1453
+
case 0xc900 ... 0xc901:
1454
+
case 0xc920 ... 0xc921:
1455
+
case 0xca00 ... 0xca07:
1456
+
case 0xca20 ... 0xca27:
1457
+
case 0xca40 ... 0xca4b:
1458
+
case 0xca60 ... 0xca68:
1459
+
case 0xca80 ... 0xca88:
1460
+
case 0xcb00 ... 0xcb0c:
1461
+
case 0xcc00 ... 0xcc12:
1462
+
case 0xcc80 ... 0xcc81:
1463
+
case 0xcd00:
1464
+
case 0xcd80 ... 0xcd82:
1465
+
case 0xce00 ... 0xce4d:
1466
+
case 0xcf00 ... 0xcf25:
1467
+
case 0xd000 ... 0xd0ff:
1468
+
case 0xd100 ... 0xd1ff:
1469
+
case 0xd200 ... 0xd2ff:
1470
+
case 0xd300 ... 0xd3ff:
1471
+
case 0xd400 ... 0xd403:
1472
+
case 0xd410 ... 0xd417:
1473
+
case 0xd470 ... 0xd497:
1474
+
case 0xd4dc ... 0xd50f:
1475
+
case 0xd520 ... 0xd543:
1476
+
case 0xd560 ... 0xd5ef:
1477
+
case 0xd600 ... 0xd663:
1478
+
case 0xda00 ... 0xda6e:
1479
+
case 0xda80 ... 0xda9e:
1480
+
case 0xdb00 ... 0xdb7f:
1481
+
case 0xdc00:
1482
+
case 0xdc20 ... 0xdc21:
1483
+
case 0xdd00 ... 0xdd17:
1484
+
case 0xde00 ... 0xde09:
1485
+
case 0xdf00 ... 0xdf1b:
1486
+
case 0xe000 ... 0xe847:
1487
+
case 0xf717 ... 0xf719:
1488
+
case 0xf720 ... 0xf723:
1489
+
case 0x1000f008:
1490
+
case 0x3fe2e000 ... 0x3fe2e003:
1491
+
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0):
1492
+
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01):
1493
+
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02):
1494
+
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0):
1495
+
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0):
1496
+
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0):
1497
+
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
1498
+
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
1499
+
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
1500
+
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0):
1501
+
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0):
1502
+
return true;
1503
+
default:
1504
+
return false;
1505
+
}
1506
+
}
1507
+
1508
+
static bool rt1320_volatile_register(struct device *dev, unsigned int reg)
1509
+
{
1510
+
switch (reg) {
1511
+
case 0xc402 ... 0xc406:
1512
+
case 0xc48c ... 0xc48f:
1513
+
case 0xc560:
1514
+
case 0xc5b5 ... 0xc5b7:
1515
+
case 0xc5fc ... 0xc5ff:
1516
+
case 0xc820:
1517
+
case 0xc900:
1518
+
case 0xc920:
1519
+
case 0xca42:
1520
+
case 0xca62:
1521
+
case 0xca82:
1522
+
case 0xcd00:
1523
+
case 0xce03:
1524
+
case 0xce10:
1525
+
case 0xce14 ... 0xce17:
1526
+
case 0xce44 ... 0xce49:
1527
+
case 0xce4c ... 0xce4d:
1528
+
case 0xcf0c:
1529
+
case 0xcf10 ... 0xcf25:
1530
+
case 0xd486 ... 0xd487:
1531
+
case 0xd4e5 ... 0xd4e6:
1532
+
case 0xd4e8 ... 0xd4ff:
1533
+
case 0xd530:
1534
+
case 0xd540:
1535
+
case 0xd543:
1536
+
case 0xdb58 ... 0xdb5f:
1537
+
case 0xdb60 ... 0xdb63:
1538
+
case 0xdb68 ... 0xdb69:
1539
+
case 0xdb6d:
1540
+
case 0xdb70 ... 0xdb71:
1541
+
case 0xdb76:
1542
+
case 0xdb7a:
1543
+
case 0xdb7c ... 0xdb7f:
1544
+
case 0xdd0c ... 0xdd13:
1545
+
case 0xde02:
1546
+
case 0xdf14 ... 0xdf1b:
1547
+
case 0xe83c ... 0xe847:
1548
+
case 0xf717 ... 0xf719:
1549
+
case 0xf720 ... 0xf723:
1550
+
case 0x10000000 ... 0x10007fff:
1551
+
case 0x1000c000 ... 0x1000dfff:
1552
+
case 0x1000f008:
1553
+
case 0x3fc2bfc4 ... 0x3fc2bfc7:
1554
+
case 0x3fe2e000 ... 0x3fe2e003:
1555
+
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0):
1556
+
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0):
1557
+
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0):
1558
+
return true;
1559
+
default:
1560
+
return false;
1561
+
}
1562
+
}
1563
+
1564
+
static bool rt1320_mbq_readable_register(struct device *dev, unsigned int reg)
1565
+
{
1566
+
switch (reg) {
1567
+
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01):
1568
+
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02):
1569
+
return true;
1570
+
default:
1571
+
return false;
1572
+
}
1573
+
}
1574
+
1575
+
static const struct regmap_config rt1320_sdw_regmap = {
1576
+
.reg_bits = 32,
1577
+
.val_bits = 8,
1578
+
.readable_reg = rt1320_readable_register,
1579
+
.volatile_reg = rt1320_volatile_register,
1580
+
.max_register = 0x41081488,
1581
+
.reg_defaults = rt1320_reg_defaults,
1582
+
.num_reg_defaults = ARRAY_SIZE(rt1320_reg_defaults),
1583
+
.cache_type = REGCACHE_MAPLE,
1584
+
.use_single_read = true,
1585
+
.use_single_write = true,
1586
+
};
1587
+
1588
+
static const struct regmap_config rt1320_mbq_regmap = {
1589
+
.name = "sdw-mbq",
1590
+
.reg_bits = 32,
1591
+
.val_bits = 16,
1592
+
.readable_reg = rt1320_mbq_readable_register,
1593
+
.max_register = 0x41000192,
1594
+
.reg_defaults = rt1320_mbq_defaults,
1595
+
.num_reg_defaults = ARRAY_SIZE(rt1320_mbq_defaults),
1596
+
.cache_type = REGCACHE_MAPLE,
1597
+
.use_single_read = true,
1598
+
.use_single_write = true,
1599
+
};
1600
+
1601
+
static int rt1320_read_prop(struct sdw_slave *slave)
1602
+
{
1603
+
struct sdw_slave_prop *prop = &slave->prop;
1604
+
int nval;
1605
+
int i, j;
1606
+
u32 bit;
1607
+
unsigned long addr;
1608
+
struct sdw_dpn_prop *dpn;
1609
+
1610
+
/*
1611
+
* Due to support the multi-lane, we call 'sdw_slave_read_prop' to get the lane mapping
1612
+
*/
1613
+
sdw_slave_read_prop(slave);
1614
+
1615
+
prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
1616
+
prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
1617
+
1618
+
prop->paging_support = true;
1619
+
prop->lane_control_support = true;
1620
+
1621
+
/* first we need to allocate memory for set bits in port lists */
1622
+
prop->source_ports = BIT(4);
1623
+
prop->sink_ports = BIT(1);
1624
+
1625
+
nval = hweight32(prop->source_ports);
1626
+
prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
1627
+
sizeof(*prop->src_dpn_prop), GFP_KERNEL);
1628
+
if (!prop->src_dpn_prop)
1629
+
return -ENOMEM;
1630
+
1631
+
i = 0;
1632
+
dpn = prop->src_dpn_prop;
1633
+
addr = prop->source_ports;
1634
+
for_each_set_bit(bit, &addr, 32) {
1635
+
dpn[i].num = bit;
1636
+
dpn[i].type = SDW_DPN_FULL;
1637
+
dpn[i].simple_ch_prep_sm = true;
1638
+
dpn[i].ch_prep_timeout = 10;
1639
+
i++;
1640
+
}
1641
+
1642
+
/* do this again for sink now */
1643
+
nval = hweight32(prop->sink_ports);
1644
+
prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
1645
+
sizeof(*prop->sink_dpn_prop), GFP_KERNEL);
1646
+
if (!prop->sink_dpn_prop)
1647
+
return -ENOMEM;
1648
+
1649
+
j = 0;
1650
+
dpn = prop->sink_dpn_prop;
1651
+
addr = prop->sink_ports;
1652
+
for_each_set_bit(bit, &addr, 32) {
1653
+
dpn[j].num = bit;
1654
+
dpn[j].type = SDW_DPN_FULL;
1655
+
dpn[j].simple_ch_prep_sm = true;
1656
+
dpn[j].ch_prep_timeout = 10;
1657
+
j++;
1658
+
}
1659
+
1660
+
/* set the timeout values */
1661
+
prop->clk_stop_timeout = 64;
1662
+
1663
+
return 0;
1664
+
}
1665
+
1666
+
static int rt1320_io_init(struct device *dev, struct sdw_slave *slave)
1667
+
{
1668
+
struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev);
1669
+
unsigned int amp_func_status, val, tmp;
1670
+
1671
+
if (rt1320->hw_init)
1672
+
return 0;
1673
+
1674
+
regcache_cache_only(rt1320->regmap, false);
1675
+
regcache_cache_only(rt1320->mbq_regmap, false);
1676
+
if (rt1320->first_hw_init) {
1677
+
regcache_cache_bypass(rt1320->regmap, true);
1678
+
regcache_cache_bypass(rt1320->mbq_regmap, true);
1679
+
} else {
1680
+
/*
1681
+
* PM runtime status is marked as 'active' only when a Slave reports as Attached
1682
+
*/
1683
+
/* update count of parent 'active' children */
1684
+
pm_runtime_set_active(&slave->dev);
1685
+
}
1686
+
1687
+
pm_runtime_get_noresume(&slave->dev);
1688
+
1689
+
if (rt1320->version_id < 0) {
1690
+
regmap_read(rt1320->regmap, RT1320_DEV_VERSION_ID_1, &val);
1691
+
rt1320->version_id = val;
1692
+
}
1693
+
1694
+
regmap_read(rt1320->regmap,
1695
+
SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), &_func_status);
1696
+
dev_dbg(dev, "%s amp func_status=0x%x\n", __func__, amp_func_status);
1697
+
1698
+
/* initialization write */
1699
+
if ((amp_func_status & FUNCTION_NEEDS_INITIALIZATION) || (!rt1320->first_hw_init)) {
1700
+
regmap_multi_reg_write(rt1320->regmap, rt1320_blind_write, ARRAY_SIZE(rt1320_blind_write));
1701
+
regmap_multi_reg_write(rt1320->regmap, rt1320_patch_code_write,
1702
+
ARRAY_SIZE(rt1320_patch_code_write));
1703
+
1704
+
regmap_write(rt1320->regmap,
1705
+
SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0),
1706
+
FUNCTION_NEEDS_INITIALIZATION);
1707
+
}
1708
+
if (!rt1320->first_hw_init) {
1709
+
regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
1710
+
RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0);
1711
+
regmap_read(rt1320->regmap, RT1320_HIFI_VER_0, &val);
1712
+
regmap_read(rt1320->regmap, RT1320_HIFI_VER_1, &tmp);
1713
+
val = (tmp << 8) | val;
1714
+
regmap_read(rt1320->regmap, RT1320_HIFI_VER_2, &tmp);
1715
+
val = (tmp << 16) | val;
1716
+
regmap_read(rt1320->regmap, RT1320_HIFI_VER_3, &tmp);
1717
+
val = (tmp << 24) | val;
1718
+
dev_dbg(dev, "%s ROM version=0x%x\n", __func__, val);
1719
+
/*
1720
+
* We call the version b which has the new DSP ROM code against version a.
1721
+
* Therefore, we read the DSP address to check the ID.
1722
+
*/
1723
+
if (val == RT1320_VER_B_ID)
1724
+
rt1320->version_id = RT1320_VB;
1725
+
regmap_write(rt1320->regmap, SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
1726
+
RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 3);
1727
+
}
1728
+
dev_dbg(dev, "%s version_id=%d\n", __func__, rt1320->version_id);
1729
+
1730
+
if (rt1320->first_hw_init) {
1731
+
regcache_cache_bypass(rt1320->regmap, false);
1732
+
regcache_cache_bypass(rt1320->mbq_regmap, false);
1733
+
regcache_mark_dirty(rt1320->regmap);
1734
+
regcache_mark_dirty(rt1320->mbq_regmap);
1735
+
}
1736
+
1737
+
/* Mark Slave initialization complete */
1738
+
rt1320->first_hw_init = true;
1739
+
rt1320->hw_init = true;
1740
+
1741
+
pm_runtime_mark_last_busy(&slave->dev);
1742
+
pm_runtime_put_autosuspend(&slave->dev);
1743
+
1744
+
dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
1745
+
return 0;
1746
+
}
1747
+
1748
+
static int rt1320_update_status(struct sdw_slave *slave,
1749
+
enum sdw_slave_status status)
1750
+
{
1751
+
struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(&slave->dev);
1752
+
1753
+
if (status == SDW_SLAVE_UNATTACHED)
1754
+
rt1320->hw_init = false;
1755
+
1756
+
/*
1757
+
* Perform initialization only if slave status is present and
1758
+
* hw_init flag is false
1759
+
*/
1760
+
if (rt1320->hw_init || status != SDW_SLAVE_ATTACHED)
1761
+
return 0;
1762
+
1763
+
/* perform I/O transfers required for Slave initialization */
1764
+
return rt1320_io_init(&slave->dev, slave);
1765
+
}
1766
+
1767
+
static int rt1320_pde23_event(struct snd_soc_dapm_widget *w,
1768
+
struct snd_kcontrol *kcontrol, int event)
1769
+
{
1770
+
struct snd_soc_component *component =
1771
+
snd_soc_dapm_to_component(w->dapm);
1772
+
struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
1773
+
unsigned char ps0 = 0x0, ps3 = 0x3;
1774
+
1775
+
switch (event) {
1776
+
case SND_SOC_DAPM_POST_PMU:
1777
+
regmap_write(rt1320->regmap,
1778
+
SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
1779
+
RT1320_SDCA_CTL_REQ_POWER_STATE, 0),
1780
+
ps0);
1781
+
break;
1782
+
case SND_SOC_DAPM_PRE_PMD:
1783
+
regmap_write(rt1320->regmap,
1784
+
SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23,
1785
+
RT1320_SDCA_CTL_REQ_POWER_STATE, 0),
1786
+
ps3);
1787
+
break;
1788
+
default:
1789
+
break;
1790
+
}
1791
+
1792
+
return 0;
1793
+
}
1794
+
1795
+
static int rt1320_set_gain_put(struct snd_kcontrol *kcontrol,
1796
+
struct snd_ctl_elem_value *ucontrol)
1797
+
{
1798
+
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1799
+
struct soc_mixer_control *mc =
1800
+
(struct soc_mixer_control *)kcontrol->private_value;
1801
+
struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
1802
+
unsigned int read_l, read_r, gain_l_val, gain_r_val;
1803
+
unsigned int lvalue, rvalue;
1804
+
const unsigned int interval_offset = 0xc0;
1805
+
1806
+
regmap_read(rt1320->mbq_regmap, mc->reg, &lvalue);
1807
+
regmap_read(rt1320->mbq_regmap, mc->rreg, &rvalue);
1808
+
1809
+
/* L Channel */
1810
+
gain_l_val = ucontrol->value.integer.value[0];
1811
+
if (gain_l_val > mc->max)
1812
+
gain_l_val = mc->max;
1813
+
gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset);
1814
+
gain_l_val &= 0xffff;
1815
+
1816
+
/* R Channel */
1817
+
gain_r_val = ucontrol->value.integer.value[1];
1818
+
if (gain_r_val > mc->max)
1819
+
gain_r_val = mc->max;
1820
+
gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset);
1821
+
gain_r_val &= 0xffff;
1822
+
1823
+
if (lvalue == gain_l_val && rvalue == gain_r_val)
1824
+
return 0;
1825
+
1826
+
/* Lch*/
1827
+
regmap_write(rt1320->mbq_regmap, mc->reg, gain_l_val);
1828
+
/* Rch */
1829
+
regmap_write(rt1320->mbq_regmap, mc->rreg, gain_r_val);
1830
+
1831
+
regmap_read(rt1320->mbq_regmap, mc->reg, &read_l);
1832
+
regmap_read(rt1320->mbq_regmap, mc->rreg, &read_r);
1833
+
if (read_r == gain_r_val && read_l == gain_l_val)
1834
+
return 1;
1835
+
1836
+
return -EIO;
1837
+
}
1838
+
1839
+
static int rt1320_set_gain_get(struct snd_kcontrol *kcontrol,
1840
+
struct snd_ctl_elem_value *ucontrol)
1841
+
{
1842
+
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1843
+
struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
1844
+
struct soc_mixer_control *mc =
1845
+
(struct soc_mixer_control *)kcontrol->private_value;
1846
+
unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0;
1847
+
const unsigned int interval_offset = 0xc0;
1848
+
1849
+
regmap_read(rt1320->mbq_regmap, mc->reg, &read_l);
1850
+
regmap_read(rt1320->mbq_regmap, mc->rreg, &read_r);
1851
+
1852
+
ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset);
1853
+
1854
+
if (read_l != read_r)
1855
+
ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset);
1856
+
else
1857
+
ctl_r = ctl_l;
1858
+
1859
+
ucontrol->value.integer.value[0] = ctl_l;
1860
+
ucontrol->value.integer.value[1] = ctl_r;
1861
+
return 0;
1862
+
}
1863
+
1864
+
static const char * const rt1320_rx_data_ch_select[] = {
1865
+
"L,R",
1866
+
"R,L",
1867
+
"L,L",
1868
+
"R,R",
1869
+
"L,L+R",
1870
+
"R,L+R",
1871
+
"L+R,L",
1872
+
"L+R,R",
1873
+
"L+R,L+R",
1874
+
};
1875
+
1876
+
static SOC_ENUM_SINGLE_DECL(rt1320_rx_data_ch_enum,
1877
+
SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0,
1878
+
rt1320_rx_data_ch_select);
1879
+
1880
+
static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0);
1881
+
1882
+
static const struct snd_kcontrol_new rt1320_snd_controls[] = {
1883
+
SOC_DOUBLE_R_EXT_TLV("FU21 Playback Volume",
1884
+
SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01),
1885
+
SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02),
1886
+
0, 0x57, 0, rt1320_set_gain_get, rt1320_set_gain_put, out_vol_tlv),
1887
+
SOC_ENUM("RX Channel Select", rt1320_rx_data_ch_enum),
1888
+
};
1889
+
1890
+
static const struct snd_kcontrol_new rt1320_spk_l_dac =
1891
+
SOC_DAPM_SINGLE_AUTODISABLE("Switch",
1892
+
SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01),
1893
+
0, 1, 1);
1894
+
static const struct snd_kcontrol_new rt1320_spk_r_dac =
1895
+
SOC_DAPM_SINGLE_AUTODISABLE("Switch",
1896
+
SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02),
1897
+
0, 1, 1);
1898
+
1899
+
static const struct snd_soc_dapm_widget rt1320_dapm_widgets[] = {
1900
+
/* Audio Interface */
1901
+
SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0),
1902
+
SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0),
1903
+
1904
+
/* Digital Interface */
1905
+
SND_SOC_DAPM_PGA("FU21", SND_SOC_NOPM, 0, 0, NULL, 0),
1906
+
SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0,
1907
+
rt1320_pde23_event,
1908
+
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1909
+
1910
+
/* Output */
1911
+
SND_SOC_DAPM_SWITCH("OT23 L", SND_SOC_NOPM, 0, 0, &rt1320_spk_l_dac),
1912
+
SND_SOC_DAPM_SWITCH("OT23 R", SND_SOC_NOPM, 0, 0, &rt1320_spk_r_dac),
1913
+
SND_SOC_DAPM_OUTPUT("SPOL"),
1914
+
SND_SOC_DAPM_OUTPUT("SPOR"),
1915
+
1916
+
/* Input */
1917
+
SND_SOC_DAPM_PGA("AEC Data", SND_SOC_NOPM, 0, 0, NULL, 0),
1918
+
SND_SOC_DAPM_SIGGEN("AEC Gen"),
1919
+
};
1920
+
1921
+
static const struct snd_soc_dapm_route rt1320_dapm_routes[] = {
1922
+
{ "FU21", NULL, "DP1RX" },
1923
+
{ "FU21", NULL, "PDE 23" },
1924
+
{ "OT23 L", "Switch", "FU21" },
1925
+
{ "OT23 R", "Switch", "FU21" },
1926
+
{ "SPOL", NULL, "OT23 L" },
1927
+
{ "SPOR", NULL, "OT23 R" },
1928
+
1929
+
{ "AEC Data", NULL, "AEC Gen" },
1930
+
{ "DP4TX", NULL, "AEC Data" },
1931
+
};
1932
+
1933
+
static int rt1320_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
1934
+
int direction)
1935
+
{
1936
+
snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
1937
+
return 0;
1938
+
}
1939
+
1940
+
static void rt1320_sdw_shutdown(struct snd_pcm_substream *substream,
1941
+
struct snd_soc_dai *dai)
1942
+
{
1943
+
snd_soc_dai_set_dma_data(dai, substream, NULL);
1944
+
}
1945
+
1946
+
static int rt1320_sdw_hw_params(struct snd_pcm_substream *substream,
1947
+
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1948
+
{
1949
+
struct snd_soc_component *component = dai->component;
1950
+
struct rt1320_sdw_priv *rt1320 =
1951
+
snd_soc_component_get_drvdata(component);
1952
+
struct sdw_stream_config stream_config;
1953
+
struct sdw_port_config port_config;
1954
+
struct sdw_stream_runtime *sdw_stream;
1955
+
int retval;
1956
+
unsigned int sampling_rate;
1957
+
1958
+
dev_dbg(dai->dev, "%s %s", __func__, dai->name);
1959
+
sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
1960
+
1961
+
if (!sdw_stream)
1962
+
return -EINVAL;
1963
+
1964
+
if (!rt1320->sdw_slave)
1965
+
return -EINVAL;
1966
+
1967
+
/* SoundWire specific configuration */
1968
+
snd_sdw_params_to_config(substream, params, &stream_config, &port_config);
1969
+
1970
+
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1971
+
if (dai->id == RT1320_AIF1)
1972
+
port_config.num = 1;
1973
+
else
1974
+
return -EINVAL;
1975
+
} else {
1976
+
if (dai->id == RT1320_AIF1)
1977
+
port_config.num = 4;
1978
+
else
1979
+
return -EINVAL;
1980
+
}
1981
+
1982
+
retval = sdw_stream_add_slave(rt1320->sdw_slave, &stream_config,
1983
+
&port_config, 1, sdw_stream);
1984
+
if (retval) {
1985
+
dev_err(dai->dev, "%s: Unable to configure port\n", __func__);
1986
+
return retval;
1987
+
}
1988
+
1989
+
/* sampling rate configuration */
1990
+
switch (params_rate(params)) {
1991
+
case 16000:
1992
+
sampling_rate = RT1320_SDCA_RATE_16000HZ;
1993
+
break;
1994
+
case 32000:
1995
+
sampling_rate = RT1320_SDCA_RATE_32000HZ;
1996
+
break;
1997
+
case 44100:
1998
+
sampling_rate = RT1320_SDCA_RATE_44100HZ;
1999
+
break;
2000
+
case 48000:
2001
+
sampling_rate = RT1320_SDCA_RATE_48000HZ;
2002
+
break;
2003
+
case 96000:
2004
+
sampling_rate = RT1320_SDCA_RATE_96000HZ;
2005
+
break;
2006
+
case 192000:
2007
+
sampling_rate = RT1320_SDCA_RATE_192000HZ;
2008
+
break;
2009
+
default:
2010
+
dev_err(component->dev, "%s: Rate %d is not supported\n",
2011
+
__func__, params_rate(params));
2012
+
return -EINVAL;
2013
+
}
2014
+
2015
+
/* set sampling frequency */
2016
+
regmap_write(rt1320->regmap,
2017
+
SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
2018
+
sampling_rate);
2019
+
2020
+
return 0;
2021
+
}
2022
+
2023
+
static int rt1320_sdw_pcm_hw_free(struct snd_pcm_substream *substream,
2024
+
struct snd_soc_dai *dai)
2025
+
{
2026
+
struct snd_soc_component *component = dai->component;
2027
+
struct rt1320_sdw_priv *rt1320 =
2028
+
snd_soc_component_get_drvdata(component);
2029
+
struct sdw_stream_runtime *sdw_stream =
2030
+
snd_soc_dai_get_dma_data(dai, substream);
2031
+
2032
+
if (!rt1320->sdw_slave)
2033
+
return -EINVAL;
2034
+
2035
+
sdw_stream_remove_slave(rt1320->sdw_slave, sdw_stream);
2036
+
return 0;
2037
+
}
2038
+
2039
+
/*
2040
+
* slave_ops: callbacks for get_clock_stop_mode, clock_stop and
2041
+
* port_prep are not defined for now
2042
+
*/
2043
+
static const struct sdw_slave_ops rt1320_slave_ops = {
2044
+
.read_prop = rt1320_read_prop,
2045
+
.update_status = rt1320_update_status,
2046
+
};
2047
+
2048
+
static int rt1320_sdw_component_probe(struct snd_soc_component *component)
2049
+
{
2050
+
int ret;
2051
+
struct rt1320_sdw_priv *rt1320 = snd_soc_component_get_drvdata(component);
2052
+
2053
+
rt1320->component = component;
2054
+
2055
+
if (!rt1320->first_hw_init)
2056
+
return 0;
2057
+
2058
+
ret = pm_runtime_resume(component->dev);
2059
+
dev_dbg(&rt1320->sdw_slave->dev, "%s pm_runtime_resume, ret=%d", __func__, ret);
2060
+
if (ret < 0 && ret != -EACCES)
2061
+
return ret;
2062
+
2063
+
return 0;
2064
+
}
2065
+
2066
+
static const struct snd_soc_component_driver soc_component_sdw_rt1320 = {
2067
+
.probe = rt1320_sdw_component_probe,
2068
+
.controls = rt1320_snd_controls,
2069
+
.num_controls = ARRAY_SIZE(rt1320_snd_controls),
2070
+
.dapm_widgets = rt1320_dapm_widgets,
2071
+
.num_dapm_widgets = ARRAY_SIZE(rt1320_dapm_widgets),
2072
+
.dapm_routes = rt1320_dapm_routes,
2073
+
.num_dapm_routes = ARRAY_SIZE(rt1320_dapm_routes),
2074
+
.endianness = 1,
2075
+
};
2076
+
2077
+
static const struct snd_soc_dai_ops rt1320_aif_dai_ops = {
2078
+
.hw_params = rt1320_sdw_hw_params,
2079
+
.hw_free = rt1320_sdw_pcm_hw_free,
2080
+
.set_stream = rt1320_set_sdw_stream,
2081
+
.shutdown = rt1320_sdw_shutdown,
2082
+
};
2083
+
2084
+
#define RT1320_STEREO_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
2085
+
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
2086
+
#define RT1320_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
2087
+
SNDRV_PCM_FMTBIT_S32_LE)
2088
+
2089
+
static struct snd_soc_dai_driver rt1320_sdw_dai[] = {
2090
+
{
2091
+
.name = "rt1320-aif1",
2092
+
.id = RT1320_AIF1,
2093
+
.playback = {
2094
+
.stream_name = "DP1 Playback",
2095
+
.channels_min = 1,
2096
+
.channels_max = 2,
2097
+
.rates = RT1320_STEREO_RATES,
2098
+
.formats = RT1320_FORMATS,
2099
+
},
2100
+
.capture = {
2101
+
.stream_name = "DP4 Capture",
2102
+
.channels_min = 1,
2103
+
.channels_max = 2,
2104
+
.rates = RT1320_STEREO_RATES,
2105
+
.formats = RT1320_FORMATS,
2106
+
},
2107
+
.ops = &rt1320_aif_dai_ops,
2108
+
},
2109
+
};
2110
+
2111
+
static int rt1320_sdw_init(struct device *dev, struct regmap *regmap,
2112
+
struct regmap *mbq_regmap, struct sdw_slave *slave)
2113
+
{
2114
+
struct rt1320_sdw_priv *rt1320;
2115
+
int ret;
2116
+
2117
+
rt1320 = devm_kzalloc(dev, sizeof(*rt1320), GFP_KERNEL);
2118
+
if (!rt1320)
2119
+
return -ENOMEM;
2120
+
2121
+
dev_set_drvdata(dev, rt1320);
2122
+
rt1320->sdw_slave = slave;
2123
+
rt1320->mbq_regmap = mbq_regmap;
2124
+
rt1320->regmap = regmap;
2125
+
2126
+
regcache_cache_only(rt1320->regmap, true);
2127
+
regcache_cache_only(rt1320->mbq_regmap, true);
2128
+
2129
+
/*
2130
+
* Mark hw_init to false
2131
+
* HW init will be performed when device reports present
2132
+
*/
2133
+
rt1320->hw_init = false;
2134
+
rt1320->first_hw_init = false;
2135
+
rt1320->version_id = -1;
2136
+
2137
+
ret = devm_snd_soc_register_component(dev,
2138
+
&soc_component_sdw_rt1320,
2139
+
rt1320_sdw_dai,
2140
+
ARRAY_SIZE(rt1320_sdw_dai));
2141
+
if (ret < 0)
2142
+
return ret;
2143
+
2144
+
/* set autosuspend parameters */
2145
+
pm_runtime_set_autosuspend_delay(dev, 3000);
2146
+
pm_runtime_use_autosuspend(dev);
2147
+
2148
+
/* make sure the device does not suspend immediately */
2149
+
pm_runtime_mark_last_busy(dev);
2150
+
2151
+
pm_runtime_enable(dev);
2152
+
2153
+
/* important note: the device is NOT tagged as 'active' and will remain
2154
+
* 'suspended' until the hardware is enumerated/initialized. This is required
2155
+
* to make sure the ASoC framework use of pm_runtime_get_sync() does not silently
2156
+
* fail with -EACCESS because of race conditions between card creation and enumeration
2157
+
*/
2158
+
2159
+
dev_dbg(dev, "%s\n", __func__);
2160
+
2161
+
return ret;
2162
+
}
2163
+
2164
+
static int rt1320_sdw_probe(struct sdw_slave *slave,
2165
+
const struct sdw_device_id *id)
2166
+
{
2167
+
struct regmap *regmap, *mbq_regmap;
2168
+
2169
+
/* Regmap Initialization */
2170
+
mbq_regmap = devm_regmap_init_sdw_mbq(slave, &rt1320_mbq_regmap);
2171
+
if (IS_ERR(mbq_regmap))
2172
+
return PTR_ERR(mbq_regmap);
2173
+
2174
+
regmap = devm_regmap_init_sdw(slave, &rt1320_sdw_regmap);
2175
+
if (IS_ERR(regmap))
2176
+
return PTR_ERR(regmap);
2177
+
2178
+
return rt1320_sdw_init(&slave->dev, regmap, mbq_regmap, slave);
2179
+
}
2180
+
2181
+
static int rt1320_sdw_remove(struct sdw_slave *slave)
2182
+
{
2183
+
pm_runtime_disable(&slave->dev);
2184
+
2185
+
return 0;
2186
+
}
2187
+
2188
+
/*
2189
+
* Version A/B will use the class id 0
2190
+
* The newer version than A/B will use the class id 1, so add it in advance
2191
+
*/
2192
+
static const struct sdw_device_id rt1320_id[] = {
2193
+
SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x0, 0),
2194
+
SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x1, 0),
2195
+
{},
2196
+
};
2197
+
MODULE_DEVICE_TABLE(sdw, rt1320_id);
2198
+
2199
+
static int __maybe_unused rt1320_dev_suspend(struct device *dev)
2200
+
{
2201
+
struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev);
2202
+
2203
+
if (!rt1320->hw_init)
2204
+
return 0;
2205
+
2206
+
regcache_cache_only(rt1320->regmap, true);
2207
+
regcache_cache_only(rt1320->mbq_regmap, true);
2208
+
return 0;
2209
+
}
2210
+
2211
+
#define RT1320_PROBE_TIMEOUT 5000
2212
+
2213
+
static int __maybe_unused rt1320_dev_resume(struct device *dev)
2214
+
{
2215
+
struct sdw_slave *slave = dev_to_sdw_dev(dev);
2216
+
struct rt1320_sdw_priv *rt1320 = dev_get_drvdata(dev);
2217
+
unsigned long time;
2218
+
2219
+
if (!rt1320->first_hw_init)
2220
+
return 0;
2221
+
2222
+
if (!slave->unattach_request)
2223
+
goto regmap_sync;
2224
+
2225
+
time = wait_for_completion_timeout(&slave->initialization_complete,
2226
+
msecs_to_jiffies(RT1320_PROBE_TIMEOUT));
2227
+
if (!time) {
2228
+
dev_err(&slave->dev, "%s: Initialization not complete, timed out\n", __func__);
2229
+
return -ETIMEDOUT;
2230
+
}
2231
+
2232
+
regmap_sync:
2233
+
slave->unattach_request = 0;
2234
+
regcache_cache_only(rt1320->regmap, false);
2235
+
regcache_sync(rt1320->regmap);
2236
+
regcache_cache_only(rt1320->mbq_regmap, false);
2237
+
regcache_sync(rt1320->mbq_regmap);
2238
+
return 0;
2239
+
}
2240
+
2241
+
static const struct dev_pm_ops rt1320_pm = {
2242
+
SET_SYSTEM_SLEEP_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume)
2243
+
SET_RUNTIME_PM_OPS(rt1320_dev_suspend, rt1320_dev_resume, NULL)
2244
+
};
2245
+
2246
+
static struct sdw_driver rt1320_sdw_driver = {
2247
+
.driver = {
2248
+
.name = "rt1320-sdca",
2249
+
.pm = &rt1320_pm,
2250
+
},
2251
+
.probe = rt1320_sdw_probe,
2252
+
.remove = rt1320_sdw_remove,
2253
+
.ops = &rt1320_slave_ops,
2254
+
.id_table = rt1320_id,
2255
+
};
2256
+
module_sdw_driver(rt1320_sdw_driver);
2257
+
2258
+
MODULE_DESCRIPTION("ASoC RT1320 driver SDCA SDW");
2259
+
MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
2260
+
MODULE_LICENSE("GPL");
+94
sound/soc/codecs/rt1320-sdw.h
+94
sound/soc/codecs/rt1320-sdw.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* rt1320-sdw.h -- RT1320 SDCA ALSA SoC audio driver header
4
+
*
5
+
* Copyright(c) 2024 Realtek Semiconductor Corp.
6
+
*/
7
+
8
+
#ifndef __RT1320_SDW_H__
9
+
#define __RT1320_SDW_H__
10
+
11
+
#include <linux/regmap.h>
12
+
#include <linux/soundwire/sdw.h>
13
+
#include <linux/soundwire/sdw_type.h>
14
+
#include <linux/soundwire/sdw_registers.h>
15
+
#include <sound/soc.h>
16
+
17
+
/* imp-defined registers */
18
+
#define RT1320_DEV_VERSION_ID_1 0xc404
19
+
20
+
#define RT1320_KR0_STATUS_CNT 0x1000f008
21
+
#define RT1320_HIFI_VER_0 0x3fe2e000
22
+
#define RT1320_HIFI_VER_1 0x3fe2e001
23
+
#define RT1320_HIFI_VER_2 0x3fe2e002
24
+
#define RT1320_HIFI_VER_3 0x3fe2e003
25
+
26
+
/* RT1320 SDCA Control - function number */
27
+
#define FUNC_NUM_AMP 0x04
28
+
29
+
/* RT1320 SDCA entity */
30
+
#define RT1320_SDCA_ENT0 0x00
31
+
#define RT1320_SDCA_ENT_PDE11 0x2a
32
+
#define RT1320_SDCA_ENT_PDE23 0x33
33
+
#define RT1320_SDCA_ENT_PDE27 0x27
34
+
#define RT1320_SDCA_ENT_FU14 0x32
35
+
#define RT1320_SDCA_ENT_FU21 0x03
36
+
#define RT1320_SDCA_ENT_FU113 0x30
37
+
#define RT1320_SDCA_ENT_CS14 0x13
38
+
#define RT1320_SDCA_ENT_CS21 0x21
39
+
#define RT1320_SDCA_ENT_CS113 0x12
40
+
#define RT1320_SDCA_ENT_SAPU 0x29
41
+
#define RT1320_SDCA_ENT_PPU21 0x04
42
+
43
+
/* RT1320 SDCA control */
44
+
#define RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX 0x10
45
+
#define RT1320_SDCA_CTL_REQ_POWER_STATE 0x01
46
+
#define RT1320_SDCA_CTL_FU_MUTE 0x01
47
+
#define RT1320_SDCA_CTL_FU_VOLUME 0x02
48
+
#define RT1320_SDCA_CTL_SAPU_PROTECTION_MODE 0x10
49
+
#define RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS 0x11
50
+
#define RT1320_SDCA_CTL_POSTURE_NUMBER 0x10
51
+
#define RT1320_SDCA_CTL_FUNC_STATUS 0x10
52
+
53
+
/* RT1320 SDCA channel */
54
+
#define CH_01 0x01
55
+
#define CH_02 0x02
56
+
57
+
/* Function_Status */
58
+
#define FUNCTION_NEEDS_INITIALIZATION BIT(5)
59
+
60
+
/* Sample Frequency Index */
61
+
#define RT1320_SDCA_RATE_16000HZ 0x04
62
+
#define RT1320_SDCA_RATE_32000HZ 0x07
63
+
#define RT1320_SDCA_RATE_44100HZ 0x08
64
+
#define RT1320_SDCA_RATE_48000HZ 0x09
65
+
#define RT1320_SDCA_RATE_96000HZ 0x0b
66
+
#define RT1320_SDCA_RATE_192000HZ 0x0d
67
+
68
+
enum {
69
+
RT1320_AIF1,
70
+
};
71
+
72
+
/*
73
+
* The version id will be useful to distinguish the capability between the different IC versions.
74
+
* Currently, VA and VB have different DSP FW versions.
75
+
*/
76
+
enum rt1320_version_id {
77
+
RT1320_VA,
78
+
RT1320_VB,
79
+
};
80
+
81
+
#define RT1320_VER_B_ID 0x07392238
82
+
83
+
struct rt1320_sdw_priv {
84
+
struct snd_soc_component *component;
85
+
struct regmap *regmap;
86
+
struct regmap *mbq_regmap;
87
+
struct sdw_slave *sdw_slave;
88
+
struct sdw_bus_params params;
89
+
bool hw_init;
90
+
bool first_hw_init;
91
+
int version_id;
92
+
};
93
+
94
+
#endif /* __RT1320_SDW_H__ */