tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-for-v4.16-rc2' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie:
"One nouveau regression fix, one AMD quirk and a full set of i915
fixes.

The i915 fixes are mostly for things caught by their CI system, main
ones being DSI panel fixes and GEM fixes"

* tag 'drm-fixes-for-v4.16-rc2' of git://people.freedesktop.org/~airlied/linux:
drm/nouveau: Make clock gate support conditional
drm/i915: Fix DSI panels with v1 MIPI sequences without a DEASSERT sequence v3
drm/i915: Free memdup-ed DSI VBT data structures on driver_unload
drm/i915: Add intel_bios_cleanup() function
drm/i915/vlv: Add cdclk workaround for DSI
drm/i915/gvt: fix one typo of render_mmio trace
drm/i915/gvt: Support BAR0 8-byte reads/writes
drm/i915/gvt: add 0xe4f0 into gen9 render list
drm/i915/pmu: Fix building without CONFIG_PM
drm/i915/pmu: Fix sleep under atomic in RC6 readout
drm/i915/pmu: Fix PMU enable vs execlists tasklet race
drm/i915: Lock out execlist tasklet while peeking inside for busy-stats
drm/i915/breadcrumbs: Ignore unsubmitted signalers
drm/i915: Don't wake the device up to check if the engine is asleep
drm/i915: Avoid truncation before clamping userspace's priority value
drm/i915/perf: Fix compiler warning for string truncation
drm/i915/perf: Fix compiler warning for string truncation
drm/amdgpu: add new device to use atpx quirk

Linus Torvalds bad57539 b63b1e57

+352 -156
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
··· 568 568 /* HG _PR3 doesn't seem to work on this A+A weston board */ 569 569 { 0x1002, 0x6900, 0x1002, 0x0124, AMDGPU_PX_QUIRK_FORCE_ATPX }, 570 570 { 0x1002, 0x6900, 0x1028, 0x0812, AMDGPU_PX_QUIRK_FORCE_ATPX }, 571 + { 0x1002, 0x6900, 0x1028, 0x0813, AMDGPU_PX_QUIRK_FORCE_ATPX }, 571 572 { 0, 0, 0, 0, 0 }, 572 573 }; 573 574
+49 -2
drivers/gpu/drm/i915/gvt/kvmgt.c
··· 733 733 return ret == 0 ? count : ret; 734 734 } 735 735 736 + static bool gtt_entry(struct mdev_device *mdev, loff_t *ppos) 737 + { 738 + struct intel_vgpu *vgpu = mdev_get_drvdata(mdev); 739 + unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos); 740 + struct intel_gvt *gvt = vgpu->gvt; 741 + int offset; 742 + 743 + /* Only allow MMIO GGTT entry access */ 744 + if (index != PCI_BASE_ADDRESS_0) 745 + return false; 746 + 747 + offset = (u64)(*ppos & VFIO_PCI_OFFSET_MASK) - 748 + intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0); 749 + 750 + return (offset >= gvt->device_info.gtt_start_offset && 751 + offset < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt)) ? 752 + true : false; 753 + } 754 + 736 755 static ssize_t intel_vgpu_read(struct mdev_device *mdev, char __user *buf, 737 756 size_t count, loff_t *ppos) 738 757 { ··· 761 742 while (count) { 762 743 size_t filled; 763 744 764 - if (count >= 4 && !(*ppos % 4)) { 745 + /* Only support GGTT entry 8 bytes read */ 746 + if (count >= 8 && !(*ppos % 8) && 747 + gtt_entry(mdev, ppos)) { 748 + u64 val; 749 + 750 + ret = intel_vgpu_rw(mdev, (char *)&val, sizeof(val), 751 + ppos, false); 752 + if (ret <= 0) 753 + goto read_err; 754 + 755 + if (copy_to_user(buf, &val, sizeof(val))) 756 + goto read_err; 757 + 758 + filled = 8; 759 + } else if (count >= 4 && !(*ppos % 4)) { 765 760 u32 val; 766 761 767 762 ret = intel_vgpu_rw(mdev, (char *)&val, sizeof(val), ··· 835 802 while (count) { 836 803 size_t filled; 837 804 838 - if (count >= 4 && !(*ppos % 4)) { 805 + /* Only support GGTT entry 8 bytes write */ 806 + if (count >= 8 && !(*ppos % 8) && 807 + gtt_entry(mdev, ppos)) { 808 + u64 val; 809 + 810 + if (copy_from_user(&val, buf, sizeof(val))) 811 + goto write_err; 812 + 813 + ret = intel_vgpu_rw(mdev, (char *)&val, sizeof(val), 814 + ppos, true); 815 + if (ret <= 0) 816 + goto write_err; 817 + 818 + filled = 8; 819 + } else if (count >= 4 && !(*ppos % 4)) { 839 820 u32 val; 840 821 841 822 if (copy_from_user(&val, buf, sizeof(val)))
+1
drivers/gpu/drm/i915/gvt/mmio_context.c
··· 118 118 {RCS, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */ 119 119 {RCS, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */ 120 120 {RCS, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */ 121 + {RCS, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */ 121 122 {RCS, TRVATTL3PTRDW(0), 0, false}, /* 0x4de0 */ 122 123 {RCS, TRVATTL3PTRDW(1), 0, false}, /* 0x4de4 */ 123 124 {RCS, TRNULLDETCT, 0, false}, /* 0x4de8 */
+1 -1
drivers/gpu/drm/i915/gvt/trace.h
··· 333 333 TP_PROTO(int old_id, int new_id, char *action, unsigned int reg, 334 334 unsigned int old_val, unsigned int new_val), 335 335 336 - TP_ARGS(old_id, new_id, action, reg, new_val, old_val), 336 + TP_ARGS(old_id, new_id, action, reg, old_val, new_val), 337 337 338 338 TP_STRUCT__entry( 339 339 __field(int, old_id)
+1 -13
drivers/gpu/drm/i915/i915_drv.c
··· 1433 1433 1434 1434 intel_modeset_cleanup(dev); 1435 1435 1436 - /* 1437 - * free the memory space allocated for the child device 1438 - * config parsed from VBT 1439 - */ 1440 - if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) { 1441 - kfree(dev_priv->vbt.child_dev); 1442 - dev_priv->vbt.child_dev = NULL; 1443 - dev_priv->vbt.child_dev_num = 0; 1444 - } 1445 - kfree(dev_priv->vbt.sdvo_lvds_vbt_mode); 1446 - dev_priv->vbt.sdvo_lvds_vbt_mode = NULL; 1447 - kfree(dev_priv->vbt.lfp_lvds_vbt_mode); 1448 - dev_priv->vbt.lfp_lvds_vbt_mode = NULL; 1436 + intel_bios_cleanup(dev_priv); 1449 1437 1450 1438 vga_switcheroo_unregister_client(pdev); 1451 1439 vga_client_register(pdev, NULL, NULL, NULL);
+2
drivers/gpu/drm/i915/i915_drv.h
··· 1349 1349 u32 size; 1350 1350 u8 *data; 1351 1351 const u8 *sequence[MIPI_SEQ_MAX]; 1352 + u8 *deassert_seq; /* Used by fixup_mipi_sequences() */ 1352 1353 } dsi; 1353 1354 1354 1355 int crt_ddc_pin; ··· 3658 3657 3659 3658 /* intel_bios.c */ 3660 3659 void intel_bios_init(struct drm_i915_private *dev_priv); 3660 + void intel_bios_cleanup(struct drm_i915_private *dev_priv); 3661 3661 bool intel_bios_is_valid_vbt(const void *buf, size_t size); 3662 3662 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv); 3663 3663 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
+1 -1
drivers/gpu/drm/i915/i915_gem_context.c
··· 803 803 804 804 case I915_CONTEXT_PARAM_PRIORITY: 805 805 { 806 - int priority = args->value; 806 + s64 priority = args->value; 807 807 808 808 if (args->size) 809 809 ret = -EINVAL;
+2 -2
drivers/gpu/drm/i915/i915_oa_cflgt3.c
··· 84 84 void 85 85 i915_perf_load_test_config_cflgt3(struct drm_i915_private *dev_priv) 86 86 { 87 - strncpy(dev_priv->perf.oa.test_config.uuid, 87 + strlcpy(dev_priv->perf.oa.test_config.uuid, 88 88 "577e8e2c-3fa0-4875-8743-3538d585e3b0", 89 - UUID_STRING_LEN); 89 + sizeof(dev_priv->perf.oa.test_config.uuid)); 90 90 dev_priv->perf.oa.test_config.id = 1; 91 91 92 92 dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
+2 -2
drivers/gpu/drm/i915/i915_oa_cnl.c
··· 96 96 void 97 97 i915_perf_load_test_config_cnl(struct drm_i915_private *dev_priv) 98 98 { 99 - strncpy(dev_priv->perf.oa.test_config.uuid, 99 + strlcpy(dev_priv->perf.oa.test_config.uuid, 100 100 "db41edd4-d8e7-4730-ad11-b9a2d6833503", 101 - UUID_STRING_LEN); 101 + sizeof(dev_priv->perf.oa.test_config.uuid)); 102 102 dev_priv->perf.oa.test_config.id = 1; 103 103 104 104 dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
+144 -89
drivers/gpu/drm/i915/i915_pmu.c
··· 285 285 return sum; 286 286 } 287 287 288 - static void i915_pmu_event_destroy(struct perf_event *event) 289 - { 290 - WARN_ON(event->parent); 291 - } 292 - 293 - static int engine_event_init(struct perf_event *event) 288 + static void engine_event_destroy(struct perf_event *event) 294 289 { 295 290 struct drm_i915_private *i915 = 296 291 container_of(event->pmu, typeof(*i915), pmu.base); 292 + struct intel_engine_cs *engine; 297 293 298 - if (!intel_engine_lookup_user(i915, engine_event_class(event), 299 - engine_event_instance(event))) 300 - return -ENODEV; 294 + engine = intel_engine_lookup_user(i915, 295 + engine_event_class(event), 296 + engine_event_instance(event)); 297 + if (WARN_ON_ONCE(!engine)) 298 + return; 301 299 302 - switch (engine_event_sample(event)) { 300 + if (engine_event_sample(event) == I915_SAMPLE_BUSY && 301 + intel_engine_supports_stats(engine)) 302 + intel_disable_engine_stats(engine); 303 + } 304 + 305 + static void i915_pmu_event_destroy(struct perf_event *event) 306 + { 307 + WARN_ON(event->parent); 308 + 309 + if (is_engine_event(event)) 310 + engine_event_destroy(event); 311 + } 312 + 313 + static int 314 + engine_event_status(struct intel_engine_cs *engine, 315 + enum drm_i915_pmu_engine_sample sample) 316 + { 317 + switch (sample) { 303 318 case I915_SAMPLE_BUSY: 304 319 case I915_SAMPLE_WAIT: 305 320 break; 306 321 case I915_SAMPLE_SEMA: 307 - if (INTEL_GEN(i915) < 6) 322 + if (INTEL_GEN(engine->i915) < 6) 308 323 return -ENODEV; 309 324 break; 310 325 default: ··· 327 312 } 328 313 329 314 return 0; 315 + } 316 + 317 + static int engine_event_init(struct perf_event *event) 318 + { 319 + struct drm_i915_private *i915 = 320 + container_of(event->pmu, typeof(*i915), pmu.base); 321 + struct intel_engine_cs *engine; 322 + u8 sample; 323 + int ret; 324 + 325 + engine = intel_engine_lookup_user(i915, engine_event_class(event), 326 + engine_event_instance(event)); 327 + if (!engine) 328 + return -ENODEV; 329 + 330 + sample = engine_event_sample(event); 331 + ret = engine_event_status(engine, sample); 332 + if (ret) 333 + return ret; 334 + 335 + if (sample == I915_SAMPLE_BUSY && intel_engine_supports_stats(engine)) 336 + ret = intel_enable_engine_stats(engine); 337 + 338 + return ret; 330 339 } 331 340 332 341 static int i915_pmu_event_init(struct perf_event *event) ··· 409 370 return 0; 410 371 } 411 372 412 - static u64 __i915_pmu_event_read(struct perf_event *event) 373 + static u64 __get_rc6(struct drm_i915_private *i915) 374 + { 375 + u64 val; 376 + 377 + val = intel_rc6_residency_ns(i915, 378 + IS_VALLEYVIEW(i915) ? 379 + VLV_GT_RENDER_RC6 : 380 + GEN6_GT_GFX_RC6); 381 + 382 + if (HAS_RC6p(i915)) 383 + val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p); 384 + 385 + if (HAS_RC6pp(i915)) 386 + val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp); 387 + 388 + return val; 389 + } 390 + 391 + static u64 get_rc6(struct drm_i915_private *i915, bool locked) 392 + { 393 + #if IS_ENABLED(CONFIG_PM) 394 + unsigned long flags; 395 + u64 val; 396 + 397 + if (intel_runtime_pm_get_if_in_use(i915)) { 398 + val = __get_rc6(i915); 399 + intel_runtime_pm_put(i915); 400 + 401 + /* 402 + * If we are coming back from being runtime suspended we must 403 + * be careful not to report a larger value than returned 404 + * previously. 405 + */ 406 + 407 + if (!locked) 408 + spin_lock_irqsave(&i915->pmu.lock, flags); 409 + 410 + if (val >= i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur) { 411 + i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur = 0; 412 + i915->pmu.sample[__I915_SAMPLE_RC6].cur = val; 413 + } else { 414 + val = i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur; 415 + } 416 + 417 + if (!locked) 418 + spin_unlock_irqrestore(&i915->pmu.lock, flags); 419 + } else { 420 + struct pci_dev *pdev = i915->drm.pdev; 421 + struct device *kdev = &pdev->dev; 422 + unsigned long flags2; 423 + 424 + /* 425 + * We are runtime suspended. 426 + * 427 + * Report the delta from when the device was suspended to now, 428 + * on top of the last known real value, as the approximated RC6 429 + * counter value. 430 + */ 431 + if (!locked) 432 + spin_lock_irqsave(&i915->pmu.lock, flags); 433 + 434 + spin_lock_irqsave(&kdev->power.lock, flags2); 435 + 436 + if (!i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur) 437 + i915->pmu.suspended_jiffies_last = 438 + kdev->power.suspended_jiffies; 439 + 440 + val = kdev->power.suspended_jiffies - 441 + i915->pmu.suspended_jiffies_last; 442 + val += jiffies - kdev->power.accounting_timestamp; 443 + 444 + spin_unlock_irqrestore(&kdev->power.lock, flags2); 445 + 446 + val = jiffies_to_nsecs(val); 447 + val += i915->pmu.sample[__I915_SAMPLE_RC6].cur; 448 + i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur = val; 449 + 450 + if (!locked) 451 + spin_unlock_irqrestore(&i915->pmu.lock, flags); 452 + } 453 + 454 + return val; 455 + #else 456 + return __get_rc6(i915); 457 + #endif 458 + } 459 + 460 + static u64 __i915_pmu_event_read(struct perf_event *event, bool locked) 413 461 { 414 462 struct drm_i915_private *i915 = 415 463 container_of(event->pmu, typeof(*i915), pmu.base); ··· 513 387 if (WARN_ON_ONCE(!engine)) { 514 388 /* Do nothing */ 515 389 } else if (sample == I915_SAMPLE_BUSY && 516 - engine->pmu.busy_stats) { 390 + intel_engine_supports_stats(engine)) { 517 391 val = ktime_to_ns(intel_engine_get_busy_time(engine)); 518 392 } else { 519 393 val = engine->pmu.sample[sample].cur; ··· 534 408 val = count_interrupts(i915); 535 409 break; 536 410 case I915_PMU_RC6_RESIDENCY: 537 - intel_runtime_pm_get(i915); 538 - val = intel_rc6_residency_ns(i915, 539 - IS_VALLEYVIEW(i915) ? 540 - VLV_GT_RENDER_RC6 : 541 - GEN6_GT_GFX_RC6); 542 - if (HAS_RC6p(i915)) 543 - val += intel_rc6_residency_ns(i915, 544 - GEN6_GT_GFX_RC6p); 545 - if (HAS_RC6pp(i915)) 546 - val += intel_rc6_residency_ns(i915, 547 - GEN6_GT_GFX_RC6pp); 548 - intel_runtime_pm_put(i915); 411 + val = get_rc6(i915, locked); 549 412 break; 550 413 } 551 414 } ··· 549 434 550 435 again: 551 436 prev = local64_read(&hwc->prev_count); 552 - new = __i915_pmu_event_read(event); 437 + new = __i915_pmu_event_read(event, false); 553 438 554 439 if (local64_cmpxchg(&hwc->prev_count, prev, new) != prev) 555 440 goto again; 556 441 557 442 local64_add(new - prev, &event->count); 558 - } 559 - 560 - static bool engine_needs_busy_stats(struct intel_engine_cs *engine) 561 - { 562 - return intel_engine_supports_stats(engine) && 563 - (engine->pmu.enable & BIT(I915_SAMPLE_BUSY)); 564 443 } 565 444 566 445 static void i915_pmu_enable(struct perf_event *event) ··· 596 487 597 488 GEM_BUG_ON(sample >= I915_PMU_SAMPLE_BITS); 598 489 GEM_BUG_ON(engine->pmu.enable_count[sample] == ~0); 599 - if (engine->pmu.enable_count[sample]++ == 0) { 600 - /* 601 - * Enable engine busy stats tracking if needed or 602 - * alternatively cancel the scheduled disable. 603 - * 604 - * If the delayed disable was pending, cancel it and 605 - * in this case do not enable since it already is. 606 - */ 607 - if (engine_needs_busy_stats(engine) && 608 - !engine->pmu.busy_stats) { 609 - engine->pmu.busy_stats = true; 610 - if (!cancel_delayed_work(&engine->pmu.disable_busy_stats)) 611 - intel_enable_engine_stats(engine); 612 - } 613 - } 490 + engine->pmu.enable_count[sample]++; 614 491 } 615 492 616 493 /* ··· 604 509 * for all listeners. Even when the event was already enabled and has 605 510 * an existing non-zero value. 606 511 */ 607 - local64_set(&event->hw.prev_count, __i915_pmu_event_read(event)); 512 + local64_set(&event->hw.prev_count, __i915_pmu_event_read(event, true)); 608 513 609 514 spin_unlock_irqrestore(&i915->pmu.lock, flags); 610 - } 611 - 612 - static void __disable_busy_stats(struct work_struct *work) 613 - { 614 - struct intel_engine_cs *engine = 615 - container_of(work, typeof(*engine), pmu.disable_busy_stats.work); 616 - 617 - intel_disable_engine_stats(engine); 618 515 } 619 516 620 517 static void i915_pmu_disable(struct perf_event *event) ··· 632 545 * Decrement the reference count and clear the enabled 633 546 * bitmask when the last listener on an event goes away. 634 547 */ 635 - if (--engine->pmu.enable_count[sample] == 0) { 548 + if (--engine->pmu.enable_count[sample] == 0) 636 549 engine->pmu.enable &= ~BIT(sample); 637 - if (!engine_needs_busy_stats(engine) && 638 - engine->pmu.busy_stats) { 639 - engine->pmu.busy_stats = false; 640 - /* 641 - * We request a delayed disable to handle the 642 - * rapid on/off cycles on events, which can 643 - * happen when tools like perf stat start, in a 644 - * nicer way. 645 - * 646 - * In addition, this also helps with busy stats 647 - * accuracy with background CPU offline/online 648 - * migration events. 649 - */ 650 - queue_delayed_work(system_wq, 651 - &engine->pmu.disable_busy_stats, 652 - round_jiffies_up_relative(HZ)); 653 - } 654 - } 655 550 } 656 551 657 552 GEM_BUG_ON(bit >= I915_PMU_MASK_BITS); ··· 866 797 867 798 void i915_pmu_register(struct drm_i915_private *i915) 868 799 { 869 - struct intel_engine_cs *engine; 870 - enum intel_engine_id id; 871 800 int ret; 872 801 873 802 if (INTEL_GEN(i915) <= 2) { ··· 887 820 hrtimer_init(&i915->pmu.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 888 821 i915->pmu.timer.function = i915_sample; 889 822 890 - for_each_engine(engine, i915, id) 891 - INIT_DELAYED_WORK(&engine->pmu.disable_busy_stats, 892 - __disable_busy_stats); 893 - 894 823 ret = perf_pmu_register(&i915->pmu.base, "i915", -1); 895 824 if (ret) 896 825 goto err; ··· 906 843 907 844 void i915_pmu_unregister(struct drm_i915_private *i915) 908 845 { 909 - struct intel_engine_cs *engine; 910 - enum intel_engine_id id; 911 - 912 846 if (!i915->pmu.base.event_init) 913 847 return; 914 848 915 849 WARN_ON(i915->pmu.enable); 916 850 917 851 hrtimer_cancel(&i915->pmu.timer); 918 - 919 - for_each_engine(engine, i915, id) { 920 - GEM_BUG_ON(engine->pmu.busy_stats); 921 - flush_delayed_work(&engine->pmu.disable_busy_stats); 922 - } 923 852 924 853 i915_pmu_unregister_cpuhp_state(i915); 925 854
+6
drivers/gpu/drm/i915/i915_pmu.h
··· 27 27 enum { 28 28 __I915_SAMPLE_FREQ_ACT = 0, 29 29 __I915_SAMPLE_FREQ_REQ, 30 + __I915_SAMPLE_RC6, 31 + __I915_SAMPLE_RC6_ESTIMATED, 30 32 __I915_NUM_PMU_SAMPLERS 31 33 }; 32 34 ··· 96 94 * struct intel_engine_cs. 97 95 */ 98 96 struct i915_pmu_sample sample[__I915_NUM_PMU_SAMPLERS]; 97 + /** 98 + * @suspended_jiffies_last: Cached suspend time from PM core. 99 + */ 100 + unsigned long suspended_jiffies_last; 99 101 }; 100 102 101 103 #ifdef CONFIG_PERF_EVENTS
+105
drivers/gpu/drm/i915/intel_bios.c
··· 947 947 return 0; 948 948 } 949 949 950 + /* 951 + * Get len of pre-fixed deassert fragment from a v1 init OTP sequence, 952 + * skip all delay + gpio operands and stop at the first DSI packet op. 953 + */ 954 + static int get_init_otp_deassert_fragment_len(struct drm_i915_private *dev_priv) 955 + { 956 + const u8 *data = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP]; 957 + int index, len; 958 + 959 + if (WARN_ON(!data || dev_priv->vbt.dsi.seq_version != 1)) 960 + return 0; 961 + 962 + /* index = 1 to skip sequence byte */ 963 + for (index = 1; data[index] != MIPI_SEQ_ELEM_END; index += len) { 964 + switch (data[index]) { 965 + case MIPI_SEQ_ELEM_SEND_PKT: 966 + return index == 1 ? 0 : index; 967 + case MIPI_SEQ_ELEM_DELAY: 968 + len = 5; /* 1 byte for operand + uint32 */ 969 + break; 970 + case MIPI_SEQ_ELEM_GPIO: 971 + len = 3; /* 1 byte for op, 1 for gpio_nr, 1 for value */ 972 + break; 973 + default: 974 + return 0; 975 + } 976 + } 977 + 978 + return 0; 979 + } 980 + 981 + /* 982 + * Some v1 VBT MIPI sequences do the deassert in the init OTP sequence. 983 + * The deassert must be done before calling intel_dsi_device_ready, so for 984 + * these devices we split the init OTP sequence into a deassert sequence and 985 + * the actual init OTP part. 986 + */ 987 + static void fixup_mipi_sequences(struct drm_i915_private *dev_priv) 988 + { 989 + u8 *init_otp; 990 + int len; 991 + 992 + /* Limit this to VLV for now. */ 993 + if (!IS_VALLEYVIEW(dev_priv)) 994 + return; 995 + 996 + /* Limit this to v1 vid-mode sequences */ 997 + if (dev_priv->vbt.dsi.config->is_cmd_mode || 998 + dev_priv->vbt.dsi.seq_version != 1) 999 + return; 1000 + 1001 + /* Only do this if there are otp and assert seqs and no deassert seq */ 1002 + if (!dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] || 1003 + !dev_priv->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET] || 1004 + dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET]) 1005 + return; 1006 + 1007 + /* The deassert-sequence ends at the first DSI packet */ 1008 + len = get_init_otp_deassert_fragment_len(dev_priv); 1009 + if (!len) 1010 + return; 1011 + 1012 + DRM_DEBUG_KMS("Using init OTP fragment to deassert reset\n"); 1013 + 1014 + /* Copy the fragment, update seq byte and terminate it */ 1015 + init_otp = (u8 *)dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP]; 1016 + dev_priv->vbt.dsi.deassert_seq = kmemdup(init_otp, len + 1, GFP_KERNEL); 1017 + if (!dev_priv->vbt.dsi.deassert_seq) 1018 + return; 1019 + dev_priv->vbt.dsi.deassert_seq[0] = MIPI_SEQ_DEASSERT_RESET; 1020 + dev_priv->vbt.dsi.deassert_seq[len] = MIPI_SEQ_ELEM_END; 1021 + /* Use the copy for deassert */ 1022 + dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET] = 1023 + dev_priv->vbt.dsi.deassert_seq; 1024 + /* Replace the last byte of the fragment with init OTP seq byte */ 1025 + init_otp[len - 1] = MIPI_SEQ_INIT_OTP; 1026 + /* And make MIPI_MIPI_SEQ_INIT_OTP point to it */ 1027 + dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] = init_otp + len - 1; 1028 + } 1029 + 950 1030 static void 951 1031 parse_mipi_sequence(struct drm_i915_private *dev_priv, 952 1032 const struct bdb_header *bdb) ··· 1095 1015 dev_priv->vbt.dsi.data = data; 1096 1016 dev_priv->vbt.dsi.size = seq_size; 1097 1017 dev_priv->vbt.dsi.seq_version = sequence->version; 1018 + 1019 + fixup_mipi_sequences(dev_priv); 1098 1020 1099 1021 DRM_DEBUG_DRIVER("MIPI related VBT parsing complete\n"); 1100 1022 return; ··· 1668 1586 1669 1587 if (bios) 1670 1588 pci_unmap_rom(pdev, bios); 1589 + } 1590 + 1591 + /** 1592 + * intel_bios_cleanup - Free any resources allocated by intel_bios_init() 1593 + * @dev_priv: i915 device instance 1594 + */ 1595 + void intel_bios_cleanup(struct drm_i915_private *dev_priv) 1596 + { 1597 + kfree(dev_priv->vbt.child_dev); 1598 + dev_priv->vbt.child_dev = NULL; 1599 + dev_priv->vbt.child_dev_num = 0; 1600 + kfree(dev_priv->vbt.sdvo_lvds_vbt_mode); 1601 + dev_priv->vbt.sdvo_lvds_vbt_mode = NULL; 1602 + kfree(dev_priv->vbt.lfp_lvds_vbt_mode); 1603 + dev_priv->vbt.lfp_lvds_vbt_mode = NULL; 1604 + kfree(dev_priv->vbt.dsi.data); 1605 + dev_priv->vbt.dsi.data = NULL; 1606 + kfree(dev_priv->vbt.dsi.pps); 1607 + dev_priv->vbt.dsi.pps = NULL; 1608 + kfree(dev_priv->vbt.dsi.config); 1609 + dev_priv->vbt.dsi.config = NULL; 1610 + kfree(dev_priv->vbt.dsi.deassert_seq); 1611 + dev_priv->vbt.dsi.deassert_seq = NULL; 1671 1612 } 1672 1613 1673 1614 /**
+10 -19
drivers/gpu/drm/i915/intel_breadcrumbs.c
··· 594 594 spin_unlock_irq(&b->rb_lock); 595 595 } 596 596 597 - static bool signal_valid(const struct drm_i915_gem_request *request) 598 - { 599 - return intel_wait_check_request(&request->signaling.wait, request); 600 - } 601 - 602 597 static bool signal_complete(const struct drm_i915_gem_request *request) 603 598 { 604 599 if (!request) 605 600 return false; 606 601 607 - /* If another process served as the bottom-half it may have already 608 - * signalled that this wait is already completed. 609 - */ 610 - if (intel_wait_complete(&request->signaling.wait)) 611 - return signal_valid(request); 612 - 613 - /* Carefully check if the request is complete, giving time for the 602 + /* 603 + * Carefully check if the request is complete, giving time for the 614 604 * seqno to be visible or if the GPU hung. 615 605 */ 616 - if (__i915_request_irq_complete(request)) 617 - return true; 618 - 619 - return false; 606 + return __i915_request_irq_complete(request); 620 607 } 621 608 622 609 static struct drm_i915_gem_request *to_signaler(struct rb_node *rb) ··· 646 659 request = i915_gem_request_get_rcu(request); 647 660 rcu_read_unlock(); 648 661 if (signal_complete(request)) { 649 - local_bh_disable(); 650 - dma_fence_signal(&request->fence); 651 - local_bh_enable(); /* kick start the tasklets */ 662 + if (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, 663 + &request->fence.flags)) { 664 + local_bh_disable(); 665 + dma_fence_signal(&request->fence); 666 + GEM_BUG_ON(!i915_gem_request_completed(request)); 667 + local_bh_enable(); /* kick start the tasklets */ 668 + } 652 669 653 670 spin_lock_irq(&b->rb_lock); 654 671
+8
drivers/gpu/drm/i915/intel_cdclk.c
··· 1952 1952 if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) 1953 1953 min_cdclk = max(2 * 96000, min_cdclk); 1954 1954 1955 + /* 1956 + * On Valleyview some DSI panels lose (v|h)sync when the clock is lower 1957 + * than 320000KHz. 1958 + */ 1959 + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && 1960 + IS_VALLEYVIEW(dev_priv)) 1961 + min_cdclk = max(320000, min_cdclk); 1962 + 1955 1963 if (min_cdclk > dev_priv->max_cdclk_freq) { 1956 1964 DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n", 1957 1965 min_cdclk, dev_priv->max_cdclk_freq);
+16 -10
drivers/gpu/drm/i915/intel_engine_cs.c
··· 1458 1458 struct drm_i915_private *dev_priv = engine->i915; 1459 1459 bool idle = true; 1460 1460 1461 - intel_runtime_pm_get(dev_priv); 1461 + /* If the whole device is asleep, the engine must be idle */ 1462 + if (!intel_runtime_pm_get_if_in_use(dev_priv)) 1463 + return true; 1462 1464 1463 1465 /* First check that no commands are left in the ring */ 1464 1466 if ((I915_READ_HEAD(engine) & HEAD_ADDR) != ··· 1945 1943 */ 1946 1944 int intel_enable_engine_stats(struct intel_engine_cs *engine) 1947 1945 { 1946 + struct intel_engine_execlists *execlists = &engine->execlists; 1948 1947 unsigned long flags; 1948 + int err = 0; 1949 1949 1950 1950 if (!intel_engine_supports_stats(engine)) 1951 1951 return -ENODEV; 1952 1952 1953 + tasklet_disable(&execlists->tasklet); 1953 1954 spin_lock_irqsave(&engine->stats.lock, flags); 1954 - if (engine->stats.enabled == ~0) 1955 - goto busy; 1955 + 1956 + if (unlikely(engine->stats.enabled == ~0)) { 1957 + err = -EBUSY; 1958 + goto unlock; 1959 + } 1960 + 1956 1961 if (engine->stats.enabled++ == 0) { 1957 - struct intel_engine_execlists *execlists = &engine->execlists; 1958 1962 const struct execlist_port *port = execlists->port; 1959 1963 unsigned int num_ports = execlists_num_ports(execlists); 1960 1964 ··· 1975 1967 if (engine->stats.active) 1976 1968 engine->stats.start = engine->stats.enabled_at; 1977 1969 } 1970 + 1971 + unlock: 1978 1972 spin_unlock_irqrestore(&engine->stats.lock, flags); 1973 + tasklet_enable(&execlists->tasklet); 1979 1974 1980 - return 0; 1981 - 1982 - busy: 1983 - spin_unlock_irqrestore(&engine->stats.lock, flags); 1984 - 1985 - return -EBUSY; 1975 + return err; 1986 1976 } 1987 1977 1988 1978 static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine)
-14
drivers/gpu/drm/i915/intel_ringbuffer.h
··· 366 366 */ 367 367 #define I915_ENGINE_SAMPLE_MAX (I915_SAMPLE_SEMA + 1) 368 368 struct i915_pmu_sample sample[I915_ENGINE_SAMPLE_MAX]; 369 - /** 370 - * @busy_stats: Has enablement of engine stats tracking been 371 - * requested. 372 - */ 373 - bool busy_stats; 374 - /** 375 - * @disable_busy_stats: Work item for busy stats disabling. 376 - * 377 - * Same as with @enable_busy_stats action, with the difference 378 - * that we delay it in case there are rapid enable-disable 379 - * actions, which can happen during tool startup (like perf 380 - * stat). 381 - */ 382 - struct delayed_work disable_busy_stats; 383 369 } pmu; 384 370 385 371 /*
+3 -3
drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
··· 301 301 void 302 302 nvkm_therm_clkgate_enable(struct nvkm_therm *therm) 303 303 { 304 - if (!therm->func->clkgate_enable || !therm->clkgating_enabled) 304 + if (!therm || !therm->func->clkgate_enable || !therm->clkgating_enabled) 305 305 return; 306 306 307 307 nvkm_debug(&therm->subdev, ··· 312 312 void 313 313 nvkm_therm_clkgate_fini(struct nvkm_therm *therm, bool suspend) 314 314 { 315 - if (!therm->func->clkgate_fini || !therm->clkgating_enabled) 315 + if (!therm || !therm->func->clkgate_fini || !therm->clkgating_enabled) 316 316 return; 317 317 318 318 nvkm_debug(&therm->subdev, ··· 395 395 nvkm_therm_clkgate_init(struct nvkm_therm *therm, 396 396 const struct nvkm_therm_clkgate_pack *p) 397 397 { 398 - if (!therm->func->clkgate_init || !therm->clkgating_enabled) 398 + if (!therm || !therm->func->clkgate_init || !therm->clkgating_enabled) 399 399 return; 400 400 401 401 therm->func->clkgate_init(therm, p);