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Merge branch 'net-stmmac-rk-cleanups-v3-mode-and-speed-for-most'

Russell King says:

====================
net: stmmac: rk: cleanups v3: mode and speed for most

Third installment in the rk cleanups, this converts the interface mode
and speed configuration for most RK SoCs.
====================

Link: https://patch.msgid.link/aYB2cKRu3DQh6yXK@shell.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

Jakub Kicinski bb23f167 667539f6

+349 -503
+349 -503
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
··· 26 26 27 27 struct rk_priv_data; 28 28 29 - struct rk_reg_speed_data { 30 - unsigned int rgmii_10; 31 - unsigned int rgmii_100; 32 - unsigned int rgmii_1000; 33 - unsigned int rmii_10; 34 - unsigned int rmii_100; 29 + struct rk_clock_fields { 30 + u16 gmii_clk_sel_mask; 31 + u16 rmii_clk_sel_mask; 32 + u16 mac_speed_mask; 35 33 }; 36 34 37 35 struct rk_gmac_ops { ··· 43 45 bool enable); 44 46 void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv); 45 47 void (*integrated_phy_powerdown)(struct rk_priv_data *bsp_priv); 48 + 49 + u16 gmac_grf_reg; 50 + u16 gmac_phy_intf_sel_mask; 51 + u16 gmac_rmii_mode_mask; 52 + 53 + u16 clock_grf_reg; 54 + struct rk_clock_fields clock; 55 + 56 + bool gmac_grf_reg_in_php; 57 + bool clock_grf_reg_in_php; 46 58 bool php_grf_required; 47 59 bool regs_valid; 48 60 u32 regs[]; ··· 98 90 99 91 struct regmap *grf; 100 92 struct regmap *php_grf; 93 + 94 + u16 gmac_grf_reg; 95 + u16 gmac_phy_intf_sel_mask; 96 + u16 gmac_rmii_mode_mask; 97 + 98 + u16 clock_grf_reg; 99 + struct rk_clock_fields clock; 101 100 }; 102 101 103 102 #define GMAC_CLK_DIV1_125M 0 104 103 #define GMAC_CLK_DIV50_2_5M 2 105 104 #define GMAC_CLK_DIV5_25M 3 106 105 107 - static int rk_set_reg_speed(struct rk_priv_data *bsp_priv, 108 - const struct rk_reg_speed_data *rsd, 109 - unsigned int reg, phy_interface_t interface, 110 - int speed) 106 + static int rk_gmac_rgmii_clk_div(int speed) 111 107 { 112 - unsigned int val; 108 + if (speed == SPEED_10) 109 + return GMAC_CLK_DIV50_2_5M; 110 + if (speed == SPEED_100) 111 + return GMAC_CLK_DIV5_25M; 112 + if (speed == SPEED_1000) 113 + return GMAC_CLK_DIV1_125M; 114 + return -EINVAL; 115 + } 113 116 114 - if (phy_interface_mode_is_rgmii(interface)) { 115 - if (speed == SPEED_10) { 116 - val = rsd->rgmii_10; 117 - } else if (speed == SPEED_100) { 118 - val = rsd->rgmii_100; 119 - } else if (speed == SPEED_1000) { 120 - val = rsd->rgmii_1000; 121 - } else { 122 - /* Phylink will not allow inappropriate speeds for 123 - * interface modes, so this should never happen. 124 - */ 125 - return -EINVAL; 126 - } 127 - } else if (interface == PHY_INTERFACE_MODE_RMII) { 128 - if (speed == SPEED_10) { 129 - val = rsd->rmii_10; 130 - } else if (speed == SPEED_100) { 131 - val = rsd->rmii_100; 132 - } else { 133 - /* Phylink will not allow inappropriate speeds for 134 - * interface modes, so this should never happen. 135 - */ 136 - return -EINVAL; 137 - } 138 - } else { 139 - /* This should never happen, as .get_interfaces() limits 140 - * the interface modes that are supported to RGMII and/or 141 - * RMII. 142 - */ 143 - return -EINVAL; 144 - } 117 + static int rk_get_phy_intf_sel(phy_interface_t interface) 118 + { 119 + int ret = stmmac_get_phy_intf_sel(interface); 145 120 146 - regmap_write(bsp_priv->grf, reg, val); 121 + /* Only RGMII and RMII are supported */ 122 + if (ret != PHY_INTF_SEL_RGMII && ret != PHY_INTF_SEL_RMII) 123 + ret = -EINVAL; 147 124 148 - return 0; 125 + return ret; 126 + } 149 127 128 + static u32 rk_encode_wm16(u16 val, u16 mask) 129 + { 130 + u32 reg_val = mask << 16; 131 + 132 + if (mask) 133 + reg_val |= mask & (val << (ffs(mask) - 1)); 134 + 135 + return reg_val; 136 + } 137 + 138 + static int rk_write_gmac_grf_reg(struct rk_priv_data *bsp_priv, u32 val) 139 + { 140 + struct regmap *regmap; 141 + 142 + if (bsp_priv->ops->gmac_grf_reg_in_php) 143 + regmap = bsp_priv->php_grf; 144 + else 145 + regmap = bsp_priv->grf; 146 + 147 + return regmap_write(regmap, bsp_priv->gmac_grf_reg, val); 148 + } 149 + 150 + static int rk_write_clock_grf_reg(struct rk_priv_data *bsp_priv, u32 val) 151 + { 152 + struct regmap *regmap; 153 + 154 + if (bsp_priv->ops->clock_grf_reg_in_php) 155 + regmap = bsp_priv->php_grf; 156 + else 157 + regmap = bsp_priv->grf; 158 + 159 + return regmap_write(regmap, bsp_priv->clock_grf_reg, val); 150 160 } 151 161 152 162 static int rk_set_clk_mac_speed(struct rk_priv_data *bsp_priv, ··· 182 156 183 157 #define GRF_FIELD(hi, lo, val) \ 184 158 FIELD_PREP_WM16(GENMASK_U16(hi, lo), val) 185 - #define GRF_FIELD_CONST(hi, lo, val) \ 186 - FIELD_PREP_WM16_CONST(GENMASK_U16(hi, lo), val) 187 159 188 160 #define GRF_BIT(nr) (BIT(nr) | BIT(nr+16)) 189 161 #define GRF_CLR_BIT(nr) (BIT(nr+16)) ··· 264 240 265 241 #define PX30_GRF_GMAC_CON1 0x0904 266 242 267 - /* PX30_GRF_GMAC_CON1 */ 268 - #define PX30_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val) 269 - #define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2) 270 - #define PX30_GMAC_SPEED_100M GRF_BIT(2) 271 - 272 243 static void px30_set_to_rmii(struct rk_priv_data *bsp_priv) 273 244 { 274 - regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, 275 - PX30_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII)); 276 - } 277 - 278 - static int px30_set_speed(struct rk_priv_data *bsp_priv, 279 - phy_interface_t interface, int speed) 280 - { 281 - struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; 282 - struct device *dev = bsp_priv->dev; 283 - unsigned int con1; 284 - long rate; 285 - 286 - if (!clk_mac_speed) { 287 - dev_err(dev, "%s: Missing clk_mac_speed clock\n", __func__); 288 - return -EINVAL; 289 - } 290 - 291 - if (speed == 10) { 292 - con1 = PX30_GMAC_SPEED_10M; 293 - rate = 2500000; 294 - } else if (speed == 100) { 295 - con1 = PX30_GMAC_SPEED_100M; 296 - rate = 25000000; 297 - } else { 298 - dev_err(dev, "unknown speed value for RMII! speed=%d", speed); 299 - return -EINVAL; 300 - } 301 - 302 - regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, con1); 303 - 304 - return clk_set_rate(clk_mac_speed, rate); 305 245 } 306 246 307 247 static const struct rk_gmac_ops px30_ops = { 308 248 .set_to_rmii = px30_set_to_rmii, 309 - .set_speed = px30_set_speed, 249 + .set_speed = rk_set_clk_mac_speed, 250 + 251 + .gmac_grf_reg = PX30_GRF_GMAC_CON1, 252 + .gmac_phy_intf_sel_mask = GENMASK_U16(6, 4), 253 + 254 + .clock_grf_reg = PX30_GRF_GMAC_CON1, 255 + .clock.mac_speed_mask = BIT_U16(2), 310 256 }; 311 257 312 258 #define RK3128_GRF_MAC_CON0 0x0168 ··· 291 297 #define RK3128_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val) 292 298 293 299 /* RK3128_GRF_MAC_CON1 */ 294 - #define RK3128_GMAC_PHY_INTF_SEL(val) GRF_FIELD(8, 6, val) 295 300 #define RK3128_GMAC_FLOW_CTRL GRF_BIT(9) 296 301 #define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) 297 - #define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10) 298 - #define RK3128_GMAC_SPEED_100M GRF_BIT(10) 299 - #define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11) 300 - #define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) 301 - #define RK3128_GMAC_CLK(val) GRF_FIELD_CONST(13, 12, val) 302 - #define RK3128_GMAC_RMII_MODE GRF_BIT(14) 303 - #define RK3128_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) 304 302 305 303 static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv, 306 304 int tx_delay, int rx_delay) 307 305 { 308 - regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 309 - RK3128_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) | 310 - RK3128_GMAC_RMII_MODE_CLR); 311 306 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0, 312 307 DELAY_ENABLE(RK3128, tx_delay, rx_delay) | 313 308 RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) | ··· 305 322 306 323 static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv) 307 324 { 308 - regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1, 309 - RK3128_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) | 310 - RK3128_GMAC_RMII_MODE); 311 - } 312 - 313 - static const struct rk_reg_speed_data rk3128_reg_speed_data = { 314 - .rgmii_10 = RK3128_GMAC_CLK(GMAC_CLK_DIV50_2_5M), 315 - .rgmii_100 = RK3128_GMAC_CLK(GMAC_CLK_DIV5_25M), 316 - .rgmii_1000 = RK3128_GMAC_CLK(GMAC_CLK_DIV1_125M), 317 - .rmii_10 = RK3128_GMAC_RMII_CLK_2_5M | RK3128_GMAC_SPEED_10M, 318 - .rmii_100 = RK3128_GMAC_RMII_CLK_25M | RK3128_GMAC_SPEED_100M, 319 - }; 320 - 321 - static int rk3128_set_speed(struct rk_priv_data *bsp_priv, 322 - phy_interface_t interface, int speed) 323 - { 324 - return rk_set_reg_speed(bsp_priv, &rk3128_reg_speed_data, 325 - RK3128_GRF_MAC_CON1, interface, speed); 326 325 } 327 326 328 327 static const struct rk_gmac_ops rk3128_ops = { 329 328 .set_to_rgmii = rk3128_set_to_rgmii, 330 329 .set_to_rmii = rk3128_set_to_rmii, 331 - .set_speed = rk3128_set_speed, 330 + 331 + .gmac_grf_reg = RK3128_GRF_MAC_CON1, 332 + .gmac_phy_intf_sel_mask = GENMASK_U16(8, 6), 333 + .gmac_rmii_mode_mask = BIT_U16(14), 334 + 335 + .clock_grf_reg = RK3128_GRF_MAC_CON1, 336 + .clock.gmii_clk_sel_mask = GENMASK_U16(13, 12), 337 + .clock.rmii_clk_sel_mask = BIT_U16(11), 338 + .clock.mac_speed_mask = BIT_U16(10), 332 339 }; 333 340 334 341 #define RK3228_GRF_MAC_CON0 0x0900 ··· 331 358 #define RK3228_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val) 332 359 333 360 /* RK3228_GRF_MAC_CON1 */ 334 - #define RK3228_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val) 335 361 #define RK3228_GMAC_FLOW_CTRL GRF_BIT(3) 336 362 #define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 337 - #define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2) 338 - #define RK3228_GMAC_SPEED_100M GRF_BIT(2) 339 - #define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7) 340 - #define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 341 - #define RK3228_GMAC_CLK(val) GRF_FIELD_CONST(9, 8, val) 342 - #define RK3228_GMAC_RMII_MODE GRF_BIT(10) 343 - #define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10) 344 363 #define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 345 364 #define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 346 365 #define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) ··· 345 380 int tx_delay, int rx_delay) 346 381 { 347 382 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 348 - RK3228_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) | 349 - RK3228_GMAC_RMII_MODE_CLR | 350 383 DELAY_ENABLE(RK3228, tx_delay, rx_delay)); 351 384 352 385 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0, ··· 354 391 355 392 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv) 356 393 { 357 - regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, 358 - RK3228_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) | 359 - RK3228_GMAC_RMII_MODE); 360 - 361 394 /* set MAC to RMII mode */ 362 395 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11)); 363 - } 364 - 365 - static const struct rk_reg_speed_data rk3228_reg_speed_data = { 366 - .rgmii_10 = RK3228_GMAC_CLK(GMAC_CLK_DIV50_2_5M), 367 - .rgmii_100 = RK3228_GMAC_CLK(GMAC_CLK_DIV5_25M), 368 - .rgmii_1000 = RK3228_GMAC_CLK(GMAC_CLK_DIV1_125M), 369 - .rmii_10 = RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_SPEED_10M, 370 - .rmii_100 = RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_SPEED_100M, 371 - }; 372 - 373 - static int rk3228_set_speed(struct rk_priv_data *bsp_priv, 374 - phy_interface_t interface, int speed) 375 - { 376 - return rk_set_reg_speed(bsp_priv, &rk3228_reg_speed_data, 377 - RK3228_GRF_MAC_CON1, interface, speed); 378 396 } 379 397 380 398 static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv) ··· 369 425 static const struct rk_gmac_ops rk3228_ops = { 370 426 .set_to_rgmii = rk3228_set_to_rgmii, 371 427 .set_to_rmii = rk3228_set_to_rmii, 372 - .set_speed = rk3228_set_speed, 373 428 .integrated_phy_powerup = rk3228_integrated_phy_powerup, 374 429 .integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown, 430 + 431 + .gmac_grf_reg = RK3228_GRF_MAC_CON1, 432 + .gmac_phy_intf_sel_mask = GENMASK_U16(6, 4), 433 + .gmac_rmii_mode_mask = BIT_U16(10), 434 + 435 + .clock_grf_reg = RK3228_GRF_MAC_CON1, 436 + .clock.gmii_clk_sel_mask = GENMASK_U16(9, 8), 437 + .clock.rmii_clk_sel_mask = BIT_U16(7), 438 + .clock.mac_speed_mask = BIT_U16(2), 375 439 }; 376 440 377 441 #define RK3288_GRF_SOC_CON1 0x0248 378 442 #define RK3288_GRF_SOC_CON3 0x0250 379 443 380 444 /*RK3288_GRF_SOC_CON1*/ 381 - #define RK3288_GMAC_PHY_INTF_SEL(val) GRF_FIELD(8, 6, val) 382 445 #define RK3288_GMAC_FLOW_CTRL GRF_BIT(9) 383 446 #define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) 384 - #define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10) 385 - #define RK3288_GMAC_SPEED_100M GRF_BIT(10) 386 - #define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11) 387 - #define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) 388 - #define RK3288_GMAC_CLK(val) GRF_FIELD_CONST(13, 12, val) 389 - #define RK3288_GMAC_RMII_MODE GRF_BIT(14) 390 - #define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) 391 447 392 448 /*RK3288_GRF_SOC_CON3*/ 393 449 #define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) ··· 400 456 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv, 401 457 int tx_delay, int rx_delay) 402 458 { 403 - regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 404 - RK3288_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) | 405 - RK3288_GMAC_RMII_MODE_CLR); 406 459 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3, 407 460 DELAY_ENABLE(RK3288, tx_delay, rx_delay) | 408 461 RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) | ··· 408 467 409 468 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv) 410 469 { 411 - regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, 412 - RK3288_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) | 413 - RK3288_GMAC_RMII_MODE); 414 - } 415 - 416 - static const struct rk_reg_speed_data rk3288_reg_speed_data = { 417 - .rgmii_10 = RK3288_GMAC_CLK(GMAC_CLK_DIV50_2_5M), 418 - .rgmii_100 = RK3288_GMAC_CLK(GMAC_CLK_DIV5_25M), 419 - .rgmii_1000 = RK3288_GMAC_CLK(GMAC_CLK_DIV1_125M), 420 - .rmii_10 = RK3288_GMAC_RMII_CLK_2_5M | RK3288_GMAC_SPEED_10M, 421 - .rmii_100 = RK3288_GMAC_RMII_CLK_25M | RK3288_GMAC_SPEED_100M, 422 - }; 423 - 424 - static int rk3288_set_speed(struct rk_priv_data *bsp_priv, 425 - phy_interface_t interface, int speed) 426 - { 427 - return rk_set_reg_speed(bsp_priv, &rk3288_reg_speed_data, 428 - RK3288_GRF_SOC_CON1, interface, speed); 429 470 } 430 471 431 472 static const struct rk_gmac_ops rk3288_ops = { 432 473 .set_to_rgmii = rk3288_set_to_rgmii, 433 474 .set_to_rmii = rk3288_set_to_rmii, 434 - .set_speed = rk3288_set_speed, 475 + 476 + .gmac_grf_reg = RK3288_GRF_SOC_CON1, 477 + .gmac_phy_intf_sel_mask = GENMASK_U16(8, 6), 478 + .gmac_rmii_mode_mask = BIT_U16(14), 479 + 480 + .clock_grf_reg = RK3288_GRF_SOC_CON1, 481 + .clock.gmii_clk_sel_mask = GENMASK_U16(13, 12), 482 + .clock.rmii_clk_sel_mask = BIT_U16(11), 483 + .clock.mac_speed_mask = BIT_U16(10), 435 484 }; 436 485 437 486 #define RK3308_GRF_MAC_CON0 0x04a0 438 487 439 488 /* RK3308_GRF_MAC_CON0 */ 440 - #define RK3308_GMAC_PHY_INTF_SEL(val) GRF_FIELD(4, 2, val) 441 489 #define RK3308_GMAC_FLOW_CTRL GRF_BIT(3) 442 490 #define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 443 - #define RK3308_GMAC_SPEED_10M GRF_CLR_BIT(0) 444 - #define RK3308_GMAC_SPEED_100M GRF_BIT(0) 445 491 446 492 static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv) 447 493 { 448 - regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0, 449 - RK3308_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII)); 450 - } 451 - 452 - static const struct rk_reg_speed_data rk3308_reg_speed_data = { 453 - .rmii_10 = RK3308_GMAC_SPEED_10M, 454 - .rmii_100 = RK3308_GMAC_SPEED_100M, 455 - }; 456 - 457 - static int rk3308_set_speed(struct rk_priv_data *bsp_priv, 458 - phy_interface_t interface, int speed) 459 - { 460 - return rk_set_reg_speed(bsp_priv, &rk3308_reg_speed_data, 461 - RK3308_GRF_MAC_CON0, interface, speed); 462 494 } 463 495 464 496 static const struct rk_gmac_ops rk3308_ops = { 465 497 .set_to_rmii = rk3308_set_to_rmii, 466 - .set_speed = rk3308_set_speed, 498 + 499 + .gmac_grf_reg = RK3308_GRF_MAC_CON0, 500 + .gmac_phy_intf_sel_mask = GENMASK_U16(4, 2), 501 + 502 + .clock_grf_reg = RK3308_GRF_MAC_CON0, 503 + .clock.mac_speed_mask = BIT_U16(0), 467 504 }; 468 505 469 506 #define RK3328_GRF_MAC_CON0 0x0900 ··· 454 535 #define RK3328_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val) 455 536 456 537 /* RK3328_GRF_MAC_CON1 */ 457 - #define RK3328_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val) 458 538 #define RK3328_GMAC_FLOW_CTRL GRF_BIT(3) 459 539 #define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 460 - #define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2) 461 - #define RK3328_GMAC_SPEED_100M GRF_BIT(2) 462 - #define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7) 463 - #define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 464 - #define RK3328_GMAC_CLK(val) GRF_FIELD_CONST(12, 11, val) 465 - #define RK3328_GMAC_RMII_MODE GRF_BIT(9) 466 - #define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9) 467 540 #define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 468 541 #define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 469 542 470 543 /* RK3328_GRF_MACPHY_CON1 */ 471 544 #define RK3328_MACPHY_RMII_MODE GRF_BIT(9) 472 545 546 + static int rk3328_init(struct rk_priv_data *bsp_priv) 547 + { 548 + switch (bsp_priv->id) { 549 + case 0: /* gmac2io */ 550 + bsp_priv->gmac_grf_reg = RK3328_GRF_MAC_CON1; 551 + bsp_priv->clock_grf_reg = RK3328_GRF_MAC_CON1; 552 + bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(12, 11); 553 + return 0; 554 + 555 + case 1: /* gmac2phy */ 556 + bsp_priv->gmac_grf_reg = RK3328_GRF_MAC_CON2; 557 + bsp_priv->clock_grf_reg = RK3328_GRF_MAC_CON2; 558 + return 0; 559 + 560 + default: 561 + return -EINVAL; 562 + } 563 + } 564 + 473 565 static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv, 474 566 int tx_delay, int rx_delay) 475 567 { 476 568 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, 477 - RK3328_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) | 478 - RK3328_GMAC_RMII_MODE_CLR | 479 569 RK3328_GMAC_RXCLK_DLY_ENABLE | 480 570 RK3328_GMAC_TXCLK_DLY_ENABLE); 481 571 ··· 495 567 496 568 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv) 497 569 { 498 - unsigned int reg; 499 - 500 - reg = bsp_priv->id ? RK3328_GRF_MAC_CON2 : RK3328_GRF_MAC_CON1; 501 - 502 - regmap_write(bsp_priv->grf, reg, 503 - RK3328_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) | 504 - RK3328_GMAC_RMII_MODE); 505 - } 506 - 507 - static const struct rk_reg_speed_data rk3328_reg_speed_data = { 508 - .rgmii_10 = RK3328_GMAC_CLK(GMAC_CLK_DIV50_2_5M), 509 - .rgmii_100 = RK3328_GMAC_CLK(GMAC_CLK_DIV5_25M), 510 - .rgmii_1000 = RK3328_GMAC_CLK(GMAC_CLK_DIV1_125M), 511 - .rmii_10 = RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_SPEED_10M, 512 - .rmii_100 = RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_SPEED_100M, 513 - }; 514 - 515 - static int rk3328_set_speed(struct rk_priv_data *bsp_priv, 516 - phy_interface_t interface, int speed) 517 - { 518 - unsigned int reg; 519 - 520 - reg = bsp_priv->id ? RK3328_GRF_MAC_CON2 : RK3328_GRF_MAC_CON1; 521 - 522 - return rk_set_reg_speed(bsp_priv, &rk3328_reg_speed_data, reg, 523 - interface, speed); 524 570 } 525 571 526 572 static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv) ··· 506 604 } 507 605 508 606 static const struct rk_gmac_ops rk3328_ops = { 607 + .init = rk3328_init, 509 608 .set_to_rgmii = rk3328_set_to_rgmii, 510 609 .set_to_rmii = rk3328_set_to_rmii, 511 - .set_speed = rk3328_set_speed, 512 610 .integrated_phy_powerup = rk3328_integrated_phy_powerup, 513 611 .integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown, 612 + 613 + .gmac_phy_intf_sel_mask = GENMASK_U16(6, 4), 614 + .gmac_rmii_mode_mask = BIT_U16(9), 615 + 616 + .clock.rmii_clk_sel_mask = BIT_U16(7), 617 + .clock.mac_speed_mask = BIT_U16(2), 514 618 515 619 .regs_valid = true, 516 620 .regs = { ··· 530 622 #define RK3366_GRF_SOC_CON7 0x041c 531 623 532 624 /* RK3366_GRF_SOC_CON6 */ 533 - #define RK3366_GMAC_PHY_INTF_SEL(val) GRF_FIELD(11, 9, val) 534 625 #define RK3366_GMAC_FLOW_CTRL GRF_BIT(8) 535 626 #define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 536 - #define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7) 537 - #define RK3366_GMAC_SPEED_100M GRF_BIT(7) 538 - #define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3) 539 - #define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 540 - #define RK3366_GMAC_CLK(val) GRF_FIELD_CONST(5, 4, val) 541 - #define RK3366_GMAC_RMII_MODE GRF_BIT(6) 542 - #define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 543 627 544 628 /* RK3366_GRF_SOC_CON7 */ 545 629 #define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) ··· 544 644 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv, 545 645 int tx_delay, int rx_delay) 546 646 { 547 - regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 548 - RK3366_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) | 549 - RK3366_GMAC_RMII_MODE_CLR); 550 647 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7, 551 648 DELAY_ENABLE(RK3366, tx_delay, rx_delay) | 552 649 RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) | ··· 552 655 553 656 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv) 554 657 { 555 - regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6, 556 - RK3366_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) | 557 - RK3366_GMAC_RMII_MODE); 558 - } 559 - 560 - static const struct rk_reg_speed_data rk3366_reg_speed_data = { 561 - .rgmii_10 = RK3366_GMAC_CLK(GMAC_CLK_DIV50_2_5M), 562 - .rgmii_100 = RK3366_GMAC_CLK(GMAC_CLK_DIV5_25M), 563 - .rgmii_1000 = RK3366_GMAC_CLK(GMAC_CLK_DIV1_125M), 564 - .rmii_10 = RK3366_GMAC_RMII_CLK_2_5M | RK3366_GMAC_SPEED_10M, 565 - .rmii_100 = RK3366_GMAC_RMII_CLK_25M | RK3366_GMAC_SPEED_100M, 566 - }; 567 - 568 - static int rk3366_set_speed(struct rk_priv_data *bsp_priv, 569 - phy_interface_t interface, int speed) 570 - { 571 - return rk_set_reg_speed(bsp_priv, &rk3366_reg_speed_data, 572 - RK3366_GRF_SOC_CON6, interface, speed); 573 658 } 574 659 575 660 static const struct rk_gmac_ops rk3366_ops = { 576 661 .set_to_rgmii = rk3366_set_to_rgmii, 577 662 .set_to_rmii = rk3366_set_to_rmii, 578 - .set_speed = rk3366_set_speed, 663 + 664 + .gmac_grf_reg = RK3366_GRF_SOC_CON6, 665 + .gmac_phy_intf_sel_mask = GENMASK_U16(11, 9), 666 + .gmac_rmii_mode_mask = BIT_U16(6), 667 + 668 + .clock_grf_reg = RK3366_GRF_SOC_CON6, 669 + .clock.gmii_clk_sel_mask = GENMASK_U16(5, 4), 670 + .clock.rmii_clk_sel_mask = BIT_U16(3), 671 + .clock.mac_speed_mask = BIT_U16(7), 579 672 }; 580 673 581 674 #define RK3368_GRF_SOC_CON15 0x043c 582 675 #define RK3368_GRF_SOC_CON16 0x0440 583 676 584 677 /* RK3368_GRF_SOC_CON15 */ 585 - #define RK3368_GMAC_PHY_INTF_SEL(val) GRF_FIELD(11, 9, val) 586 678 #define RK3368_GMAC_FLOW_CTRL GRF_BIT(8) 587 679 #define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 588 - #define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7) 589 - #define RK3368_GMAC_SPEED_100M GRF_BIT(7) 590 - #define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3) 591 - #define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 592 - #define RK3368_GMAC_CLK(val) GRF_FIELD_CONST(5, 4, val) 593 - #define RK3368_GMAC_RMII_MODE GRF_BIT(6) 594 - #define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 595 680 596 681 /* RK3368_GRF_SOC_CON16 */ 597 682 #define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) ··· 586 707 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv, 587 708 int tx_delay, int rx_delay) 588 709 { 589 - regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 590 - RK3368_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) | 591 - RK3368_GMAC_RMII_MODE_CLR); 592 710 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16, 593 711 DELAY_ENABLE(RK3368, tx_delay, rx_delay) | 594 712 RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) | ··· 594 718 595 719 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv) 596 720 { 597 - regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15, 598 - RK3368_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) | 599 - RK3368_GMAC_RMII_MODE); 600 - } 601 - 602 - static const struct rk_reg_speed_data rk3368_reg_speed_data = { 603 - .rgmii_10 = RK3368_GMAC_CLK(GMAC_CLK_DIV50_2_5M), 604 - .rgmii_100 = RK3368_GMAC_CLK(GMAC_CLK_DIV5_25M), 605 - .rgmii_1000 = RK3368_GMAC_CLK(GMAC_CLK_DIV1_125M), 606 - .rmii_10 = RK3368_GMAC_RMII_CLK_2_5M | RK3368_GMAC_SPEED_10M, 607 - .rmii_100 = RK3368_GMAC_RMII_CLK_25M | RK3368_GMAC_SPEED_100M, 608 - }; 609 - 610 - static int rk3368_set_speed(struct rk_priv_data *bsp_priv, 611 - phy_interface_t interface, int speed) 612 - { 613 - return rk_set_reg_speed(bsp_priv, &rk3368_reg_speed_data, 614 - RK3368_GRF_SOC_CON15, interface, speed); 615 721 } 616 722 617 723 static const struct rk_gmac_ops rk3368_ops = { 618 724 .set_to_rgmii = rk3368_set_to_rgmii, 619 725 .set_to_rmii = rk3368_set_to_rmii, 620 - .set_speed = rk3368_set_speed, 726 + 727 + .gmac_grf_reg = RK3368_GRF_SOC_CON15, 728 + .gmac_phy_intf_sel_mask = GENMASK_U16(11, 9), 729 + .gmac_rmii_mode_mask = BIT_U16(6), 730 + 731 + .clock_grf_reg = RK3368_GRF_SOC_CON15, 732 + .clock.gmii_clk_sel_mask = GENMASK_U16(5, 4), 733 + .clock.rmii_clk_sel_mask = BIT_U16(3), 734 + .clock.mac_speed_mask = BIT_U16(7), 621 735 }; 622 736 623 737 #define RK3399_GRF_SOC_CON5 0xc214 624 738 #define RK3399_GRF_SOC_CON6 0xc218 625 739 626 740 /* RK3399_GRF_SOC_CON5 */ 627 - #define RK3399_GMAC_PHY_INTF_SEL(val) GRF_FIELD(11, 9, val) 628 741 #define RK3399_GMAC_FLOW_CTRL GRF_BIT(8) 629 742 #define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) 630 - #define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7) 631 - #define RK3399_GMAC_SPEED_100M GRF_BIT(7) 632 - #define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3) 633 - #define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 634 - #define RK3399_GMAC_CLK(val) GRF_FIELD_CONST(5, 4, val) 635 - #define RK3399_GMAC_RMII_MODE GRF_BIT(6) 636 - #define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 637 743 638 744 /* RK3399_GRF_SOC_CON6 */ 639 745 #define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) ··· 628 770 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv, 629 771 int tx_delay, int rx_delay) 630 772 { 631 - regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 632 - RK3399_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) | 633 - RK3399_GMAC_RMII_MODE_CLR); 634 773 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6, 635 774 DELAY_ENABLE(RK3399, tx_delay, rx_delay) | 636 775 RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) | ··· 636 781 637 782 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv) 638 783 { 639 - regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5, 640 - RK3399_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) | 641 - RK3399_GMAC_RMII_MODE); 642 - } 643 - 644 - static const struct rk_reg_speed_data rk3399_reg_speed_data = { 645 - .rgmii_10 = RK3399_GMAC_CLK(GMAC_CLK_DIV50_2_5M), 646 - .rgmii_100 = RK3399_GMAC_CLK(GMAC_CLK_DIV5_25M), 647 - .rgmii_1000 = RK3399_GMAC_CLK(GMAC_CLK_DIV1_125M), 648 - .rmii_10 = RK3399_GMAC_RMII_CLK_2_5M | RK3399_GMAC_SPEED_10M, 649 - .rmii_100 = RK3399_GMAC_RMII_CLK_25M | RK3399_GMAC_SPEED_100M, 650 - }; 651 - 652 - static int rk3399_set_speed(struct rk_priv_data *bsp_priv, 653 - phy_interface_t interface, int speed) 654 - { 655 - return rk_set_reg_speed(bsp_priv, &rk3399_reg_speed_data, 656 - RK3399_GRF_SOC_CON5, interface, speed); 657 784 } 658 785 659 786 static const struct rk_gmac_ops rk3399_ops = { 660 787 .set_to_rgmii = rk3399_set_to_rgmii, 661 788 .set_to_rmii = rk3399_set_to_rmii, 662 - .set_speed = rk3399_set_speed, 789 + 790 + .gmac_grf_reg = RK3399_GRF_SOC_CON5, 791 + .gmac_phy_intf_sel_mask = GENMASK_U16(11, 9), 792 + .gmac_rmii_mode_mask = BIT_U16(6), 793 + 794 + .clock_grf_reg = RK3399_GRF_SOC_CON5, 795 + .clock.gmii_clk_sel_mask = GENMASK_U16(5, 4), 796 + .clock.rmii_clk_sel_mask = BIT_U16(3), 797 + .clock.mac_speed_mask = BIT_U16(7), 663 798 }; 664 799 665 800 #define RK3506_GRF_SOC_CON8 0x0020 ··· 657 812 658 813 #define RK3506_GMAC_RMII_MODE GRF_BIT(1) 659 814 660 - #define RK3506_GMAC_CLK_RMII_DIV2 GRF_BIT(3) 661 - #define RK3506_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(3) 662 - 663 815 #define RK3506_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(5) 664 816 #define RK3506_GMAC_CLK_SELECT_IO GRF_BIT(5) 665 817 666 818 #define RK3506_GMAC_CLK_RMII_GATE GRF_BIT(2) 667 819 #define RK3506_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(2) 820 + 821 + static int rk3506_init(struct rk_priv_data *bsp_priv) 822 + { 823 + switch (bsp_priv->id) { 824 + case 0: 825 + bsp_priv->clock_grf_reg = RK3506_GRF_SOC_CON8; 826 + return 0; 827 + 828 + case 1: 829 + bsp_priv->clock_grf_reg = RK3506_GRF_SOC_CON11; 830 + return 0; 831 + 832 + default: 833 + return -EINVAL; 834 + } 835 + } 668 836 669 837 static void rk3506_set_to_rmii(struct rk_priv_data *bsp_priv) 670 838 { ··· 685 827 686 828 offset = (id == 1) ? RK3506_GRF_SOC_CON11 : RK3506_GRF_SOC_CON8; 687 829 regmap_write(bsp_priv->grf, offset, RK3506_GMAC_RMII_MODE); 688 - } 689 - 690 - static const struct rk_reg_speed_data rk3506_reg_speed_data = { 691 - .rmii_10 = RK3506_GMAC_CLK_RMII_DIV20, 692 - .rmii_100 = RK3506_GMAC_CLK_RMII_DIV2, 693 - }; 694 - 695 - static int rk3506_set_speed(struct rk_priv_data *bsp_priv, 696 - phy_interface_t interface, int speed) 697 - { 698 - unsigned int id = bsp_priv->id, offset; 699 - 700 - offset = (id == 1) ? RK3506_GRF_SOC_CON11 : RK3506_GRF_SOC_CON8; 701 - return rk_set_reg_speed(bsp_priv, &rk3506_reg_speed_data, 702 - offset, interface, speed); 703 830 } 704 831 705 832 static void rk3506_set_clock_selection(struct rk_priv_data *bsp_priv, ··· 702 859 } 703 860 704 861 static const struct rk_gmac_ops rk3506_ops = { 862 + .init = rk3506_init, 705 863 .set_to_rmii = rk3506_set_to_rmii, 706 - .set_speed = rk3506_set_speed, 707 864 .set_clock_selection = rk3506_set_clock_selection, 865 + 866 + .clock.rmii_clk_sel_mask = BIT_U16(3), 867 + 708 868 .regs_valid = true, 709 869 .regs = { 710 870 0xff4c8000, /* gmac0 */ ··· 737 891 #define RK3528_GMAC1_CLK_SELECT_CRU GRF_CLR_BIT(12) 738 892 #define RK3528_GMAC1_CLK_SELECT_IO GRF_BIT(12) 739 893 740 - #define RK3528_GMAC0_CLK_RMII_DIV2 GRF_BIT(3) 741 - #define RK3528_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(3) 742 - #define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10) 743 - #define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10) 744 - 745 - #define RK3528_GMAC1_CLK_RGMII(val) GRF_FIELD_CONST(11, 10, val) 746 - 747 894 #define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2) 748 895 #define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2) 749 896 #define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9) 750 897 #define RK3528_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(9) 898 + 899 + static int rk3528_init(struct rk_priv_data *bsp_priv) 900 + { 901 + switch (bsp_priv->id) { 902 + case 0: 903 + bsp_priv->clock_grf_reg = RK3528_VO_GRF_GMAC_CON; 904 + bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(3); 905 + return 0; 906 + 907 + case 1: 908 + bsp_priv->clock_grf_reg = RK3528_VPU_GRF_GMAC_CON5; 909 + bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(11, 10); 910 + bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(10); 911 + return 0; 912 + 913 + default: 914 + return -EINVAL; 915 + } 916 + } 751 917 752 918 static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv, 753 919 int tx_delay, int rx_delay) ··· 782 924 RK3528_GMAC1_PHY_INTF_SEL_RMII); 783 925 else 784 926 regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, 785 - RK3528_GMAC0_PHY_INTF_SEL_RMII | 786 - RK3528_GMAC0_CLK_RMII_DIV2); 787 - } 788 - 789 - static const struct rk_reg_speed_data rk3528_gmac0_reg_speed_data = { 790 - .rmii_10 = RK3528_GMAC0_CLK_RMII_DIV20, 791 - .rmii_100 = RK3528_GMAC0_CLK_RMII_DIV2, 792 - }; 793 - 794 - static const struct rk_reg_speed_data rk3528_gmac1_reg_speed_data = { 795 - .rgmii_10 = RK3528_GMAC1_CLK_RGMII(GMAC_CLK_DIV50_2_5M), 796 - .rgmii_100 = RK3528_GMAC1_CLK_RGMII(GMAC_CLK_DIV5_25M), 797 - .rgmii_1000 = RK3528_GMAC1_CLK_RGMII(GMAC_CLK_DIV1_125M), 798 - .rmii_10 = RK3528_GMAC1_CLK_RMII_DIV20, 799 - .rmii_100 = RK3528_GMAC1_CLK_RMII_DIV2, 800 - }; 801 - 802 - static int rk3528_set_speed(struct rk_priv_data *bsp_priv, 803 - phy_interface_t interface, int speed) 804 - { 805 - const struct rk_reg_speed_data *rsd; 806 - unsigned int reg; 807 - 808 - if (bsp_priv->id == 1) { 809 - rsd = &rk3528_gmac1_reg_speed_data; 810 - reg = RK3528_VPU_GRF_GMAC_CON5; 811 - } else { 812 - rsd = &rk3528_gmac0_reg_speed_data; 813 - reg = RK3528_VO_GRF_GMAC_CON; 814 - } 815 - 816 - return rk_set_reg_speed(bsp_priv, rsd, reg, interface, speed); 927 + RK3528_GMAC0_PHY_INTF_SEL_RMII); 817 928 } 818 929 819 930 static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv, ··· 814 987 } 815 988 816 989 static const struct rk_gmac_ops rk3528_ops = { 990 + .init = rk3528_init, 817 991 .set_to_rgmii = rk3528_set_to_rgmii, 818 992 .set_to_rmii = rk3528_set_to_rmii, 819 - .set_speed = rk3528_set_speed, 820 993 .set_clock_selection = rk3528_set_clock_selection, 821 994 .integrated_phy_powerup = rk3528_integrated_phy_powerup, 822 995 .integrated_phy_powerdown = rk3528_integrated_phy_powerdown, ··· 834 1007 #define RK3568_GRF_GMAC1_CON1 0x038c 835 1008 836 1009 /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */ 837 - #define RK3568_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val) 838 1010 #define RK3568_GMAC_FLOW_CTRL GRF_BIT(3) 839 1011 #define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 840 1012 #define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) ··· 844 1018 /* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */ 845 1019 #define RK3568_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val) 846 1020 #define RK3568_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val) 1021 + 1022 + static int rk3568_init(struct rk_priv_data *bsp_priv) 1023 + { 1024 + switch (bsp_priv->id) { 1025 + case 0: 1026 + bsp_priv->gmac_grf_reg = RK3568_GRF_GMAC0_CON1; 1027 + return 0; 1028 + 1029 + case 1: 1030 + bsp_priv->gmac_grf_reg = RK3568_GRF_GMAC1_CON1; 1031 + return 0; 1032 + 1033 + default: 1034 + return -EINVAL; 1035 + } 1036 + } 847 1037 848 1038 static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv, 849 1039 int tx_delay, int rx_delay) ··· 876 1034 RK3568_GMAC_CLK_TX_DL_CFG(tx_delay)); 877 1035 878 1036 regmap_write(bsp_priv->grf, con1, 879 - RK3568_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) | 880 1037 RK3568_GMAC_RXCLK_DLY_ENABLE | 881 1038 RK3568_GMAC_TXCLK_DLY_ENABLE); 882 1039 } 883 1040 884 1041 static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv) 885 1042 { 886 - u32 con1; 887 - 888 - con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : 889 - RK3568_GRF_GMAC0_CON1; 890 - regmap_write(bsp_priv->grf, con1, 891 - RK3568_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII)); 892 1043 } 893 1044 894 1045 static const struct rk_gmac_ops rk3568_ops = { 1046 + .init = rk3568_init, 895 1047 .set_to_rgmii = rk3568_set_to_rgmii, 896 1048 .set_to_rmii = rk3568_set_to_rmii, 897 1049 .set_speed = rk_set_clk_mac_speed, 1050 + 1051 + .gmac_phy_intf_sel_mask = GENMASK_U16(6, 4), 1052 + 898 1053 .regs_valid = true, 899 1054 .regs = { 900 1055 0xfe2a0000, /* gmac0 */ ··· 918 1079 #define RK3576_GRF_GMAC_CON0 0X0020 919 1080 #define RK3576_GRF_GMAC_CON1 0X0024 920 1081 921 - #define RK3576_GMAC_RMII_MODE GRF_BIT(3) 922 - #define RK3576_GMAC_RGMII_MODE GRF_CLR_BIT(3) 923 - 924 1082 #define RK3576_GMAC_CLK_SELECT_IO GRF_BIT(7) 925 1083 #define RK3576_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(7) 926 1084 927 - #define RK3576_GMAC_CLK_RMII_DIV2 GRF_BIT(5) 928 - #define RK3576_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(5) 929 - 930 - #define RK3576_GMAC_CLK_RGMII(val) GRF_FIELD_CONST(6, 5, val) 931 - 932 1085 #define RK3576_GMAC_CLK_RMII_GATE GRF_BIT(4) 933 1086 #define RK3576_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(4) 1087 + 1088 + static int rk3576_init(struct rk_priv_data *bsp_priv) 1089 + { 1090 + switch (bsp_priv->id) { 1091 + case 0: 1092 + bsp_priv->gmac_grf_reg = RK3576_GRF_GMAC_CON0; 1093 + bsp_priv->clock_grf_reg = RK3576_GRF_GMAC_CON0; 1094 + return 0; 1095 + 1096 + case 1: 1097 + bsp_priv->gmac_grf_reg = RK3576_GRF_GMAC_CON1; 1098 + bsp_priv->clock_grf_reg = RK3576_GRF_GMAC_CON1; 1099 + return 0; 1100 + 1101 + default: 1102 + return -EINVAL; 1103 + } 1104 + } 934 1105 935 1106 static void rk3576_set_to_rgmii(struct rk_priv_data *bsp_priv, 936 1107 int tx_delay, int rx_delay) 937 1108 { 938 1109 unsigned int offset_con; 939 - 940 - offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 941 - RK3576_GRF_GMAC_CON0; 942 - 943 - regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RGMII_MODE); 944 1110 945 1111 offset_con = bsp_priv->id == 1 ? RK3576_VCCIO0_1_3_IOC_CON4 : 946 1112 RK3576_VCCIO0_1_3_IOC_CON2; ··· 967 1123 968 1124 static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv) 969 1125 { 970 - unsigned int offset_con; 971 - 972 - offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 973 - RK3576_GRF_GMAC_CON0; 974 - 975 - regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RMII_MODE); 976 - } 977 - 978 - static const struct rk_reg_speed_data rk3578_reg_speed_data = { 979 - .rgmii_10 = RK3576_GMAC_CLK_RGMII(GMAC_CLK_DIV50_2_5M), 980 - .rgmii_100 = RK3576_GMAC_CLK_RGMII(GMAC_CLK_DIV5_25M), 981 - .rgmii_1000 = RK3576_GMAC_CLK_RGMII(GMAC_CLK_DIV1_125M), 982 - .rmii_10 = RK3576_GMAC_CLK_RMII_DIV20, 983 - .rmii_100 = RK3576_GMAC_CLK_RMII_DIV2, 984 - }; 985 - 986 - static int rk3576_set_gmac_speed(struct rk_priv_data *bsp_priv, 987 - phy_interface_t interface, int speed) 988 - { 989 - unsigned int offset_con; 990 - 991 - offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 : 992 - RK3576_GRF_GMAC_CON0; 993 - 994 - return rk_set_reg_speed(bsp_priv, &rk3578_reg_speed_data, offset_con, 995 - interface, speed); 996 1126 } 997 1127 998 1128 static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input, ··· 986 1168 } 987 1169 988 1170 static const struct rk_gmac_ops rk3576_ops = { 1171 + .init = rk3576_init, 989 1172 .set_to_rgmii = rk3576_set_to_rgmii, 990 1173 .set_to_rmii = rk3576_set_to_rmii, 991 - .set_speed = rk3576_set_gmac_speed, 992 1174 .set_clock_selection = rk3576_set_clock_selection, 1175 + 1176 + .gmac_rmii_mode_mask = BIT_U16(3), 1177 + 1178 + .clock.gmii_clk_sel_mask = GENMASK_U16(6, 5), 1179 + .clock.rmii_clk_sel_mask = BIT_U16(5), 1180 + 993 1181 .php_grf_required = true, 994 1182 .regs_valid = true, 995 1183 .regs = { ··· 1022 1198 #define RK3588_GRF_GMAC_CON0 0X0008 1023 1199 #define RK3588_GRF_CLK_CON1 0X0070 1024 1200 1025 - #define RK3588_GMAC_PHY_INTF_SEL(id, val) \ 1026 - (GRF_FIELD(5, 3, val) << ((id) * 6)) 1027 - 1028 1201 #define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id)) 1029 1202 #define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id)) 1030 1203 1031 1204 #define RK3588_GMAC_CLK_SELECT_CRU(id) GRF_BIT(5 * (id) + 4) 1032 1205 #define RK3588_GMAC_CLK_SELECT_IO(id) GRF_CLR_BIT(5 * (id) + 4) 1033 1206 1034 - #define RK3588_GMA_CLK_RMII_DIV2(id) GRF_BIT(5 * (id) + 2) 1035 - #define RK3588_GMA_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2) 1036 - 1037 - #define RK3588_GMAC_CLK_RGMII(id, val) \ 1038 - (GRF_FIELD_CONST(3, 2, val) << ((id) * 5)) 1039 - 1040 1207 #define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1) 1041 1208 #define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1) 1209 + 1210 + static int rk3588_init(struct rk_priv_data *bsp_priv) 1211 + { 1212 + switch (bsp_priv->id) { 1213 + case 0: 1214 + bsp_priv->gmac_phy_intf_sel_mask = GENMASK_U16(5, 3); 1215 + bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(3, 2); 1216 + bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(2); 1217 + return 0; 1218 + 1219 + case 1: 1220 + bsp_priv->gmac_phy_intf_sel_mask = GENMASK_U16(11, 9); 1221 + bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(8, 7); 1222 + bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(7); 1223 + return 0; 1224 + 1225 + default: 1226 + return -EINVAL; 1227 + } 1228 + } 1042 1229 1043 1230 static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv, 1044 1231 int tx_delay, int rx_delay) ··· 1058 1223 1059 1224 offset_con = bsp_priv->id == 1 ? RK3588_GRF_GMAC_CON9 : 1060 1225 RK3588_GRF_GMAC_CON8; 1061 - 1062 - regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0, 1063 - RK3588_GMAC_PHY_INTF_SEL(id, PHY_INTF_SEL_RGMII)); 1064 1226 1065 1227 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, 1066 1228 RK3588_GMAC_CLK_RGMII_MODE(id)); ··· 1073 1241 1074 1242 static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv) 1075 1243 { 1076 - regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0, 1077 - RK3588_GMAC_PHY_INTF_SEL(bsp_priv->id, PHY_INTF_SEL_RMII)); 1078 - 1079 1244 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, 1080 1245 RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id)); 1081 - } 1082 - 1083 - static int rk3588_set_gmac_speed(struct rk_priv_data *bsp_priv, 1084 - phy_interface_t interface, int speed) 1085 - { 1086 - unsigned int val = 0, id = bsp_priv->id; 1087 - 1088 - switch (speed) { 1089 - case 10: 1090 - if (interface == PHY_INTERFACE_MODE_RMII) 1091 - val = RK3588_GMA_CLK_RMII_DIV20(id); 1092 - else 1093 - val = RK3588_GMAC_CLK_RGMII(id, GMAC_CLK_DIV50_2_5M); 1094 - break; 1095 - case 100: 1096 - if (interface == PHY_INTERFACE_MODE_RMII) 1097 - val = RK3588_GMA_CLK_RMII_DIV2(id); 1098 - else 1099 - val = RK3588_GMAC_CLK_RGMII(id, GMAC_CLK_DIV5_25M); 1100 - break; 1101 - case 1000: 1102 - if (interface != PHY_INTERFACE_MODE_RMII) 1103 - val = RK3588_GMAC_CLK_RGMII(id, GMAC_CLK_DIV1_125M); 1104 - else 1105 - goto err; 1106 - break; 1107 - default: 1108 - goto err; 1109 - } 1110 - 1111 - regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val); 1112 - 1113 - return 0; 1114 - err: 1115 - return -EINVAL; 1116 1246 } 1117 1247 1118 1248 static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input, ··· 1090 1296 } 1091 1297 1092 1298 static const struct rk_gmac_ops rk3588_ops = { 1299 + .init = rk3588_init, 1093 1300 .set_to_rgmii = rk3588_set_to_rgmii, 1094 1301 .set_to_rmii = rk3588_set_to_rmii, 1095 - .set_speed = rk3588_set_gmac_speed, 1096 1302 .set_clock_selection = rk3588_set_clock_selection, 1303 + 1304 + .gmac_grf_reg_in_php = true, 1305 + .gmac_grf_reg = RK3588_GRF_GMAC_CON0, 1306 + 1307 + .clock_grf_reg_in_php = true, 1308 + .clock_grf_reg = RK3588_GRF_CLK_CON1, 1309 + 1097 1310 .php_grf_required = true, 1098 1311 .regs_valid = true, 1099 1312 .regs = { ··· 1113 1312 #define RV1108_GRF_GMAC_CON0 0X0900 1114 1313 1115 1314 /* RV1108_GRF_GMAC_CON0 */ 1116 - #define RV1108_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val) 1117 1315 #define RV1108_GMAC_FLOW_CTRL GRF_BIT(3) 1118 1316 #define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) 1119 - #define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2) 1120 - #define RV1108_GMAC_SPEED_100M GRF_BIT(2) 1121 - #define RV1108_GMAC_RMII_CLK_25M GRF_BIT(7) 1122 - #define RV1108_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 1123 1317 1124 1318 static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv) 1125 1319 { 1126 - regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0, 1127 - RV1108_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII)); 1128 - } 1129 - 1130 - static const struct rk_reg_speed_data rv1108_reg_speed_data = { 1131 - .rmii_10 = RV1108_GMAC_RMII_CLK_2_5M | RV1108_GMAC_SPEED_10M, 1132 - .rmii_100 = RV1108_GMAC_RMII_CLK_25M | RV1108_GMAC_SPEED_100M, 1133 - }; 1134 - 1135 - static int rv1108_set_speed(struct rk_priv_data *bsp_priv, 1136 - phy_interface_t interface, int speed) 1137 - { 1138 - return rk_set_reg_speed(bsp_priv, &rv1108_reg_speed_data, 1139 - RV1108_GRF_GMAC_CON0, interface, speed); 1140 1320 } 1141 1321 1142 1322 static const struct rk_gmac_ops rv1108_ops = { 1143 1323 .set_to_rmii = rv1108_set_to_rmii, 1144 - .set_speed = rv1108_set_speed, 1324 + 1325 + .gmac_grf_reg = RV1108_GRF_GMAC_CON0, 1326 + .gmac_phy_intf_sel_mask = GENMASK_U16(6, 4), 1327 + 1328 + .clock_grf_reg = RV1108_GRF_GMAC_CON0, 1329 + .clock.rmii_clk_sel_mask = BIT_U16(7), 1330 + .clock.mac_speed_mask = BIT_U16(2), 1145 1331 }; 1146 1332 1147 1333 #define RV1126_GRF_GMAC_CON0 0X0070 ··· 1136 1348 #define RV1126_GRF_GMAC_CON2 0X0078 1137 1349 1138 1350 /* RV1126_GRF_GMAC_CON0 */ 1139 - #define RV1126_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val) 1140 1351 #define RV1126_GMAC_FLOW_CTRL GRF_BIT(7) 1141 1352 #define RV1126_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(7) 1142 1353 #define RV1126_GMAC_M0_RXCLK_DLY_ENABLE GRF_BIT(1) ··· 1158 1371 int tx_delay, int rx_delay) 1159 1372 { 1160 1373 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0, 1161 - RV1126_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) | 1162 1374 RV1126_GMAC_M0_RXCLK_DLY_ENABLE | 1163 1375 RV1126_GMAC_M0_TXCLK_DLY_ENABLE | 1164 1376 RV1126_GMAC_M1_RXCLK_DLY_ENABLE | ··· 1174 1388 1175 1389 static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv) 1176 1390 { 1177 - regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0, 1178 - RV1126_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII)); 1179 1391 } 1180 1392 1181 1393 static const struct rk_gmac_ops rv1126_ops = { 1182 1394 .set_to_rgmii = rv1126_set_to_rgmii, 1183 1395 .set_to_rmii = rv1126_set_to_rmii, 1184 1396 .set_speed = rk_set_clk_mac_speed, 1397 + 1398 + .gmac_grf_reg = RV1126_GRF_GMAC_CON0, 1399 + .gmac_phy_intf_sel_mask = GENMASK_U16(6, 4), 1185 1400 }; 1186 1401 1187 1402 static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat) ··· 1406 1619 1407 1620 bsp_priv->dev = dev; 1408 1621 1622 + /* Set the default phy_intf_sel and RMII mode register parameters. */ 1623 + bsp_priv->gmac_grf_reg = ops->gmac_grf_reg; 1624 + bsp_priv->gmac_phy_intf_sel_mask = ops->gmac_phy_intf_sel_mask; 1625 + bsp_priv->gmac_rmii_mode_mask = ops->gmac_rmii_mode_mask; 1626 + 1627 + /* Set the default clock control register related parameters */ 1628 + bsp_priv->clock_grf_reg = ops->clock_grf_reg; 1629 + bsp_priv->clock = ops->clock; 1630 + 1409 1631 if (ops->init) { 1410 1632 ret = ops->init(bsp_priv); 1411 1633 if (ret) { ··· 1451 1655 static int rk_gmac_powerup(struct rk_priv_data *bsp_priv) 1452 1656 { 1453 1657 struct device *dev = bsp_priv->dev; 1658 + u32 val; 1454 1659 int ret; 1660 + u8 intf; 1455 1661 1456 1662 ret = rk_gmac_check_ops(bsp_priv); 1457 1663 if (ret) 1458 1664 return ret; 1459 1665 1666 + ret = rk_get_phy_intf_sel(bsp_priv->phy_iface); 1667 + if (ret < 0) 1668 + return ret; 1669 + 1670 + intf = ret; 1671 + 1460 1672 ret = gmac_clk_enable(bsp_priv, true); 1461 1673 if (ret) 1462 1674 return ret; 1675 + 1676 + if (bsp_priv->gmac_phy_intf_sel_mask || 1677 + bsp_priv->gmac_rmii_mode_mask) { 1678 + /* If defined, encode the phy_intf_sel value */ 1679 + val = rk_encode_wm16(intf, bsp_priv->gmac_phy_intf_sel_mask); 1680 + 1681 + /* If defined, encode the RMII mode mask setting. */ 1682 + val |= rk_encode_wm16(intf == PHY_INTF_SEL_RMII, 1683 + bsp_priv->gmac_rmii_mode_mask); 1684 + 1685 + ret = rk_write_gmac_grf_reg(bsp_priv, val); 1686 + if (ret < 0) { 1687 + gmac_clk_enable(bsp_priv, false); 1688 + return ret; 1689 + } 1690 + } 1463 1691 1464 1692 /*rmii or rgmii*/ 1465 1693 switch (bsp_priv->phy_iface) { ··· 1553 1733 phy_interface_t interface, int speed) 1554 1734 { 1555 1735 struct rk_priv_data *bsp_priv = bsp_priv_; 1736 + int ret = -EINVAL; 1737 + bool is_100m; 1738 + u32 val; 1556 1739 1557 - if (bsp_priv->ops->set_speed) 1558 - return bsp_priv->ops->set_speed(bsp_priv, interface, speed); 1740 + if (bsp_priv->ops->set_speed) { 1741 + ret = bsp_priv->ops->set_speed(bsp_priv, interface, speed); 1742 + if (ret < 0) 1743 + return ret; 1744 + } 1559 1745 1560 - return -EINVAL; 1746 + if (phy_interface_mode_is_rgmii(interface) && 1747 + bsp_priv->clock.gmii_clk_sel_mask) { 1748 + ret = rk_gmac_rgmii_clk_div(speed); 1749 + if (ret < 0) 1750 + return ret; 1751 + 1752 + val = rk_encode_wm16(ret, bsp_priv->clock.gmii_clk_sel_mask); 1753 + 1754 + ret = rk_write_clock_grf_reg(bsp_priv, val); 1755 + } else if (interface == PHY_INTERFACE_MODE_RMII && 1756 + (bsp_priv->clock.rmii_clk_sel_mask || 1757 + bsp_priv->clock.mac_speed_mask)) { 1758 + is_100m = speed == SPEED_100; 1759 + val = rk_encode_wm16(is_100m, bsp_priv->clock.mac_speed_mask) | 1760 + rk_encode_wm16(is_100m, 1761 + bsp_priv->clock.rmii_clk_sel_mask); 1762 + 1763 + ret = rk_write_clock_grf_reg(bsp_priv, val); 1764 + } 1765 + 1766 + return ret; 1561 1767 } 1562 1768 1563 1769 static int rk_gmac_suspend(struct device *dev, void *bsp_priv_)