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gpu: nova-core: falcon: Add support to check if RISC-V is active

Add definition for RISCV_CPUCTL register and use it in a new falcon API
to check if the RISC-V core of a Falcon is active. It is required by
the sequencer to know if the GSP's RISCV processor is active.

Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Message-ID: <20251110-gsp_boot-v9-13-8ae4058e3c0e@nvidia.com>

authored by

Joel Fernandes and committed by
Alexandre Courbot bb58d1ae 19b0a6e7

+15 -1
+9
drivers/gpu/nova-core/falcon.rs
··· 612 612 self.hal 613 613 .signature_reg_fuse_version(self, bar, engine_id_mask, ucode_id) 614 614 } 615 + 616 + /// Check if the RISC-V core is active. 617 + /// 618 + /// Returns `true` if the RISC-V core is active, `false` otherwise. 619 + #[expect(unused)] 620 + pub(crate) fn is_riscv_active(&self, bar: &Bar0) -> bool { 621 + let cpuctl = regs::NV_PRISCV_RISCV_CPUCTL::read(bar, &E::ID); 622 + cpuctl.active_stat() 623 + } 615 624 }
+6 -1
drivers/gpu/nova-core/regs.rs
··· 339 339 340 340 // PRISCV 341 341 342 - register!(NV_PRISCV_RISCV_BCR_CTRL @ PFalconBase[0x00001668] { 342 + register!(NV_PRISCV_RISCV_CPUCTL @ PFalcon2Base[0x00000388] { 343 + 0:0 halted as bool; 344 + 7:7 active_stat as bool; 345 + }); 346 + 347 + register!(NV_PRISCV_RISCV_BCR_CTRL @ PFalcon2Base[0x00000668] { 343 348 0:0 valid as bool; 344 349 4:4 core_select as bool => PeregrineCoreSelect; 345 350 8:8 br_fetch as bool;