Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (27 commits)
gpu/stub: fix acpi_video build error, fix stub kconfig dependencies
drm/radeon/kms: dynamically allocate power state space
drm/radeon/kms: fix s/r issues with bios scratch regs
agp: ensure GART has an address before enabling it
Revert "agp: AMD AGP is used on UP1100 & UP1500 alpha boxen"
amd-k7-agp: remove non-x86 code
drm/radeon/kms/evergreen: always set certain VGT regs at CP init
drm/radeon/kms: add updated ib_execute function for evergreen
drm/radeon: remove 0x4243 pci id
drm/radeon/kms: Enable new pll calculation for avivo+ asics
drm/radeon/kms: add new pll algo for avivo asics
drm/radeon/kms: add pll debugging output
drm/radeon/kms: switch back to min->max pll post divider iteration
drm/radeon/kms: rv6xx+ thermal sensor fixes
drm/nv50: fix display on 0x50
drm/nouveau: correctly pair hwmon_init and hwmon_fini
drm/i915: Only bind to function 0 of the PCI device
drm/i915: Suppress spurious vblank interrupts
drm: Avoid leak of adjusted mode along quick set_mode paths
drm: Simplify and defend later checks when disabling a crtc
...
+398
-158
+1
-1
drivers/char/agp/Kconfig
+1
-1
drivers/char/agp/Kconfig
-19
drivers/char/agp/amd-k7-agp.c
-19
drivers/char/agp/amd-k7-agp.c
···
41
41
if (page_map->real == NULL)
42
42
return -ENOMEM;
43
43
44
-
#ifndef CONFIG_X86
45
-
SetPageReserved(virt_to_page(page_map->real));
46
-
global_cache_flush();
47
-
page_map->remapped = ioremap_nocache(virt_to_phys(page_map->real),
48
-
PAGE_SIZE);
49
-
if (page_map->remapped == NULL) {
50
-
ClearPageReserved(virt_to_page(page_map->real));
51
-
free_page((unsigned long) page_map->real);
52
-
page_map->real = NULL;
53
-
return -ENOMEM;
54
-
}
55
-
global_cache_flush();
56
-
#else
57
44
set_memory_uc((unsigned long)page_map->real, 1);
58
45
page_map->remapped = page_map->real;
59
-
#endif
60
46
61
47
for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) {
62
48
writel(agp_bridge->scratch_page, page_map->remapped+i);
···
54
68
55
69
static void amd_free_page_map(struct amd_page_map *page_map)
56
70
{
57
-
#ifndef CONFIG_X86
58
-
iounmap(page_map->remapped);
59
-
ClearPageReserved(virt_to_page(page_map->real));
60
-
#else
61
71
set_memory_wb((unsigned long)page_map->real, 1);
62
-
#endif
63
72
free_page((unsigned long) page_map->real);
64
73
}
65
74
+16
-11
drivers/char/agp/intel-agp.c
+16
-11
drivers/char/agp/intel-agp.c
···
774
774
dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
775
775
776
776
/*
777
-
* If the device has not been properly setup, the following will catch
778
-
* the problem and should stop the system from crashing.
779
-
* 20030610 - hamish@zot.org
780
-
*/
781
-
if (pci_enable_device(pdev)) {
782
-
dev_err(&pdev->dev, "can't enable PCI device\n");
783
-
agp_put_bridge(bridge);
784
-
return -ENODEV;
785
-
}
786
-
787
-
/*
788
777
* The following fixes the case where the BIOS has "forgotten" to
789
778
* provide an address range for the GART.
790
779
* 20030610 - hamish@zot.org
780
+
* This happens before pci_enable_device() intentionally;
781
+
* calling pci_enable_device() before assigning the resource
782
+
* will result in the GART being disabled on machines with such
783
+
* BIOSs (the GART ends up with a BAR starting at 0, which
784
+
* conflicts a lot of other devices).
791
785
*/
792
786
r = &pdev->resource[0];
793
787
if (!r->start && r->end) {
···
790
796
agp_put_bridge(bridge);
791
797
return -ENODEV;
792
798
}
799
+
}
800
+
801
+
/*
802
+
* If the device has not been properly setup, the following will catch
803
+
* the problem and should stop the system from crashing.
804
+
* 20030610 - hamish@zot.org
805
+
*/
806
+
if (pci_enable_device(pdev)) {
807
+
dev_err(&pdev->dev, "can't enable PCI device\n");
808
+
agp_put_bridge(bridge);
809
+
return -ENODEV;
793
810
}
794
811
795
812
/* Fill in the mode register */
+20
drivers/gpu/drm/drm_crtc.c
+20
drivers/gpu/drm/drm_crtc.c
···
2674
2674
mutex_unlock(&dev->mode_config.mutex);
2675
2675
return ret;
2676
2676
}
2677
+
2678
+
void drm_mode_config_reset(struct drm_device *dev)
2679
+
{
2680
+
struct drm_crtc *crtc;
2681
+
struct drm_encoder *encoder;
2682
+
struct drm_connector *connector;
2683
+
2684
+
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2685
+
if (crtc->funcs->reset)
2686
+
crtc->funcs->reset(crtc);
2687
+
2688
+
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
2689
+
if (encoder->funcs->reset)
2690
+
encoder->funcs->reset(encoder);
2691
+
2692
+
list_for_each_entry(connector, &dev->mode_config.connector_list, head)
2693
+
if (connector->funcs->reset)
2694
+
connector->funcs->reset(connector);
2695
+
}
2696
+
EXPORT_SYMBOL(drm_mode_config_reset);
+11
-10
drivers/gpu/drm/drm_crtc_helper.c
+11
-10
drivers/gpu/drm/drm_crtc_helper.c
···
343
343
struct drm_encoder *encoder;
344
344
bool ret = true;
345
345
346
-
adjusted_mode = drm_mode_duplicate(dev, mode);
347
-
348
346
crtc->enabled = drm_helper_crtc_in_use(crtc);
349
-
350
347
if (!crtc->enabled)
351
348
return true;
349
+
350
+
adjusted_mode = drm_mode_duplicate(dev, mode);
352
351
353
352
saved_hwmode = crtc->hwmode;
354
353
saved_mode = crtc->mode;
···
436
437
*/
437
438
drm_calc_timestamping_constants(crtc);
438
439
439
-
/* XXX free adjustedmode */
440
-
drm_mode_destroy(dev, adjusted_mode);
441
440
/* FIXME: add subpixel order */
442
441
done:
442
+
drm_mode_destroy(dev, adjusted_mode);
443
443
if (!ret) {
444
444
crtc->hwmode = saved_hwmode;
445
445
crtc->mode = saved_mode;
···
495
497
496
498
crtc_funcs = set->crtc->helper_private;
497
499
500
+
if (!set->mode)
501
+
set->fb = NULL;
502
+
498
503
if (set->fb) {
499
504
DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
500
505
set->crtc->base.id, set->fb->base.id,
501
506
(int)set->num_connectors, set->x, set->y);
502
507
} else {
503
-
DRM_DEBUG_KMS("[CRTC:%d] [NOFB] #connectors=%d (x y) (%i %i)\n",
504
-
set->crtc->base.id, (int)set->num_connectors,
505
-
set->x, set->y);
508
+
DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
509
+
set->mode = NULL;
510
+
set->num_connectors = 0;
506
511
}
507
512
508
513
dev = set->crtc->dev;
···
650
649
mode_changed = true;
651
650
652
651
if (mode_changed) {
653
-
set->crtc->enabled = (set->mode != NULL);
654
-
if (set->mode != NULL) {
652
+
set->crtc->enabled = drm_helper_crtc_in_use(set->crtc);
653
+
if (set->crtc->enabled) {
655
654
DRM_DEBUG_KMS("attempting to set mode from"
656
655
" userspace\n");
657
656
drm_mode_debug_printmodeline(set->mode);
+4
-3
drivers/gpu/drm/drm_irq.c
+4
-3
drivers/gpu/drm/drm_irq.c
···
1250
1250
* Drivers should call this routine in their vblank interrupt handlers to
1251
1251
* update the vblank counter and send any signals that may be pending.
1252
1252
*/
1253
-
void drm_handle_vblank(struct drm_device *dev, int crtc)
1253
+
bool drm_handle_vblank(struct drm_device *dev, int crtc)
1254
1254
{
1255
1255
u32 vblcount;
1256
1256
s64 diff_ns;
···
1258
1258
unsigned long irqflags;
1259
1259
1260
1260
if (!dev->num_crtcs)
1261
-
return;
1261
+
return false;
1262
1262
1263
1263
/* Need timestamp lock to prevent concurrent execution with
1264
1264
* vblank enable/disable, as this would cause inconsistent
···
1269
1269
/* Vblank irq handling disabled. Nothing to do. */
1270
1270
if (!dev->vblank_enabled[crtc]) {
1271
1271
spin_unlock_irqrestore(&dev->vblank_time_lock, irqflags);
1272
-
return;
1272
+
return false;
1273
1273
}
1274
1274
1275
1275
/* Fetch corresponding timestamp for this vblank interval from
···
1311
1311
drm_handle_vblank_events(dev, crtc);
1312
1312
1313
1313
spin_unlock_irqrestore(&dev->vblank_time_lock, irqflags);
1314
+
return true;
1314
1315
}
1315
1316
EXPORT_SYMBOL(drm_handle_vblank);
+10
drivers/gpu/drm/i915/i915_drv.c
+10
drivers/gpu/drm/i915/i915_drv.c
···
354
354
error = i915_gem_init_ringbuffer(dev);
355
355
mutex_unlock(&dev->struct_mutex);
356
356
357
+
drm_mode_config_reset(dev);
357
358
drm_irq_install(dev);
358
359
359
360
/* Resume the modeset for every activated CRTC */
···
543
542
544
543
mutex_unlock(&dev->struct_mutex);
545
544
drm_irq_uninstall(dev);
545
+
drm_mode_config_reset(dev);
546
546
drm_irq_install(dev);
547
547
mutex_lock(&dev->struct_mutex);
548
548
}
···
568
566
static int __devinit
569
567
i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
570
568
{
569
+
/* Only bind to function 0 of the device. Early generations
570
+
* used function 1 as a placeholder for multi-head. This causes
571
+
* us confusion instead, especially on the systems where both
572
+
* functions have the same PCI-ID!
573
+
*/
574
+
if (PCI_FUNC(pdev->devfn))
575
+
return -ENODEV;
576
+
571
577
return drm_get_pci_dev(pdev, ent, &driver);
572
578
}
573
579
+4
-4
drivers/gpu/drm/i915/i915_irq.c
+4
-4
drivers/gpu/drm/i915/i915_irq.c
···
1196
1196
intel_finish_page_flip_plane(dev, 1);
1197
1197
}
1198
1198
1199
-
if (pipea_stats & vblank_status) {
1199
+
if (pipea_stats & vblank_status &&
1200
+
drm_handle_vblank(dev, 0)) {
1200
1201
vblank++;
1201
-
drm_handle_vblank(dev, 0);
1202
1202
if (!dev_priv->flip_pending_is_done) {
1203
1203
i915_pageflip_stall_check(dev, 0);
1204
1204
intel_finish_page_flip(dev, 0);
1205
1205
}
1206
1206
}
1207
1207
1208
-
if (pipeb_stats & vblank_status) {
1208
+
if (pipeb_stats & vblank_status &&
1209
+
drm_handle_vblank(dev, 1)) {
1209
1210
vblank++;
1210
-
drm_handle_vblank(dev, 1);
1211
1211
if (!dev_priv->flip_pending_is_done) {
1212
1212
i915_pageflip_stall_check(dev, 1);
1213
1213
intel_finish_page_flip(dev, 1);
+10
drivers/gpu/drm/i915/intel_crt.c
+10
drivers/gpu/drm/i915/intel_crt.c
···
535
535
return 0;
536
536
}
537
537
538
+
static void intel_crt_reset(struct drm_connector *connector)
539
+
{
540
+
struct drm_device *dev = connector->dev;
541
+
struct intel_crt *crt = intel_attached_crt(connector);
542
+
543
+
if (HAS_PCH_SPLIT(dev))
544
+
crt->force_hotplug_required = 1;
545
+
}
546
+
538
547
/*
539
548
* Routines for controlling stuff on the analog port
540
549
*/
···
557
548
};
558
549
559
550
static const struct drm_connector_funcs intel_crt_connector_funcs = {
551
+
.reset = intel_crt_reset,
560
552
.dpms = drm_helper_connector_dpms,
561
553
.detect = intel_crt_detect,
562
554
.fill_modes = drm_helper_probe_single_connector_modes,
+14
-3
drivers/gpu/drm/i915/intel_display.c
+14
-3
drivers/gpu/drm/i915/intel_display.c
···
5551
5551
return ret;
5552
5552
}
5553
5553
5554
+
static void intel_crtc_reset(struct drm_crtc *crtc)
5555
+
{
5556
+
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5557
+
5558
+
/* Reset flags back to the 'unknown' status so that they
5559
+
* will be correctly set on the initial modeset.
5560
+
*/
5561
+
intel_crtc->cursor_addr = 0;
5562
+
intel_crtc->dpms_mode = -1;
5563
+
intel_crtc->active = true; /* force the pipe off on setup_init_config */
5564
+
}
5565
+
5554
5566
static struct drm_crtc_helper_funcs intel_helper_funcs = {
5555
5567
.dpms = intel_crtc_dpms,
5556
5568
.mode_fixup = intel_crtc_mode_fixup,
···
5574
5562
};
5575
5563
5576
5564
static const struct drm_crtc_funcs intel_crtc_funcs = {
5565
+
.reset = intel_crtc_reset,
5577
5566
.cursor_set = intel_crtc_cursor_set,
5578
5567
.cursor_move = intel_crtc_cursor_move,
5579
5568
.gamma_set = intel_crtc_gamma_set,
···
5665
5652
dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5666
5653
dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5667
5654
5668
-
intel_crtc->cursor_addr = 0;
5669
-
intel_crtc->dpms_mode = -1;
5670
-
intel_crtc->active = true; /* force the pipe off on setup_init_config */
5655
+
intel_crtc_reset(&intel_crtc->base);
5671
5656
5672
5657
if (HAS_PCH_SPLIT(dev)) {
5673
5658
intel_helper_funcs.prepare = ironlake_crtc_prepare;
+23
-23
drivers/gpu/drm/i915/intel_sdvo.c
+23
-23
drivers/gpu/drm/i915/intel_sdvo.c
···
473
473
return false;
474
474
}
475
475
476
-
i = 3;
477
-
while (status == SDVO_CMD_STATUS_PENDING && i--) {
478
-
if (!intel_sdvo_read_byte(intel_sdvo,
479
-
SDVO_I2C_CMD_STATUS,
480
-
&status))
481
-
return false;
482
-
}
483
-
if (status != SDVO_CMD_STATUS_SUCCESS) {
484
-
DRM_DEBUG_KMS("command returns response %s [%d]\n",
485
-
status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP ? cmd_status_names[status] : "???",
486
-
status);
487
-
return false;
488
-
}
489
-
490
476
return true;
491
477
}
492
478
···
483
497
u8 status;
484
498
int i;
485
499
500
+
DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
501
+
486
502
/*
487
503
* The documentation states that all commands will be
488
504
* processed within 15µs, and that we need only poll
···
493
505
*
494
506
* Check 5 times in case the hardware failed to read the docs.
495
507
*/
496
-
do {
508
+
if (!intel_sdvo_read_byte(intel_sdvo,
509
+
SDVO_I2C_CMD_STATUS,
510
+
&status))
511
+
goto log_fail;
512
+
513
+
while (status == SDVO_CMD_STATUS_PENDING && retry--) {
514
+
udelay(15);
497
515
if (!intel_sdvo_read_byte(intel_sdvo,
498
516
SDVO_I2C_CMD_STATUS,
499
517
&status))
500
-
return false;
501
-
} while (status == SDVO_CMD_STATUS_PENDING && --retry);
518
+
goto log_fail;
519
+
}
502
520
503
-
DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
504
521
if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
505
522
DRM_LOG_KMS("(%s)", cmd_status_names[status]);
506
523
else
···
526
533
return true;
527
534
528
535
log_fail:
529
-
DRM_LOG_KMS("\n");
536
+
DRM_LOG_KMS("... failed\n");
530
537
return false;
531
538
}
532
539
···
543
550
static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
544
551
u8 ddc_bus)
545
552
{
553
+
/* This must be the immediately preceding write before the i2c xfer */
546
554
return intel_sdvo_write_cmd(intel_sdvo,
547
555
SDVO_CMD_SET_CONTROL_BUS_SWITCH,
548
556
&ddc_bus, 1);
···
551
557
552
558
static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
553
559
{
554
-
return intel_sdvo_write_cmd(intel_sdvo, cmd, data, len);
560
+
if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
561
+
return false;
562
+
563
+
return intel_sdvo_read_response(intel_sdvo, NULL, 0);
555
564
}
556
565
557
566
static bool
···
856
859
857
860
intel_dip_infoframe_csum(&avi_if);
858
861
859
-
if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_INDEX,
862
+
if (!intel_sdvo_set_value(intel_sdvo,
863
+
SDVO_CMD_SET_HBUF_INDEX,
860
864
set_buf_index, 2))
861
865
return false;
862
866
863
867
for (i = 0; i < sizeof(avi_if); i += 8) {
864
-
if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_DATA,
868
+
if (!intel_sdvo_set_value(intel_sdvo,
869
+
SDVO_CMD_SET_HBUF_DATA,
865
870
data, 8))
866
871
return false;
867
872
data++;
868
873
}
869
874
870
-
return intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_TXRATE,
875
+
return intel_sdvo_set_value(intel_sdvo,
876
+
SDVO_CMD_SET_HBUF_TXRATE,
871
877
&tx_rate, 1);
872
878
}
873
879
+1
-1
drivers/gpu/drm/nouveau/nouveau_pm.c
+1
-1
drivers/gpu/drm/nouveau/nouveau_pm.c
+1
-2
drivers/gpu/drm/nouveau/nv50_evo.c
+1
-2
drivers/gpu/drm/nouveau/nv50_evo.c
+16
-2
drivers/gpu/drm/radeon/atombios_crtc.c
+16
-2
drivers/gpu/drm/radeon/atombios_crtc.c
···
555
555
dp_clock = dig_connector->dp_clock;
556
556
}
557
557
}
558
+
/* this might work properly with the new pll algo */
558
559
#if 0 /* doesn't work properly on some laptops */
559
560
/* use recommended ref_div for ss */
560
561
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
···
573
572
adjusted_clock = mode->clock * 2;
574
573
if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
575
574
pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
575
+
/* rv515 needs more testing with this option */
576
+
if (rdev->family != CHIP_RV515) {
577
+
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
578
+
pll->flags |= RADEON_PLL_IS_LCD;
579
+
}
576
580
} else {
577
581
if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
578
582
pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
···
957
951
/* adjust pixel clock as needed */
958
952
adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss);
959
953
960
-
radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
961
-
&ref_div, &post_div);
954
+
/* rv515 seems happier with the old algo */
955
+
if (rdev->family == CHIP_RV515)
956
+
radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
957
+
&ref_div, &post_div);
958
+
else if (ASIC_IS_AVIVO(rdev))
959
+
radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
960
+
&ref_div, &post_div);
961
+
else
962
+
radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
963
+
&ref_div, &post_div);
962
964
963
965
atombios_crtc_program_ss(crtc, ATOM_DISABLE, radeon_crtc->pll_id, &ss);
964
966
+31
-10
drivers/gpu/drm/radeon/evergreen.c
+31
-10
drivers/gpu/drm/radeon/evergreen.c
···
97
97
}
98
98
99
99
/* get temperature in millidegrees */
100
-
u32 evergreen_get_temp(struct radeon_device *rdev)
100
+
int evergreen_get_temp(struct radeon_device *rdev)
101
101
{
102
102
u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
103
103
ASIC_T_SHIFT;
104
104
u32 actual_temp = 0;
105
105
106
-
if ((temp >> 10) & 1)
107
-
actual_temp = 0;
108
-
else if ((temp >> 9) & 1)
106
+
if (temp & 0x400)
107
+
actual_temp = -256;
108
+
else if (temp & 0x200)
109
109
actual_temp = 255;
110
-
else
111
-
actual_temp = (temp >> 1) & 0xff;
110
+
else if (temp & 0x100) {
111
+
actual_temp = temp & 0x1ff;
112
+
actual_temp |= ~0x1ff;
113
+
} else
114
+
actual_temp = temp & 0xff;
112
115
113
-
return actual_temp * 1000;
116
+
return (actual_temp * 1000) / 2;
114
117
}
115
118
116
-
u32 sumo_get_temp(struct radeon_device *rdev)
119
+
int sumo_get_temp(struct radeon_device *rdev)
117
120
{
118
121
u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
119
-
u32 actual_temp = (temp >> 1) & 0xff;
122
+
int actual_temp = temp - 49;
120
123
121
124
return actual_temp * 1000;
122
125
}
···
1185
1182
/*
1186
1183
* CP.
1187
1184
*/
1185
+
void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1186
+
{
1187
+
/* set to DX10/11 mode */
1188
+
radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0));
1189
+
radeon_ring_write(rdev, 1);
1190
+
/* FIXME: implement */
1191
+
radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1192
+
radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
1193
+
radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
1194
+
radeon_ring_write(rdev, ib->length_dw);
1195
+
}
1196
+
1188
1197
1189
1198
static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1190
1199
{
···
1248
1233
cp_me = 0xff;
1249
1234
WREG32(CP_ME_CNTL, cp_me);
1250
1235
1251
-
r = radeon_ring_lock(rdev, evergreen_default_size + 15);
1236
+
r = radeon_ring_lock(rdev, evergreen_default_size + 19);
1252
1237
if (r) {
1253
1238
DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1254
1239
return r;
···
1280
1265
radeon_ring_write(rdev, 0xffffffff);
1281
1266
radeon_ring_write(rdev, 0xffffffff);
1282
1267
radeon_ring_write(rdev, 0xffffffff);
1268
+
1269
+
radeon_ring_write(rdev, 0xc0026900);
1270
+
radeon_ring_write(rdev, 0x00000316);
1271
+
radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1272
+
radeon_ring_write(rdev, 0x00000010); /* */
1283
1273
1284
1274
radeon_ring_unlock_commit(rdev);
1285
1275
···
2092
2072
WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2093
2073
2094
2074
WREG32(VGT_GS_VERTEX_REUSE, 16);
2075
+
WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
2095
2076
WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2096
2077
2097
2078
WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
+7
-3
drivers/gpu/drm/radeon/evergreen_blit_kms.c
+7
-3
drivers/gpu/drm/radeon/evergreen_blit_kms.c
···
232
232
233
233
}
234
234
235
-
/* emits 34 */
235
+
/* emits 36 */
236
236
static void
237
237
set_default_state(struct radeon_device *rdev)
238
238
{
···
499
499
radeon_ring_write(rdev, 0x00000000);
500
500
radeon_ring_write(rdev, 0x00000000);
501
501
502
+
/* set to DX10/11 mode */
503
+
radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0));
504
+
radeon_ring_write(rdev, 1);
505
+
502
506
/* emit an IB pointing at default state */
503
507
dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
504
508
gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
···
683
679
/* calculate number of loops correctly */
684
680
ring_size = num_loops * dwords_per_loop;
685
681
/* set default + shaders */
686
-
ring_size += 50; /* shaders + def state */
682
+
ring_size += 52; /* shaders + def state */
687
683
ring_size += 10; /* fence emit for VB IB */
688
684
ring_size += 5; /* done copy */
689
685
ring_size += 10; /* fence emit for done copy */
···
691
687
if (r)
692
688
return r;
693
689
694
-
set_default_state(rdev); /* 34 */
690
+
set_default_state(rdev); /* 36 */
695
691
set_shaders(rdev); /* 16 */
696
692
return 0;
697
693
}
+2
drivers/gpu/drm/radeon/evergreend.h
+2
drivers/gpu/drm/radeon/evergreend.h
···
240
240
#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
241
241
#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
242
242
#define PA_SC_LINE_STIPPLE 0x28A0C
243
+
#define PA_SU_LINE_STIPPLE_VALUE 0x8A60
243
244
#define PA_SC_LINE_STIPPLE_STATE 0x8B10
244
245
245
246
#define SCRATCH_REG0 0x8500
···
653
652
#define PACKET3_DISPATCH_DIRECT 0x15
654
653
#define PACKET3_DISPATCH_INDIRECT 0x16
655
654
#define PACKET3_INDIRECT_BUFFER_END 0x17
655
+
#define PACKET3_MODE_CONTROL 0x18
656
656
#define PACKET3_SET_PREDICATION 0x20
657
657
#define PACKET3_REG_RMW 0x21
658
658
#define PACKET3_COND_EXEC 0x22
+6
-2
drivers/gpu/drm/radeon/r600.c
+6
-2
drivers/gpu/drm/radeon/r600.c
···
97
97
static void r600_pcie_gen2_enable(struct radeon_device *rdev);
98
98
99
99
/* get temperature in millidegrees */
100
-
u32 rv6xx_get_temp(struct radeon_device *rdev)
100
+
int rv6xx_get_temp(struct radeon_device *rdev)
101
101
{
102
102
u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
103
103
ASIC_T_SHIFT;
104
+
int actual_temp = temp & 0xff;
104
105
105
-
return temp * 1000;
106
+
if (temp & 0x100)
107
+
actual_temp -= 256;
108
+
109
+
return actual_temp * 1000;
106
110
}
107
111
108
112
void r600_pm_get_dynpm_state(struct radeon_device *rdev)
+5
-6
drivers/gpu/drm/radeon/radeon.h
+5
-6
drivers/gpu/drm/radeon/radeon.h
···
179
179
void radeon_atombios_get_power_modes(struct radeon_device *rdev);
180
180
void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level);
181
181
void rs690_pm_info(struct radeon_device *rdev);
182
-
extern u32 rv6xx_get_temp(struct radeon_device *rdev);
183
-
extern u32 rv770_get_temp(struct radeon_device *rdev);
184
-
extern u32 evergreen_get_temp(struct radeon_device *rdev);
185
-
extern u32 sumo_get_temp(struct radeon_device *rdev);
182
+
extern int rv6xx_get_temp(struct radeon_device *rdev);
183
+
extern int rv770_get_temp(struct radeon_device *rdev);
184
+
extern int evergreen_get_temp(struct radeon_device *rdev);
185
+
extern int sumo_get_temp(struct radeon_device *rdev);
186
186
187
187
/*
188
188
* Fences.
···
812
812
fixed20_12 sclk;
813
813
fixed20_12 mclk;
814
814
fixed20_12 needed_bandwidth;
815
-
/* XXX: use a define for num power modes */
816
-
struct radeon_power_state power_state[8];
815
+
struct radeon_power_state *power_state;
817
816
/* number of valid power states */
818
817
int num_power_states;
819
818
int current_power_state_index;
+3
-3
drivers/gpu/drm/radeon/radeon_asic.c
+3
-3
drivers/gpu/drm/radeon/radeon_asic.c
···
759
759
.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
760
760
.gart_set_page = &rs600_gart_set_page,
761
761
.ring_test = &r600_ring_test,
762
-
.ring_ib_execute = &r600_ring_ib_execute,
762
+
.ring_ib_execute = &evergreen_ring_ib_execute,
763
763
.irq_set = &evergreen_irq_set,
764
764
.irq_process = &evergreen_irq_process,
765
765
.get_vblank_counter = &evergreen_get_vblank_counter,
···
805
805
.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
806
806
.gart_set_page = &rs600_gart_set_page,
807
807
.ring_test = &r600_ring_test,
808
-
.ring_ib_execute = &r600_ring_ib_execute,
808
+
.ring_ib_execute = &evergreen_ring_ib_execute,
809
809
.irq_set = &evergreen_irq_set,
810
810
.irq_process = &evergreen_irq_process,
811
811
.get_vblank_counter = &evergreen_get_vblank_counter,
···
848
848
.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
849
849
.gart_set_page = &rs600_gart_set_page,
850
850
.ring_test = &r600_ring_test,
851
-
.ring_ib_execute = &r600_ring_ib_execute,
851
+
.ring_ib_execute = &evergreen_ring_ib_execute,
852
852
.irq_set = &evergreen_irq_set,
853
853
.irq_process = &evergreen_irq_process,
854
854
.get_vblank_counter = &evergreen_get_vblank_counter,
+1
drivers/gpu/drm/radeon/radeon_asic.h
+1
drivers/gpu/drm/radeon/radeon_asic.h
···
355
355
bool evergreen_gpu_is_lockup(struct radeon_device *rdev);
356
356
int evergreen_asic_reset(struct radeon_device *rdev);
357
357
void evergreen_bandwidth_update(struct radeon_device *rdev);
358
+
void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
358
359
int evergreen_copy_blit(struct radeon_device *rdev,
359
360
uint64_t src_offset, uint64_t dst_offset,
360
361
unsigned num_pages, struct radeon_fence *fence);
+33
-26
drivers/gpu/drm/radeon/radeon_atombios.c
+33
-26
drivers/gpu/drm/radeon/radeon_atombios.c
···
1163
1163
p1pll->pll_out_min = 64800;
1164
1164
else
1165
1165
p1pll->pll_out_min = 20000;
1166
-
} else if (p1pll->pll_out_min > 64800) {
1167
-
/* Limiting the pll output range is a good thing generally as
1168
-
* it limits the number of possible pll combinations for a given
1169
-
* frequency presumably to the ones that work best on each card.
1170
-
* However, certain duallink DVI monitors seem to like
1171
-
* pll combinations that would be limited by this at least on
1172
-
* pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
1173
-
* family.
1174
-
*/
1175
-
p1pll->pll_out_min = 64800;
1176
1166
}
1177
1167
1178
1168
p1pll->pll_in_min =
···
1977
1987
num_modes = power_info->info.ucNumOfPowerModeEntries;
1978
1988
if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1979
1989
num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1990
+
rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
1991
+
if (!rdev->pm.power_state)
1992
+
return state_index;
1980
1993
/* last mode is usually default, array is low to high */
1981
1994
for (i = 0; i < num_modes; i++) {
1982
1995
rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
···
2331
2338
power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2332
2339
2333
2340
radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2341
+
rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2342
+
power_info->pplib.ucNumStates, GFP_KERNEL);
2343
+
if (!rdev->pm.power_state)
2344
+
return state_index;
2334
2345
/* first mode is usually default, followed by low to high */
2335
2346
for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2336
2347
mode_index = 0;
···
2415
2418
non_clock_info_array = (struct NonClockInfoArray *)
2416
2419
(mode_info->atom_context->bios + data_offset +
2417
2420
power_info->pplib.usNonClockInfoArrayOffset);
2421
+
rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2422
+
state_array->ucNumEntries, GFP_KERNEL);
2423
+
if (!rdev->pm.power_state)
2424
+
return state_index;
2418
2425
for (i = 0; i < state_array->ucNumEntries; i++) {
2419
2426
mode_index = 0;
2420
2427
power_state = (union pplib_power_state *)&state_array->states[i];
···
2492
2491
break;
2493
2492
}
2494
2493
} else {
2495
-
/* add the default mode */
2496
-
rdev->pm.power_state[state_index].type =
2497
-
POWER_STATE_TYPE_DEFAULT;
2498
-
rdev->pm.power_state[state_index].num_clock_modes = 1;
2499
-
rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2500
-
rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2501
-
rdev->pm.power_state[state_index].default_clock_mode =
2502
-
&rdev->pm.power_state[state_index].clock_info[0];
2503
-
rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2504
-
rdev->pm.power_state[state_index].pcie_lanes = 16;
2505
-
rdev->pm.default_power_state_index = state_index;
2506
-
rdev->pm.power_state[state_index].flags = 0;
2507
-
state_index++;
2494
+
rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2495
+
if (rdev->pm.power_state) {
2496
+
/* add the default mode */
2497
+
rdev->pm.power_state[state_index].type =
2498
+
POWER_STATE_TYPE_DEFAULT;
2499
+
rdev->pm.power_state[state_index].num_clock_modes = 1;
2500
+
rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2501
+
rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2502
+
rdev->pm.power_state[state_index].default_clock_mode =
2503
+
&rdev->pm.power_state[state_index].clock_info[0];
2504
+
rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2505
+
rdev->pm.power_state[state_index].pcie_lanes = 16;
2506
+
rdev->pm.default_power_state_index = state_index;
2507
+
rdev->pm.power_state[state_index].flags = 0;
2508
+
state_index++;
2509
+
}
2508
2510
}
2509
2511
2510
2512
rdev->pm.num_power_states = state_index;
···
2623
2619
bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2624
2620
2625
2621
/* tell the bios not to handle mode switching */
2626
-
bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
2622
+
bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
2627
2623
2628
2624
if (rdev->family >= CHIP_R600) {
2629
2625
WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
···
2674
2670
else
2675
2671
bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2676
2672
2677
-
if (lock)
2673
+
if (lock) {
2678
2674
bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2679
-
else
2675
+
bios_6_scratch &= ~ATOM_S6_ACC_MODE;
2676
+
} else {
2680
2677
bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2678
+
bios_6_scratch |= ATOM_S6_ACC_MODE;
2679
+
}
2681
2680
2682
2681
if (rdev->family >= CHIP_R600)
2683
2682
WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
+11
drivers/gpu/drm/radeon/radeon_combios.c
+11
drivers/gpu/drm/radeon/radeon_combios.c
···
2442
2442
2443
2443
rdev->pm.default_power_state_index = -1;
2444
2444
2445
+
/* allocate 2 power states */
2446
+
rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
2447
+
if (!rdev->pm.power_state) {
2448
+
rdev->pm.default_power_state_index = state_index;
2449
+
rdev->pm.num_power_states = 0;
2450
+
2451
+
rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2452
+
rdev->pm.current_clock_mode_index = 0;
2453
+
return;
2454
+
}
2455
+
2445
2456
if (rdev->flags & RADEON_IS_MOBILITY) {
2446
2457
offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2447
2458
if (offset) {
+124
-8
drivers/gpu/drm/radeon/radeon_display.c
+124
-8
drivers/gpu/drm/radeon/radeon_display.c
···
780
780
return ret;
781
781
}
782
782
783
+
/* avivo */
784
+
static void avivo_get_fb_div(struct radeon_pll *pll,
785
+
u32 target_clock,
786
+
u32 post_div,
787
+
u32 ref_div,
788
+
u32 *fb_div,
789
+
u32 *frac_fb_div)
790
+
{
791
+
u32 tmp = post_div * ref_div;
792
+
793
+
tmp *= target_clock;
794
+
*fb_div = tmp / pll->reference_freq;
795
+
*frac_fb_div = tmp % pll->reference_freq;
796
+
}
797
+
798
+
static u32 avivo_get_post_div(struct radeon_pll *pll,
799
+
u32 target_clock)
800
+
{
801
+
u32 vco, post_div, tmp;
802
+
803
+
if (pll->flags & RADEON_PLL_USE_POST_DIV)
804
+
return pll->post_div;
805
+
806
+
if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
807
+
if (pll->flags & RADEON_PLL_IS_LCD)
808
+
vco = pll->lcd_pll_out_min;
809
+
else
810
+
vco = pll->pll_out_min;
811
+
} else {
812
+
if (pll->flags & RADEON_PLL_IS_LCD)
813
+
vco = pll->lcd_pll_out_max;
814
+
else
815
+
vco = pll->pll_out_max;
816
+
}
817
+
818
+
post_div = vco / target_clock;
819
+
tmp = vco % target_clock;
820
+
821
+
if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
822
+
if (tmp)
823
+
post_div++;
824
+
} else {
825
+
if (!tmp)
826
+
post_div--;
827
+
}
828
+
829
+
return post_div;
830
+
}
831
+
832
+
#define MAX_TOLERANCE 10
833
+
834
+
void radeon_compute_pll_avivo(struct radeon_pll *pll,
835
+
u32 freq,
836
+
u32 *dot_clock_p,
837
+
u32 *fb_div_p,
838
+
u32 *frac_fb_div_p,
839
+
u32 *ref_div_p,
840
+
u32 *post_div_p)
841
+
{
842
+
u32 target_clock = freq / 10;
843
+
u32 post_div = avivo_get_post_div(pll, target_clock);
844
+
u32 ref_div = pll->min_ref_div;
845
+
u32 fb_div = 0, frac_fb_div = 0, tmp;
846
+
847
+
if (pll->flags & RADEON_PLL_USE_REF_DIV)
848
+
ref_div = pll->reference_div;
849
+
850
+
if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
851
+
avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
852
+
frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
853
+
if (frac_fb_div >= 5) {
854
+
frac_fb_div -= 5;
855
+
frac_fb_div = frac_fb_div / 10;
856
+
frac_fb_div++;
857
+
}
858
+
if (frac_fb_div >= 10) {
859
+
fb_div++;
860
+
frac_fb_div = 0;
861
+
}
862
+
} else {
863
+
while (ref_div <= pll->max_ref_div) {
864
+
avivo_get_fb_div(pll, target_clock, post_div, ref_div,
865
+
&fb_div, &frac_fb_div);
866
+
if (frac_fb_div >= (pll->reference_freq / 2))
867
+
fb_div++;
868
+
frac_fb_div = 0;
869
+
tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
870
+
tmp = (tmp * 10000) / target_clock;
871
+
872
+
if (tmp > (10000 + MAX_TOLERANCE))
873
+
ref_div++;
874
+
else if (tmp >= (10000 - MAX_TOLERANCE))
875
+
break;
876
+
else
877
+
ref_div++;
878
+
}
879
+
}
880
+
881
+
*dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
882
+
(ref_div * post_div * 10);
883
+
*fb_div_p = fb_div;
884
+
*frac_fb_div_p = frac_fb_div;
885
+
*ref_div_p = ref_div;
886
+
*post_div_p = post_div;
887
+
DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
888
+
*dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
889
+
}
890
+
891
+
/* pre-avivo */
783
892
static inline uint32_t radeon_div(uint64_t n, uint32_t d)
784
893
{
785
894
uint64_t mod;
···
899
790
return n;
900
791
}
901
792
902
-
void radeon_compute_pll(struct radeon_pll *pll,
903
-
uint64_t freq,
904
-
uint32_t *dot_clock_p,
905
-
uint32_t *fb_div_p,
906
-
uint32_t *frac_fb_div_p,
907
-
uint32_t *ref_div_p,
908
-
uint32_t *post_div_p)
793
+
void radeon_compute_pll_legacy(struct radeon_pll *pll,
794
+
uint64_t freq,
795
+
uint32_t *dot_clock_p,
796
+
uint32_t *fb_div_p,
797
+
uint32_t *frac_fb_div_p,
798
+
uint32_t *ref_div_p,
799
+
uint32_t *post_div_p)
909
800
{
910
801
uint32_t min_ref_div = pll->min_ref_div;
911
802
uint32_t max_ref_div = pll->max_ref_div;
···
935
826
pll_out_max = pll->pll_out_max;
936
827
}
937
828
829
+
if (pll_out_min > 64800)
830
+
pll_out_min = 64800;
831
+
938
832
if (pll->flags & RADEON_PLL_USE_REF_DIV)
939
833
min_ref_div = max_ref_div = pll->reference_div;
940
834
else {
···
961
849
max_fractional_feed_div = pll->max_frac_feedback_div;
962
850
}
963
851
964
-
for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
852
+
for (post_div = min_post_div; post_div <= max_post_div; ++post_div) {
965
853
uint32_t ref_div;
966
854
967
855
if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
···
1077
965
*frac_fb_div_p = best_frac_feedback_div;
1078
966
*ref_div_p = best_ref_div;
1079
967
*post_div_p = best_post_div;
968
+
DRM_DEBUG_KMS("%d %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
969
+
freq, best_freq / 1000, best_feedback_div, best_frac_feedback_div,
970
+
best_ref_div, best_post_div);
971
+
1080
972
}
1081
973
1082
974
static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
+1
-1
drivers/gpu/drm/radeon/radeon_encoders.c
+1
-1
drivers/gpu/drm/radeon/radeon_encoders.c
+3
-3
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+3
-3
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
···
778
778
DRM_DEBUG_KMS("\n");
779
779
780
780
if (!use_bios_divs) {
781
-
radeon_compute_pll(pll, mode->clock,
782
-
&freq, &feedback_div, &frac_fb_div,
783
-
&reference_div, &post_divider);
781
+
radeon_compute_pll_legacy(pll, mode->clock,
782
+
&freq, &feedback_div, &frac_fb_div,
783
+
&reference_div, &post_divider);
784
784
785
785
for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
786
786
if (post_div->divider == post_divider)
+16
-7
drivers/gpu/drm/radeon/radeon_mode.h
+16
-7
drivers/gpu/drm/radeon/radeon_mode.h
···
149
149
#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
150
150
#define RADEON_PLL_USE_POST_DIV (1 << 12)
151
151
#define RADEON_PLL_IS_LCD (1 << 13)
152
+
#define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
152
153
153
154
struct radeon_pll {
154
155
/* reference frequency */
···
511
510
struct radeon_atom_ss *ss,
512
511
int id, u32 clock);
513
512
514
-
extern void radeon_compute_pll(struct radeon_pll *pll,
515
-
uint64_t freq,
516
-
uint32_t *dot_clock_p,
517
-
uint32_t *fb_div_p,
518
-
uint32_t *frac_fb_div_p,
519
-
uint32_t *ref_div_p,
520
-
uint32_t *post_div_p);
513
+
extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
514
+
uint64_t freq,
515
+
uint32_t *dot_clock_p,
516
+
uint32_t *fb_div_p,
517
+
uint32_t *frac_fb_div_p,
518
+
uint32_t *ref_div_p,
519
+
uint32_t *post_div_p);
520
+
521
+
extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
522
+
u32 freq,
523
+
u32 *dot_clock_p,
524
+
u32 *fb_div_p,
525
+
u32 *frac_fb_div_p,
526
+
u32 *ref_div_p,
527
+
u32 *post_div_p);
521
528
522
529
extern void radeon_setup_encoder_clones(struct drm_device *dev);
523
530
+4
-1
drivers/gpu/drm/radeon/radeon_pm.c
+4
-1
drivers/gpu/drm/radeon/radeon_pm.c
···
430
430
{
431
431
struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
432
432
struct radeon_device *rdev = ddev->dev_private;
433
-
u32 temp;
433
+
int temp;
434
434
435
435
switch (rdev->pm.int_thermal_type) {
436
436
case THERMAL_TYPE_RV6XX:
···
645
645
unregister_acpi_notifier(&rdev->acpi_nb);
646
646
#endif
647
647
}
648
+
649
+
if (rdev->pm.power_state)
650
+
kfree(rdev->pm.power_state);
648
651
649
652
radeon_hwmon_fini(rdev);
650
653
}
+12
-7
drivers/gpu/drm/radeon/rv770.c
+12
-7
drivers/gpu/drm/radeon/rv770.c
···
78
78
}
79
79
80
80
/* get temperature in millidegrees */
81
-
u32 rv770_get_temp(struct radeon_device *rdev)
81
+
int rv770_get_temp(struct radeon_device *rdev)
82
82
{
83
83
u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
84
84
ASIC_T_SHIFT;
85
-
u32 actual_temp = 0;
85
+
int actual_temp;
86
86
87
-
if ((temp >> 9) & 1)
88
-
actual_temp = 0;
89
-
else
90
-
actual_temp = (temp >> 1) & 0xff;
87
+
if (temp & 0x400)
88
+
actual_temp = -256;
89
+
else if (temp & 0x200)
90
+
actual_temp = 255;
91
+
else if (temp & 0x100) {
92
+
actual_temp = temp & 0x1ff;
93
+
actual_temp |= ~0x1ff;
94
+
} else
95
+
actual_temp = temp & 0xff;
91
96
92
-
return actual_temp * 1000;
97
+
return (actual_temp * 1000) / 2;
93
98
}
94
99
95
100
void rv770_pm_misc(struct radeon_device *rdev)
+1
-1
include/drm/drmP.h
+1
-1
include/drm/drmP.h
···
1367
1367
extern u32 drm_vblank_count(struct drm_device *dev, int crtc);
1368
1368
extern u32 drm_vblank_count_and_time(struct drm_device *dev, int crtc,
1369
1369
struct timeval *vblanktime);
1370
-
extern void drm_handle_vblank(struct drm_device *dev, int crtc);
1370
+
extern bool drm_handle_vblank(struct drm_device *dev, int crtc);
1371
1371
extern int drm_vblank_get(struct drm_device *dev, int crtc);
1372
1372
extern void drm_vblank_put(struct drm_device *dev, int crtc);
1373
1373
extern void drm_vblank_off(struct drm_device *dev, int crtc);
+7
include/drm/drm_crtc.h
+7
include/drm/drm_crtc.h
···
275
275
276
276
/**
277
277
* drm_crtc_funcs - control CRTCs for a given device
278
+
* @reset: reset CRTC after state has been invalidate (e.g. resume)
278
279
* @dpms: control display power levels
279
280
* @save: save CRTC state
280
281
* @resore: restore CRTC state
···
303
302
void (*save)(struct drm_crtc *crtc); /* suspend? */
304
303
/* Restore CRTC state */
305
304
void (*restore)(struct drm_crtc *crtc); /* resume? */
305
+
/* Reset CRTC state */
306
+
void (*reset)(struct drm_crtc *crtc);
306
307
307
308
/* cursor controls */
308
309
int (*cursor_set)(struct drm_crtc *crtc, struct drm_file *file_priv,
···
382
379
* @dpms: set power state (see drm_crtc_funcs above)
383
380
* @save: save connector state
384
381
* @restore: restore connector state
382
+
* @reset: reset connector after state has been invalidate (e.g. resume)
385
383
* @mode_valid: is this mode valid on the given connector?
386
384
* @mode_fixup: try to fixup proposed mode for this connector
387
385
* @mode_set: set this mode
···
400
396
void (*dpms)(struct drm_connector *connector, int mode);
401
397
void (*save)(struct drm_connector *connector);
402
398
void (*restore)(struct drm_connector *connector);
399
+
void (*reset)(struct drm_connector *connector);
403
400
404
401
/* Check to see if anything is attached to the connector.
405
402
* @force is set to false whilst polling, true when checking the
···
418
413
};
419
414
420
415
struct drm_encoder_funcs {
416
+
void (*reset)(struct drm_encoder *encoder);
421
417
void (*destroy)(struct drm_encoder *encoder);
422
418
};
423
419
···
662
656
struct drm_display_mode *mode);
663
657
extern void drm_mode_debug_printmodeline(struct drm_display_mode *mode);
664
658
extern void drm_mode_config_init(struct drm_device *dev);
659
+
extern void drm_mode_config_reset(struct drm_device *dev);
665
660
extern void drm_mode_config_cleanup(struct drm_device *dev);
666
661
extern void drm_mode_set_name(struct drm_display_mode *mode);
667
662
extern bool drm_mode_equal(struct drm_display_mode *mode1, struct drm_display_mode *mode2);
-1
include/drm/drm_pciids.h
-1
include/drm/drm_pciids.h
···
28
28
{0x1002, 0x4156, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
29
29
{0x1002, 0x4237, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP}, \
30
30
{0x1002, 0x4242, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
31
-
{0x1002, 0x4243, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
32
31
{0x1002, 0x4336, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS100|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \
33
32
{0x1002, 0x4337, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \
34
33
{0x1002, 0x4437, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \