Merge tag 'i2c-for-7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux

+4

Documentation/devicetree/bindings/eeprom/at24.yaml

··· 116 116 - const: atmel,24c02 117 117 - items: 118 118 - enum: 119 + - belling,bl24c04a 119 120 - giantec,gt24c04a 120 121 - onnn,cat24c04 121 122 - onnn,cat24c05 ··· 125 124 - items: 126 125 - enum: 127 126 - belling,bl24c16a 127 + - belling,bl24c16f 128 128 - renesas,r1ex24016 129 129 - const: atmel,24c16 130 130 - items: ··· 134 132 - items: 135 133 - enum: 136 134 - belling,bl24s64 135 + - giantec,gt24p64a 137 136 - onnn,n24s64b 138 137 - puya,p24c64f 139 138 - const: atmel,24c64 ··· 142 139 - enum: 143 140 - giantec,gt24p128e 144 141 - giantec,gt24p128f 142 + - puya,p24c128f 145 143 - renesas,r1ex24128 146 144 - samsung,s524ad0xd1 147 145 - const: atmel,24c128

+1

Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml

··· 26 26 - microchip,sam9x60-i2c 27 27 - items: 28 28 - enum: 29 + - microchip,lan9691-i2c 29 30 - microchip,sama7d65-i2c 30 31 - microchip,sama7g5-i2c 31 32 - microchip,sam9x7-i2c

+1

Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml

··· 54 54 - enum: 55 55 - mediatek,mt6878-i2c 56 56 - mediatek,mt6991-i2c 57 + - mediatek,mt8189-i2c 57 58 - mediatek,mt8196-i2c 58 59 - const: mediatek,mt8188-i2c 59 60 - items:

+3

Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml

··· 41 41 default: 400000 42 42 maximum: 3300000 43 43 44 + resets: 45 + maxItems: 1 46 + 44 47 required: 45 48 - compatible 46 49 - reg

+2 -9

drivers/i2c/busses/Kconfig

··· 569 569 help 570 570 This option enables support for the Synopsys DesignWare I2C adapter. 571 571 This driver includes support for the I2C host on the Synopsys 572 - Designware I2C adapter. 572 + Designware I2C adapter, and the I2C slave when enabled (select 573 + I2C_SLAVE). 573 574 574 575 To compile the driver as a module, choose M here: the module will be 575 576 called i2c-designware-core. 576 577 577 578 if I2C_DESIGNWARE_CORE 578 579 579 - config I2C_DESIGNWARE_SLAVE 580 - bool "Synopsys DesignWare Slave" 581 - select I2C_SLAVE 582 - help 583 - If you say yes to this option, support will be included for the 584 - Synopsys DesignWare I2C slave adapter. 585 - 586 580 config I2C_DESIGNWARE_PLATFORM 587 581 tristate "Synopsys DesignWare Platform driver" 588 582 depends on (ACPI && COMMON_CLK) || !ACPI 589 - select MFD_SYSCON if MIPS_BAIKAL_T1 590 583 default I2C_DESIGNWARE_CORE 591 584 help 592 585 If you say yes to this option, support will be included for the

+1 -1

drivers/i2c/busses/Makefile

··· 53 53 obj-$(CONFIG_I2C_DESIGNWARE_CORE) += i2c-designware-core.o 54 54 i2c-designware-core-y := i2c-designware-common.o 55 55 i2c-designware-core-y += i2c-designware-master.o 56 - i2c-designware-core-$(CONFIG_I2C_DESIGNWARE_SLAVE) += i2c-designware-slave.o 56 + i2c-designware-core-$(CONFIG_I2C_SLAVE) += i2c-designware-slave.o 57 57 obj-$(CONFIG_I2C_DESIGNWARE_PLATFORM) += i2c-designware-platform.o 58 58 i2c-designware-platform-y := i2c-designware-platdrv.o 59 59 i2c-designware-platform-$(CONFIG_I2C_DESIGNWARE_AMDPSP) += i2c-designware-amdpsp.o

+5 -3

drivers/i2c/busses/i2c-amd-mp2-pci.c

··· 456 456 457 457 struct amd_mp2_dev *amd_mp2_find_device(void) 458 458 { 459 + struct amd_mp2_dev *privdata; 459 460 struct device *dev; 460 461 struct pci_dev *pci_dev; 461 - struct amd_mp2_dev *mp2_dev; 462 462 463 463 dev = driver_find_next_device(&amd_mp2_pci_driver.driver, NULL); 464 464 if (!dev) 465 465 return NULL; 466 466 467 467 pci_dev = to_pci_dev(dev); 468 - mp2_dev = (struct amd_mp2_dev *)pci_get_drvdata(pci_dev); 468 + privdata = pci_get_drvdata(pci_dev); 469 + 469 470 put_device(dev); 470 - return mp2_dev; 471 + 472 + return privdata; 471 473 } 472 474 EXPORT_SYMBOL_GPL(amd_mp2_find_device); 473 475

+2 -2

drivers/i2c/busses/i2c-designware-amdisp.c

··· 163 163 164 164 if (!i_dev->shared_with_punit) 165 165 i2c_dw_prepare_clk(i_dev, true); 166 - if (i_dev->init) 167 - i_dev->init(i_dev); 166 + 167 + i2c_dw_init(i_dev); 168 168 169 169 return 0; 170 170 }

+218 -28

drivers/i2c/busses/i2c-designware-common.c

··· 12 12 #define DEFAULT_SYMBOL_NAMESPACE "I2C_DW_COMMON" 13 13 14 14 #include <linux/acpi.h> 15 + #include <linux/bitfield.h> 15 16 #include <linux/clk.h> 16 17 #include <linux/delay.h> 17 18 #include <linux/device.h> ··· 34 33 #include <linux/units.h> 35 34 36 35 #include "i2c-designware-core.h" 36 + 37 + #define DW_IC_DEFAULT_BUS_CAPACITANCE_pF 100 38 + #define DW_IC_ABORT_TIMEOUT_US 10 39 + #define DW_IC_BUSY_POLL_TIMEOUT_US (1 * USEC_PER_MSEC) 37 40 38 41 static const char *const abort_sources[] = { 39 42 [ABRT_7B_ADDR_NOACK] = ··· 111 106 struct dw_i2c_dev *dev = context; 112 107 113 108 *val = readw(dev->base + reg) | 114 - (readw(dev->base + reg + 2) << 16); 109 + (readw(dev->base + reg + DW_IC_REG_STEP_BYTES) << DW_IC_REG_WORD_SHIFT); 115 110 116 111 return 0; 117 112 } ··· 121 116 struct dw_i2c_dev *dev = context; 122 117 123 118 writew(val, dev->base + reg); 124 - writew(val >> 16, dev->base + reg + 2); 119 + writew(val >> DW_IC_REG_WORD_SHIFT, dev->base + reg + DW_IC_REG_STEP_BYTES); 125 120 126 121 return 0; 127 122 } ··· 136 131 * 137 132 * Return: 0 on success, or negative errno otherwise. 138 133 */ 139 - int i2c_dw_init_regmap(struct dw_i2c_dev *dev) 134 + static int i2c_dw_init_regmap(struct dw_i2c_dev *dev) 140 135 { 141 136 struct regmap_config map_cfg = { 142 137 .reg_bits = 32, ··· 170 165 if (reg == swab32(DW_IC_COMP_TYPE_VALUE)) { 171 166 map_cfg.reg_read = dw_reg_read_swab; 172 167 map_cfg.reg_write = dw_reg_write_swab; 173 - } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) { 168 + } else if (reg == lower_16_bits(DW_IC_COMP_TYPE_VALUE)) { 174 169 map_cfg.reg_read = dw_reg_read_word; 175 170 map_cfg.reg_write = dw_reg_write_word; 176 171 } else if (reg != DW_IC_COMP_TYPE_VALUE) { ··· 243 238 struct platform_device *pdev = to_platform_device(device); 244 239 struct dw_i2c_dev *dev = dev_get_drvdata(device); 245 240 246 - switch (dev->flags & MODEL_MASK) { 247 - case MODEL_MSCC_OCELOT: 241 + if (device_is_compatible(dev->dev, "mscc,ocelot-i2c")) { 248 242 dev->ext = devm_platform_ioremap_resource(pdev, 1); 249 243 if (!IS_ERR(dev->ext)) 250 244 dev->set_sda_hold_time = mscc_twi_set_sda_hold_time; 251 - break; 252 - default: 253 - break; 254 245 } 255 246 } 256 247 ··· 359 358 360 359 #endif /* CONFIG_ACPI */ 361 360 361 + static void i2c_dw_configure_mode(struct dw_i2c_dev *dev, int mode) 362 + { 363 + switch (mode) { 364 + case DW_IC_MASTER: 365 + regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2); 366 + regmap_write(dev->map, DW_IC_RX_TL, 0); 367 + regmap_write(dev->map, DW_IC_CON, dev->master_cfg); 368 + break; 369 + case DW_IC_SLAVE: 370 + dev->status = 0; 371 + regmap_write(dev->map, DW_IC_TX_TL, 0); 372 + regmap_write(dev->map, DW_IC_RX_TL, 0); 373 + regmap_write(dev->map, DW_IC_CON, dev->slave_cfg); 374 + regmap_write(dev->map, DW_IC_SAR, dev->slave->addr); 375 + regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_SLAVE_MASK); 376 + __i2c_dw_enable(dev); 377 + break; 378 + default: 379 + WARN(1, "Invalid mode %d\n", mode); 380 + return; 381 + } 382 + } 383 + 384 + static void i2c_dw_write_timings(struct dw_i2c_dev *dev) 385 + { 386 + /* Write standard speed timing parameters */ 387 + regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt); 388 + regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt); 389 + 390 + /* Write fast mode/fast mode plus timing parameters */ 391 + regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt); 392 + regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt); 393 + 394 + /* Write high speed timing parameters */ 395 + regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt); 396 + regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt); 397 + } 398 + 399 + /** 400 + * i2c_dw_set_mode() - Select the controller mode of operation - master or slave 401 + * @dev: device private data 402 + * @mode: I2C mode of operation 403 + * 404 + * Configures the controller to operate in @mode. This function needs to be 405 + * called when ever a mode swap is required. 406 + * 407 + * Setting the slave mode does not have an effect before a slave device is 408 + * registered. So before the slave device is registered, the controller is kept 409 + * in master mode regardless of @mode. 410 + * 411 + * The controller must be disabled before this function is called. 412 + */ 413 + void i2c_dw_set_mode(struct dw_i2c_dev *dev, int mode) 414 + { 415 + if (mode == DW_IC_SLAVE && !dev->slave) 416 + mode = DW_IC_MASTER; 417 + if (dev->mode == mode) 418 + return; 419 + 420 + i2c_dw_configure_mode(dev, mode); 421 + dev->mode = mode; 422 + } 423 + 424 + /** 425 + * i2c_dw_init() - Initialize the DesignWare I2C hardware 426 + * @dev: device private data 427 + * 428 + * This functions configures and enables the DesigWare I2C hardware. 429 + * 430 + * Return: 0 on success, or negative errno otherwise. 431 + */ 432 + int i2c_dw_init(struct dw_i2c_dev *dev) 433 + { 434 + int ret; 435 + 436 + ret = i2c_dw_acquire_lock(dev); 437 + if (ret) 438 + return ret; 439 + 440 + /* Disable the adapter */ 441 + __i2c_dw_disable(dev); 442 + 443 + /* 444 + * Mask SMBus interrupts to block storms from broken 445 + * firmware that leaves IC_SMBUS=1; the handler never 446 + * services them. 447 + */ 448 + regmap_write(dev->map, DW_IC_SMBUS_INTR_MASK, 0); 449 + 450 + i2c_dw_write_timings(dev); 451 + 452 + /* Write SDA hold time if supported */ 453 + if (dev->sda_hold_time) 454 + regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time); 455 + 456 + i2c_dw_configure_mode(dev, dev->mode); 457 + 458 + i2c_dw_release_lock(dev); 459 + 460 + return 0; 461 + } 462 + EXPORT_SYMBOL_GPL(i2c_dw_init); 463 + 362 464 static void i2c_dw_adjust_bus_speed(struct dw_i2c_dev *dev) 363 465 { 364 466 u32 acpi_speed = i2c_dw_acpi_round_bus_speed(dev->dev); ··· 488 384 i2c_parse_fw_timings(device, t, false); 489 385 490 386 if (device_property_read_u32(device, "snps,bus-capacitance-pf", &dev->bus_capacitance_pF)) 491 - dev->bus_capacitance_pF = 100; 387 + dev->bus_capacitance_pF = DW_IC_DEFAULT_BUS_CAPACITANCE_pF; 492 388 493 389 dev->clk_freq_optimized = device_property_read_bool(device, "snps,clk-freq-optimized"); 494 390 ··· 561 457 return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tLOW + tf), MICRO) - 1 + offset; 562 458 } 563 459 564 - int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev) 460 + static int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev) 565 461 { 566 462 unsigned int reg; 567 463 int ret; ··· 643 539 644 540 regmap_write(dev->map, DW_IC_ENABLE, enable | DW_IC_ENABLE_ABORT); 645 541 ret = regmap_read_poll_timeout(dev->map, DW_IC_ENABLE, enable, 646 - !(enable & DW_IC_ENABLE_ABORT), 10, 647 - 100); 542 + !(enable & DW_IC_ENABLE_ABORT), 543 + DW_IC_ABORT_TIMEOUT_US, 544 + 10 * DW_IC_ABORT_TIMEOUT_US); 648 545 if (ret) 649 546 dev_err(dev->dev, "timeout while trying to abort current transfer\n"); 650 547 } ··· 657 552 * in that case this test reads zero and exits the loop. 658 553 */ 659 554 regmap_read(dev->map, DW_IC_ENABLE_STATUS, &status); 660 - if ((status & 1) == 0) 555 + if (!(status & 1)) 661 556 return; 662 557 663 558 /* ··· 740 635 741 636 ret = regmap_read_poll_timeout(dev->map, DW_IC_STATUS, status, 742 637 !(status & DW_IC_STATUS_ACTIVITY), 743 - 1100, 20000); 638 + DW_IC_BUSY_POLL_TIMEOUT_US, 639 + 20 * DW_IC_BUSY_POLL_TIMEOUT_US); 744 640 if (ret) { 745 641 dev_warn(dev->dev, "timeout waiting for bus ready\n"); 746 642 ··· 778 672 return -EIO; 779 673 } 780 674 781 - int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev) 675 + static int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev) 782 676 { 783 677 u32 tx_fifo_depth, rx_fifo_depth; 784 678 unsigned int param; ··· 805 699 if (ret) 806 700 return ret; 807 701 808 - tx_fifo_depth = ((param >> 16) & 0xff) + 1; 809 - rx_fifo_depth = ((param >> 8) & 0xff) + 1; 702 + tx_fifo_depth = FIELD_GET(DW_IC_FIFO_TX_FIELD, param) + 1; 703 + rx_fifo_depth = FIELD_GET(DW_IC_FIFO_RX_FIELD, param) + 1; 810 704 if (!dev->tx_fifo_depth) { 811 705 dev->tx_fifo_depth = tx_fifo_depth; 812 706 dev->rx_fifo_depth = rx_fifo_depth; 813 - } else if (tx_fifo_depth >= 2) { 707 + } else if (tx_fifo_depth >= DW_IC_FIFO_MIN_DEPTH) { 814 708 dev->tx_fifo_depth = min_t(u32, dev->tx_fifo_depth, 815 709 tx_fifo_depth); 816 710 dev->rx_fifo_depth = min_t(u32, dev->rx_fifo_depth, ··· 847 741 } 848 742 EXPORT_SYMBOL_GPL(i2c_dw_disable); 849 743 744 + static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) 745 + { 746 + struct dw_i2c_dev *dev = dev_id; 747 + 748 + if (dev->mode == DW_IC_SLAVE) 749 + return i2c_dw_isr_slave(dev); 750 + 751 + return i2c_dw_isr_master(dev); 752 + } 753 + 754 + static const struct i2c_algorithm i2c_dw_algo = { 755 + .xfer = i2c_dw_xfer, 756 + .functionality = i2c_dw_func, 757 + #if IS_ENABLED(CONFIG_I2C_SLAVE) 758 + .reg_slave = i2c_dw_reg_slave, 759 + .unreg_slave = i2c_dw_unreg_slave, 760 + #endif 761 + }; 762 + 763 + static const struct i2c_adapter_quirks i2c_dw_quirks = { 764 + .flags = I2C_AQ_NO_ZERO_LEN, 765 + }; 766 + 850 767 int i2c_dw_probe(struct dw_i2c_dev *dev) 851 768 { 769 + struct i2c_adapter *adap = &dev->adapter; 770 + unsigned long irq_flags; 771 + int ret; 772 + 852 773 device_set_node(&dev->adapter.dev, dev_fwnode(dev->dev)); 853 774 854 - switch (dev->mode) { 855 - case DW_IC_SLAVE: 856 - return i2c_dw_probe_slave(dev); 857 - case DW_IC_MASTER: 858 - return i2c_dw_probe_master(dev); 859 - default: 860 - dev_err(dev->dev, "Wrong operation mode: %d\n", dev->mode); 861 - return -EINVAL; 775 + ret = i2c_dw_init_regmap(dev); 776 + if (ret) 777 + return ret; 778 + 779 + ret = i2c_dw_set_sda_hold(dev); 780 + if (ret) 781 + return ret; 782 + 783 + ret = i2c_dw_set_fifo_size(dev); 784 + if (ret) 785 + return ret; 786 + 787 + ret = i2c_dw_probe_master(dev); 788 + if (ret) 789 + return ret; 790 + 791 + ret = i2c_dw_init(dev); 792 + if (ret) 793 + return ret; 794 + 795 + if (!adap->name[0]) 796 + strscpy(adap->name, "Synopsys DesignWare I2C adapter"); 797 + 798 + adap->retries = 3; 799 + adap->algo = &i2c_dw_algo; 800 + adap->quirks = &i2c_dw_quirks; 801 + adap->dev.parent = dev->dev; 802 + i2c_set_adapdata(adap, dev); 803 + 804 + /* 805 + * REVISIT: The mode check may not be necessary. 806 + * For now keeping the flags as they were originally. 807 + */ 808 + if (dev->mode == DW_IC_SLAVE) 809 + irq_flags = IRQF_SHARED; 810 + else if (dev->flags & ACCESS_NO_IRQ_SUSPEND) 811 + irq_flags = IRQF_NO_SUSPEND; 812 + else 813 + irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND; 814 + 815 + ret = i2c_dw_acquire_lock(dev); 816 + if (ret) 817 + return ret; 818 + 819 + __i2c_dw_write_intr_mask(dev, 0); 820 + i2c_dw_release_lock(dev); 821 + 822 + if (!(dev->flags & ACCESS_POLLING)) { 823 + ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, 824 + irq_flags, dev_name(dev->dev), dev); 825 + if (ret) 826 + return ret; 862 827 } 828 + 829 + /* 830 + * Increment PM usage count during adapter registration in order to 831 + * avoid possible spurious runtime suspend when adapter device is 832 + * registered to the device core and immediate resume in case bus has 833 + * registered I2C slaves that do I2C transfers in their probe. 834 + */ 835 + ACQUIRE(pm_runtime_noresume, pm)(dev->dev); 836 + ret = ACQUIRE_ERR(pm_runtime_noresume, &pm); 837 + if (ret) 838 + return ret; 839 + 840 + return i2c_add_numbered_adapter(adap); 863 841 } 864 842 EXPORT_SYMBOL_GPL(i2c_dw_probe); 865 843 ··· 987 797 if (!dev->shared_with_punit) 988 798 i2c_dw_prepare_clk(dev, true); 989 799 990 - dev->init(dev); 800 + i2c_dw_init(dev); 991 801 992 802 return 0; 993 803 }

+26 -14

drivers/i2c/busses/i2c-designware-core.h

··· 13 13 #include <linux/completion.h> 14 14 #include <linux/errno.h> 15 15 #include <linux/i2c.h> 16 + #include <linux/irqreturn.h> 16 17 #include <linux/pm.h> 17 18 #include <linux/regmap.h> 18 19 #include <linux/types.h> ··· 41 40 42 41 #define DW_IC_DATA_CMD_DAT GENMASK(7, 0) 43 42 #define DW_IC_DATA_CMD_FIRST_DATA_BYTE BIT(11) 43 + 44 + /* 45 + * Register access parameters 46 + */ 47 + #define DW_IC_REG_STEP_BYTES 2 48 + #define DW_IC_REG_WORD_SHIFT 16 49 + 50 + /* 51 + * FIFO depth configuration 52 + */ 53 + #define DW_IC_FIFO_TX_FIELD GENMASK(23, 16) 54 + #define DW_IC_FIFO_RX_FIELD GENMASK(15, 8) 55 + #define DW_IC_FIFO_MIN_DEPTH 2 44 56 45 57 /* 46 58 * Registers offset ··· 253 239 * @semaphore_idx: Index of table with semaphore type attached to the bus. It's 254 240 * -1 if there is no semaphore. 255 241 * @shared_with_punit: true if this bus is shared with the SoC's PUNIT 256 - * @init: function to initialize the I2C hardware 257 242 * @set_sda_hold_time: callback to retrieve IP specific SDA hold timing 258 243 * @mode: operation mode - DW_IC_MASTER or DW_IC_SLAVE 259 244 * @rinfo: I²C GPIO recovery information ··· 313 300 void (*release_lock)(void); 314 301 int semaphore_idx; 315 302 bool shared_with_punit; 316 - int (*init)(struct dw_i2c_dev *dev); 317 303 int (*set_sda_hold_time)(struct dw_i2c_dev *dev); 318 304 int mode; 319 305 struct i2c_bus_recovery_info rinfo; ··· 325 313 #define ARBITRATION_SEMAPHORE BIT(2) 326 314 #define ACCESS_POLLING BIT(3) 327 315 328 - #define MODEL_MSCC_OCELOT BIT(8) 329 - #define MODEL_BAIKAL_BT1 BIT(9) 330 316 #define MODEL_AMD_NAVI_GPU BIT(10) 331 317 #define MODEL_WANGXUN_SP BIT(11) 332 318 #define MODEL_MASK GENMASK(11, 8) ··· 343 333 int (*probe)(struct dw_i2c_dev *dev); 344 334 }; 345 335 346 - int i2c_dw_init_regmap(struct dw_i2c_dev *dev); 347 336 u32 i2c_dw_scl_hcnt(struct dw_i2c_dev *dev, unsigned int reg, u32 ic_clk, 348 337 u32 tSYMBOL, u32 tf, int offset); 349 338 u32 i2c_dw_scl_lcnt(struct dw_i2c_dev *dev, unsigned int reg, u32 ic_clk, 350 339 u32 tLOW, u32 tf, int offset); 351 - int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev); 352 340 u32 i2c_dw_clk_rate(struct dw_i2c_dev *dev); 353 341 int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare); 354 342 int i2c_dw_acquire_lock(struct dw_i2c_dev *dev); 355 343 void i2c_dw_release_lock(struct dw_i2c_dev *dev); 356 344 int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev); 357 345 int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev); 358 - int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev); 359 346 u32 i2c_dw_func(struct i2c_adapter *adap); 347 + irqreturn_t i2c_dw_isr_master(struct dw_i2c_dev *dev); 360 348 361 349 extern const struct dev_pm_ops i2c_dw_dev_pm_ops; 362 350 ··· 394 386 extern void i2c_dw_configure_master(struct dw_i2c_dev *dev); 395 387 extern int i2c_dw_probe_master(struct dw_i2c_dev *dev); 396 388 397 - #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_SLAVE) 389 + int i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num); 390 + 391 + #if IS_ENABLED(CONFIG_I2C_SLAVE) 398 392 extern void i2c_dw_configure_slave(struct dw_i2c_dev *dev); 399 - extern int i2c_dw_probe_slave(struct dw_i2c_dev *dev); 393 + irqreturn_t i2c_dw_isr_slave(struct dw_i2c_dev *dev); 394 + int i2c_dw_reg_slave(struct i2c_client *client); 395 + int i2c_dw_unreg_slave(struct i2c_client *client); 400 396 #else 401 397 static inline void i2c_dw_configure_slave(struct dw_i2c_dev *dev) { } 402 - static inline int i2c_dw_probe_slave(struct dw_i2c_dev *dev) { return -EINVAL; } 398 + static inline irqreturn_t i2c_dw_isr_slave(struct dw_i2c_dev *dev) { return IRQ_NONE; } 403 399 #endif 404 400 405 401 static inline void i2c_dw_configure(struct dw_i2c_dev *dev) 406 402 { 407 - if (i2c_detect_slave_mode(dev->dev)) 408 - i2c_dw_configure_slave(dev); 409 - else 410 - i2c_dw_configure_master(dev); 403 + i2c_dw_configure_slave(dev); 404 + i2c_dw_configure_master(dev); 411 405 } 412 406 413 407 int i2c_dw_probe(struct dw_i2c_dev *dev); 408 + int i2c_dw_init(struct dw_i2c_dev *dev); 409 + void i2c_dw_set_mode(struct dw_i2c_dev *dev, int mode); 414 410 415 411 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL) 416 412 int i2c_dw_baytrail_probe_lock_support(struct dw_i2c_dev *dev);

+27 -160

drivers/i2c/busses/i2c-designware-master.c

··· 31 31 #define AMD_TIMEOUT_MAX_US 250 32 32 #define AMD_MASTERCFG_MASK GENMASK(15, 0) 33 33 34 - static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev) 35 - { 36 - /* Configure Tx/Rx FIFO threshold levels */ 37 - regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2); 38 - regmap_write(dev->map, DW_IC_RX_TL, 0); 39 - 40 - /* Configure the I2C master */ 41 - regmap_write(dev->map, DW_IC_CON, dev->master_cfg); 42 - } 43 - 44 34 static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev) 45 35 { 46 36 unsigned int comp_param1; ··· 181 191 dev->hs_hcnt, dev->hs_lcnt); 182 192 } 183 193 184 - ret = i2c_dw_set_sda_hold(dev); 185 - if (ret) 186 - return ret; 187 - 188 194 dev_dbg(dev->dev, "Bus speed: %s\n", i2c_freq_mode_string(t->bus_freq_hz)); 189 - return 0; 190 - } 191 - 192 - /** 193 - * i2c_dw_init_master() - Initialize the DesignWare I2C master hardware 194 - * @dev: device private data 195 - * 196 - * This functions configures and enables the I2C master. 197 - * This function is called during I2C init function, and in case of timeout at 198 - * run time. 199 - * 200 - * Return: 0 on success, or negative errno otherwise. 201 - */ 202 - static int i2c_dw_init_master(struct dw_i2c_dev *dev) 203 - { 204 - int ret; 205 - 206 - ret = i2c_dw_acquire_lock(dev); 207 - if (ret) 208 - return ret; 209 - 210 - /* Disable the adapter */ 211 - __i2c_dw_disable(dev); 212 - 213 - /* 214 - * Mask SMBus interrupts to block storms from broken 215 - * firmware that leaves IC_SMBUS=1; the handler never 216 - * services them. 217 - */ 218 - regmap_write(dev->map, DW_IC_SMBUS_INTR_MASK, 0); 219 - 220 - /* Write standard speed timing parameters */ 221 - regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt); 222 - regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt); 223 - 224 - /* Write fast mode/fast mode plus timing parameters */ 225 - regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt); 226 - regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt); 227 - 228 - /* Write high speed timing parameters if supported */ 229 - if (dev->hs_hcnt && dev->hs_lcnt) { 230 - regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt); 231 - regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt); 232 - } 233 - 234 - /* Write SDA hold time if supported */ 235 - if (dev->sda_hold_time) 236 - regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time); 237 - 238 - i2c_dw_configure_fifo_master(dev); 239 - i2c_dw_release_lock(dev); 240 - 241 195 return 0; 242 196 } 243 197 ··· 193 259 194 260 /* Disable the adapter */ 195 261 __i2c_dw_disable(dev); 262 + 263 + i2c_dw_set_mode(dev, DW_IC_MASTER); 196 264 197 265 /* If the slave address is ten bit address, enable 10BITADDR */ 198 266 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) { ··· 289 353 * Initiate and continue master read/write transaction with polling 290 354 * based transfer routine afterward write messages into the Tx buffer. 291 355 */ 292 - static int amd_i2c_dw_xfer_quirk(struct i2c_adapter *adap, struct i2c_msg *msgs, int num_msgs) 356 + static int amd_i2c_dw_xfer_quirk(struct dw_i2c_dev *dev, struct i2c_msg *msgs, int num_msgs) 293 357 { 294 - struct dw_i2c_dev *dev = i2c_get_adapdata(adap); 295 358 int msg_wrt_idx, msg_itr_lmt, buf_len, data_idx; 296 359 int cmd = 0, status; 297 360 u8 *tx_buf; 298 361 unsigned int val; 362 + 363 + ACQUIRE(pm_runtime_active_auto_try, pm)(dev->dev); 364 + if (ACQUIRE_ERR(pm_runtime_active_auto_try, &pm)) 365 + return -ENXIO; 299 366 300 367 /* 301 368 * In order to enable the interrupt for UCSI i.e. AMD NAVI GPU card, ··· 510 571 * after receiving the first byte. 511 572 */ 512 573 len += (flags & I2C_CLIENT_PEC) ? 2 : 1; 513 - dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding); 574 + dev->tx_buf_len = len - min(len, dev->rx_outstanding); 514 575 msgs[dev->msg_read_idx].len = len; 515 576 msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN; 516 577 ··· 532 593 unsigned int rx_valid; 533 594 534 595 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { 596 + u32 flags = msgs[dev->msg_read_idx].flags; 535 597 unsigned int tmp; 536 598 u32 len; 537 599 u8 *buf; 538 600 539 - if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD)) 601 + if (!(flags & I2C_M_RD)) 540 602 continue; 541 603 542 604 if (!(dev->status & STATUS_READ_IN_PROGRESS)) { ··· 551 611 regmap_read(dev->map, DW_IC_RXFLR, &rx_valid); 552 612 553 613 for (; len > 0 && rx_valid > 0; len--, rx_valid--) { 554 - u32 flags = msgs[dev->msg_read_idx].flags; 555 - 556 614 regmap_read(dev->map, DW_IC_DATA_CMD, &tmp); 557 615 tmp &= DW_IC_DATA_CMD_DAT; 558 616 /* Ensure length byte is a valid value */ ··· 687 749 * Interrupt service routine. This gets called whenever an I2C master interrupt 688 750 * occurs. 689 751 */ 690 - static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) 752 + irqreturn_t i2c_dw_isr_master(struct dw_i2c_dev *dev) 691 753 { 692 - struct dw_i2c_dev *dev = dev_id; 693 754 unsigned int stat, enabled; 694 755 695 756 regmap_read(dev->map, DW_IC_ENABLE, &enabled); ··· 749 812 * Prepare controller for a transaction and call i2c_dw_xfer_msg. 750 813 */ 751 814 static int 752 - i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 815 + i2c_dw_xfer_common(struct dw_i2c_dev *dev, struct i2c_msg msgs[], int num) 753 816 { 754 - struct dw_i2c_dev *dev = i2c_get_adapdata(adap); 755 817 int ret; 756 818 757 819 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); 758 820 759 821 pm_runtime_get_sync(dev->dev); 760 - 761 - switch (dev->flags & MODEL_MASK) { 762 - case MODEL_AMD_NAVI_GPU: 763 - ret = amd_i2c_dw_xfer_quirk(adap, msgs, num); 764 - goto done_nolock; 765 - default: 766 - break; 767 - } 768 822 769 823 reinit_completion(&dev->cmd_complete); 770 824 dev->msgs = msgs; ··· 783 855 ret = i2c_dw_wait_transfer(dev); 784 856 if (ret) { 785 857 dev_err(dev->dev, "controller timed out\n"); 786 - /* i2c_dw_init_master() implicitly disables the adapter */ 858 + /* i2c_dw_init() implicitly disables the adapter */ 787 859 i2c_recover_bus(&dev->adapter); 788 - i2c_dw_init_master(dev); 860 + i2c_dw_init(dev); 789 861 goto done; 790 862 } 791 863 ··· 833 905 ret = -EIO; 834 906 835 907 done: 908 + i2c_dw_set_mode(dev, DW_IC_SLAVE); 909 + 836 910 i2c_dw_release_lock(dev); 837 911 838 912 done_nolock: ··· 843 913 return ret; 844 914 } 845 915 846 - static const struct i2c_algorithm i2c_dw_algo = { 847 - .xfer = i2c_dw_xfer, 848 - .functionality = i2c_dw_func, 849 - }; 916 + int i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 917 + { 918 + struct dw_i2c_dev *dev = i2c_get_adapdata(adap); 850 919 851 - static const struct i2c_adapter_quirks i2c_dw_quirks = { 852 - .flags = I2C_AQ_NO_ZERO_LEN, 853 - }; 920 + if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU) 921 + return amd_i2c_dw_xfer_quirk(dev, msgs, num); 922 + 923 + return i2c_dw_xfer_common(dev, msgs, num); 924 + } 854 925 855 926 void i2c_dw_configure_master(struct dw_i2c_dev *dev) 856 927 { 857 928 struct i2c_timings *t = &dev->timings; 858 929 859 - dev->functionality = I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY; 930 + dev->functionality |= I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY; 860 931 861 932 dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE | 862 933 DW_IC_CON_RESTART_EN; ··· 892 961 893 962 i2c_dw_prepare_clk(dev, true); 894 963 reset_control_deassert(dev->rst); 895 - i2c_dw_init_master(dev); 964 + i2c_dw_init(dev); 896 965 } 897 966 898 967 static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev) ··· 936 1005 937 1006 int i2c_dw_probe_master(struct dw_i2c_dev *dev) 938 1007 { 939 - struct i2c_adapter *adap = &dev->adapter; 940 - unsigned long irq_flags; 941 1008 unsigned int ic_con; 942 1009 int ret; 943 1010 944 1011 init_completion(&dev->cmd_complete); 945 1012 946 - dev->init = i2c_dw_init_master; 947 - 948 - ret = i2c_dw_init_regmap(dev); 949 - if (ret) 950 - return ret; 951 - 952 1013 ret = i2c_dw_set_timings_master(dev); 953 - if (ret) 954 - return ret; 955 - 956 - ret = i2c_dw_set_fifo_size(dev); 957 1014 if (ret) 958 1015 return ret; 959 1016 ··· 964 1045 if (ic_con & DW_IC_CON_BUS_CLEAR_CTRL) 965 1046 dev->master_cfg |= DW_IC_CON_BUS_CLEAR_CTRL; 966 1047 967 - ret = dev->init(dev); 968 - if (ret) 969 - return ret; 970 - 971 - if (!adap->name[0]) 972 - scnprintf(adap->name, sizeof(adap->name), 973 - "Synopsys DesignWare I2C adapter"); 974 - adap->retries = 3; 975 - adap->algo = &i2c_dw_algo; 976 - adap->quirks = &i2c_dw_quirks; 977 - adap->dev.parent = dev->dev; 978 - i2c_set_adapdata(adap, dev); 979 - 980 - if (dev->flags & ACCESS_NO_IRQ_SUSPEND) { 981 - irq_flags = IRQF_NO_SUSPEND; 982 - } else { 983 - irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND; 984 - } 985 - 986 - ret = i2c_dw_acquire_lock(dev); 987 - if (ret) 988 - return ret; 989 - 990 - __i2c_dw_write_intr_mask(dev, 0); 991 - i2c_dw_release_lock(dev); 992 - 993 - if (!(dev->flags & ACCESS_POLLING)) { 994 - ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, 995 - irq_flags, dev_name(dev->dev), dev); 996 - if (ret) 997 - return dev_err_probe(dev->dev, ret, 998 - "failure requesting irq %i: %d\n", 999 - dev->irq, ret); 1000 - } 1001 - 1002 - ret = i2c_dw_init_recovery_info(dev); 1003 - if (ret) 1004 - return ret; 1005 - 1006 - /* 1007 - * Increment PM usage count during adapter registration in order to 1008 - * avoid possible spurious runtime suspend when adapter device is 1009 - * registered to the device core and immediate resume in case bus has 1010 - * registered I2C slaves that do I2C transfers in their probe. 1011 - */ 1012 - pm_runtime_get_noresume(dev->dev); 1013 - ret = i2c_add_numbered_adapter(adap); 1014 - if (ret) 1015 - dev_err(dev->dev, "failure adding adapter: %d\n", ret); 1016 - pm_runtime_put_noidle(dev->dev); 1017 - 1018 - return ret; 1048 + return i2c_dw_init_recovery_info(dev); 1019 1049 } 1020 - EXPORT_SYMBOL_GPL(i2c_dw_probe_master); 1021 1050 1022 1051 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter"); 1023 1052 MODULE_LICENSE("GPL");

+2 -70

drivers/i2c/busses/i2c-designware-platdrv.c

··· 37 37 return clk_get_rate(dev->clk) / HZ_PER_KHZ; 38 38 } 39 39 40 - #ifdef CONFIG_OF 41 - #define BT1_I2C_CTL 0x100 42 - #define BT1_I2C_CTL_ADDR_MASK GENMASK(7, 0) 43 - #define BT1_I2C_CTL_WR BIT(8) 44 - #define BT1_I2C_CTL_GO BIT(31) 45 - #define BT1_I2C_DI 0x104 46 - #define BT1_I2C_DO 0x108 47 - 48 - static int bt1_i2c_read(void *context, unsigned int reg, unsigned int *val) 49 - { 50 - struct dw_i2c_dev *dev = context; 51 - int ret; 52 - 53 - /* 54 - * Note these methods shouldn't ever fail because the system controller 55 - * registers are memory mapped. We check the return value just in case. 56 - */ 57 - ret = regmap_write(dev->sysmap, BT1_I2C_CTL, 58 - BT1_I2C_CTL_GO | (reg & BT1_I2C_CTL_ADDR_MASK)); 59 - if (ret) 60 - return ret; 61 - 62 - return regmap_read(dev->sysmap, BT1_I2C_DO, val); 63 - } 64 - 65 - static int bt1_i2c_write(void *context, unsigned int reg, unsigned int val) 66 - { 67 - struct dw_i2c_dev *dev = context; 68 - int ret; 69 - 70 - ret = regmap_write(dev->sysmap, BT1_I2C_DI, val); 71 - if (ret) 72 - return ret; 73 - 74 - return regmap_write(dev->sysmap, BT1_I2C_CTL, 75 - BT1_I2C_CTL_GO | BT1_I2C_CTL_WR | (reg & BT1_I2C_CTL_ADDR_MASK)); 76 - } 77 - 78 - static const struct regmap_config bt1_i2c_cfg = { 79 - .reg_bits = 32, 80 - .val_bits = 32, 81 - .reg_stride = 4, 82 - .fast_io = true, 83 - .reg_read = bt1_i2c_read, 84 - .reg_write = bt1_i2c_write, 85 - .max_register = DW_IC_COMP_TYPE, 86 - }; 87 - 88 - static int bt1_i2c_request_regs(struct dw_i2c_dev *dev) 89 - { 90 - dev->sysmap = syscon_node_to_regmap(dev->dev->of_node->parent); 91 - if (IS_ERR(dev->sysmap)) 92 - return PTR_ERR(dev->sysmap); 93 - 94 - dev->map = devm_regmap_init(dev->dev, NULL, dev, &bt1_i2c_cfg); 95 - return PTR_ERR_OR_ZERO(dev->map); 96 - } 97 - #else 98 - static int bt1_i2c_request_regs(struct dw_i2c_dev *dev) 99 - { 100 - return -ENODEV; 101 - } 102 - #endif 103 - 104 40 static int dw_i2c_get_parent_regmap(struct dw_i2c_dev *dev) 105 41 { 106 42 dev->map = dev_get_regmap(dev->dev->parent, NULL); ··· 63 127 return dw_i2c_get_parent_regmap(dev); 64 128 65 129 switch (dev->flags & MODEL_MASK) { 66 - case MODEL_BAIKAL_BT1: 67 - ret = bt1_i2c_request_regs(dev); 68 - break; 69 130 case MODEL_WANGXUN_SP: 70 131 ret = dw_i2c_get_parent_regmap(dev); 71 132 break; ··· 267 334 } 268 335 269 336 static const struct of_device_id dw_i2c_of_match[] = { 270 - { .compatible = "snps,designware-i2c", }, 271 - { .compatible = "mscc,ocelot-i2c", .data = (void *)MODEL_MSCC_OCELOT }, 272 - { .compatible = "baikal,bt1-sys-i2c", .data = (void *)MODEL_BAIKAL_BT1 }, 337 + { .compatible = "mscc,ocelot-i2c" }, 338 + { .compatible = "snps,designware-i2c" }, 273 339 {} 274 340 }; 275 341 MODULE_DEVICE_TABLE(of, dw_i2c_of_match);

+20 -111

drivers/i2c/busses/i2c-designware-slave.c

··· 21 21 22 22 #include "i2c-designware-core.h" 23 23 24 - static void i2c_dw_configure_fifo_slave(struct dw_i2c_dev *dev) 24 + int i2c_dw_reg_slave(struct i2c_client *slave) 25 25 { 26 - /* Configure Tx/Rx FIFO threshold levels. */ 27 - regmap_write(dev->map, DW_IC_TX_TL, 0); 28 - regmap_write(dev->map, DW_IC_RX_TL, 0); 29 - 30 - /* Configure the I2C slave. */ 31 - regmap_write(dev->map, DW_IC_CON, dev->slave_cfg); 32 - regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_SLAVE_MASK); 33 - } 34 - 35 - /** 36 - * i2c_dw_init_slave() - Initialize the DesignWare i2c slave hardware 37 - * @dev: device private data 38 - * 39 - * This function configures and enables the I2C in slave mode. 40 - * This function is called during I2C init function, and in case of timeout at 41 - * run time. 42 - * 43 - * Return: 0 on success, or negative errno otherwise. 44 - */ 45 - static int i2c_dw_init_slave(struct dw_i2c_dev *dev) 46 - { 26 + struct dw_i2c_dev *dev = i2c_get_adapdata(slave->adapter); 47 27 int ret; 28 + 29 + if (!i2c_check_functionality(slave->adapter, I2C_FUNC_SLAVE)) 30 + return -EOPNOTSUPP; 31 + if (dev->slave) 32 + return -EBUSY; 33 + if (slave->flags & I2C_CLIENT_TEN) 34 + return -EAFNOSUPPORT; 48 35 49 36 ret = i2c_dw_acquire_lock(dev); 50 37 if (ret) 51 38 return ret; 52 39 53 - /* Disable the adapter. */ 54 - __i2c_dw_disable(dev); 40 + pm_runtime_get_sync(dev->dev); 41 + __i2c_dw_disable_nowait(dev); 42 + dev->slave = slave; 43 + i2c_dw_set_mode(dev, DW_IC_SLAVE); 55 44 56 - /* Write SDA hold time if supported */ 57 - if (dev->sda_hold_time) 58 - regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time); 59 - 60 - i2c_dw_configure_fifo_slave(dev); 61 45 i2c_dw_release_lock(dev); 62 46 63 47 return 0; 64 48 } 65 49 66 - static int i2c_dw_reg_slave(struct i2c_client *slave) 67 - { 68 - struct dw_i2c_dev *dev = i2c_get_adapdata(slave->adapter); 69 - 70 - if (dev->slave) 71 - return -EBUSY; 72 - if (slave->flags & I2C_CLIENT_TEN) 73 - return -EAFNOSUPPORT; 74 - pm_runtime_get_sync(dev->dev); 75 - 76 - /* 77 - * Set slave address in the IC_SAR register, 78 - * the address to which the DW_apb_i2c responds. 79 - */ 80 - __i2c_dw_disable_nowait(dev); 81 - regmap_write(dev->map, DW_IC_SAR, slave->addr); 82 - dev->slave = slave; 83 - 84 - __i2c_dw_enable(dev); 85 - 86 - dev->status = 0; 87 - 88 - return 0; 89 - } 90 - 91 - static int i2c_dw_unreg_slave(struct i2c_client *slave) 50 + int i2c_dw_unreg_slave(struct i2c_client *slave) 92 51 { 93 52 struct dw_i2c_dev *dev = i2c_get_adapdata(slave->adapter); 94 53 ··· 55 96 i2c_dw_disable(dev); 56 97 synchronize_irq(dev->irq); 57 98 dev->slave = NULL; 99 + i2c_dw_set_mode(dev, DW_IC_MASTER); 58 100 pm_runtime_put_sync_suspend(dev->dev); 59 101 60 102 return 0; ··· 112 152 * Interrupt service routine. This gets called whenever an I2C slave interrupt 113 153 * occurs. 114 154 */ 115 - static irqreturn_t i2c_dw_isr_slave(int this_irq, void *dev_id) 155 + irqreturn_t i2c_dw_isr_slave(struct dw_i2c_dev *dev) 116 156 { 117 - struct dw_i2c_dev *dev = dev_id; 118 157 unsigned int raw_stat, stat, enabled, tmp; 119 158 u8 val = 0, slave_activity; 120 159 ··· 176 217 return IRQ_HANDLED; 177 218 } 178 219 179 - static const struct i2c_algorithm i2c_dw_algo = { 180 - .functionality = i2c_dw_func, 181 - .reg_slave = i2c_dw_reg_slave, 182 - .unreg_slave = i2c_dw_unreg_slave, 183 - }; 184 - 185 220 void i2c_dw_configure_slave(struct dw_i2c_dev *dev) 186 221 { 187 - dev->functionality = I2C_FUNC_SLAVE; 222 + if (dev->flags & ACCESS_POLLING) 223 + return; 224 + 225 + dev->functionality |= I2C_FUNC_SLAVE; 188 226 189 227 dev->slave_cfg = DW_IC_CON_RX_FIFO_FULL_HLD_CTRL | 190 228 DW_IC_CON_RESTART_EN | DW_IC_CON_STOP_DET_IFADDRESSED; 191 - 192 - dev->mode = DW_IC_SLAVE; 193 229 } 194 230 EXPORT_SYMBOL_GPL(i2c_dw_configure_slave); 195 - 196 - int i2c_dw_probe_slave(struct dw_i2c_dev *dev) 197 - { 198 - struct i2c_adapter *adap = &dev->adapter; 199 - int ret; 200 - 201 - dev->init = i2c_dw_init_slave; 202 - 203 - ret = i2c_dw_init_regmap(dev); 204 - if (ret) 205 - return ret; 206 - 207 - ret = i2c_dw_set_sda_hold(dev); 208 - if (ret) 209 - return ret; 210 - 211 - ret = i2c_dw_set_fifo_size(dev); 212 - if (ret) 213 - return ret; 214 - 215 - ret = dev->init(dev); 216 - if (ret) 217 - return ret; 218 - 219 - snprintf(adap->name, sizeof(adap->name), 220 - "Synopsys DesignWare I2C Slave adapter"); 221 - adap->retries = 3; 222 - adap->algo = &i2c_dw_algo; 223 - adap->dev.parent = dev->dev; 224 - i2c_set_adapdata(adap, dev); 225 - 226 - ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr_slave, 227 - IRQF_SHARED, dev_name(dev->dev), dev); 228 - if (ret) 229 - return dev_err_probe(dev->dev, ret, 230 - "failure requesting IRQ %i: %d\n", 231 - dev->irq, ret); 232 - 233 - ret = i2c_add_numbered_adapter(adap); 234 - if (ret) 235 - dev_err(dev->dev, "failure adding adapter: %d\n", ret); 236 - 237 - return ret; 238 - } 239 - EXPORT_SYMBOL_GPL(i2c_dw_probe_slave); 240 231 241 232 MODULE_AUTHOR("Luis Oliveira <lolivei@synopsys.com>"); 242 233 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus slave adapter");

+154 -37

drivers/i2c/busses/i2c-imx-lpi2c.c

··· 5 5 * Copyright 2016 Freescale Semiconductor, Inc. 6 6 */ 7 7 8 + #include <linux/bitfield.h> 8 9 #include <linux/clk.h> 9 10 #include <linux/completion.h> 10 11 #include <linux/delay.h> ··· 91 90 #define MRDR_RXEMPTY BIT(14) 92 91 #define MDER_TDDE BIT(0) 93 92 #define MDER_RDDE BIT(1) 93 + #define MSR_RDF_ASSERTED(x) FIELD_GET(MSR_RDF, (x)) 94 94 95 95 #define SCR_SEN BIT(0) 96 96 #define SCR_RST BIT(1) ··· 133 131 #define CHUNK_DATA 256 134 132 135 133 #define I2C_PM_TIMEOUT 10 /* ms */ 134 + #define I2C_PM_LONG_TIMEOUT_MS 1000 /* Avoid dead lock caused by big clock prepare lock */ 136 135 #define I2C_DMA_THRESHOLD 8 /* bytes */ 137 136 138 137 enum lpi2c_imx_mode { ··· 149 146 TWO_PIN_OO, 150 147 TWO_PIN_PP, 151 148 FOUR_PIN_PP, 149 + }; 150 + 151 + struct imx_lpi2c_hwdata { 152 + bool need_request_free_irq; /* Needed by irqsteer */ 153 + bool need_prepare_unprepare_clk; /* Needed by LPCG */ 152 154 }; 153 155 154 156 struct lpi2c_imx_dma { ··· 194 186 bool can_use_dma; 195 187 struct lpi2c_imx_dma *dma; 196 188 struct i2c_client *target; 189 + int irq; 190 + const struct imx_lpi2c_hwdata *hwdata; 191 + }; 192 + 193 + static const struct imx_lpi2c_hwdata imx7ulp_lpi2c_hwdata = { 194 + }; 195 + 196 + static const struct imx_lpi2c_hwdata imx8qxp_lpi2c_hwdata = { 197 + .need_request_free_irq = true, 198 + .need_prepare_unprepare_clk = true, 199 + }; 200 + 201 + static const struct imx_lpi2c_hwdata imx8qm_lpi2c_hwdata = { 202 + .need_request_free_irq = true, 203 + .need_prepare_unprepare_clk = true, 197 204 }; 198 205 199 206 #define lpi2c_imx_read_msr_poll_timeout(atomic, val, cond) \ ··· 484 461 485 462 static bool lpi2c_imx_read_rxfifo(struct lpi2c_imx_struct *lpi2c_imx, bool atomic) 486 463 { 487 - unsigned int blocklen, remaining; 464 + unsigned int remaining; 488 465 unsigned int temp, data; 489 466 490 467 do { ··· 494 471 495 472 lpi2c_imx->rx_buf[lpi2c_imx->delivered++] = data & 0xff; 496 473 } while (1); 497 - 498 - /* 499 - * First byte is the length of remaining packet in the SMBus block 500 - * data read. Add it to msgs->len. 501 - */ 502 - if (lpi2c_imx->block_data) { 503 - blocklen = lpi2c_imx->rx_buf[0]; 504 - lpi2c_imx->msglen += blocklen; 505 - } 506 474 507 475 remaining = lpi2c_imx->msglen - lpi2c_imx->delivered; 508 476 ··· 507 493 lpi2c_imx_set_rx_watermark(lpi2c_imx); 508 494 509 495 /* multiple receive commands */ 510 - if (lpi2c_imx->block_data) { 511 - lpi2c_imx->block_data = 0; 512 - temp = remaining; 513 - temp |= (RECV_DATA << 8); 514 - writel(temp, lpi2c_imx->base + LPI2C_MTDR); 515 - } else if (!(lpi2c_imx->delivered & 0xff)) { 496 + if (!(lpi2c_imx->delivered & 0xff)) { 516 497 temp = (remaining > CHUNK_DATA ? CHUNK_DATA : remaining) - 1; 517 498 temp |= (RECV_DATA << 8); 518 499 writel(temp, lpi2c_imx->base + LPI2C_MTDR); ··· 545 536 return err; 546 537 } 547 538 548 - static void lpi2c_imx_read_init(struct lpi2c_imx_struct *lpi2c_imx, 549 - struct i2c_msg *msgs) 539 + static unsigned int lpi2c_SMBus_block_read_length_byte(struct lpi2c_imx_struct *lpi2c_imx) 550 540 { 551 - unsigned int temp; 541 + unsigned int data; 542 + 543 + data = readl(lpi2c_imx->base + LPI2C_MRDR); 544 + lpi2c_imx->rx_buf[lpi2c_imx->delivered++] = data & 0xff; 545 + 546 + return data; 547 + } 548 + 549 + static int lpi2c_imx_read_init(struct lpi2c_imx_struct *lpi2c_imx, 550 + struct i2c_msg *msgs) 551 + { 552 + unsigned int temp, val, block_len; 553 + int ret; 552 554 553 555 lpi2c_imx->rx_buf = msgs->buf; 554 556 lpi2c_imx->block_data = msgs->flags & I2C_M_RECV_LEN; 555 557 556 558 lpi2c_imx_set_rx_watermark(lpi2c_imx); 557 - temp = msgs->len > CHUNK_DATA ? CHUNK_DATA - 1 : msgs->len - 1; 558 - temp |= (RECV_DATA << 8); 559 - writel(temp, lpi2c_imx->base + LPI2C_MTDR); 559 + 560 + if (!lpi2c_imx->block_data) { 561 + temp = msgs->len > CHUNK_DATA ? CHUNK_DATA - 1 : msgs->len - 1; 562 + temp |= (RECV_DATA << 8); 563 + writel(temp, lpi2c_imx->base + LPI2C_MTDR); 564 + } else { 565 + /* 566 + * The LPI2C controller automatically sends a NACK after the last byte of a 567 + * receive command, unless the next command in MTDR is also a receive command. 568 + * If MTDR is empty when a receive completes, a NACK is sent by default. 569 + * 570 + * To comply with the SMBus block read spec, we start with a 2-byte read: 571 + * The first byte in RXFIFO is the block length. Once this byte arrives, the 572 + * controller immediately updates MTDR with the next read command, ensuring 573 + * continuous ACK instead of NACK. 574 + * 575 + * The second byte is the first block data byte. Therefore, the subsequent 576 + * read command should request (block_len - 1) bytes, since one data byte 577 + * has already been read. 578 + */ 579 + 580 + writel((RECV_DATA << 8) | 0x01, lpi2c_imx->base + LPI2C_MTDR); 581 + 582 + ret = readl_poll_timeout(lpi2c_imx->base + LPI2C_MSR, val, 583 + MSR_RDF_ASSERTED(val), 1, 1000); 584 + if (ret) { 585 + dev_err(&lpi2c_imx->adapter.dev, "SMBus read count failed %d\n", ret); 586 + return ret; 587 + } 588 + 589 + /* Read block length byte and confirm this SMBus transfer meets protocol */ 590 + block_len = lpi2c_SMBus_block_read_length_byte(lpi2c_imx); 591 + if (block_len == 0 || block_len > I2C_SMBUS_BLOCK_MAX) { 592 + dev_err(&lpi2c_imx->adapter.dev, "Invalid SMBus block read length\n"); 593 + return -EPROTO; 594 + } 595 + 596 + /* 597 + * When block_len shows more bytes need to be read, update second read command to 598 + * keep MTDR non-empty and ensuring continuous ACKs. Only update command register 599 + * here. All block bytes will be read out at IRQ handler or lpi2c_imx_read_atomic() 600 + * function. 601 + */ 602 + if (block_len > 1) 603 + writel((RECV_DATA << 8) | (block_len - 2), lpi2c_imx->base + LPI2C_MTDR); 604 + 605 + lpi2c_imx->msglen += block_len; 606 + msgs->len += block_len; 607 + } 608 + 609 + return 0; 560 610 } 561 611 562 612 static bool lpi2c_imx_read_chunk_atomic(struct lpi2c_imx_struct *lpi2c_imx) ··· 660 592 if (!lpi2c_imx->can_use_dma) 661 593 return false; 662 594 595 + /* DMA is not suitable for SMBus block read */ 596 + if (msg->flags & I2C_M_RECV_LEN) 597 + return false; 598 + 663 599 /* 664 600 * A system-wide suspend or resume transition is in progress. LPI2C should use PIO to 665 601 * transfer data to avoid issue caused by no ready DMA HW resource. ··· 681 609 static int lpi2c_imx_pio_xfer(struct lpi2c_imx_struct *lpi2c_imx, 682 610 struct i2c_msg *msg) 683 611 { 612 + int ret; 613 + 684 614 reinit_completion(&lpi2c_imx->complete); 685 615 686 616 if (msg->flags & I2C_M_RD) { 687 - lpi2c_imx_read_init(lpi2c_imx, msg); 617 + ret = lpi2c_imx_read_init(lpi2c_imx, msg); 618 + if (ret) 619 + return ret; 688 620 lpi2c_imx_intctrl(lpi2c_imx, MIER_RDIE | MIER_NDIE); 689 621 } else { 690 622 lpi2c_imx_write(lpi2c_imx, msg); ··· 700 624 static int lpi2c_imx_pio_xfer_atomic(struct lpi2c_imx_struct *lpi2c_imx, 701 625 struct i2c_msg *msg) 702 626 { 627 + int ret; 628 + 703 629 if (msg->flags & I2C_M_RD) { 704 - lpi2c_imx_read_init(lpi2c_imx, msg); 630 + ret = lpi2c_imx_read_init(lpi2c_imx, msg); 631 + if (ret) 632 + return ret; 705 633 return lpi2c_imx_read_atomic(lpi2c_imx, msg); 706 634 } 707 635 ··· 1450 1370 }; 1451 1371 1452 1372 static const struct of_device_id lpi2c_imx_of_match[] = { 1453 - { .compatible = "fsl,imx7ulp-lpi2c" }, 1373 + { .compatible = "fsl,imx7ulp-lpi2c", .data = &imx7ulp_lpi2c_hwdata,}, 1374 + { .compatible = "fsl,imx8qxp-lpi2c", .data = &imx8qxp_lpi2c_hwdata,}, 1375 + { .compatible = "fsl,imx8qm-lpi2c", .data = &imx8qm_lpi2c_hwdata,}, 1454 1376 { } 1455 1377 }; 1456 1378 MODULE_DEVICE_TABLE(of, lpi2c_imx_of_match); ··· 1463 1381 struct resource *res; 1464 1382 dma_addr_t phy_addr; 1465 1383 unsigned int temp; 1466 - int irq, ret; 1384 + int ret; 1467 1385 1468 1386 lpi2c_imx = devm_kzalloc(&pdev->dev, sizeof(*lpi2c_imx), GFP_KERNEL); 1469 1387 if (!lpi2c_imx) 1470 1388 return -ENOMEM; 1471 1389 1390 + lpi2c_imx->hwdata = of_device_get_match_data(&pdev->dev); 1391 + if (!lpi2c_imx->hwdata) 1392 + return -ENODEV; 1393 + 1472 1394 lpi2c_imx->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1473 1395 if (IS_ERR(lpi2c_imx->base)) 1474 1396 return PTR_ERR(lpi2c_imx->base); 1475 1397 1476 - irq = platform_get_irq(pdev, 0); 1477 - if (irq < 0) 1478 - return irq; 1398 + lpi2c_imx->irq = platform_get_irq(pdev, 0); 1399 + if (lpi2c_imx->irq < 0) 1400 + return lpi2c_imx->irq; 1479 1401 1480 1402 lpi2c_imx->adapter.owner = THIS_MODULE; 1481 1403 lpi2c_imx->adapter.algo = &lpi2c_imx_algo; ··· 1499 1413 if (ret) 1500 1414 lpi2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ; 1501 1415 1502 - ret = devm_request_irq(&pdev->dev, irq, lpi2c_imx_isr, IRQF_NO_SUSPEND, 1416 + ret = devm_request_irq(&pdev->dev, lpi2c_imx->irq, lpi2c_imx_isr, IRQF_NO_SUSPEND, 1503 1417 pdev->name, lpi2c_imx); 1504 1418 if (ret) 1505 - return dev_err_probe(&pdev->dev, ret, "can't claim irq %d\n", irq); 1419 + return dev_err_probe(&pdev->dev, ret, "can't claim irq %d\n", lpi2c_imx->irq); 1506 1420 1507 1421 i2c_set_adapdata(&lpi2c_imx->adapter, lpi2c_imx); 1508 1422 platform_set_drvdata(pdev, lpi2c_imx); ··· 1525 1439 return dev_err_probe(&pdev->dev, -EINVAL, 1526 1440 "can't get I2C peripheral clock rate\n"); 1527 1441 1528 - pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT); 1442 + if (lpi2c_imx->hwdata->need_prepare_unprepare_clk) 1443 + pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_LONG_TIMEOUT_MS); 1444 + else 1445 + pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT); 1446 + 1529 1447 pm_runtime_use_autosuspend(&pdev->dev); 1530 1448 pm_runtime_get_noresume(&pdev->dev); 1531 1449 pm_runtime_set_active(&pdev->dev); ··· 1584 1494 static int __maybe_unused lpi2c_runtime_suspend(struct device *dev) 1585 1495 { 1586 1496 struct lpi2c_imx_struct *lpi2c_imx = dev_get_drvdata(dev); 1497 + bool need_prepare_unprepare_clk = lpi2c_imx->hwdata->need_prepare_unprepare_clk; 1498 + bool need_request_free_irq = lpi2c_imx->hwdata->need_request_free_irq; 1587 1499 1588 - clk_bulk_disable(lpi2c_imx->num_clks, lpi2c_imx->clks); 1500 + if (need_request_free_irq) 1501 + devm_free_irq(dev, lpi2c_imx->irq, lpi2c_imx); 1502 + 1503 + if (need_prepare_unprepare_clk) 1504 + clk_bulk_disable_unprepare(lpi2c_imx->num_clks, lpi2c_imx->clks); 1505 + else 1506 + clk_bulk_disable(lpi2c_imx->num_clks, lpi2c_imx->clks); 1589 1507 pinctrl_pm_select_sleep_state(dev); 1590 1508 1591 1509 return 0; ··· 1602 1504 static int __maybe_unused lpi2c_runtime_resume(struct device *dev) 1603 1505 { 1604 1506 struct lpi2c_imx_struct *lpi2c_imx = dev_get_drvdata(dev); 1507 + bool need_prepare_unprepare_clk = lpi2c_imx->hwdata->need_prepare_unprepare_clk; 1508 + bool need_request_free_irq = lpi2c_imx->hwdata->need_request_free_irq; 1605 1509 int ret; 1606 1510 1607 1511 pinctrl_pm_select_default_state(dev); 1608 - ret = clk_bulk_enable(lpi2c_imx->num_clks, lpi2c_imx->clks); 1609 - if (ret) { 1610 - dev_err(dev, "failed to enable I2C clock, ret=%d\n", ret); 1611 - return ret; 1512 + if (need_prepare_unprepare_clk) { 1513 + ret = clk_bulk_prepare_enable(lpi2c_imx->num_clks, lpi2c_imx->clks); 1514 + if (ret) { 1515 + dev_err(dev, "failed to enable I2C clock, ret=%d\n", ret); 1516 + return ret; 1517 + } 1518 + } else { 1519 + ret = clk_bulk_enable(lpi2c_imx->num_clks, lpi2c_imx->clks); 1520 + if (ret) { 1521 + dev_err(dev, "failed to enable clock %d\n", ret); 1522 + return ret; 1523 + } 1524 + } 1525 + 1526 + if (need_request_free_irq) { 1527 + ret = devm_request_irq(dev, lpi2c_imx->irq, lpi2c_imx_isr, IRQF_NO_SUSPEND, 1528 + dev_name(dev), lpi2c_imx); 1529 + if (ret) { 1530 + dev_err(dev, "can't claim irq %d\n", lpi2c_imx->irq); 1531 + return ret; 1532 + } 1612 1533 } 1613 1534 1614 1535 return 0;

+13 -6

drivers/i2c/busses/i2c-k1.c

··· 4 4 */ 5 5 6 6 #include <linux/bitfield.h> 7 - #include <linux/clk.h> 8 - #include <linux/i2c.h> 9 - #include <linux/iopoll.h> 10 - #include <linux/module.h> 11 - #include <linux/of_address.h> 12 - #include <linux/platform_device.h> 7 + #include <linux/clk.h> 8 + #include <linux/i2c.h> 9 + #include <linux/iopoll.h> 10 + #include <linux/module.h> 11 + #include <linux/of_address.h> 12 + #include <linux/platform_device.h> 13 + #include <linux/reset.h> 13 14 14 15 /* spacemit i2c registers */ 15 16 #define SPACEMIT_ICR 0x0 /* Control register */ ··· 535 534 struct device *dev = &pdev->dev; 536 535 struct device_node *of_node = pdev->dev.of_node; 537 536 struct spacemit_i2c_dev *i2c; 537 + struct reset_control *rst; 538 538 int ret; 539 539 540 540 i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL); ··· 579 577 clk = devm_clk_get_enabled(dev, "bus"); 580 578 if (IS_ERR(clk)) 581 579 return dev_err_probe(dev, PTR_ERR(clk), "failed to enable bus clock"); 580 + 581 + rst = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL); 582 + if (IS_ERR(rst)) 583 + return dev_err_probe(dev, PTR_ERR(rst), 584 + "failed to acquire deasserted reset\n"); 582 585 583 586 spacemit_i2c_reset(i2c); 584 587

+3 -10

drivers/i2c/busses/i2c-mlxbf.c

··· 20 20 #include <linux/platform_device.h> 21 21 #include <linux/string.h> 22 22 #include <linux/string_choices.h> 23 + #include <linux/units.h> 23 24 24 25 /* Defines what functionality is present. */ 25 26 #define MLXBF_I2C_FUNC_SMBUS_BLOCK \ ··· 66 65 * strongly dependent on the core clock frequency of the SMBus 67 66 * Master. Default value is set to 400MHz. 68 67 */ 69 - #define MLXBF_I2C_TYU_PLL_OUT_FREQ (400 * 1000 * 1000) 68 + #define MLXBF_I2C_TYU_PLL_OUT_FREQ (400 * HZ_PER_MHZ) 70 69 /* Reference clock for Bluefield - 156 MHz. */ 71 70 #define MLXBF_I2C_PLL_IN_FREQ 156250000ULL 72 71 73 72 /* Constant used to determine the PLL frequency. */ 74 73 #define MLNXBF_I2C_COREPLL_CONST 16384ULL 75 - 76 - #define MLXBF_I2C_FREQUENCY_1GHZ 1000000000ULL 77 74 78 75 /* PLL registers. */ 79 76 #define MLXBF_I2C_CORE_PLL_REG1 0x4 ··· 323 324 .end = (addr) + (size) - 1, \ 324 325 .name = (str) \ 325 326 } 326 - 327 - enum { 328 - MLXBF_I2C_TIMING_100KHZ = 100000, 329 - MLXBF_I2C_TIMING_400KHZ = 400000, 330 - MLXBF_I2C_TIMING_1000KHZ = 1000000, 331 - }; 332 327 333 328 enum { 334 329 MLXBF_I2C_F_READ = BIT(0), ··· 1076 1083 * Frequency 1077 1084 */ 1078 1085 frequency = priv->frequency; 1079 - ticks = div_u64(nanoseconds * frequency, MLXBF_I2C_FREQUENCY_1GHZ); 1086 + ticks = div_u64(nanoseconds * frequency, HZ_PER_GHZ); 1080 1087 /* 1081 1088 * The number of ticks is rounded down and if minimum is equal to 1 1082 1089 * then add one tick.

+6 -5

drivers/i2c/busses/i2c-mt65xx.c

··· 24 24 #include <linux/scatterlist.h> 25 25 #include <linux/sched.h> 26 26 #include <linux/slab.h> 27 + #include <linux/units.h> 27 28 28 29 #define I2C_RS_TRANSFER (1 << 4) 29 30 #define I2C_ARB_LOST (1 << 3) ··· 686 685 * Check and Calculate i2c ac-timing 687 686 * 688 687 * Hardware design: 689 - * sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src 688 + * sample_ns = (HZ_PER_GHZ * (sample_cnt + 1)) / clk_src 690 689 * xxx_cnt_div = spec->min_xxx_ns / sample_ns 691 690 * 692 691 * Sample_ns is rounded down for xxx_cnt_div would be greater ··· 702 701 { 703 702 const struct i2c_spec_values *spec; 704 703 unsigned int su_sta_cnt, low_cnt, high_cnt, max_step_cnt; 705 - unsigned int sda_max, sda_min, clk_ns, max_sta_cnt = 0x3f; 706 - unsigned int sample_ns = div_u64(1000000000ULL * (sample_cnt + 1), 707 - clk_src); 704 + unsigned int sda_max, sda_min, max_sta_cnt = 0x3f; 705 + unsigned int clk_ns, sample_ns; 708 706 709 707 if (!i2c->dev_comp->timing_adjust) 710 708 return 0; ··· 713 713 714 714 spec = mtk_i2c_get_spec(check_speed); 715 715 716 + sample_ns = div_u64(1ULL * HZ_PER_GHZ * (sample_cnt + 1), clk_src); 716 717 if (i2c->dev_comp->ltiming_adjust) 717 - clk_ns = 1000000000 / clk_src; 718 + clk_ns = HZ_PER_GHZ / clk_src; 718 719 else 719 720 clk_ns = sample_ns / 2; 720 721

+4 -3

drivers/i2c/busses/i2c-nomadik.c

··· 31 31 #include <linux/pm_runtime.h> 32 32 #include <linux/regmap.h> 33 33 #include <linux/slab.h> 34 + #include <linux/units.h> 34 35 35 36 #define DRIVER_NAME "nmk-i2c" 36 37 ··· 420 419 * modes are 250ns, 100ns, 10ns respectively. 421 420 * 422 421 * As the time for one cycle T in nanoseconds is 423 - * T = (1/f) * 1000000000 => 424 - * slsu = cycles / (1000000000 / f) + 1 422 + * T = (1/f) * HZ_PER_GHZ => 423 + * slsu = cycles / (HZ_PER_GHZ / f) + 1 425 424 */ 426 - ns = DIV_ROUND_UP_ULL(1000000000ULL, i2c_clk); 425 + ns = DIV_ROUND_UP(HZ_PER_GHZ, i2c_clk); 427 426 switch (priv->sm) { 428 427 case I2C_FREQ_MODE_FAST: 429 428 case I2C_FREQ_MODE_FAST_PLUS:

+6 -6

drivers/i2c/busses/i2c-rk3x.c

··· 19 19 #include <linux/of_irq.h> 20 20 #include <linux/spinlock.h> 21 21 #include <linux/clk.h> 22 + #include <linux/units.h> 22 23 #include <linux/wait.h> 23 24 #include <linux/mfd/syscon.h> 24 25 #include <linux/regmap.h> ··· 897 896 898 897 clk_disable(i2c->pclk); 899 898 900 - t_low_ns = div_u64(((u64)calc.div_low + 1) * 8 * 1000000000, clk_rate); 901 - t_high_ns = div_u64(((u64)calc.div_high + 1) * 8 * 1000000000, 902 - clk_rate); 899 + t_low_ns = div_u64(8ULL * HZ_PER_GHZ * (calc.div_low + 1), clk_rate); 900 + t_high_ns = div_u64(8ULL * HZ_PER_GHZ * (calc.div_high + 1), clk_rate); 903 901 dev_dbg(i2c->dev, 904 - "CLK %lukhz, Req %uns, Act low %lluns high %lluns\n", 905 - clk_rate / 1000, 906 - 1000000000 / t->bus_freq_hz, 902 + "CLK %lukHz, Req %luns, Act low %lluns high %lluns\n", 903 + clk_rate / HZ_PER_KHZ, 904 + HZ_PER_GHZ / t->bus_freq_hz, 907 905 t_low_ns, t_high_ns); 908 906 } 909 907

+8 -9

drivers/i2c/busses/i2c-rtl9300.c

··· 129 129 130 130 static int rtl9300_i2c_config_chan(struct rtl9300_i2c *i2c, struct rtl9300_i2c_chan *chan) 131 131 { 132 - struct rtl9300_i2c_drv_data *drv_data; 132 + const struct rtl9300_i2c_drv_data *drv_data; 133 133 int ret; 134 134 135 135 if (i2c->sda_num == chan->sda_num) ··· 139 139 if (ret) 140 140 return ret; 141 141 142 - drv_data = (struct rtl9300_i2c_drv_data *)device_get_match_data(i2c->dev); 142 + drv_data = device_get_match_data(i2c->dev); 143 143 ret = drv_data->select_scl(i2c, i2c->scl_num); 144 144 if (ret) 145 145 return ret; ··· 371 371 { 372 372 struct device *dev = &pdev->dev; 373 373 struct rtl9300_i2c *i2c; 374 - struct fwnode_handle *child; 375 - struct rtl9300_i2c_drv_data *drv_data; 374 + const struct rtl9300_i2c_drv_data *drv_data; 376 375 struct reg_field fields[F_NUM_FIELDS]; 377 376 u32 clock_freq, scl_num, sda_num; 378 377 int ret, i = 0; ··· 398 399 399 400 platform_set_drvdata(pdev, i2c); 400 401 401 - drv_data = (struct rtl9300_i2c_drv_data *)device_get_match_data(i2c->dev); 402 + drv_data = device_get_match_data(i2c->dev); 402 403 if (device_get_child_node_count(dev) > drv_data->max_nchan) 403 404 return dev_err_probe(dev, -EINVAL, "Too many channels\n"); 404 405 ··· 414 415 return ret; 415 416 416 417 i = 0; 417 - device_for_each_child_node(dev, child) { 418 + for_each_child_of_node_scoped(dev->of_node, child) { 418 419 struct rtl9300_i2c_chan *chan = &i2c->chans[i]; 419 420 struct i2c_adapter *adap = &chan->adap; 420 421 421 - ret = fwnode_property_read_u32(child, "reg", &sda_num); 422 + ret = of_property_read_u32(child, "reg", &sda_num); 422 423 if (ret) 423 424 return ret; 424 425 425 - ret = fwnode_property_read_u32(child, "clock-frequency", &clock_freq); 426 + ret = of_property_read_u32(child, "clock-frequency", &clock_freq); 426 427 if (ret) 427 428 clock_freq = I2C_MAX_STANDARD_MODE_FREQ; 428 429 ··· 448 449 adap->retries = 3; 449 450 adap->dev.parent = dev; 450 451 i2c_set_adapdata(adap, chan); 451 - adap->dev.of_node = to_of_node(child); 452 + adap->dev.of_node = child; 452 453 snprintf(adap->name, sizeof(adap->name), "%s SDA%d\n", dev_name(dev), sda_num); 453 454 i++; 454 455

+2 -1

drivers/i2c/busses/i2c-st.c

··· 20 20 #include <linux/of.h> 21 21 #include <linux/pinctrl/consumer.h> 22 22 #include <linux/platform_device.h> 23 + #include <linux/units.h> 23 24 24 25 /* SSC registers */ 25 26 #define SSC_BRG 0x000 ··· 286 285 writel_relaxed(val, i2c_dev->base + SSC_CTL); 287 286 288 287 rate = clk_get_rate(i2c_dev->clk); 289 - ns_per_clk = 1000000000 / rate; 288 + ns_per_clk = HZ_PER_GHZ / rate; 290 289 291 290 /* Baudrate */ 292 291 val = rate / (2 * t->rate);

+2 -1

drivers/i2c/busses/i2c-synquacer.c

··· 18 18 #include <linux/sched.h> 19 19 #include <linux/slab.h> 20 20 #include <linux/spinlock.h> 21 + #include <linux/units.h> 21 22 22 23 #define WAIT_PCLK(n, rate) \ 23 - ndelay(DIV_ROUND_UP(DIV_ROUND_UP(1000000000, rate), n) + 10) 24 + ndelay(DIV_ROUND_UP(DIV_ROUND_UP(HZ_PER_GHZ, rate), n) + 10) 24 25 25 26 /* I2C register address definitions */ 26 27 #define SYNQUACER_I2C_REG_BSR (0x00 << 2) // Bus Status

+258 -48

drivers/i2c/busses/i2c-tegra.c

··· 85 85 #define PACKET_HEADER0_PROTOCOL GENMASK(7, 4) 86 86 #define PACKET_HEADER0_PROTOCOL_I2C 1 87 87 88 + #define I2C_HEADER_HS_MODE BIT(22) 88 89 #define I2C_HEADER_CONT_ON_NAK BIT(21) 89 90 #define I2C_HEADER_READ BIT(19) 90 91 #define I2C_HEADER_10BIT_ADDR BIT(18) ··· 136 135 #define I2C_MST_FIFO_STATUS_RX GENMASK(7, 0) 137 136 138 137 #define I2C_MASTER_RESET_CNTRL 0x0a8 138 + 139 + #define I2C_SW_MUTEX 0x0ec 140 + #define I2C_SW_MUTEX_REQUEST GENMASK(3, 0) 141 + #define I2C_SW_MUTEX_GRANT GENMASK(7, 4) 142 + #define I2C_SW_MUTEX_ID_CCPLEX 9 143 + 144 + /* SW mutex acquire timeout value in microseconds. */ 145 + #define I2C_SW_MUTEX_TIMEOUT_US (25 * USEC_PER_MSEC) 139 146 140 147 /* configuration load timeout in microseconds */ 141 148 #define I2C_CONFIG_LOAD_TIMEOUT 1000000 ··· 205 196 * @has_apb_dma: Support of APBDMA on corresponding Tegra chip. 206 197 * @tlow_std_mode: Low period of the clock in standard mode. 207 198 * @thigh_std_mode: High period of the clock in standard mode. 208 - * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes. 209 - * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus modes. 199 + * @tlow_fast_mode: Low period of the clock in fast mode. 200 + * @thigh_fast_mode: High period of the clock in fast mode. 201 + * @tlow_fastplus_mode: Low period of the clock in fast-plus mode. 202 + * @thigh_fastplus_mode: High period of the clock in fast-plus mode. 203 + * @tlow_hs_mode: Low period of the clock in HS mode. 204 + * @thigh_hs_mode: High period of the clock in HS mode. 210 205 * @setup_hold_time_std_mode: Setup and hold time for start and stop conditions 211 206 * in standard mode. 212 - * @setup_hold_time_fast_fast_plus_mode: Setup and hold time for start and stop 213 - * conditions in fast/fast-plus modes. 207 + * @setup_hold_time_fast_mode: Setup and hold time for start and stop 208 + * conditions in fast mode. 209 + * @setup_hold_time_fastplus_mode: Setup and hold time for start and stop 210 + * conditions in fast-plus mode. 214 211 * @setup_hold_time_hs_mode: Setup and hold time for start and stop conditions 215 212 * in HS mode. 216 213 * @has_interface_timing_reg: Has interface timing register to program the tuned 217 214 * timing settings. 215 + * @enable_hs_mode_support: Enable support for high speed (HS) mode transfers. 216 + * @has_mutex: Has mutex register for mutual exclusion with other firmwares or VMs. 218 217 */ 219 218 struct tegra_i2c_hw_feature { 220 219 bool has_continue_xfer_support; ··· 241 224 bool has_apb_dma; 242 225 u32 tlow_std_mode; 243 226 u32 thigh_std_mode; 244 - u32 tlow_fast_fastplus_mode; 245 - u32 thigh_fast_fastplus_mode; 227 + u32 tlow_fast_mode; 228 + u32 thigh_fast_mode; 229 + u32 tlow_fastplus_mode; 230 + u32 thigh_fastplus_mode; 231 + u32 tlow_hs_mode; 232 + u32 thigh_hs_mode; 246 233 u32 setup_hold_time_std_mode; 247 - u32 setup_hold_time_fast_fast_plus_mode; 234 + u32 setup_hold_time_fast_mode; 235 + u32 setup_hold_time_fastplus_mode; 248 236 u32 setup_hold_time_hs_mode; 249 237 bool has_interface_timing_reg; 238 + bool enable_hs_mode_support; 239 + bool has_mutex; 250 240 }; 251 241 252 242 /** ··· 264 240 * @div_clk: clock reference for div clock of I2C controller 265 241 * @clocks: array of I2C controller clocks 266 242 * @nclocks: number of clocks in the array 267 - * @rst: reset control for the I2C controller 268 243 * @base: ioremapped registers cookie 269 244 * @base_phys: physical base address of the I2C controller 270 245 * @cont_id: I2C controller ID, used for packet header ··· 292 269 struct i2c_adapter adapter; 293 270 294 271 const struct tegra_i2c_hw_feature *hw; 295 - struct reset_control *rst; 296 272 unsigned int cont_id; 297 273 unsigned int irq; 298 274 ··· 396 374 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 397 375 } 398 376 377 + static bool tegra_i2c_mutex_acquired(struct tegra_i2c_dev *i2c_dev) 378 + { 379 + unsigned int reg = tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX); 380 + u32 val, id; 381 + 382 + val = readl(i2c_dev->base + reg); 383 + id = FIELD_GET(I2C_SW_MUTEX_GRANT, val); 384 + 385 + return id == I2C_SW_MUTEX_ID_CCPLEX; 386 + } 387 + 388 + static bool tegra_i2c_mutex_trylock(struct tegra_i2c_dev *i2c_dev) 389 + { 390 + unsigned int reg = tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX); 391 + u32 val, id; 392 + 393 + val = readl(i2c_dev->base + reg); 394 + id = FIELD_GET(I2C_SW_MUTEX_GRANT, val); 395 + if (id != 0 && id != I2C_SW_MUTEX_ID_CCPLEX) 396 + return false; 397 + 398 + val = FIELD_PREP(I2C_SW_MUTEX_REQUEST, I2C_SW_MUTEX_ID_CCPLEX); 399 + writel(val, i2c_dev->base + reg); 400 + 401 + return tegra_i2c_mutex_acquired(i2c_dev); 402 + } 403 + 404 + static int tegra_i2c_mutex_lock(struct tegra_i2c_dev *i2c_dev) 405 + { 406 + bool locked; 407 + int ret; 408 + 409 + if (!i2c_dev->hw->has_mutex) 410 + return 0; 411 + 412 + if (i2c_dev->atomic_mode) 413 + ret = read_poll_timeout_atomic(tegra_i2c_mutex_trylock, locked, locked, 414 + USEC_PER_MSEC, I2C_SW_MUTEX_TIMEOUT_US, 415 + false, i2c_dev); 416 + else 417 + ret = read_poll_timeout(tegra_i2c_mutex_trylock, locked, locked, USEC_PER_MSEC, 418 + I2C_SW_MUTEX_TIMEOUT_US, false, i2c_dev); 419 + 420 + if (ret) 421 + dev_warn(i2c_dev->dev, "failed to acquire mutex\n"); 422 + 423 + return ret; 424 + } 425 + 426 + static int tegra_i2c_mutex_unlock(struct tegra_i2c_dev *i2c_dev) 427 + { 428 + unsigned int reg = tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX); 429 + u32 val, id; 430 + 431 + if (!i2c_dev->hw->has_mutex) 432 + return 0; 433 + 434 + val = readl(i2c_dev->base + reg); 435 + 436 + id = FIELD_GET(I2C_SW_MUTEX_GRANT, val); 437 + if (id && id != I2C_SW_MUTEX_ID_CCPLEX) { 438 + dev_warn(i2c_dev->dev, "unable to unlock mutex, mutex is owned by: %u\n", id); 439 + return -EPERM; 440 + } 441 + 442 + writel(0, i2c_dev->base + reg); 443 + 444 + return 0; 445 + } 446 + 399 447 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 400 448 { 401 449 u32 int_mask; ··· 540 448 541 449 if (IS_VI(i2c_dev)) 542 450 return 0; 451 + 452 + if (!of_property_present(i2c_dev->dev->of_node, "dmas")) { 453 + dev_dbg(i2c_dev->dev, "DMA not available, falling back to PIO\n"); 454 + return 0; 455 + } 543 456 544 457 if (i2c_dev->hw->has_apb_dma) { 545 458 if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) { ··· 731 634 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) 732 635 { 733 636 u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode; 637 + u32 max_bus_freq_hz; 734 638 struct i2c_timings *t = &i2c_dev->timings; 735 639 int err; 736 640 ··· 770 672 if (IS_VI(i2c_dev)) 771 673 tegra_i2c_vi_init(i2c_dev); 772 674 773 - switch (t->bus_freq_hz) { 774 - case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ: 775 - default: 776 - tlow = i2c_dev->hw->tlow_fast_fastplus_mode; 777 - thigh = i2c_dev->hw->thigh_fast_fastplus_mode; 778 - tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode; 675 + if (i2c_dev->hw->enable_hs_mode_support) 676 + max_bus_freq_hz = I2C_MAX_HIGH_SPEED_MODE_FREQ; 677 + else 678 + max_bus_freq_hz = I2C_MAX_FAST_MODE_PLUS_FREQ; 779 679 780 - if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) 781 - non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode; 782 - else 783 - non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode; 784 - break; 680 + if (WARN_ON(t->bus_freq_hz > max_bus_freq_hz)) 681 + t->bus_freq_hz = max_bus_freq_hz; 785 682 786 - case 0 ... I2C_MAX_STANDARD_MODE_FREQ: 683 + if (t->bus_freq_hz <= I2C_MAX_STANDARD_MODE_FREQ) { 787 684 tlow = i2c_dev->hw->tlow_std_mode; 788 685 thigh = i2c_dev->hw->thigh_std_mode; 789 686 tsu_thd = i2c_dev->hw->setup_hold_time_std_mode; 790 687 non_hs_mode = i2c_dev->hw->clk_divisor_std_mode; 791 - break; 688 + } else if (t->bus_freq_hz <= I2C_MAX_FAST_MODE_FREQ) { 689 + tlow = i2c_dev->hw->tlow_fast_mode; 690 + thigh = i2c_dev->hw->thigh_fast_mode; 691 + tsu_thd = i2c_dev->hw->setup_hold_time_fast_mode; 692 + non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode; 693 + } else if (t->bus_freq_hz <= I2C_MAX_FAST_MODE_PLUS_FREQ) { 694 + tlow = i2c_dev->hw->tlow_fastplus_mode; 695 + thigh = i2c_dev->hw->thigh_fastplus_mode; 696 + tsu_thd = i2c_dev->hw->setup_hold_time_fastplus_mode; 697 + non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode; 698 + } else { 699 + /* 700 + * When using HS mode, i.e. when the bus frequency is greater than fast plus mode, 701 + * the non-hs timing registers will be used for sending the master code byte for 702 + * transition to HS mode. Configure the non-hs timing registers for Fast Mode to 703 + * send the master code byte at 400kHz. 704 + */ 705 + tlow = i2c_dev->hw->tlow_fast_mode; 706 + thigh = i2c_dev->hw->thigh_fast_mode; 707 + tsu_thd = i2c_dev->hw->setup_hold_time_fast_mode; 708 + non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode; 792 709 } 793 710 794 711 /* make sure clock divisor programmed correctly */ ··· 824 711 */ 825 712 if (i2c_dev->hw->has_interface_timing_reg && tsu_thd) 826 713 i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1); 714 + 715 + /* Write HS mode registers. These will get used only for HS mode*/ 716 + if (i2c_dev->hw->enable_hs_mode_support) { 717 + tlow = i2c_dev->hw->tlow_hs_mode; 718 + thigh = i2c_dev->hw->thigh_hs_mode; 719 + tsu_thd = i2c_dev->hw->setup_hold_time_hs_mode; 720 + 721 + val = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, thigh) | 722 + FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, tlow); 723 + i2c_writel(i2c_dev, val, I2C_HS_INTERFACE_TIMING_0); 724 + i2c_writel(i2c_dev, tsu_thd, I2C_HS_INTERFACE_TIMING_1); 725 + } 827 726 828 727 clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1); 829 728 ··· 1334 1209 if (msg->flags & I2C_M_RD) 1335 1210 packet_header |= I2C_HEADER_READ; 1336 1211 1212 + if (i2c_dev->timings.bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) 1213 + packet_header |= I2C_HEADER_HS_MODE; 1214 + 1337 1215 if (i2c_dev->dma_mode && !i2c_dev->msg_read) 1338 1216 *dma_buf++ = packet_header; 1339 1217 else ··· 1521 1393 return ret; 1522 1394 } 1523 1395 1396 + ret = tegra_i2c_mutex_lock(i2c_dev); 1397 + if (ret) 1398 + return ret; 1399 + 1524 1400 for (i = 0; i < num; i++) { 1525 1401 enum msg_end_type end_type = MSG_END_STOP; 1526 1402 ··· 1554 1422 break; 1555 1423 } 1556 1424 1425 + ret = tegra_i2c_mutex_unlock(i2c_dev); 1557 1426 pm_runtime_put(i2c_dev->dev); 1558 1427 1559 1428 return ret ?: i; ··· 1624 1491 .has_apb_dma = true, 1625 1492 .tlow_std_mode = 0x4, 1626 1493 .thigh_std_mode = 0x2, 1627 - .tlow_fast_fastplus_mode = 0x4, 1628 - .thigh_fast_fastplus_mode = 0x2, 1494 + .tlow_fast_mode = 0x4, 1495 + .thigh_fast_mode = 0x2, 1496 + .tlow_fastplus_mode = 0x4, 1497 + .thigh_fastplus_mode = 0x2, 1629 1498 .setup_hold_time_std_mode = 0x0, 1630 - .setup_hold_time_fast_fast_plus_mode = 0x0, 1499 + .setup_hold_time_fast_mode = 0x0, 1500 + .setup_hold_time_fastplus_mode = 0x0, 1631 1501 .setup_hold_time_hs_mode = 0x0, 1632 1502 .has_interface_timing_reg = false, 1503 + .enable_hs_mode_support = false, 1504 + .has_mutex = false, 1633 1505 }; 1634 1506 1635 1507 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { ··· 1654 1516 .has_apb_dma = true, 1655 1517 .tlow_std_mode = 0x4, 1656 1518 .thigh_std_mode = 0x2, 1657 - .tlow_fast_fastplus_mode = 0x4, 1658 - .thigh_fast_fastplus_mode = 0x2, 1519 + .tlow_fast_mode = 0x4, 1520 + .thigh_fast_mode = 0x2, 1521 + .tlow_fastplus_mode = 0x4, 1522 + .thigh_fastplus_mode = 0x2, 1659 1523 .setup_hold_time_std_mode = 0x0, 1660 - .setup_hold_time_fast_fast_plus_mode = 0x0, 1524 + .setup_hold_time_fast_mode = 0x0, 1525 + .setup_hold_time_fastplus_mode = 0x0, 1661 1526 .setup_hold_time_hs_mode = 0x0, 1662 1527 .has_interface_timing_reg = false, 1528 + .enable_hs_mode_support = false, 1529 + .has_mutex = false, 1663 1530 }; 1664 1531 1665 1532 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { ··· 1684 1541 .has_apb_dma = true, 1685 1542 .tlow_std_mode = 0x4, 1686 1543 .thigh_std_mode = 0x2, 1687 - .tlow_fast_fastplus_mode = 0x4, 1688 - .thigh_fast_fastplus_mode = 0x2, 1544 + .tlow_fast_mode = 0x4, 1545 + .thigh_fast_mode = 0x2, 1546 + .tlow_fastplus_mode = 0x4, 1547 + .thigh_fastplus_mode = 0x2, 1689 1548 .setup_hold_time_std_mode = 0x0, 1690 - .setup_hold_time_fast_fast_plus_mode = 0x0, 1549 + .setup_hold_time_fast_mode = 0x0, 1550 + .setup_hold_time_fastplus_mode = 0x0, 1691 1551 .setup_hold_time_hs_mode = 0x0, 1692 1552 .has_interface_timing_reg = false, 1553 + .enable_hs_mode_support = false, 1554 + .has_mutex = false, 1693 1555 }; 1694 1556 1695 1557 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { ··· 1714 1566 .has_apb_dma = true, 1715 1567 .tlow_std_mode = 0x4, 1716 1568 .thigh_std_mode = 0x2, 1717 - .tlow_fast_fastplus_mode = 0x4, 1718 - .thigh_fast_fastplus_mode = 0x2, 1569 + .tlow_fast_mode = 0x4, 1570 + .thigh_fast_mode = 0x2, 1571 + .tlow_fastplus_mode = 0x4, 1572 + .thigh_fastplus_mode = 0x2, 1719 1573 .setup_hold_time_std_mode = 0x0, 1720 - .setup_hold_time_fast_fast_plus_mode = 0x0, 1574 + .setup_hold_time_fast_mode = 0x0, 1575 + .setup_hold_time_fastplus_mode = 0x0, 1721 1576 .setup_hold_time_hs_mode = 0x0, 1722 1577 .has_interface_timing_reg = true, 1578 + .enable_hs_mode_support = false, 1579 + .has_mutex = false, 1723 1580 }; 1724 1581 1725 1582 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { ··· 1744 1591 .has_apb_dma = true, 1745 1592 .tlow_std_mode = 0x4, 1746 1593 .thigh_std_mode = 0x2, 1747 - .tlow_fast_fastplus_mode = 0x4, 1748 - .thigh_fast_fastplus_mode = 0x2, 1594 + .tlow_fast_mode = 0x4, 1595 + .thigh_fast_mode = 0x2, 1596 + .tlow_fastplus_mode = 0x4, 1597 + .thigh_fastplus_mode = 0x2, 1749 1598 .setup_hold_time_std_mode = 0, 1750 - .setup_hold_time_fast_fast_plus_mode = 0, 1599 + .setup_hold_time_fast_mode = 0, 1600 + .setup_hold_time_fastplus_mode = 0, 1751 1601 .setup_hold_time_hs_mode = 0, 1752 1602 .has_interface_timing_reg = true, 1603 + .enable_hs_mode_support = false, 1604 + .has_mutex = false, 1753 1605 }; 1754 1606 1755 1607 static const struct tegra_i2c_hw_feature tegra186_i2c_hw = { ··· 1774 1616 .has_apb_dma = false, 1775 1617 .tlow_std_mode = 0x4, 1776 1618 .thigh_std_mode = 0x3, 1777 - .tlow_fast_fastplus_mode = 0x4, 1778 - .thigh_fast_fastplus_mode = 0x2, 1619 + .tlow_fast_mode = 0x4, 1620 + .thigh_fast_mode = 0x2, 1621 + .tlow_fastplus_mode = 0x4, 1622 + .thigh_fastplus_mode = 0x2, 1779 1623 .setup_hold_time_std_mode = 0, 1780 - .setup_hold_time_fast_fast_plus_mode = 0, 1624 + .setup_hold_time_fast_mode = 0, 1625 + .setup_hold_time_fastplus_mode = 0, 1781 1626 .setup_hold_time_hs_mode = 0, 1782 1627 .has_interface_timing_reg = true, 1628 + .enable_hs_mode_support = false, 1629 + .has_mutex = false, 1783 1630 }; 1784 1631 1785 1632 static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { ··· 1804 1641 .has_apb_dma = false, 1805 1642 .tlow_std_mode = 0x8, 1806 1643 .thigh_std_mode = 0x7, 1807 - .tlow_fast_fastplus_mode = 0x2, 1808 - .thigh_fast_fastplus_mode = 0x2, 1644 + .tlow_fast_mode = 0x2, 1645 + .thigh_fast_mode = 0x2, 1646 + .tlow_fastplus_mode = 0x2, 1647 + .thigh_fastplus_mode = 0x2, 1648 + .tlow_hs_mode = 0x8, 1649 + .thigh_hs_mode = 0x3, 1809 1650 .setup_hold_time_std_mode = 0x08080808, 1810 - .setup_hold_time_fast_fast_plus_mode = 0x02020202, 1651 + .setup_hold_time_fast_mode = 0x02020202, 1652 + .setup_hold_time_fastplus_mode = 0x02020202, 1811 1653 .setup_hold_time_hs_mode = 0x090909, 1812 1654 .has_interface_timing_reg = true, 1655 + .enable_hs_mode_support = true, 1656 + .has_mutex = false, 1813 1657 }; 1814 1658 1815 1659 static const struct tegra_i2c_hw_feature tegra256_i2c_hw = { 1816 1660 .has_continue_xfer_support = true, 1817 1661 .has_per_pkt_xfer_complete_irq = true, 1818 - .clk_divisor_hs_mode = 7, 1662 + .clk_divisor_hs_mode = 9, 1819 1663 .clk_divisor_std_mode = 0x7a, 1820 1664 .clk_divisor_fast_mode = 0x40, 1821 - .clk_divisor_fast_plus_mode = 0x19, 1665 + .clk_divisor_fast_plus_mode = 0x14, 1822 1666 .has_config_load_reg = true, 1823 1667 .has_multi_master_mode = true, 1824 1668 .has_slcg_override_reg = true, ··· 1836 1666 .has_apb_dma = false, 1837 1667 .tlow_std_mode = 0x8, 1838 1668 .thigh_std_mode = 0x7, 1839 - .tlow_fast_fastplus_mode = 0x3, 1840 - .thigh_fast_fastplus_mode = 0x3, 1669 + .tlow_fast_mode = 0x4, 1670 + .thigh_fast_mode = 0x2, 1671 + .tlow_fastplus_mode = 0x4, 1672 + .thigh_fastplus_mode = 0x4, 1673 + .tlow_hs_mode = 0x3, 1674 + .thigh_hs_mode = 0x2, 1841 1675 .setup_hold_time_std_mode = 0x08080808, 1842 - .setup_hold_time_fast_fast_plus_mode = 0x02020202, 1676 + .setup_hold_time_fast_mode = 0x04010101, 1677 + .setup_hold_time_fastplus_mode = 0x04020202, 1678 + .setup_hold_time_hs_mode = 0x030303, 1679 + .has_interface_timing_reg = true, 1680 + .enable_hs_mode_support = true, 1681 + .has_mutex = true, 1682 + }; 1683 + 1684 + static const struct tegra_i2c_hw_feature tegra264_i2c_hw = { 1685 + .has_continue_xfer_support = true, 1686 + .has_per_pkt_xfer_complete_irq = true, 1687 + .clk_divisor_hs_mode = 1, 1688 + .clk_divisor_std_mode = 0x1d, 1689 + .clk_divisor_fast_mode = 0x15, 1690 + .clk_divisor_fast_plus_mode = 0x8, 1691 + .has_config_load_reg = true, 1692 + .has_multi_master_mode = true, 1693 + .has_slcg_override_reg = true, 1694 + .has_mst_fifo = true, 1695 + .has_mst_reset = true, 1696 + .quirks = &tegra194_i2c_quirks, 1697 + .supports_bus_clear = true, 1698 + .has_apb_dma = false, 1699 + .tlow_std_mode = 0x8, 1700 + .thigh_std_mode = 0x7, 1701 + .tlow_fast_mode = 0x2, 1702 + .thigh_fast_mode = 0x2, 1703 + .tlow_fastplus_mode = 0x2, 1704 + .thigh_fastplus_mode = 0x2, 1705 + .tlow_hs_mode = 0x4, 1706 + .thigh_hs_mode = 0x2, 1707 + .setup_hold_time_std_mode = 0x08080808, 1708 + .setup_hold_time_fast_mode = 0x02020202, 1709 + .setup_hold_time_fastplus_mode = 0x02020202, 1843 1710 .setup_hold_time_hs_mode = 0x090909, 1844 1711 .has_interface_timing_reg = true, 1712 + .enable_hs_mode_support = true, 1713 + .has_mutex = true, 1845 1714 }; 1846 1715 1847 1716 static const struct of_device_id tegra_i2c_of_match[] = { 1717 + { .compatible = "nvidia,tegra264-i2c", .data = &tegra264_i2c_hw, }, 1848 1718 { .compatible = "nvidia,tegra256-i2c", .data = &tegra256_i2c_hw, }, 1849 1719 { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, }, 1850 1720 { .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, },

+5 -5

drivers/i2c/i2c-core-base.c

··· 1090 1090 struct i2c_client *client; 1091 1091 struct device *dev; 1092 1092 1093 - if (!fwnode) 1093 + if (IS_ERR_OR_NULL(fwnode)) 1094 1094 return NULL; 1095 1095 1096 1096 dev = bus_find_device_by_fwnode(&i2c_bus_type, fwnode); ··· 1476 1476 if (!i2c_check_functionality(adap, I2C_FUNC_SMBUS_HOST_NOTIFY)) 1477 1477 return 0; 1478 1478 1479 - domain = irq_domain_create_linear(adap->dev.parent->fwnode, 1479 + domain = irq_domain_create_linear(dev_fwnode(adap->dev.parent), 1480 1480 I2C_ADDR_7BITS_COUNT, 1481 1481 &i2c_host_notify_irq_ops, adap); 1482 1482 if (!domain) ··· 1852 1852 1853 1853 static int i2c_dev_or_parent_fwnode_match(struct device *dev, const void *data) 1854 1854 { 1855 - if (dev_fwnode(dev) == data) 1855 + if (device_match_fwnode(dev, data)) 1856 1856 return 1; 1857 1857 1858 - if (dev->parent && dev_fwnode(dev->parent) == data) 1858 + if (dev->parent && device_match_fwnode(dev->parent, data)) 1859 1859 return 1; 1860 1860 1861 1861 return 0; ··· 1875 1875 struct i2c_adapter *adapter; 1876 1876 struct device *dev; 1877 1877 1878 - if (!fwnode) 1878 + if (IS_ERR_OR_NULL(fwnode)) 1879 1879 return NULL; 1880 1880 1881 1881 dev = bus_find_device(&i2c_bus_type, NULL, fwnode,

+7 -13

drivers/misc/eeprom/at24.c

··· 657 657 if (!i2c_fn_i2c && !i2c_fn_block) 658 658 page_size = 1; 659 659 660 - if (!page_size) { 661 - dev_err(dev, "page_size must not be 0!\n"); 662 - return -EINVAL; 663 - } 660 + if (!page_size) 661 + return dev_err_probe(dev, -EINVAL, "page_size must not be 0!\n"); 664 662 665 663 if (!is_power_of_2(page_size)) 666 664 dev_warn(dev, "page_size looks suspicious (no power of 2)!\n"); ··· 672 674 (flags & AT24_FLAG_ADDR16) ? 65536 : 256); 673 675 } 674 676 675 - if ((flags & AT24_FLAG_SERIAL) && (flags & AT24_FLAG_MAC)) { 676 - dev_err(dev, 677 - "invalid device data - cannot have both AT24_FLAG_SERIAL & AT24_FLAG_MAC."); 678 - return -EINVAL; 679 - } 677 + if ((flags & AT24_FLAG_SERIAL) && (flags & AT24_FLAG_MAC)) 678 + return dev_err_probe(dev, -EINVAL, 679 + "invalid device data - cannot have both AT24_FLAG_SERIAL & AT24_FLAG_MAC."); 680 680 681 681 regmap_config.val_bits = 8; 682 682 regmap_config.reg_bits = (flags & AT24_FLAG_ADDR16) ? 16 : 8; ··· 755 759 full_power = acpi_dev_state_d0(&client->dev); 756 760 if (full_power) { 757 761 err = regulator_enable(at24->vcc_reg); 758 - if (err) { 759 - dev_err(dev, "Failed to enable vcc regulator\n"); 760 - return err; 761 - } 762 + if (err) 763 + return dev_err_probe(dev, err, "Failed to enable vcc regulator\n"); 762 764 763 765 pm_runtime_set_active(dev); 764 766 }

+3

include/linux/units.h

··· 25 25 #define MICROHZ_PER_HZ 1000000UL 26 26 #define MILLIHZ_PER_HZ 1000UL 27 27 28 + /* Hz based multipliers */ 28 29 #define HZ_PER_KHZ 1000UL 29 30 #define HZ_PER_MHZ 1000000UL 31 + #define HZ_PER_GHZ 1000000000UL 30 32 33 + /* kHz based multipliers */ 31 34 #define KHZ_PER_MHZ 1000UL 32 35 #define KHZ_PER_GHZ 1000000UL 33 36

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