Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: Use RMW accessors for changing LNKCTL2
Convert open coded RMW accesses for LNKCTL2 to use
pcie_capability_clear_and_set_word() which makes its easier to
understand what the code tries to do.
LNKCTL2 is not really owned by any driver because it is a collection of
control bits that PCI core might need to touch. RMW accessors already
have support for proper locking for a selected set of registers
(LNKCTL2 is not yet among them but likely will be in the future) to
avoid losing concurrent updates.
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Suggested-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Ilpo Järvinen
and committed by
Alex Deucher
bb87e511
a5fc4e50
+30
-52
+15
-26
drivers/gpu/drm/amd/amdgpu/cik.c
+15
-26
drivers/gpu/drm/amd/amdgpu/cik.c
···
1638
1638
PCI_EXP_LNKCTL_HAWD);
1639
1639
1640
1640
/* linkctl2 */
1641
-
pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
1642
-
&tmp16);
1643
-
tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
1644
-
PCI_EXP_LNKCTL2_TX_MARGIN);
1645
-
tmp16 |= (bridge_cfg2 &
1646
-
(PCI_EXP_LNKCTL2_ENTER_COMP |
1647
-
PCI_EXP_LNKCTL2_TX_MARGIN));
1648
-
pcie_capability_write_word(root,
1649
-
PCI_EXP_LNKCTL2,
1650
-
tmp16);
1651
-
1652
-
pcie_capability_read_word(adev->pdev,
1653
-
PCI_EXP_LNKCTL2,
1654
-
&tmp16);
1655
-
tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
1656
-
PCI_EXP_LNKCTL2_TX_MARGIN);
1657
-
tmp16 |= (gpu_cfg2 &
1658
-
(PCI_EXP_LNKCTL2_ENTER_COMP |
1659
-
PCI_EXP_LNKCTL2_TX_MARGIN));
1660
-
pcie_capability_write_word(adev->pdev,
1661
-
PCI_EXP_LNKCTL2,
1662
-
tmp16);
1641
+
pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL2,
1642
+
PCI_EXP_LNKCTL2_ENTER_COMP |
1643
+
PCI_EXP_LNKCTL2_TX_MARGIN,
1644
+
bridge_cfg2 &
1645
+
(PCI_EXP_LNKCTL2_ENTER_COMP |
1646
+
PCI_EXP_LNKCTL2_TX_MARGIN));
1647
+
pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL2,
1648
+
PCI_EXP_LNKCTL2_ENTER_COMP |
1649
+
PCI_EXP_LNKCTL2_TX_MARGIN,
1650
+
gpu_cfg2 &
1651
+
(PCI_EXP_LNKCTL2_ENTER_COMP |
1652
+
PCI_EXP_LNKCTL2_TX_MARGIN));
1663
1653
1664
1654
tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
1665
1655
tmp &= ~PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK;
···
1664
1674
speed_cntl &= ~PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK;
1665
1675
WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl);
1666
1676
1667
-
pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL2, &tmp16);
1668
-
tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
1669
-
1677
+
tmp16 = 0;
1670
1678
if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1671
1679
tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
1672
1680
else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1673
1681
tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
1674
1682
else
1675
1683
tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
1676
-
pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL2, tmp16);
1684
+
pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL2,
1685
+
PCI_EXP_LNKCTL2_TLS, tmp16);
1677
1686
1678
1687
speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);
1679
1688
speed_cntl |= PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK;
+15
-26
drivers/gpu/drm/amd/amdgpu/si.c
+15
-26
drivers/gpu/drm/amd/amdgpu/si.c
···
2331
2331
gpu_cfg &
2332
2332
PCI_EXP_LNKCTL_HAWD);
2333
2333
2334
-
pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
2335
-
&tmp16);
2336
-
tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
2337
-
PCI_EXP_LNKCTL2_TX_MARGIN);
2338
-
tmp16 |= (bridge_cfg2 &
2339
-
(PCI_EXP_LNKCTL2_ENTER_COMP |
2340
-
PCI_EXP_LNKCTL2_TX_MARGIN));
2341
-
pcie_capability_write_word(root,
2342
-
PCI_EXP_LNKCTL2,
2343
-
tmp16);
2344
-
2345
-
pcie_capability_read_word(adev->pdev,
2346
-
PCI_EXP_LNKCTL2,
2347
-
&tmp16);
2348
-
tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
2349
-
PCI_EXP_LNKCTL2_TX_MARGIN);
2350
-
tmp16 |= (gpu_cfg2 &
2351
-
(PCI_EXP_LNKCTL2_ENTER_COMP |
2352
-
PCI_EXP_LNKCTL2_TX_MARGIN));
2353
-
pcie_capability_write_word(adev->pdev,
2354
-
PCI_EXP_LNKCTL2,
2355
-
tmp16);
2334
+
pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL2,
2335
+
PCI_EXP_LNKCTL2_ENTER_COMP |
2336
+
PCI_EXP_LNKCTL2_TX_MARGIN,
2337
+
bridge_cfg2 &
2338
+
(PCI_EXP_LNKCTL2_ENTER_COMP |
2339
+
PCI_EXP_LNKCTL2_TX_MARGIN));
2340
+
pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL2,
2341
+
PCI_EXP_LNKCTL2_ENTER_COMP |
2342
+
PCI_EXP_LNKCTL2_TX_MARGIN,
2343
+
gpu_cfg2 &
2344
+
(PCI_EXP_LNKCTL2_ENTER_COMP |
2345
+
PCI_EXP_LNKCTL2_TX_MARGIN));
2356
2346
2357
2347
tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
2358
2348
tmp &= ~LC_SET_QUIESCE;
···
2355
2365
speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
2356
2366
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
2357
2367
2358
-
pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL2, &tmp16);
2359
-
tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
2360
-
2368
+
tmp16 = 0;
2361
2369
if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
2362
2370
tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
2363
2371
else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
2364
2372
tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
2365
2373
else
2366
2374
tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
2367
-
pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL2, tmp16);
2375
+
pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL2,
2376
+
PCI_EXP_LNKCTL2_TLS, tmp16);
2368
2377
2369
2378
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2370
2379
speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;