Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
arm64: dts: qcom: sm6350: Set up DDR & L3 scaling
Add the CPU OPP tables including core frequency and L3 bus frequency.
The L3 throughput values were chosen by studying the frequencies
available in HW LUT and picking the highest one that's less than the
CPU frequency. DDR clock rates come from the vendor kernel.
Available values from the HW LUT:
300000000
556800000
652800000
806400000
844800000
940800000
1132800000
1209600000
1286400000
1401600000
1459200000
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230104171643.1004054-3-konrad.dybcio@linaro.org
authored by
Konrad Dybcio
and committed by
Bjorn Andersson
bba95227
e17a8065
+159
+140
arch/arm64/boot/dts/qcom/sm6350.dtsi
+140
arch/arm64/boot/dts/qcom/sm6350.dtsi
···
8
8
#include <dt-bindings/clock/qcom,rpmh.h>
9
9
#include <dt-bindings/dma/qcom-gpi.h>
10
10
#include <dt-bindings/gpio/gpio.h>
11
+
#include <dt-bindings/interconnect/qcom,icc.h>
12
+
#include <dt-bindings/interconnect/qcom,osm-l3.h>
11
13
#include <dt-bindings/interconnect/qcom,sm6350.h>
12
14
#include <dt-bindings/interrupt-controller/arm-gic.h>
13
15
#include <dt-bindings/mailbox/qcom-ipcc.h>
···
49
47
dynamic-power-coefficient = <100>;
50
48
next-level-cache = <&L2_0>;
51
49
qcom,freq-domain = <&cpufreq_hw 0>;
50
+
operating-points-v2 = <&cpu0_opp_table>;
51
+
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
52
+
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
53
+
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
52
54
#cooling-cells = <2>;
53
55
L2_0: l2-cache {
54
56
compatible = "cache";
···
74
68
dynamic-power-coefficient = <100>;
75
69
next-level-cache = <&L2_100>;
76
70
qcom,freq-domain = <&cpufreq_hw 0>;
71
+
operating-points-v2 = <&cpu0_opp_table>;
72
+
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
73
+
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
74
+
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
77
75
#cooling-cells = <2>;
78
76
L2_100: l2-cache {
79
77
compatible = "cache";
···
95
85
dynamic-power-coefficient = <100>;
96
86
next-level-cache = <&L2_200>;
97
87
qcom,freq-domain = <&cpufreq_hw 0>;
88
+
operating-points-v2 = <&cpu0_opp_table>;
89
+
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
90
+
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
91
+
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
98
92
#cooling-cells = <2>;
99
93
L2_200: l2-cache {
100
94
compatible = "cache";
···
116
102
dynamic-power-coefficient = <100>;
117
103
next-level-cache = <&L2_300>;
118
104
qcom,freq-domain = <&cpufreq_hw 0>;
105
+
operating-points-v2 = <&cpu0_opp_table>;
106
+
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
107
+
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
108
+
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
119
109
#cooling-cells = <2>;
120
110
L2_300: l2-cache {
121
111
compatible = "cache";
···
137
119
dynamic-power-coefficient = <100>;
138
120
next-level-cache = <&L2_400>;
139
121
qcom,freq-domain = <&cpufreq_hw 0>;
122
+
operating-points-v2 = <&cpu0_opp_table>;
123
+
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
124
+
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
125
+
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
140
126
#cooling-cells = <2>;
141
127
L2_400: l2-cache {
142
128
compatible = "cache";
···
158
136
dynamic-power-coefficient = <100>;
159
137
next-level-cache = <&L2_500>;
160
138
qcom,freq-domain = <&cpufreq_hw 0>;
139
+
operating-points-v2 = <&cpu0_opp_table>;
140
+
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
141
+
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
142
+
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
161
143
#cooling-cells = <2>;
162
144
L2_500: l2-cache {
163
145
compatible = "cache";
···
180
154
dynamic-power-coefficient = <703>;
181
155
next-level-cache = <&L2_600>;
182
156
qcom,freq-domain = <&cpufreq_hw 1>;
157
+
operating-points-v2 = <&cpu6_opp_table>;
158
+
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
159
+
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
160
+
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
183
161
#cooling-cells = <2>;
184
162
L2_600: l2-cache {
185
163
compatible = "cache";
···
201
171
dynamic-power-coefficient = <703>;
202
172
next-level-cache = <&L2_700>;
203
173
qcom,freq-domain = <&cpufreq_hw 1>;
174
+
operating-points-v2 = <&cpu6_opp_table>;
175
+
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
176
+
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
177
+
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
204
178
#cooling-cells = <2>;
205
179
L2_700: l2-cache {
206
180
compatible = "cache";
···
261
227
device_type = "memory";
262
228
/* We expect the bootloader to fill in the size */
263
229
reg = <0x0 0x80000000 0x0 0x0>;
230
+
};
231
+
232
+
cpu0_opp_table: opp-table-cpu0 {
233
+
compatible = "operating-points-v2";
234
+
opp-shared;
235
+
236
+
opp-300000000 {
237
+
opp-hz = /bits/ 64 <300000000>;
238
+
/* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */
239
+
opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>;
240
+
};
241
+
242
+
opp-576000000 {
243
+
opp-hz = /bits/ 64 <576000000>;
244
+
opp-peak-kBps = <(547000 * 4 * 2 * 2) (556800 * 16 * 2)>;
245
+
};
246
+
247
+
opp-768000000 {
248
+
opp-hz = /bits/ 64 <768000000>;
249
+
opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>;
250
+
};
251
+
252
+
opp-1017600000 {
253
+
opp-hz = /bits/ 64 <1017600000>;
254
+
opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>;
255
+
};
256
+
257
+
opp-1248000000 {
258
+
opp-hz = /bits/ 64 <1248000000>;
259
+
opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>;
260
+
};
261
+
262
+
opp-1324800000 {
263
+
opp-hz = /bits/ 64 <1324800000>;
264
+
opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1286400 * 16 * 2)>;
265
+
};
266
+
267
+
opp-1516800000 {
268
+
opp-hz = /bits/ 64 <1516800000>;
269
+
opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
270
+
};
271
+
272
+
opp-1612800000 {
273
+
opp-hz = /bits/ 64 <1612800000>;
274
+
opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
275
+
};
276
+
277
+
opp-1708800000 {
278
+
opp-hz = /bits/ 64 <1708800000>;
279
+
opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
280
+
};
281
+
};
282
+
283
+
cpu6_opp_table: opp-table-cpu6 {
284
+
compatible = "operating-points-v2";
285
+
opp-shared;
286
+
287
+
opp-300000000 {
288
+
opp-hz = /bits/ 64 <300000000>;
289
+
opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>;
290
+
};
291
+
292
+
opp-787200000 {
293
+
opp-hz = /bits/ 64 <787200000>;
294
+
opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>;
295
+
};
296
+
297
+
opp-979200000 {
298
+
opp-hz = /bits/ 64 <979200000>;
299
+
opp-peak-kBps = <(768000 * 4 * 2 * 2) (940800 * 16 * 2)>;
300
+
};
301
+
302
+
opp-1036800000 {
303
+
opp-hz = /bits/ 64 <1036800000>;
304
+
opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>;
305
+
};
306
+
307
+
opp-1248000000 {
308
+
opp-hz = /bits/ 64 <1248000000>;
309
+
opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>;
310
+
};
311
+
312
+
opp-1401600000 {
313
+
opp-hz = /bits/ 64 <1401600000>;
314
+
opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1401600 * 16 * 2)>;
315
+
};
316
+
317
+
opp-1555200000 {
318
+
opp-hz = /bits/ 64 <1555200000>;
319
+
opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
320
+
};
321
+
322
+
opp-1766400000 {
323
+
opp-hz = /bits/ 64 <1766400000>;
324
+
opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
325
+
};
326
+
327
+
opp-1900800000 {
328
+
opp-hz = /bits/ 64 <1900800000>;
329
+
opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
330
+
};
331
+
332
+
opp-2073600000 {
333
+
opp-hz = /bits/ 64 <2073600000>;
334
+
opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
335
+
};
264
336
};
265
337
266
338
pmu {
+19
arch/arm64/boot/dts/qcom/sm7225.dtsi
+19
arch/arm64/boot/dts/qcom/sm7225.dtsi
···
14
14
&CPU5 { compatible = "qcom,kryo570"; };
15
15
&CPU6 { compatible = "qcom,kryo570"; };
16
16
&CPU7 { compatible = "qcom,kryo570"; };
17
+
18
+
&cpu0_opp_table {
19
+
opp-1804800000 {
20
+
opp-hz = /bits/ 64 <1804800000>;
21
+
opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
22
+
};
23
+
};
24
+
25
+
&cpu6_opp_table {
26
+
opp-2131200000 {
27
+
opp-hz = /bits/ 64 <2131200000>;
28
+
opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
29
+
};
30
+
31
+
opp-2208000000 {
32
+
opp-hz = /bits/ 64 <2208000000>;
33
+
opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
34
+
};
35
+
};