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phy: exynos5-usbdrd: support isolating HS and SS ports independently

Some versions of this IP have been integrated using separate PMU power
control registers for the HS and SS parts. One example is the Google
Tensor gs101 SoC.

Such SoCs can now set pmu_offset_usbdrd0_phy_ss in their
exynos5_usbdrd_phy_drvdata for the SS phy to the appropriate value.

The existing 'usbdrdphy' alias can not be used in this case because
that is meant for determining the correct PMU offset if multiple
distinct PHYs exist in the system (as opposed to one PHY with multiple
isolators).

Signed-off-by: André Draszik <andre.draszik@linaro.org>
Tested-by: Will McVicker <willmcvicker@google.com>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Tested-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20240617-usb-phy-gs101-v3-2-b66de9ae7424@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

André Draszik and committed by
Vinod Koul bbb28a1d e340c041

+13 -10
+13 -10
drivers/phy/samsung/phy-exynos5-usbdrd.c
··· 186 186 const struct exynos5_usbdrd_phy_config *phy_cfg; 187 187 const struct phy_ops *phy_ops; 188 188 u32 pmu_offset_usbdrd0_phy; 189 + u32 pmu_offset_usbdrd0_phy_ss; 189 190 u32 pmu_offset_usbdrd1_phy; 190 191 bool has_common_clk_gate; 191 192 }; ··· 1066 1065 if (channel < 0) 1067 1066 dev_dbg(dev, "Not a multi-controller usbdrd phy\n"); 1068 1067 1069 - switch (channel) { 1070 - case 1: 1071 - pmu_offset = phy_drd->drv_data->pmu_offset_usbdrd1_phy; 1072 - break; 1073 - case 0: 1074 - default: 1075 - pmu_offset = phy_drd->drv_data->pmu_offset_usbdrd0_phy; 1076 - break; 1077 - } 1078 - 1079 1068 /* Get Vbus regulators */ 1080 1069 phy_drd->vbus = devm_regulator_get(dev, "vbus"); 1081 1070 if (IS_ERR(phy_drd->vbus)) { ··· 1100 1109 phy_drd->phys[i].phy = phy; 1101 1110 phy_drd->phys[i].index = i; 1102 1111 phy_drd->phys[i].reg_pmu = reg_pmu; 1112 + switch (channel) { 1113 + case 1: 1114 + pmu_offset = drv_data->pmu_offset_usbdrd1_phy; 1115 + break; 1116 + case 0: 1117 + default: 1118 + pmu_offset = drv_data->pmu_offset_usbdrd0_phy; 1119 + if (i == EXYNOS5_DRDPHY_PIPE3 && drv_data 1120 + ->pmu_offset_usbdrd0_phy_ss) 1121 + pmu_offset = drv_data->pmu_offset_usbdrd0_phy_ss; 1122 + break; 1123 + } 1103 1124 phy_drd->phys[i].pmu_offset = pmu_offset; 1104 1125 phy_drd->phys[i].phy_cfg = &drv_data->phy_cfg[i]; 1105 1126 phy_set_drvdata(phy, &phy_drd->phys[i]);