tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull perf fixes from Ingo Molnar:
"Two hw-enablement patches, two race fixes, three fixes for regressions
of semantics, plus a number of tooling fixes"

* 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
perf/x86/intel: Add proper condition to run sched_task callbacks
perf/core: Fix locking for children siblings group read
perf/core: Fix scheduling regression of pinned groups
perf/x86/intel: Fix debug_store reset field for freq events
perf/x86/intel: Add Goldmont Plus CPU PMU support
perf/x86/intel: Enable C-state residency events for Apollo Lake
perf symbols: Accept zero as the kernel base address
Revert "perf/core: Drop kernel samples even though :u is specified"
perf annotate: Fix broken arrow at row 0 connecting jmp instruction to its target
perf evsel: State in the default event name if attr.exclude_kernel is set
perf evsel: Fix attr.exclude_kernel setting for default cycles:p

Linus Torvalds bbcdea65 8b810a3a

+221 -42
+160 -4
arch/x86/events/intel/core.c
··· 1708 1708 }, 1709 1709 }; 1710 1710 1711 + static __initconst const u64 glp_hw_cache_event_ids 1712 + [PERF_COUNT_HW_CACHE_MAX] 1713 + [PERF_COUNT_HW_CACHE_OP_MAX] 1714 + [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1715 + [C(L1D)] = { 1716 + [C(OP_READ)] = { 1717 + [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1718 + [C(RESULT_MISS)] = 0x0, 1719 + }, 1720 + [C(OP_WRITE)] = { 1721 + [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1722 + [C(RESULT_MISS)] = 0x0, 1723 + }, 1724 + [C(OP_PREFETCH)] = { 1725 + [C(RESULT_ACCESS)] = 0x0, 1726 + [C(RESULT_MISS)] = 0x0, 1727 + }, 1728 + }, 1729 + [C(L1I)] = { 1730 + [C(OP_READ)] = { 1731 + [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */ 1732 + [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */ 1733 + }, 1734 + [C(OP_WRITE)] = { 1735 + [C(RESULT_ACCESS)] = -1, 1736 + [C(RESULT_MISS)] = -1, 1737 + }, 1738 + [C(OP_PREFETCH)] = { 1739 + [C(RESULT_ACCESS)] = 0x0, 1740 + [C(RESULT_MISS)] = 0x0, 1741 + }, 1742 + }, 1743 + [C(LL)] = { 1744 + [C(OP_READ)] = { 1745 + [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1746 + [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1747 + }, 1748 + [C(OP_WRITE)] = { 1749 + [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1750 + [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */ 1751 + }, 1752 + [C(OP_PREFETCH)] = { 1753 + [C(RESULT_ACCESS)] = 0x0, 1754 + [C(RESULT_MISS)] = 0x0, 1755 + }, 1756 + }, 1757 + [C(DTLB)] = { 1758 + [C(OP_READ)] = { 1759 + [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ 1760 + [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ 1761 + }, 1762 + [C(OP_WRITE)] = { 1763 + [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ 1764 + [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ 1765 + }, 1766 + [C(OP_PREFETCH)] = { 1767 + [C(RESULT_ACCESS)] = 0x0, 1768 + [C(RESULT_MISS)] = 0x0, 1769 + }, 1770 + }, 1771 + [C(ITLB)] = { 1772 + [C(OP_READ)] = { 1773 + [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */ 1774 + [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */ 1775 + }, 1776 + [C(OP_WRITE)] = { 1777 + [C(RESULT_ACCESS)] = -1, 1778 + [C(RESULT_MISS)] = -1, 1779 + }, 1780 + [C(OP_PREFETCH)] = { 1781 + [C(RESULT_ACCESS)] = -1, 1782 + [C(RESULT_MISS)] = -1, 1783 + }, 1784 + }, 1785 + [C(BPU)] = { 1786 + [C(OP_READ)] = { 1787 + [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ 1788 + [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ 1789 + }, 1790 + [C(OP_WRITE)] = { 1791 + [C(RESULT_ACCESS)] = -1, 1792 + [C(RESULT_MISS)] = -1, 1793 + }, 1794 + [C(OP_PREFETCH)] = { 1795 + [C(RESULT_ACCESS)] = -1, 1796 + [C(RESULT_MISS)] = -1, 1797 + }, 1798 + }, 1799 + }; 1800 + 1801 + static __initconst const u64 glp_hw_cache_extra_regs 1802 + [PERF_COUNT_HW_CACHE_MAX] 1803 + [PERF_COUNT_HW_CACHE_OP_MAX] 1804 + [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1805 + [C(LL)] = { 1806 + [C(OP_READ)] = { 1807 + [C(RESULT_ACCESS)] = GLM_DEMAND_READ| 1808 + GLM_LLC_ACCESS, 1809 + [C(RESULT_MISS)] = GLM_DEMAND_READ| 1810 + GLM_LLC_MISS, 1811 + }, 1812 + [C(OP_WRITE)] = { 1813 + [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE| 1814 + GLM_LLC_ACCESS, 1815 + [C(RESULT_MISS)] = GLM_DEMAND_WRITE| 1816 + GLM_LLC_MISS, 1817 + }, 1818 + [C(OP_PREFETCH)] = { 1819 + [C(RESULT_ACCESS)] = 0x0, 1820 + [C(RESULT_MISS)] = 0x0, 1821 + }, 1822 + }, 1823 + }; 1824 + 1711 1825 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */ 1712 1826 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */ 1713 1827 #define KNL_MCDRAM_LOCAL BIT_ULL(21) ··· 3130 3016 return 0; 3131 3017 } 3132 3018 3019 + static struct event_constraint counter0_constraint = 3020 + INTEL_ALL_EVENT_CONSTRAINT(0, 0x1); 3021 + 3133 3022 static struct event_constraint counter2_constraint = 3134 3023 EVENT_CONSTRAINT(0, 0x4, 0); 3135 3024 ··· 3150 3033 return &counter2_constraint; 3151 3034 return &emptyconstraint; 3152 3035 } 3036 + 3037 + return c; 3038 + } 3039 + 3040 + static struct event_constraint * 3041 + glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 3042 + struct perf_event *event) 3043 + { 3044 + struct event_constraint *c; 3045 + 3046 + /* :ppp means to do reduced skid PEBS which is PMC0 only. */ 3047 + if (event->attr.precise_ip == 3) 3048 + return &counter0_constraint; 3049 + 3050 + c = intel_get_event_constraints(cpuc, idx, event); 3153 3051 3154 3052 return c; 3155 3053 } ··· 3397 3265 static void intel_pmu_sched_task(struct perf_event_context *ctx, 3398 3266 bool sched_in) 3399 3267 { 3400 - if (x86_pmu.pebs_active) 3401 - intel_pmu_pebs_sched_task(ctx, sched_in); 3402 - if (x86_pmu.lbr_nr) 3403 - intel_pmu_lbr_sched_task(ctx, sched_in); 3268 + intel_pmu_pebs_sched_task(ctx, sched_in); 3269 + intel_pmu_lbr_sched_task(ctx, sched_in); 3404 3270 } 3405 3271 3406 3272 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); ··· 3966 3836 x86_pmu.flags |= PMU_FL_HAS_RSP_1; 3967 3837 x86_pmu.cpu_events = glm_events_attrs; 3968 3838 pr_cont("Goldmont events, "); 3839 + break; 3840 + 3841 + case INTEL_FAM6_ATOM_GEMINI_LAKE: 3842 + memcpy(hw_cache_event_ids, glp_hw_cache_event_ids, 3843 + sizeof(hw_cache_event_ids)); 3844 + memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs, 3845 + sizeof(hw_cache_extra_regs)); 3846 + 3847 + intel_pmu_lbr_init_skl(); 3848 + 3849 + x86_pmu.event_constraints = intel_slm_event_constraints; 3850 + x86_pmu.pebs_constraints = intel_glp_pebs_event_constraints; 3851 + x86_pmu.extra_regs = intel_glm_extra_regs; 3852 + /* 3853 + * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS 3854 + * for precise cycles. 3855 + */ 3856 + x86_pmu.pebs_aliases = NULL; 3857 + x86_pmu.pebs_prec_dist = true; 3858 + x86_pmu.lbr_pt_coexist = true; 3859 + x86_pmu.flags |= PMU_FL_HAS_RSP_1; 3860 + x86_pmu.get_event_constraints = glp_get_event_constraints; 3861 + x86_pmu.cpu_events = glm_events_attrs; 3862 + /* Goldmont Plus has 4-wide pipeline */ 3863 + event_attr_td_total_slots_scale_glm.event_str = "4"; 3864 + pr_cont("Goldmont plus events, "); 3969 3865 break; 3970 3866 3971 3867 case INTEL_FAM6_WESTMERE:
+20 -6
arch/x86/events/intel/cstate.c
··· 40 40 * Model specific counters: 41 41 * MSR_CORE_C1_RES: CORE C1 Residency Counter 42 42 * perf code: 0x00 43 - * Available model: SLM,AMT 43 + * Available model: SLM,AMT,GLM 44 44 * Scope: Core (each processor core has a MSR) 45 45 * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter 46 46 * perf code: 0x01 47 - * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL 47 + * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM 48 48 * Scope: Core 49 49 * MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter 50 50 * perf code: 0x02 51 51 * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW 52 - * SKL,KNL 52 + * SKL,KNL,GLM 53 53 * Scope: Core 54 54 * MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter 55 55 * perf code: 0x03 ··· 57 57 * Scope: Core 58 58 * MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter. 59 59 * perf code: 0x00 60 - * Available model: SNB,IVB,HSW,BDW,SKL,KNL 60 + * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM 61 61 * Scope: Package (physical package) 62 62 * MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter. 63 63 * perf code: 0x01 64 64 * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL 65 + * GLM 65 66 * Scope: Package (physical package) 66 67 * MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter. 67 68 * perf code: 0x02 68 69 * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW 69 - * SKL,KNL 70 + * SKL,KNL,GLM 70 71 * Scope: Package (physical package) 71 72 * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter. 72 73 * perf code: 0x03 ··· 83 82 * Scope: Package (physical package) 84 83 * MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter. 85 84 * perf code: 0x06 86 - * Available model: HSW ULT only 85 + * Available model: HSW ULT, GLM 87 86 * Scope: Package (physical package) 88 87 * 89 88 */ ··· 505 504 }; 506 505 507 506 507 + static const struct cstate_model glm_cstates __initconst = { 508 + .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | 509 + BIT(PERF_CSTATE_CORE_C3_RES) | 510 + BIT(PERF_CSTATE_CORE_C6_RES), 511 + 512 + .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | 513 + BIT(PERF_CSTATE_PKG_C3_RES) | 514 + BIT(PERF_CSTATE_PKG_C6_RES) | 515 + BIT(PERF_CSTATE_PKG_C10_RES), 516 + }; 517 + 508 518 509 519 #define X86_CSTATES_MODEL(model, states) \ 510 520 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long) &(states) } ··· 558 546 559 547 X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNL, knl_cstates), 560 548 X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNM, knl_cstates), 549 + 550 + X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT, glm_cstates), 561 551 { }, 562 552 }; 563 553 MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
+16 -6
arch/x86/events/intel/ds.c
··· 606 606 x86_pmu.drain_pebs(&regs); 607 607 } 608 608 609 - void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in) 610 - { 611 - if (!sched_in) 612 - intel_pmu_drain_pebs_buffer(); 613 - } 614 - 615 609 /* 616 610 * PEBS 617 611 */ ··· 642 648 struct event_constraint intel_glm_pebs_event_constraints[] = { 643 649 /* Allow all events as PEBS with no flags */ 644 650 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1), 651 + EVENT_CONSTRAINT_END 652 + }; 653 + 654 + struct event_constraint intel_glp_pebs_event_constraints[] = { 655 + /* Allow all events as PEBS with no flags */ 656 + INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), 645 657 EVENT_CONSTRAINT_END 646 658 }; 647 659 ··· 816 816 return cpuc->n_pebs && (cpuc->n_pebs == cpuc->n_large_pebs); 817 817 } 818 818 819 + void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in) 820 + { 821 + struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 822 + 823 + if (!sched_in && pebs_needs_sched_cb(cpuc)) 824 + intel_pmu_drain_pebs_buffer(); 825 + } 826 + 819 827 static inline void pebs_update_threshold(struct cpu_hw_events *cpuc) 820 828 { 821 829 struct debug_store *ds = cpuc->ds; ··· 897 889 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) { 898 890 ds->pebs_event_reset[hwc->idx] = 899 891 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask; 892 + } else { 893 + ds->pebs_event_reset[hwc->idx] = 0; 900 894 } 901 895 } 902 896
+4
arch/x86/events/intel/lbr.c
··· 380 380 381 381 void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in) 382 382 { 383 + struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 383 384 struct x86_perf_task_context *task_ctx; 385 + 386 + if (!cpuc->lbr_users) 387 + return; 384 388 385 389 /* 386 390 * If LBR callstack feature is enabled and the stack was saved when
+2
arch/x86/events/perf_event.h
··· 879 879 880 880 extern struct event_constraint intel_glm_pebs_event_constraints[]; 881 881 882 + extern struct event_constraint intel_glp_pebs_event_constraints[]; 883 + 882 884 extern struct event_constraint intel_nehalem_pebs_event_constraints[]; 883 885 884 886 extern struct event_constraint intel_westmere_pebs_event_constraints[];
+12 -21
kernel/events/core.c
··· 1452 1452 1453 1453 lockdep_assert_held(&ctx->lock); 1454 1454 1455 + /* 1456 + * It's 'group type', really, because if our group leader is 1457 + * pinned, so are we. 1458 + */ 1459 + if (event->group_leader != event) 1460 + event = event->group_leader; 1461 + 1455 1462 event_type = event->attr.pinned ? EVENT_PINNED : EVENT_FLEXIBLE; 1456 1463 if (!ctx->task) 1457 1464 event_type |= EVENT_CPU; ··· 4385 4378 static int __perf_read_group_add(struct perf_event *leader, 4386 4379 u64 read_format, u64 *values) 4387 4380 { 4381 + struct perf_event_context *ctx = leader->ctx; 4388 4382 struct perf_event *sub; 4383 + unsigned long flags; 4389 4384 int n = 1; /* skip @nr */ 4390 4385 int ret; 4391 4386 ··· 4417 4408 if (read_format & PERF_FORMAT_ID) 4418 4409 values[n++] = primary_event_id(leader); 4419 4410 4411 + raw_spin_lock_irqsave(&ctx->lock, flags); 4412 + 4420 4413 list_for_each_entry(sub, &leader->sibling_list, group_entry) { 4421 4414 values[n++] += perf_event_count(sub); 4422 4415 if (read_format & PERF_FORMAT_ID) 4423 4416 values[n++] = primary_event_id(sub); 4424 4417 } 4425 4418 4419 + raw_spin_unlock_irqrestore(&ctx->lock, flags); 4426 4420 return 0; 4427 4421 } 4428 4422 ··· 7333 7321 return __perf_event_account_interrupt(event, 1); 7334 7322 } 7335 7323 7336 - static bool sample_is_allowed(struct perf_event *event, struct pt_regs *regs) 7337 - { 7338 - /* 7339 - * Due to interrupt latency (AKA "skid"), we may enter the 7340 - * kernel before taking an overflow, even if the PMU is only 7341 - * counting user events. 7342 - * To avoid leaking information to userspace, we must always 7343 - * reject kernel samples when exclude_kernel is set. 7344 - */ 7345 - if (event->attr.exclude_kernel && !user_mode(regs)) 7346 - return false; 7347 - 7348 - return true; 7349 - } 7350 - 7351 7324 /* 7352 7325 * Generic event overflow handling, sampling. 7353 7326 */ ··· 7352 7355 return 0; 7353 7356 7354 7357 ret = __perf_event_account_interrupt(event, throttle); 7355 - 7356 - /* 7357 - * For security, drop the skid kernel samples if necessary. 7358 - */ 7359 - if (!sample_is_allowed(event, regs)) 7360 - return ret; 7361 7358 7362 7359 /* 7363 7360 * XXX event_limit might not quite work as expected on inherited
+1 -1
tools/perf/ui/browser.c
··· 704 704 ui_browser__gotorc(browser, row, column + 1); 705 705 SLsmg_draw_hline(2); 706 706 707 - if (row++ == 0) 707 + if (++row == 0) 708 708 goto out; 709 709 } else 710 710 row = 0;
+5 -3
tools/perf/util/evsel.c
··· 273 273 struct perf_event_attr attr = { 274 274 .type = PERF_TYPE_HARDWARE, 275 275 .config = PERF_COUNT_HW_CPU_CYCLES, 276 - .exclude_kernel = 1, 276 + .exclude_kernel = geteuid() != 0, 277 277 }; 278 278 struct perf_evsel *evsel; 279 279 ··· 298 298 goto out; 299 299 300 300 /* use asprintf() because free(evsel) assumes name is allocated */ 301 - if (asprintf(&evsel->name, "cycles%.*s", 302 - attr.precise_ip ? attr.precise_ip + 1 : 0, ":ppp") < 0) 301 + if (asprintf(&evsel->name, "cycles%s%s%.*s", 302 + (attr.precise_ip || attr.exclude_kernel) ? ":" : "", 303 + attr.exclude_kernel ? "u" : "", 304 + attr.precise_ip ? attr.precise_ip + 1 : 0, "ppp") < 0) 303 305 goto error_free; 304 306 out: 305 307 return evsel;
+1 -1
tools/perf/util/machine.c
··· 2209 2209 machine->kernel_start = 1ULL << 63; 2210 2210 if (map) { 2211 2211 err = map__load(map); 2212 - if (map->start) 2212 + if (!err) 2213 2213 machine->kernel_start = map->start; 2214 2214 } 2215 2215 return err;