Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/cx0: Rename intel_clear_response_ready flag
Rename the non static intel_clear_response_ready_flag to
intel_cx0_clear_response_ready_flag so that we follow the
naming standards of non static function.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Nemesa Garg <nemesa.garg@intel.com>
Link: https://patch.msgid.link/20260122044859.753682-2-suraj.kandpal@intel.com
+10
-10
+7
-7
drivers/gpu/drm/i915/display/intel_cx0_phy.c
+7
-7
drivers/gpu/drm/i915/display/intel_cx0_phy.c
···
128
128
intel_display_power_put(display, POWER_DOMAIN_DC_OFF, wakeref);
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}
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-
void intel_clear_response_ready_flag(struct intel_encoder *encoder,
132
-
int lane)
131
+
void intel_cx0_clear_response_ready_flag(struct intel_encoder *encoder,
132
+
int lane)
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{
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struct intel_display *display = to_intel_display(encoder);
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135
···
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return;
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}
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-
intel_clear_response_ready_flag(encoder, lane);
159
+
intel_cx0_clear_response_ready_flag(encoder, lane);
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}
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int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
···
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return -ETIMEDOUT;
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}
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-
intel_clear_response_ready_flag(encoder, lane);
226
+
intel_cx0_clear_response_ready_flag(encoder, lane);
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intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
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XELPDP_PORT_M2P_TRANSACTION_PENDING |
···
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if (ack < 0)
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return ack;
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-
intel_clear_response_ready_flag(encoder, lane);
237
+
intel_cx0_clear_response_ready_flag(encoder, lane);
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/*
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* FIXME: Workaround to let HW to settle
···
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return -ETIMEDOUT;
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}
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-
intel_clear_response_ready_flag(encoder, lane);
299
+
intel_cx0_clear_response_ready_flag(encoder, lane);
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intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
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XELPDP_PORT_M2P_TRANSACTION_PENDING |
···
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return -EINVAL;
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}
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329
-
intel_clear_response_ready_flag(encoder, lane);
329
+
intel_cx0_clear_response_ready_flag(encoder, lane);
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/*
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* FIXME: Workaround to let HW to settle
+2
-2
drivers/gpu/drm/i915/display/intel_cx0_phy.h
+2
-2
drivers/gpu/drm/i915/display/intel_cx0_phy.h
···
25
25
struct intel_encoder;
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struct intel_hdmi;
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27
28
-
void intel_clear_response_ready_flag(struct intel_encoder *encoder,
29
-
int lane);
28
+
void intel_cx0_clear_response_ready_flag(struct intel_encoder *encoder,
29
+
int lane);
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bool intel_encoder_is_c10phy(struct intel_encoder *encoder);
31
31
void intel_mtl_pll_enable(struct intel_encoder *encoder,
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32
struct intel_dpll *pll,
+1
-1
drivers/gpu/drm/i915/display/intel_lt_phy.c
+1
-1
drivers/gpu/drm/i915/display/intel_lt_phy.c
···
1053
1053
* This is the time PHY takes to settle down after programming the PHY.
1054
1054
*/
1055
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udelay(150);
1056
-
intel_clear_response_ready_flag(encoder, lane);
1056
+
intel_cx0_clear_response_ready_flag(encoder, lane);
1057
1057
intel_lt_phy_clear_status_p2p(encoder, lane);
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return 0;