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KVM: arm64: Inherit RESx bits from FGT register descriptors

The FGT registers have their computed RESx bits stashed in specific
descriptors, which we can easily use when computing the masks used
for the guest.

This removes a bit of boilerplate code.

Reviewed-by: Joey Gouly <joey.gouly@arm.com>
Reviewed-by: Fuad Tabba <tabba@google.com>
Tested-by: Fuad Tabba <tabba@google.com>
Link: https://patch.msgid.link/20260202184329.2724080-7-maz@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>

Marc Zyngier bbea2763 f9d58956

+5 -11
+5 -11
arch/arm64/kvm/config.c
··· 1342 1342 resx = compute_resx_bits(kvm, r->bit_feat_map, r->bit_feat_map_sz, 1343 1343 require, exclude); 1344 1344 1345 + if (r->feat_map.flags & MASKS_POINTER) { 1346 + resx.res0 |= r->feat_map.masks->res0; 1347 + resx.res1 |= r->feat_map.masks->res1; 1348 + } 1349 + 1345 1350 tmp = compute_resx_bits(kvm, &r->feat_map, 1, require, exclude); 1346 1351 1347 1352 resx.res0 |= tmp.res0; ··· 1427 1422 switch (reg) { 1428 1423 case HFGRTR_EL2: 1429 1424 resx = compute_reg_resx_bits(kvm, &hfgrtr_desc, 0, 0); 1430 - resx.res1 |= HFGRTR_EL2_RES1; 1431 1425 break; 1432 1426 case HFGWTR_EL2: 1433 1427 resx = compute_reg_resx_bits(kvm, &hfgwtr_desc, 0, 0); 1434 - resx.res1 |= HFGWTR_EL2_RES1; 1435 1428 break; 1436 1429 case HFGITR_EL2: 1437 1430 resx = compute_reg_resx_bits(kvm, &hfgitr_desc, 0, 0); 1438 - resx.res1 |= HFGITR_EL2_RES1; 1439 1431 break; 1440 1432 case HDFGRTR_EL2: 1441 1433 resx = compute_reg_resx_bits(kvm, &hdfgrtr_desc, 0, 0); 1442 - resx.res1 |= HDFGRTR_EL2_RES1; 1443 1434 break; 1444 1435 case HDFGWTR_EL2: 1445 1436 resx = compute_reg_resx_bits(kvm, &hdfgwtr_desc, 0, 0); 1446 - resx.res1 |= HDFGWTR_EL2_RES1; 1447 1437 break; 1448 1438 case HAFGRTR_EL2: 1449 1439 resx = compute_reg_resx_bits(kvm, &hafgrtr_desc, 0, 0); 1450 - resx.res1 |= HAFGRTR_EL2_RES1; 1451 1440 break; 1452 1441 case HFGRTR2_EL2: 1453 1442 resx = compute_reg_resx_bits(kvm, &hfgrtr2_desc, 0, 0); 1454 - resx.res1 |= HFGRTR2_EL2_RES1; 1455 1443 break; 1456 1444 case HFGWTR2_EL2: 1457 1445 resx = compute_reg_resx_bits(kvm, &hfgwtr2_desc, 0, 0); 1458 - resx.res1 |= HFGWTR2_EL2_RES1; 1459 1446 break; 1460 1447 case HFGITR2_EL2: 1461 1448 resx = compute_reg_resx_bits(kvm, &hfgitr2_desc, 0, 0); 1462 - resx.res1 |= HFGITR2_EL2_RES1; 1463 1449 break; 1464 1450 case HDFGRTR2_EL2: 1465 1451 resx = compute_reg_resx_bits(kvm, &hdfgrtr2_desc, 0, 0); 1466 - resx.res1 |= HDFGRTR2_EL2_RES1; 1467 1452 break; 1468 1453 case HDFGWTR2_EL2: 1469 1454 resx = compute_reg_resx_bits(kvm, &hdfgwtr2_desc, 0, 0); 1470 - resx.res1 |= HDFGWTR2_EL2_RES1; 1471 1455 break; 1472 1456 case HCRX_EL2: 1473 1457 resx = compute_reg_resx_bits(kvm, &hcrx_desc, 0, 0);