Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch '20241011-sa8775p-mm-v4-resend-patches-v5-0-4a9f17dc683a@quicinc.com' into clk-for-6.13
Merge SA8775P multimedia clock bindings through topic branch to allow
the constants to be made available to DeviceTree source as well.
+445
+62
Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml
+62
Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/qcom,sa8775p-camcc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Camera Clock & Reset Controller on SA8775P
8
+
9
+
maintainers:
10
+
- Taniya Das <quic_tdas@quicinc.com>
11
+
12
+
description: |
13
+
Qualcomm camera clock control module provides the clocks, resets and power
14
+
domains on SA8775p.
15
+
16
+
See also: include/dt-bindings/clock/qcom,sa8775p-camcc.h
17
+
18
+
properties:
19
+
compatible:
20
+
enum:
21
+
- qcom,sa8775p-camcc
22
+
23
+
clocks:
24
+
items:
25
+
- description: Camera AHB clock from GCC
26
+
- description: Board XO source
27
+
- description: Board active XO source
28
+
- description: Sleep clock source
29
+
30
+
power-domains:
31
+
maxItems: 1
32
+
description: MMCX power domain
33
+
34
+
required:
35
+
- compatible
36
+
- clocks
37
+
- power-domains
38
+
- '#power-domain-cells'
39
+
40
+
allOf:
41
+
- $ref: qcom,gcc.yaml#
42
+
43
+
unevaluatedProperties: false
44
+
45
+
examples:
46
+
- |
47
+
#include <dt-bindings/clock/qcom,rpmh.h>
48
+
#include <dt-bindings/power/qcom-rpmpd.h>
49
+
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
50
+
clock-controller@ade0000 {
51
+
compatible = "qcom,sa8775p-camcc";
52
+
reg = <0x0ade0000 0x20000>;
53
+
clocks = <&gcc GCC_CAMERA_AHB_CLK>,
54
+
<&rpmhcc RPMH_CXO_CLK>,
55
+
<&rpmhcc RPMH_CXO_CLK_A>,
56
+
<&sleep_clk>;
57
+
power-domains = <&rpmhpd SA8775P_MMCX>;
58
+
#clock-cells = <1>;
59
+
#reset-cells = <1>;
60
+
#power-domain-cells = <1>;
61
+
};
62
+
...
+79
Documentation/devicetree/bindings/clock/qcom,sa8775p-dispcc.yaml
+79
Documentation/devicetree/bindings/clock/qcom,sa8775p-dispcc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/qcom,sa8775p-dispcc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Display Clock & Reset Controller on SA8775P
8
+
9
+
maintainers:
10
+
- Taniya Das <quic_tdas@quicinc.com>
11
+
12
+
description: |
13
+
Qualcomm display clock control module provides the clocks, resets and power
14
+
domains on SA8775P.
15
+
16
+
See also: include/dt-bindings/clock/qcom,sa8775p-dispcc.h
17
+
18
+
properties:
19
+
compatible:
20
+
enum:
21
+
- qcom,sa8775p-dispcc0
22
+
- qcom,sa8775p-dispcc1
23
+
24
+
clocks:
25
+
items:
26
+
- description: GCC AHB clock source
27
+
- description: Board XO source
28
+
- description: Board XO_AO source
29
+
- description: Sleep clock source
30
+
- description: Link clock from DP0 PHY
31
+
- description: VCO DIV clock from DP0 PHY
32
+
- description: Link clock from DP1 PHY
33
+
- description: VCO DIV clock from DP1 PHY
34
+
- description: Byte clock from DSI0 PHY
35
+
- description: Pixel clock from DSI0 PHY
36
+
- description: Byte clock from DSI1 PHY
37
+
- description: Pixel clock from DSI1 PHY
38
+
39
+
power-domains:
40
+
maxItems: 1
41
+
description: MMCX power domain
42
+
43
+
required:
44
+
- compatible
45
+
- clocks
46
+
- power-domains
47
+
- '#power-domain-cells'
48
+
49
+
allOf:
50
+
- $ref: qcom,gcc.yaml#
51
+
52
+
unevaluatedProperties: false
53
+
54
+
examples:
55
+
- |
56
+
#include <dt-bindings/clock/qcom,rpmh.h>
57
+
#include <dt-bindings/power/qcom-rpmpd.h>
58
+
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
59
+
clock-controller@af00000 {
60
+
compatible = "qcom,sa8775p-dispcc0";
61
+
reg = <0x0af00000 0x20000>;
62
+
clocks = <&gcc GCC_DISP_AHB_CLK>,
63
+
<&rpmhcc RPMH_CXO_CLK>,
64
+
<&rpmhcc RPMH_CXO_CLK_A>,
65
+
<&sleep_clk>,
66
+
<&dp_phy0 0>,
67
+
<&dp_phy0 1>,
68
+
<&dp_phy1 2>,
69
+
<&dp_phy1 3>,
70
+
<&dsi_phy0 0>,
71
+
<&dsi_phy0 1>,
72
+
<&dsi_phy1 2>,
73
+
<&dsi_phy1 3>;
74
+
power-domains = <&rpmhpd SA8775P_MMCX>;
75
+
#clock-cells = <1>;
76
+
#reset-cells = <1>;
77
+
#power-domain-cells = <1>;
78
+
};
79
+
...
+62
Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml
+62
Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/qcom,sa8775p-videocc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Video Clock & Reset Controller on SA8775P
8
+
9
+
maintainers:
10
+
- Taniya Das <quic_tdas@quicinc.com>
11
+
12
+
description: |
13
+
Qualcomm video clock control module provides the clocks, resets and power
14
+
domains on SA8775P.
15
+
16
+
See also: include/dt-bindings/clock/qcom,sa8775p-videocc.h
17
+
18
+
properties:
19
+
compatible:
20
+
enum:
21
+
- qcom,sa8775p-videocc
22
+
23
+
clocks:
24
+
items:
25
+
- description: Video AHB clock from GCC
26
+
- description: Board XO source
27
+
- description: Board active XO source
28
+
- description: Sleep Clock source
29
+
30
+
power-domains:
31
+
maxItems: 1
32
+
description: MMCX power domain
33
+
34
+
required:
35
+
- compatible
36
+
- clocks
37
+
- power-domains
38
+
- '#power-domain-cells'
39
+
40
+
allOf:
41
+
- $ref: qcom,gcc.yaml#
42
+
43
+
unevaluatedProperties: false
44
+
45
+
examples:
46
+
- |
47
+
#include <dt-bindings/clock/qcom,rpmh.h>
48
+
#include <dt-bindings/power/qcom-rpmpd.h>
49
+
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
50
+
videocc: clock-controller@abf0000 {
51
+
compatible = "qcom,sa8775p-videocc";
52
+
reg = <0x0abf0000 0x10000>;
53
+
clocks = <&gcc GCC_VIDEO_AHB_CLK>,
54
+
<&rpmhcc RPMH_CXO_CLK>,
55
+
<&rpmhcc RPMH_CXO_CLK_A>,
56
+
<&sleep_clk>;
57
+
power-domains = <&rpmhpd SA8775P_MMCX>;
58
+
#clock-cells = <1>;
59
+
#reset-cells = <1>;
60
+
#power-domain-cells = <1>;
61
+
};
62
+
...
+108
include/dt-bindings/clock/qcom,sa8775p-camcc.h
+108
include/dt-bindings/clock/qcom,sa8775p-camcc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#ifndef _DT_BINDINGS_CLK_QCOM_SA8775P_CAM_CC_H
7
+
#define _DT_BINDINGS_CLK_QCOM_SA8775P_CAM_CC_H
8
+
9
+
/* CAM_CC clocks */
10
+
#define CAM_CC_CAMNOC_AXI_CLK 0
11
+
#define CAM_CC_CAMNOC_AXI_CLK_SRC 1
12
+
#define CAM_CC_CAMNOC_DCD_XO_CLK 2
13
+
#define CAM_CC_CAMNOC_XO_CLK 3
14
+
#define CAM_CC_CCI_0_CLK 4
15
+
#define CAM_CC_CCI_0_CLK_SRC 5
16
+
#define CAM_CC_CCI_1_CLK 6
17
+
#define CAM_CC_CCI_1_CLK_SRC 7
18
+
#define CAM_CC_CCI_2_CLK 8
19
+
#define CAM_CC_CCI_2_CLK_SRC 9
20
+
#define CAM_CC_CCI_3_CLK 10
21
+
#define CAM_CC_CCI_3_CLK_SRC 11
22
+
#define CAM_CC_CORE_AHB_CLK 12
23
+
#define CAM_CC_CPAS_AHB_CLK 13
24
+
#define CAM_CC_CPAS_FAST_AHB_CLK 14
25
+
#define CAM_CC_CPAS_IFE_0_CLK 15
26
+
#define CAM_CC_CPAS_IFE_1_CLK 16
27
+
#define CAM_CC_CPAS_IFE_LITE_CLK 17
28
+
#define CAM_CC_CPAS_IPE_CLK 18
29
+
#define CAM_CC_CPAS_SFE_LITE_0_CLK 19
30
+
#define CAM_CC_CPAS_SFE_LITE_1_CLK 20
31
+
#define CAM_CC_CPHY_RX_CLK_SRC 21
32
+
#define CAM_CC_CSI0PHYTIMER_CLK 22
33
+
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 23
34
+
#define CAM_CC_CSI1PHYTIMER_CLK 24
35
+
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 25
36
+
#define CAM_CC_CSI2PHYTIMER_CLK 26
37
+
#define CAM_CC_CSI2PHYTIMER_CLK_SRC 27
38
+
#define CAM_CC_CSI3PHYTIMER_CLK 28
39
+
#define CAM_CC_CSI3PHYTIMER_CLK_SRC 29
40
+
#define CAM_CC_CSID_CLK 30
41
+
#define CAM_CC_CSID_CLK_SRC 31
42
+
#define CAM_CC_CSID_CSIPHY_RX_CLK 32
43
+
#define CAM_CC_CSIPHY0_CLK 33
44
+
#define CAM_CC_CSIPHY1_CLK 34
45
+
#define CAM_CC_CSIPHY2_CLK 35
46
+
#define CAM_CC_CSIPHY3_CLK 36
47
+
#define CAM_CC_FAST_AHB_CLK_SRC 37
48
+
#define CAM_CC_GDSC_CLK 38
49
+
#define CAM_CC_ICP_AHB_CLK 39
50
+
#define CAM_CC_ICP_CLK 40
51
+
#define CAM_CC_ICP_CLK_SRC 41
52
+
#define CAM_CC_IFE_0_CLK 42
53
+
#define CAM_CC_IFE_0_CLK_SRC 43
54
+
#define CAM_CC_IFE_0_FAST_AHB_CLK 44
55
+
#define CAM_CC_IFE_1_CLK 45
56
+
#define CAM_CC_IFE_1_CLK_SRC 46
57
+
#define CAM_CC_IFE_1_FAST_AHB_CLK 47
58
+
#define CAM_CC_IFE_LITE_AHB_CLK 48
59
+
#define CAM_CC_IFE_LITE_CLK 49
60
+
#define CAM_CC_IFE_LITE_CLK_SRC 50
61
+
#define CAM_CC_IFE_LITE_CPHY_RX_CLK 51
62
+
#define CAM_CC_IFE_LITE_CSID_CLK 52
63
+
#define CAM_CC_IFE_LITE_CSID_CLK_SRC 53
64
+
#define CAM_CC_IPE_AHB_CLK 54
65
+
#define CAM_CC_IPE_CLK 55
66
+
#define CAM_CC_IPE_CLK_SRC 56
67
+
#define CAM_CC_IPE_FAST_AHB_CLK 57
68
+
#define CAM_CC_MCLK0_CLK 58
69
+
#define CAM_CC_MCLK0_CLK_SRC 59
70
+
#define CAM_CC_MCLK1_CLK 60
71
+
#define CAM_CC_MCLK1_CLK_SRC 61
72
+
#define CAM_CC_MCLK2_CLK 62
73
+
#define CAM_CC_MCLK2_CLK_SRC 63
74
+
#define CAM_CC_MCLK3_CLK 64
75
+
#define CAM_CC_MCLK3_CLK_SRC 65
76
+
#define CAM_CC_PLL0 66
77
+
#define CAM_CC_PLL0_OUT_EVEN 67
78
+
#define CAM_CC_PLL0_OUT_ODD 68
79
+
#define CAM_CC_PLL2 69
80
+
#define CAM_CC_PLL3 70
81
+
#define CAM_CC_PLL3_OUT_EVEN 71
82
+
#define CAM_CC_PLL4 72
83
+
#define CAM_CC_PLL4_OUT_EVEN 73
84
+
#define CAM_CC_PLL5 74
85
+
#define CAM_CC_PLL5_OUT_EVEN 75
86
+
#define CAM_CC_SFE_LITE_0_CLK 76
87
+
#define CAM_CC_SFE_LITE_0_FAST_AHB_CLK 77
88
+
#define CAM_CC_SFE_LITE_1_CLK 78
89
+
#define CAM_CC_SFE_LITE_1_FAST_AHB_CLK 79
90
+
#define CAM_CC_SLEEP_CLK 80
91
+
#define CAM_CC_SLEEP_CLK_SRC 81
92
+
#define CAM_CC_SLOW_AHB_CLK_SRC 82
93
+
#define CAM_CC_SM_OBS_CLK 83
94
+
#define CAM_CC_XO_CLK_SRC 84
95
+
#define CAM_CC_QDSS_DEBUG_XO_CLK 85
96
+
97
+
/* CAM_CC power domains */
98
+
#define CAM_CC_TITAN_TOP_GDSC 0
99
+
100
+
/* CAM_CC resets */
101
+
#define CAM_CC_ICP_BCR 0
102
+
#define CAM_CC_IFE_0_BCR 1
103
+
#define CAM_CC_IFE_1_BCR 2
104
+
#define CAM_CC_IPE_0_BCR 3
105
+
#define CAM_CC_SFE_LITE_0_BCR 4
106
+
#define CAM_CC_SFE_LITE_1_BCR 5
107
+
108
+
#endif
+87
include/dt-bindings/clock/qcom,sa8775p-dispcc.h
+87
include/dt-bindings/clock/qcom,sa8775p-dispcc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#ifndef _DT_BINDINGS_CLK_QCOM_SA8775P_DISP_CC_H
7
+
#define _DT_BINDINGS_CLK_QCOM_SA8775P_DISP_CC_H
8
+
9
+
/* DISP_CC_0/1 clocks */
10
+
#define MDSS_DISP_CC_MDSS_AHB1_CLK 0
11
+
#define MDSS_DISP_CC_MDSS_AHB_CLK 1
12
+
#define MDSS_DISP_CC_MDSS_AHB_CLK_SRC 2
13
+
#define MDSS_DISP_CC_MDSS_BYTE0_CLK 3
14
+
#define MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC 4
15
+
#define MDSS_DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5
16
+
#define MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK 6
17
+
#define MDSS_DISP_CC_MDSS_BYTE1_CLK 7
18
+
#define MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC 8
19
+
#define MDSS_DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 9
20
+
#define MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK 10
21
+
#define MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK 11
22
+
#define MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 12
23
+
#define MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK 13
24
+
#define MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK_SRC 14
25
+
#define MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK 15
26
+
#define MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 16
27
+
#define MDSS_DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 17
28
+
#define MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 18
29
+
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK 19
30
+
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 20
31
+
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK 21
32
+
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 22
33
+
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK 23
34
+
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC 24
35
+
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK 25
36
+
#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC 26
37
+
#define MDSS_DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 27
38
+
#define MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK 28
39
+
#define MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 29
40
+
#define MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK 30
41
+
#define MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK_SRC 31
42
+
#define MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK 32
43
+
#define MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 33
44
+
#define MDSS_DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 34
45
+
#define MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 35
46
+
#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK 36
47
+
#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 37
48
+
#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK 38
49
+
#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 39
50
+
#define MDSS_DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 40
51
+
#define MDSS_DISP_CC_MDSS_ESC0_CLK 41
52
+
#define MDSS_DISP_CC_MDSS_ESC0_CLK_SRC 42
53
+
#define MDSS_DISP_CC_MDSS_ESC1_CLK 43
54
+
#define MDSS_DISP_CC_MDSS_ESC1_CLK_SRC 44
55
+
#define MDSS_DISP_CC_MDSS_MDP1_CLK 45
56
+
#define MDSS_DISP_CC_MDSS_MDP_CLK 46
57
+
#define MDSS_DISP_CC_MDSS_MDP_CLK_SRC 47
58
+
#define MDSS_DISP_CC_MDSS_MDP_LUT1_CLK 48
59
+
#define MDSS_DISP_CC_MDSS_MDP_LUT_CLK 49
60
+
#define MDSS_DISP_CC_MDSS_NON_GDSC_AHB_CLK 50
61
+
#define MDSS_DISP_CC_MDSS_PCLK0_CLK 51
62
+
#define MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC 52
63
+
#define MDSS_DISP_CC_MDSS_PCLK1_CLK 53
64
+
#define MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC 54
65
+
#define MDSS_DISP_CC_MDSS_PLL_LOCK_MONITOR_CLK 55
66
+
#define MDSS_DISP_CC_MDSS_RSCC_AHB_CLK 56
67
+
#define MDSS_DISP_CC_MDSS_RSCC_VSYNC_CLK 57
68
+
#define MDSS_DISP_CC_MDSS_VSYNC1_CLK 58
69
+
#define MDSS_DISP_CC_MDSS_VSYNC_CLK 59
70
+
#define MDSS_DISP_CC_MDSS_VSYNC_CLK_SRC 60
71
+
#define MDSS_DISP_CC_PLL0 61
72
+
#define MDSS_DISP_CC_PLL1 62
73
+
#define MDSS_DISP_CC_SLEEP_CLK 63
74
+
#define MDSS_DISP_CC_SLEEP_CLK_SRC 64
75
+
#define MDSS_DISP_CC_SM_OBS_CLK 65
76
+
#define MDSS_DISP_CC_XO_CLK 66
77
+
#define MDSS_DISP_CC_XO_CLK_SRC 67
78
+
79
+
/* DISP_CC_0/1 power domains */
80
+
#define MDSS_DISP_CC_MDSS_CORE_GDSC 0
81
+
#define MDSS_DISP_CC_MDSS_CORE_INT2_GDSC 1
82
+
83
+
/* DISP_CC_0/1 resets */
84
+
#define MDSS_DISP_CC_MDSS_CORE_BCR 0
85
+
#define MDSS_DISP_CC_MDSS_RSCC_BCR 1
86
+
87
+
#endif
+47
include/dt-bindings/clock/qcom,sa8775p-videocc.h
+47
include/dt-bindings/clock/qcom,sa8775p-videocc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#ifndef _DT_BINDINGS_CLK_QCOM_SA8775P_VIDEO_CC_H
7
+
#define _DT_BINDINGS_CLK_QCOM_SA8775P_VIDEO_CC_H
8
+
9
+
/* VIDEO_CC clocks */
10
+
#define VIDEO_CC_AHB_CLK 0
11
+
#define VIDEO_CC_AHB_CLK_SRC 1
12
+
#define VIDEO_CC_MVS0_CLK 2
13
+
#define VIDEO_CC_MVS0_CLK_SRC 3
14
+
#define VIDEO_CC_MVS0_DIV_CLK_SRC 4
15
+
#define VIDEO_CC_MVS0C_CLK 5
16
+
#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 6
17
+
#define VIDEO_CC_MVS1_CLK 7
18
+
#define VIDEO_CC_MVS1_CLK_SRC 8
19
+
#define VIDEO_CC_MVS1_DIV_CLK_SRC 9
20
+
#define VIDEO_CC_MVS1C_CLK 10
21
+
#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 11
22
+
#define VIDEO_CC_PLL_LOCK_MONITOR_CLK 12
23
+
#define VIDEO_CC_SLEEP_CLK 13
24
+
#define VIDEO_CC_SLEEP_CLK_SRC 14
25
+
#define VIDEO_CC_SM_DIV_CLK_SRC 15
26
+
#define VIDEO_CC_SM_OBS_CLK 16
27
+
#define VIDEO_CC_XO_CLK 17
28
+
#define VIDEO_CC_XO_CLK_SRC 18
29
+
#define VIDEO_PLL0 19
30
+
#define VIDEO_PLL1 20
31
+
32
+
/* VIDEO_CC power domains */
33
+
#define VIDEO_CC_MVS0C_GDSC 0
34
+
#define VIDEO_CC_MVS0_GDSC 1
35
+
#define VIDEO_CC_MVS1C_GDSC 2
36
+
#define VIDEO_CC_MVS1_GDSC 3
37
+
38
+
/* VIDEO_CC resets */
39
+
#define VIDEO_CC_INTERFACE_BCR 0
40
+
#define VIDEO_CC_MVS0_BCR 1
41
+
#define VIDEO_CC_MVS0C_CLK_ARES 2
42
+
#define VIDEO_CC_MVS0C_BCR 3
43
+
#define VIDEO_CC_MVS1_BCR 4
44
+
#define VIDEO_CC_MVS1C_CLK_ARES 5
45
+
#define VIDEO_CC_MVS1C_BCR 6
46
+
47
+
#endif