tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

drm/amdgpu: Fix xcc_id input for soc_v1_0_grbm_select

Ensure the GRBM_GFX_CNTL is programmed correctly

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Hawking Zhang and committed by
Alex Deucher bc35ae1a 09a75a23

+4 -4
+4 -4
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
··· 1448 1448 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, tmp); 1449 1449 } 1450 1450 } 1451 - soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 1451 + soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1452 1452 1453 1453 mutex_unlock(&adev->srbm_mutex); 1454 1454 ··· 1776 1776 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START_HI, 1777 1777 mec_hdr->ucode_start_addr_hi >> 2); 1778 1778 } 1779 - soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 1779 + soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1780 1780 1781 1781 /* reset mec pipe */ 1782 1782 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL); ··· 1821 1821 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START_HI, 1822 1822 cp_hdr->ucode_start_addr_hi >> 2); 1823 1823 } 1824 - soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 1824 + soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1825 1825 mutex_unlock(&adev->srbm_mutex); 1826 1826 } 1827 1827 ··· 2017 2017 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2018 2018 } 2019 2019 mutex_unlock(&adev->srbm_mutex); 2020 - soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 2020 + soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2021 2021 2022 2022 /* Trigger an invalidation of the L1 instruction caches */ 2023 2023 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL);