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phy: qcom-qmp-ufs: drop support for non-UFS PHY types

Drop remaining support for PHY types other than UFS.

Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220607213203.2819885-18-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Dmitry Baryshkov and committed by
Vinod Koul bc3e83d7 f575ac2d

+35 -577
+35 -577
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
··· 986 986 struct qcom_qmp *qmp = qphy->qmp; 987 987 const struct qmp_phy_cfg *cfg = qphy->cfg; 988 988 void __iomem *serdes = qphy->serdes; 989 - const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 990 989 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; 991 990 int serdes_tbl_num = cfg->serdes_tbl_num; 992 991 int ret; ··· 994 995 if (cfg->serdes_tbl_sec) 995 996 qcom_qmp_phy_ufs_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, 996 997 cfg->serdes_tbl_num_sec); 997 - 998 - if (cfg->type == PHY_TYPE_DP) { 999 - switch (dp_opts->link_rate) { 1000 - case 1620: 1001 - qcom_qmp_phy_ufs_configure(serdes, cfg->regs, 1002 - cfg->serdes_tbl_rbr, 1003 - cfg->serdes_tbl_rbr_num); 1004 - break; 1005 - case 2700: 1006 - qcom_qmp_phy_ufs_configure(serdes, cfg->regs, 1007 - cfg->serdes_tbl_hbr, 1008 - cfg->serdes_tbl_hbr_num); 1009 - break; 1010 - case 5400: 1011 - qcom_qmp_phy_ufs_configure(serdes, cfg->regs, 1012 - cfg->serdes_tbl_hbr2, 1013 - cfg->serdes_tbl_hbr2_num); 1014 - break; 1015 - case 8100: 1016 - qcom_qmp_phy_ufs_configure(serdes, cfg->regs, 1017 - cfg->serdes_tbl_hbr3, 1018 - cfg->serdes_tbl_hbr3_num); 1019 - break; 1020 - default: 1021 - /* Other link rates aren't supported */ 1022 - return -EINVAL; 1023 - } 1024 - } 1025 - 1026 998 1027 999 if (cfg->has_phy_com_ctrl) { 1028 1000 void __iomem *status; ··· 1014 1044 return ret; 1015 1045 } 1016 1046 } 1017 - 1018 - return 0; 1019 - } 1020 - 1021 - static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) 1022 - { 1023 - const struct phy_configure_opts_dp *dp_opts = &opts->dp; 1024 - struct qmp_phy *qphy = phy_get_drvdata(phy); 1025 - const struct qmp_phy_cfg *cfg = qphy->cfg; 1026 - 1027 - memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts)); 1028 - if (qphy->dp_opts.set_voltages) { 1029 - cfg->configure_dp_tx(qphy); 1030 - qphy->dp_opts.set_voltages = 0; 1031 - } 1032 - 1033 - return 0; 1034 - } 1035 - 1036 - static int qcom_qmp_dp_phy_calibrate(struct phy *phy) 1037 - { 1038 - struct qmp_phy *qphy = phy_get_drvdata(phy); 1039 - const struct qmp_phy_cfg *cfg = qphy->cfg; 1040 - 1041 - if (cfg->calibrate_dp_phy) 1042 - return cfg->calibrate_dp_phy(qphy); 1043 1047 1044 1048 return 0; 1045 1049 } ··· 1187 1243 if (ret) 1188 1244 return ret; 1189 1245 1190 - if (cfg->type == PHY_TYPE_DP) 1191 - cfg->dp_aux_init(qphy); 1192 - 1193 1246 return 0; 1194 1247 } 1195 1248 ··· 1237 1296 cfg->tx_tbl_num_sec, 2); 1238 1297 } 1239 1298 1240 - /* Configure special DP tx tunings */ 1241 - if (cfg->type == PHY_TYPE_DP) 1242 - cfg->configure_dp_tx(qphy); 1243 - 1244 1299 qcom_qmp_phy_ufs_configure_lane(rx, cfg->regs, 1245 1300 cfg->rx_tbl, cfg->rx_tbl_num, 1); 1246 1301 if (cfg->rx_tbl_sec) ··· 1252 1315 cfg->rx_tbl_num_sec, 2); 1253 1316 } 1254 1317 1255 - /* Configure link rate, swing, etc. */ 1256 - if (cfg->type == PHY_TYPE_DP) { 1257 - cfg->configure_dp_phy(qphy); 1258 - } else { 1259 - qcom_qmp_phy_ufs_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); 1260 - if (cfg->pcs_tbl_sec) 1261 - qcom_qmp_phy_ufs_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, 1262 - cfg->pcs_tbl_num_sec); 1263 - } 1318 + qcom_qmp_phy_ufs_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); 1319 + if (cfg->pcs_tbl_sec) 1320 + qcom_qmp_phy_ufs_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, 1321 + cfg->pcs_tbl_num_sec); 1264 1322 1265 1323 ret = reset_control_deassert(qmp->ufs_reset); 1266 1324 if (ret) ··· 1267 1335 qcom_qmp_phy_ufs_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, 1268 1336 cfg->pcs_misc_tbl_num_sec); 1269 1337 1270 - /* 1271 - * Pull out PHY from POWER DOWN state. 1272 - * This is active low enable signal to power-down PHY. 1273 - */ 1274 - if(cfg->type == PHY_TYPE_PCIE) 1275 - qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); 1276 - 1277 1338 if (cfg->has_pwrdn_delay) 1278 1339 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); 1279 1340 1280 - if (cfg->type != PHY_TYPE_DP) { 1281 - /* Pull PHY out of reset state */ 1282 - if (!cfg->no_pcs_sw_reset) 1283 - qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1284 - /* start SerDes and Phy-Coding-Sublayer */ 1285 - qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 1341 + /* Pull PHY out of reset state */ 1342 + if (!cfg->no_pcs_sw_reset) 1343 + qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1344 + /* start SerDes and Phy-Coding-Sublayer */ 1345 + qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 1286 1346 1287 - if (cfg->type == PHY_TYPE_UFS) { 1288 - status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; 1289 - mask = PCS_READY; 1290 - ready = PCS_READY; 1291 - } else { 1292 - status = pcs + cfg->regs[QPHY_PCS_STATUS]; 1293 - mask = cfg->phy_status; 1294 - ready = 0; 1295 - } 1347 + status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; 1348 + mask = PCS_READY; 1349 + ready = PCS_READY; 1296 1350 1297 - ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, 1298 - PHY_INIT_COMPLETE_TIMEOUT); 1299 - if (ret) { 1300 - dev_err(qmp->dev, "phy initialization timed-out\n"); 1301 - goto err_disable_pipe_clk; 1302 - } 1351 + ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, 1352 + PHY_INIT_COMPLETE_TIMEOUT); 1353 + if (ret) { 1354 + dev_err(qmp->dev, "phy initialization timed-out\n"); 1355 + goto err_disable_pipe_clk; 1303 1356 } 1304 1357 return 0; 1305 1358 ··· 1304 1387 1305 1388 clk_disable_unprepare(qphy->pipe_clk); 1306 1389 1307 - if (cfg->type == PHY_TYPE_DP) { 1308 - /* Assert DP PHY power down */ 1309 - writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); 1390 + /* PHY reset */ 1391 + if (!cfg->no_pcs_sw_reset) 1392 + qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1393 + 1394 + /* stop SerDes and Phy-Coding-Sublayer */ 1395 + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 1396 + 1397 + /* Put PHY into POWER DOWN state: active low */ 1398 + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { 1399 + qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 1400 + cfg->pwrdn_ctrl); 1310 1401 } else { 1311 - /* PHY reset */ 1312 - if (!cfg->no_pcs_sw_reset) 1313 - qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1314 - 1315 - /* stop SerDes and Phy-Coding-Sublayer */ 1316 - qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 1317 - 1318 - /* Put PHY into POWER DOWN state: active low */ 1319 - if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { 1320 - qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 1321 - cfg->pwrdn_ctrl); 1322 - } else { 1323 - qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, 1324 - cfg->pwrdn_ctrl); 1325 - } 1402 + qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, 1403 + cfg->pwrdn_ctrl); 1326 1404 } 1327 1405 1328 1406 return 0; ··· 1367 1455 struct qmp_phy *qphy = phy_get_drvdata(phy); 1368 1456 1369 1457 qphy->mode = mode; 1370 - 1371 - return 0; 1372 - } 1373 - 1374 - static void qcom_qmp_phy_ufs_enable_autonomous_mode(struct qmp_phy *qphy) 1375 - { 1376 - const struct qmp_phy_cfg *cfg = qphy->cfg; 1377 - void __iomem *pcs = qphy->pcs; 1378 - void __iomem *pcs_misc = qphy->pcs_misc; 1379 - u32 intr_mask; 1380 - 1381 - if (qphy->mode == PHY_MODE_USB_HOST_SS || 1382 - qphy->mode == PHY_MODE_USB_DEVICE_SS) 1383 - intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 1384 - else 1385 - intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; 1386 - 1387 - /* Clear any pending interrupts status */ 1388 - qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 1389 - /* Writing 1 followed by 0 clears the interrupt */ 1390 - qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 1391 - 1392 - qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 1393 - ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); 1394 - 1395 - /* Enable required PHY autonomous mode interrupts */ 1396 - qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); 1397 - 1398 - /* Enable i/o clamp_n for autonomous mode */ 1399 - if (pcs_misc) 1400 - qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 1401 - } 1402 - 1403 - static void qcom_qmp_phy_ufs_disable_autonomous_mode(struct qmp_phy *qphy) 1404 - { 1405 - const struct qmp_phy_cfg *cfg = qphy->cfg; 1406 - void __iomem *pcs = qphy->pcs; 1407 - void __iomem *pcs_misc = qphy->pcs_misc; 1408 - 1409 - /* Disable i/o clamp_n on resume for normal mode */ 1410 - if (pcs_misc) 1411 - qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 1412 - 1413 - qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 1414 - ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); 1415 - 1416 - qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 1417 - /* Writing 1 followed by 0 clears the interrupt */ 1418 - qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 1419 - } 1420 - 1421 - static int __maybe_unused qcom_qmp_phy_ufs_runtime_suspend(struct device *dev) 1422 - { 1423 - struct qcom_qmp *qmp = dev_get_drvdata(dev); 1424 - struct qmp_phy *qphy = qmp->phys[0]; 1425 - const struct qmp_phy_cfg *cfg = qphy->cfg; 1426 - 1427 - dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode); 1428 - 1429 - /* Supported only for USB3 PHY and luckily USB3 is the first phy */ 1430 - if (cfg->type != PHY_TYPE_USB3) 1431 - return 0; 1432 - 1433 - if (!qmp->init_count) { 1434 - dev_vdbg(dev, "PHY not initialized, bailing out\n"); 1435 - return 0; 1436 - } 1437 - 1438 - qcom_qmp_phy_ufs_enable_autonomous_mode(qphy); 1439 - 1440 - clk_disable_unprepare(qphy->pipe_clk); 1441 - clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 1442 - 1443 - return 0; 1444 - } 1445 - 1446 - static int __maybe_unused qcom_qmp_phy_ufs_runtime_resume(struct device *dev) 1447 - { 1448 - struct qcom_qmp *qmp = dev_get_drvdata(dev); 1449 - struct qmp_phy *qphy = qmp->phys[0]; 1450 - const struct qmp_phy_cfg *cfg = qphy->cfg; 1451 - int ret = 0; 1452 - 1453 - dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode); 1454 - 1455 - /* Supported only for USB3 PHY and luckily USB3 is the first phy */ 1456 - if (cfg->type != PHY_TYPE_USB3) 1457 - return 0; 1458 - 1459 - if (!qmp->init_count) { 1460 - dev_vdbg(dev, "PHY not initialized, bailing out\n"); 1461 - return 0; 1462 - } 1463 - 1464 - ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 1465 - if (ret) 1466 - return ret; 1467 - 1468 - ret = clk_prepare_enable(qphy->pipe_clk); 1469 - if (ret) { 1470 - dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 1471 - clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 1472 - return ret; 1473 - } 1474 - 1475 - qcom_qmp_phy_ufs_disable_autonomous_mode(qphy); 1476 1458 1477 1459 return 0; 1478 1460 } ··· 1428 1622 return devm_clk_bulk_get(dev, num, qmp->clks); 1429 1623 } 1430 1624 1431 - static void phy_clk_release_provider(void *res) 1432 - { 1433 - of_clk_del_provider(res); 1434 - } 1435 - 1436 - /* 1437 - * Register a fixed rate pipe clock. 1438 - * 1439 - * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 1440 - * controls it. The <s>_pipe_clk coming out of the GCC is requested 1441 - * by the PHY driver for its operations. 1442 - * We register the <s>_pipe_clksrc here. The gcc driver takes care 1443 - * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 1444 - * Below picture shows this relationship. 1445 - * 1446 - * +---------------+ 1447 - * | PHY block |<<---------------------------------------+ 1448 - * | | | 1449 - * | +-------+ | +-----+ | 1450 - * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 1451 - * clk | +-------+ | +-----+ 1452 - * +---------------+ 1453 - */ 1454 - static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) 1455 - { 1456 - struct clk_fixed_rate *fixed; 1457 - struct clk_init_data init = { }; 1458 - int ret; 1459 - 1460 - ret = of_property_read_string(np, "clock-output-names", &init.name); 1461 - if (ret) { 1462 - dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 1463 - return ret; 1464 - } 1465 - 1466 - fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); 1467 - if (!fixed) 1468 - return -ENOMEM; 1469 - 1470 - init.ops = &clk_fixed_rate_ops; 1471 - 1472 - /* controllers using QMP phys use 125MHz pipe clock interface */ 1473 - fixed->fixed_rate = 125000000; 1474 - fixed->hw.init = &init; 1475 - 1476 - ret = devm_clk_hw_register(qmp->dev, &fixed->hw); 1477 - if (ret) 1478 - return ret; 1479 - 1480 - ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); 1481 - if (ret) 1482 - return ret; 1483 - 1484 - /* 1485 - * Roll a devm action because the clock provider is the child node, but 1486 - * the child node is not actually a device. 1487 - */ 1488 - return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 1489 - } 1490 - 1491 - /* 1492 - * Display Port PLL driver block diagram for branch clocks 1493 - * 1494 - * +------------------------------+ 1495 - * | DP_VCO_CLK | 1496 - * | | 1497 - * | +-------------------+ | 1498 - * | | (DP PLL/VCO) | | 1499 - * | +---------+---------+ | 1500 - * | v | 1501 - * | +----------+-----------+ | 1502 - * | | hsclk_divsel_clk_src | | 1503 - * | +----------+-----------+ | 1504 - * +------------------------------+ 1505 - * | 1506 - * +---------<---------v------------>----------+ 1507 - * | | 1508 - * +--------v----------------+ | 1509 - * | dp_phy_pll_link_clk | | 1510 - * | link_clk | | 1511 - * +--------+----------------+ | 1512 - * | | 1513 - * | | 1514 - * v v 1515 - * Input to DISPCC block | 1516 - * for link clk, crypto clk | 1517 - * and interface clock | 1518 - * | 1519 - * | 1520 - * +--------<------------+-----------------+---<---+ 1521 - * | | | 1522 - * +----v---------+ +--------v-----+ +--------v------+ 1523 - * | vco_divided | | vco_divided | | vco_divided | 1524 - * | _clk_src | | _clk_src | | _clk_src | 1525 - * | | | | | | 1526 - * |divsel_six | | divsel_two | | divsel_four | 1527 - * +-------+------+ +-----+--------+ +--------+------+ 1528 - * | | | 1529 - * v---->----------v-------------<------v 1530 - * | 1531 - * +----------+-----------------+ 1532 - * | dp_phy_pll_vco_div_clk | 1533 - * +---------+------------------+ 1534 - * | 1535 - * v 1536 - * Input to DISPCC block 1537 - * for DP pixel clock 1538 - * 1539 - */ 1540 - static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, 1541 - struct clk_rate_request *req) 1542 - { 1543 - switch (req->rate) { 1544 - case 1620000000UL / 2: 1545 - case 2700000000UL / 2: 1546 - /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ 1547 - return 0; 1548 - default: 1549 - return -EINVAL; 1550 - } 1551 - } 1552 - 1553 - static unsigned long 1554 - qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1555 - { 1556 - const struct qmp_phy_dp_clks *dp_clks; 1557 - const struct qmp_phy *qphy; 1558 - const struct phy_configure_opts_dp *dp_opts; 1559 - 1560 - dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw); 1561 - qphy = dp_clks->qphy; 1562 - dp_opts = &qphy->dp_opts; 1563 - 1564 - switch (dp_opts->link_rate) { 1565 - case 1620: 1566 - return 1620000000UL / 2; 1567 - case 2700: 1568 - return 2700000000UL / 2; 1569 - case 5400: 1570 - return 5400000000UL / 4; 1571 - case 8100: 1572 - return 8100000000UL / 6; 1573 - default: 1574 - return 0; 1575 - } 1576 - } 1577 - 1578 - static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = { 1579 - .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate, 1580 - .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate, 1581 - }; 1582 - 1583 - static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw, 1584 - struct clk_rate_request *req) 1585 - { 1586 - switch (req->rate) { 1587 - case 162000000: 1588 - case 270000000: 1589 - case 540000000: 1590 - case 810000000: 1591 - return 0; 1592 - default: 1593 - return -EINVAL; 1594 - } 1595 - } 1596 - 1597 - static unsigned long 1598 - qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1599 - { 1600 - const struct qmp_phy_dp_clks *dp_clks; 1601 - const struct qmp_phy *qphy; 1602 - const struct phy_configure_opts_dp *dp_opts; 1603 - 1604 - dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw); 1605 - qphy = dp_clks->qphy; 1606 - dp_opts = &qphy->dp_opts; 1607 - 1608 - switch (dp_opts->link_rate) { 1609 - case 1620: 1610 - case 2700: 1611 - case 5400: 1612 - case 8100: 1613 - return dp_opts->link_rate * 100000; 1614 - default: 1615 - return 0; 1616 - } 1617 - } 1618 - 1619 - static const struct clk_ops qcom_qmp_dp_link_clk_ops = { 1620 - .determine_rate = qcom_qmp_dp_link_clk_determine_rate, 1621 - .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate, 1622 - }; 1623 - 1624 - static struct clk_hw * 1625 - qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) 1626 - { 1627 - struct qmp_phy_dp_clks *dp_clks = data; 1628 - unsigned int idx = clkspec->args[0]; 1629 - 1630 - if (idx >= 2) { 1631 - pr_err("%s: invalid index %u\n", __func__, idx); 1632 - return ERR_PTR(-EINVAL); 1633 - } 1634 - 1635 - if (idx == 0) 1636 - return &dp_clks->dp_link_hw; 1637 - 1638 - return &dp_clks->dp_pixel_hw; 1639 - } 1640 - 1641 - static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy, 1642 - struct device_node *np) 1643 - { 1644 - struct clk_init_data init = { }; 1645 - struct qmp_phy_dp_clks *dp_clks; 1646 - char name[64]; 1647 - int ret; 1648 - 1649 - dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL); 1650 - if (!dp_clks) 1651 - return -ENOMEM; 1652 - 1653 - dp_clks->qphy = qphy; 1654 - qphy->dp_clks = dp_clks; 1655 - 1656 - snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); 1657 - init.ops = &qcom_qmp_dp_link_clk_ops; 1658 - init.name = name; 1659 - dp_clks->dp_link_hw.init = &init; 1660 - ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw); 1661 - if (ret) 1662 - return ret; 1663 - 1664 - snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); 1665 - init.ops = &qcom_qmp_dp_pixel_clk_ops; 1666 - init.name = name; 1667 - dp_clks->dp_pixel_hw.init = &init; 1668 - ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw); 1669 - if (ret) 1670 - return ret; 1671 - 1672 - ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks); 1673 - if (ret) 1674 - return ret; 1675 - 1676 - /* 1677 - * Roll a devm action because the clock provider is the child node, but 1678 - * the child node is not actually a device. 1679 - */ 1680 - return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 1681 - } 1682 - 1683 - static const struct phy_ops qcom_qmp_phy_ufs_gen_ops = { 1684 - .init = qcom_qmp_phy_ufs_enable, 1685 - .exit = qcom_qmp_phy_ufs_disable, 1686 - .set_mode = qcom_qmp_phy_ufs_set_mode, 1687 - .owner = THIS_MODULE, 1688 - }; 1689 - 1690 - static const struct phy_ops qcom_qmp_phy_ufs_dp_ops = { 1691 - .init = qcom_qmp_phy_ufs_init, 1692 - .configure = qcom_qmp_dp_phy_configure, 1693 - .power_on = qcom_qmp_phy_ufs_power_on, 1694 - .calibrate = qcom_qmp_dp_phy_calibrate, 1695 - .power_off = qcom_qmp_phy_ufs_power_off, 1696 - .exit = qcom_qmp_phy_ufs_exit, 1697 - .set_mode = qcom_qmp_phy_ufs_set_mode, 1698 - .owner = THIS_MODULE, 1699 - }; 1700 - 1701 - static const struct phy_ops qcom_qmp_pcie_ufs_ops = { 1625 + static const struct phy_ops qcom_qmp_ufs_ops = { 1702 1626 .power_on = qcom_qmp_phy_ufs_enable, 1703 1627 .power_off = qcom_qmp_phy_ufs_disable, 1704 1628 .set_mode = qcom_qmp_phy_ufs_set_mode, ··· 1447 1911 struct qcom_qmp *qmp = dev_get_drvdata(dev); 1448 1912 struct phy *generic_phy; 1449 1913 struct qmp_phy *qphy; 1450 - const struct phy_ops *ops; 1451 1914 char prop_name[MAX_PROP_NAME]; 1452 1915 int ret; 1453 1916 ··· 1503 1968 if (!qphy->pcs_misc) 1504 1969 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 1505 1970 1506 - /* 1507 - * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3 1508 - * based phys, so they essentially have pipe clock. So, 1509 - * we return error in case phy is USB3 or PIPE type. 1510 - * Otherwise, we initialize pipe clock to NULL for 1511 - * all phys that don't need this. 1512 - */ 1513 - snprintf(prop_name, sizeof(prop_name), "pipe%d", id); 1514 - qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name); 1515 - if (IS_ERR(qphy->pipe_clk)) { 1516 - if (cfg->type == PHY_TYPE_PCIE || 1517 - cfg->type == PHY_TYPE_USB3) { 1518 - ret = PTR_ERR(qphy->pipe_clk); 1519 - if (ret != -EPROBE_DEFER) 1520 - dev_err(dev, 1521 - "failed to get lane%d pipe_clk, %d\n", 1522 - id, ret); 1523 - return ret; 1524 - } 1525 - qphy->pipe_clk = NULL; 1526 - } 1527 - 1528 1971 /* Get lane reset, if any */ 1529 1972 if (cfg->has_lane_rst) { 1530 1973 snprintf(prop_name, sizeof(prop_name), "lane%d", id); ··· 1517 2004 return ret; 1518 2005 } 1519 2006 1520 - if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE) 1521 - ops = &qcom_qmp_pcie_ufs_ops; 1522 - else if (cfg->type == PHY_TYPE_DP) 1523 - ops = &qcom_qmp_phy_ufs_dp_ops; 1524 - else 1525 - ops = &qcom_qmp_phy_ufs_gen_ops; 1526 - 1527 - generic_phy = devm_phy_create(dev, np, ops); 2007 + generic_phy = devm_phy_create(dev, np, &qcom_qmp_ufs_ops); 1528 2008 if (IS_ERR(generic_phy)) { 1529 2009 ret = PTR_ERR(generic_phy); 1530 2010 dev_err(dev, "failed to create qphy %d\n", ret); ··· 1572 2066 }; 1573 2067 MODULE_DEVICE_TABLE(of, qcom_qmp_phy_ufs_of_match_table); 1574 2068 1575 - static const struct dev_pm_ops qcom_qmp_phy_ufs_pm_ops = { 1576 - SET_RUNTIME_PM_OPS(qcom_qmp_phy_ufs_runtime_suspend, 1577 - qcom_qmp_phy_ufs_runtime_resume, NULL) 1578 - }; 1579 - 1580 2069 static int qcom_qmp_phy_ufs_probe(struct platform_device *pdev) 1581 2070 { 1582 2071 struct qcom_qmp *qmp; ··· 1579 2078 struct device_node *child; 1580 2079 struct phy_provider *phy_provider; 1581 2080 void __iomem *serdes; 1582 - void __iomem *usb_serdes; 1583 - void __iomem *dp_serdes = NULL; 1584 - const struct qmp_phy_combo_cfg *combo_cfg = NULL; 1585 2081 const struct qmp_phy_cfg *cfg = NULL; 1586 - const struct qmp_phy_cfg *usb_cfg = NULL; 1587 - const struct qmp_phy_cfg *dp_cfg = NULL; 1588 2082 int num, id, expected_phys; 1589 2083 int ret; 1590 2084 ··· 1596 2100 return -EINVAL; 1597 2101 1598 2102 /* per PHY serdes; usually located at base address */ 1599 - usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0); 2103 + serdes = devm_platform_ioremap_resource(pdev, 0); 1600 2104 if (IS_ERR(serdes)) 1601 2105 return PTR_ERR(serdes); 1602 2106 1603 2107 /* per PHY dp_com; if PHY has dp_com control block */ 1604 - if (combo_cfg || cfg->has_phy_dp_com_ctrl) { 2108 + if (cfg->has_phy_dp_com_ctrl) { 1605 2109 qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); 1606 2110 if (IS_ERR(qmp->dp_com)) 1607 2111 return PTR_ERR(qmp->dp_com); 1608 2112 } 1609 2113 1610 - if (combo_cfg) { 1611 - /* Only two serdes for combo PHY */ 1612 - dp_serdes = devm_platform_ioremap_resource(pdev, 2); 1613 - if (IS_ERR(dp_serdes)) 1614 - return PTR_ERR(dp_serdes); 1615 - 1616 - dp_cfg = combo_cfg->dp_cfg; 1617 - expected_phys = 2; 1618 - } else { 1619 - expected_phys = cfg->nlanes; 1620 - } 2114 + expected_phys = cfg->nlanes; 1621 2115 1622 2116 mutex_init(&qmp->phy_mutex); 1623 2117 ··· 1646 2160 1647 2161 id = 0; 1648 2162 for_each_available_child_of_node(dev->of_node, child) { 1649 - if (of_node_name_eq(child, "dp-phy")) { 1650 - cfg = dp_cfg; 1651 - serdes = dp_serdes; 1652 - } else if (of_node_name_eq(child, "usb3-phy")) { 1653 - cfg = usb_cfg; 1654 - serdes = usb_serdes; 1655 - } 1656 - 1657 2163 /* Create per-lane phy */ 1658 2164 ret = qcom_qmp_phy_ufs_create(dev, child, id, serdes, cfg); 1659 2165 if (ret) { ··· 1654 2176 goto err_node_put; 1655 2177 } 1656 2178 1657 - /* 1658 - * Register the pipe clock provided by phy. 1659 - * See function description to see details of this pipe clock. 1660 - */ 1661 - if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) { 1662 - ret = phy_pipe_clk_register(qmp, child); 1663 - if (ret) { 1664 - dev_err(qmp->dev, 1665 - "failed to register pipe clock source\n"); 1666 - goto err_node_put; 1667 - } 1668 - } else if (cfg->type == PHY_TYPE_DP) { 1669 - ret = phy_dp_clks_register(qmp, qmp->phys[id], child); 1670 - if (ret) { 1671 - dev_err(qmp->dev, 1672 - "failed to register DP clock source\n"); 1673 - goto err_node_put; 1674 - } 1675 - } 1676 2179 id++; 1677 2180 } 1678 2181 ··· 1675 2216 .probe = qcom_qmp_phy_ufs_probe, 1676 2217 .driver = { 1677 2218 .name = "qcom-qmp-ufs-phy", 1678 - .pm = &qcom_qmp_phy_ufs_pm_ops, 1679 2219 .of_match_table = qcom_qmp_phy_ufs_of_match_table, 1680 2220 }, 1681 2221 };