Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-next-2018-11-02' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie:
"Pretty much a normal fixes pull pre-rc1, mostly amdgpu fixes, one i915
link training regression fix, and a couple of minor panel/bridge fixes
and a panel quirk"
* tag 'drm-next-2018-11-02' of git://anongit.freedesktop.org/drm/drm: (37 commits)
drm/amdgpu: revert "enable gfxoff in non-sriov and stutter mode by default"
drm/amd/pp: Print warning if od_sclk/mclk out of range
drm/amd/pp: Fix pp_sclk/mclk_od not work on Vega10
drm/amd/pp: Fix pp_sclk/mclk_od not work on smu7
drm/amd/powerplay: no MGPU fan boost enablement on DPM disabled
drm/amdgpu: Fix skipping hangged job reset during gpu recover.
drm/amd/powerplay: revise Vega20 pptable version check
drm/amd/display: set backlight level limit to 1
drm/panel: simple: Innolux TV123WAM is actually P120ZDG-BF1
dt-bindings: drm/panel: simple: Innolux TV123WAM is actually P120ZDG-BF1
drm/bridge: ti-sn65dsi86: Remove the mystery delay
drm/panel: simple: Add "no-hpd" delay for Innolux TV123WAM
drm/panel: simple: Support panels with HPD where HPD isn't connected
dt-bindings: drm/panel: simple: Add no-hpd property
drm/edid: Add 6 bpc quirk for BOE panel.
drm/amdgpu: fix reporting of failed msg sent to SMU (v2)
drm/amdgpu: Fix compute ring 1.0.0 failure after reset
drm/amdgpu: fix VM leaf walking
drm/amdgpu: fix amdgpu_vm_fini
drm/amd/powerplay: commonize the API for retrieving current clocks
...
+364
-175
+5
-3
Documentation/devicetree/bindings/display/panel/innolux,tv123wam.txt
Documentation/devicetree/bindings/display/panel/innolux,p120zdg-bf1.txt
+5
-3
Documentation/devicetree/bindings/display/panel/innolux,tv123wam.txt
Documentation/devicetree/bindings/display/panel/innolux,p120zdg-bf1.txt
···
1
-
Innolux TV123WAM 12.3 inch eDP 2K display panel
1
+
Innolux P120ZDG-BF1 12.02 inch eDP 2K display panel
2
2
3
3
This binding is compatible with the simple-panel binding, which is specified
4
4
in simple-panel.txt in this directory.
5
5
6
6
Required properties:
7
-
- compatible: should be "innolux,tv123wam"
7
+
- compatible: should be "innolux,p120zdg-bf1"
8
8
- power-supply: regulator to provide the supply voltage
9
9
10
10
Optional properties:
11
11
- enable-gpios: GPIO pin to enable or disable the panel
12
12
- backlight: phandle of the backlight device attached to the panel
13
+
- no-hpd: If HPD isn't hooked up; add this property.
13
14
14
15
Example:
15
16
panel_edp: panel-edp {
16
-
compatible = "innolux,tv123wam";
17
+
compatible = "innolux,p120zdg-bf1";
17
18
enable-gpios = <&msmgpio 31 GPIO_ACTIVE_LOW>;
18
19
power-supply = <&pm8916_l2>;
19
20
backlight = <&backlight>;
21
+
no-hpd;
20
22
};
+3
Documentation/devicetree/bindings/display/panel/simple-panel.txt
+3
Documentation/devicetree/bindings/display/panel/simple-panel.txt
···
11
11
- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
12
12
- enable-gpios: GPIO pin to enable or disable the panel
13
13
- backlight: phandle of the backlight device attached to the panel
14
+
- no-hpd: This panel is supposed to communicate that it's ready via HPD
15
+
(hot plug detect) signal, but the signal isn't hooked up so we should
16
+
hardcode the max delay from the panel spec when powering up the panel.
14
17
15
18
Example:
16
19
+4
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+4
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
···
135
135
* 2. power off the acp tiles
136
136
* 3. check and enter ulv state
137
137
*/
138
-
if (adev->powerplay.pp_funcs->set_powergating_by_smu)
138
+
if (adev->powerplay.pp_funcs &&
139
+
adev->powerplay.pp_funcs->set_powergating_by_smu)
139
140
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
140
141
}
141
142
return 0;
···
518
517
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
519
518
bool enable = state == AMD_PG_STATE_GATE ? true : false;
520
519
521
-
if (adev->powerplay.pp_funcs->set_powergating_by_smu)
520
+
if (adev->powerplay.pp_funcs &&
521
+
adev->powerplay.pp_funcs->set_powergating_by_smu)
522
522
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable);
523
523
524
524
return 0;
+2
-4
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+2
-4
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
···
1493
1493
}
1494
1494
1495
1495
adev->powerplay.pp_feature = amdgpu_pp_feature_mask;
1496
-
if (amdgpu_sriov_vf(adev))
1497
-
adev->powerplay.pp_feature &= ~PP_GFXOFF_MASK;
1498
1496
1499
1497
for (i = 0; i < adev->num_ip_blocks; i++) {
1500
1498
if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
···
1598
1600
}
1599
1601
}
1600
1602
1601
-
if (adev->powerplay.pp_funcs->load_firmware) {
1603
+
if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->load_firmware) {
1602
1604
r = adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
1603
1605
if (r) {
1604
1606
pr_err("firmware loading failed\n");
···
3339
3341
3340
3342
kthread_park(ring->sched.thread);
3341
3343
3342
-
if (job && job->base.sched == &ring->sched)
3344
+
if (job && job->base.sched != &ring->sched)
3343
3345
continue;
3344
3346
3345
3347
drm_sched_hw_job_reset(&ring->sched, job ? &job->base : NULL);
+2
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+2
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
···
114
114
uint amdgpu_sdma_phase_quantum = 32;
115
115
char *amdgpu_disable_cu = NULL;
116
116
char *amdgpu_virtual_display = NULL;
117
-
/* OverDrive(bit 14) disabled by default*/
118
-
uint amdgpu_pp_feature_mask = 0xffffbfff;
117
+
/* OverDrive(bit 14),gfxoff(bit 15),stutter mode(bit 17) disabled by default*/
118
+
uint amdgpu_pp_feature_mask = 0xfffd3fff;
119
119
int amdgpu_ngg = 0;
120
120
int amdgpu_prim_buf_per_se = 0;
121
121
int amdgpu_pos_buf_per_se = 0;
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+12
-3
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+12
-3
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
···
704
704
return ret;
705
705
706
706
if (adev->powerplay.pp_funcs->force_clock_level)
707
-
amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
707
+
ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
708
+
709
+
if (ret)
710
+
return -EINVAL;
708
711
709
712
return count;
710
713
}
···
740
737
return ret;
741
738
742
739
if (adev->powerplay.pp_funcs->force_clock_level)
743
-
amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
740
+
ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
741
+
742
+
if (ret)
743
+
return -EINVAL;
744
744
745
745
return count;
746
746
}
···
776
770
return ret;
777
771
778
772
if (adev->powerplay.pp_funcs->force_clock_level)
779
-
amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
773
+
ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
774
+
775
+
if (ret)
776
+
return -EINVAL;
780
777
781
778
return count;
782
779
}
+5
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+5
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
···
542
542
struct amdgpu_vm_pt_cursor *cursor)
543
543
{
544
544
amdgpu_vm_pt_next(adev, cursor);
545
-
while (amdgpu_vm_pt_descendant(adev, cursor));
545
+
if (cursor->pfn != ~0ll)
546
+
while (amdgpu_vm_pt_descendant(adev, cursor));
546
547
}
547
548
548
549
/**
···
3235
3234
}
3236
3235
rbtree_postorder_for_each_entry_safe(mapping, tmp,
3237
3236
&vm->va.rb_root, rb) {
3237
+
/* Don't remove the mapping here, we don't want to trigger a
3238
+
* rebalance and the tree is about to be destroyed anyway.
3239
+
*/
3238
3240
list_del(&mapping->list);
3239
-
amdgpu_vm_it_remove(mapping, &vm->va);
3240
3241
kfree(mapping);
3241
3242
}
3242
3243
list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
+4
-2
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+4
-2
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
···
4815
4815
if (r)
4816
4816
goto done;
4817
4817
4818
-
/* Test KCQs */
4819
-
for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4818
+
/* Test KCQs - reversing the order of rings seems to fix ring test failure
4819
+
* after GPU reset
4820
+
*/
4821
+
for (i = adev->gfx.num_compute_rings - 1; i >= 0; i--) {
4820
4822
ring = &adev->gfx.compute_ring[i];
4821
4823
ring->ready = true;
4822
4824
r = amdgpu_ring_test_ring(ring);
+1
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+1
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
···
280
280
return;
281
281
282
282
if (enable && adev->pg_flags & AMD_PG_SUPPORT_MMHUB) {
283
-
if (adev->powerplay.pp_funcs->set_powergating_by_smu)
283
+
if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_powergating_by_smu)
284
284
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GMC, true);
285
285
286
286
}
+4
-2
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+4
-2
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
···
1366
1366
int r;
1367
1367
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1368
1368
1369
-
if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs->set_powergating_by_smu)
1369
+
if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs &&
1370
+
adev->powerplay.pp_funcs->set_powergating_by_smu)
1370
1371
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false);
1371
1372
1372
1373
sdma_v4_0_init_golden_registers(adev);
···
1387
1386
sdma_v4_0_ctx_switch_enable(adev, false);
1388
1387
sdma_v4_0_enable(adev, false);
1389
1388
1390
-
if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs->set_powergating_by_smu)
1389
+
if (adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs
1390
+
&& adev->powerplay.pp_funcs->set_powergating_by_smu)
1391
1391
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true);
1392
1392
1393
1393
return 0;
+7
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+7
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
1524
1524
{
1525
1525
struct amdgpu_display_manager *dm = bl_get_data(bd);
1526
1526
1527
+
/*
1528
+
* PWM interperts 0 as 100% rather than 0% because of HW
1529
+
* limitation for level 0.So limiting minimum brightness level
1530
+
* to 1.
1531
+
*/
1532
+
if (bd->props.brightness < 1)
1533
+
return 1;
1527
1534
if (dc_link_set_backlight_level(dm->backlight_link,
1528
1535
bd->props.brightness, 0, 0))
1529
1536
return 0;
+11
-5
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+11
-5
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
···
101
101
adev->pm.pm_display_cfg.displays[i].controller_id = dc_cfg->pipe_idx + 1;
102
102
}
103
103
104
-
if (adev->powerplay.pp_funcs->display_configuration_change)
104
+
if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->display_configuration_change)
105
105
adev->powerplay.pp_funcs->display_configuration_change(
106
106
adev->powerplay.pp_handle,
107
107
&adev->pm.pm_display_cfg);
···
304
304
struct amd_pp_simple_clock_info validation_clks = { 0 };
305
305
uint32_t i;
306
306
307
-
if (adev->powerplay.pp_funcs->get_clock_by_type) {
307
+
if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_clock_by_type) {
308
308
if (adev->powerplay.pp_funcs->get_clock_by_type(pp_handle,
309
309
dc_to_pp_clock_type(clk_type), &pp_clks)) {
310
310
/* Error in pplib. Provide default values. */
···
315
315
316
316
pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type);
317
317
318
-
if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks) {
318
+
if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_display_mode_validation_clocks) {
319
319
if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks(
320
320
pp_handle, &validation_clks)) {
321
321
/* Error in pplib. Provide default values. */
···
398
398
struct pp_clock_levels_with_voltage pp_clk_info = {0};
399
399
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
400
400
401
+
if (!pp_funcs || !pp_funcs->get_clock_by_type_with_voltage)
402
+
return false;
403
+
401
404
if (pp_funcs->get_clock_by_type_with_voltage(pp_handle,
402
405
dc_to_pp_clock_type(clk_type),
403
406
&pp_clk_info))
···
441
438
if (!pp_clock_request.clock_type)
442
439
return false;
443
440
444
-
if (adev->powerplay.pp_funcs->display_clock_voltage_request)
441
+
if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->display_clock_voltage_request)
445
442
ret = adev->powerplay.pp_funcs->display_clock_voltage_request(
446
443
adev->powerplay.pp_handle,
447
444
&pp_clock_request);
···
458
455
struct amd_pp_clock_info pp_clk_info = {0};
459
456
int ret = 0;
460
457
461
-
if (adev->powerplay.pp_funcs->get_current_clocks)
458
+
if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_current_clocks)
462
459
ret = adev->powerplay.pp_funcs->get_current_clocks(
463
460
adev->powerplay.pp_handle,
464
461
&pp_clk_info);
···
507
504
508
505
wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets;
509
506
wm_with_clock_ranges.num_wm_mcif_sets = ranges->num_writer_wm_sets;
507
+
508
+
if (!pp_funcs || !pp_funcs->set_watermarks_for_clocks_ranges)
509
+
return;
510
510
511
511
for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) {
512
512
if (ranges->reader_wm_sets[i].wm_inst > 3)
+1
-1
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
···
568
568
569
569
static const struct encoder_feature_support link_enc_feature = {
570
570
.max_hdmi_deep_color = COLOR_DEPTH_121212,
571
-
.max_hdmi_pixel_clock = 594000,
571
+
.max_hdmi_pixel_clock = 300000,
572
572
.flags.bits.IS_HBR2_CAPABLE = true,
573
573
.flags.bits.IS_TPS3_CAPABLE = true
574
574
};
+24
-9
drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+24
-9
drivers/gpu/drm/amd/powerplay/amd_powerplay.c
···
723
723
pr_info("%s was not implemented.\n", __func__);
724
724
return 0;
725
725
}
726
+
727
+
if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
728
+
pr_info("force clock level is for dpm manual mode only.\n");
729
+
return -EINVAL;
730
+
}
731
+
726
732
mutex_lock(&hwmgr->smu_lock);
727
-
if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)
728
-
ret = hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
729
-
else
730
-
ret = -EINVAL;
733
+
ret = hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
731
734
mutex_unlock(&hwmgr->smu_lock);
732
735
return ret;
733
736
}
···
966
963
static int pp_set_power_limit(void *handle, uint32_t limit)
967
964
{
968
965
struct pp_hwmgr *hwmgr = handle;
966
+
uint32_t max_power_limit;
969
967
970
968
if (!hwmgr || !hwmgr->pm_en)
971
969
return -EINVAL;
···
979
975
if (limit == 0)
980
976
limit = hwmgr->default_power_limit;
981
977
982
-
if (limit > hwmgr->default_power_limit)
978
+
max_power_limit = hwmgr->default_power_limit;
979
+
if (hwmgr->od_enabled) {
980
+
max_power_limit *= (100 + hwmgr->platform_descriptor.TDPODLimit);
981
+
max_power_limit /= 100;
982
+
}
983
+
984
+
if (limit > max_power_limit)
983
985
return -EINVAL;
984
986
985
987
mutex_lock(&hwmgr->smu_lock);
···
1004
994
1005
995
mutex_lock(&hwmgr->smu_lock);
1006
996
1007
-
if (default_limit)
997
+
if (default_limit) {
1008
998
*limit = hwmgr->default_power_limit;
999
+
if (hwmgr->od_enabled) {
1000
+
*limit *= (100 + hwmgr->platform_descriptor.TDPODLimit);
1001
+
*limit /= 100;
1002
+
}
1003
+
}
1009
1004
else
1010
1005
*limit = hwmgr->power_limit;
1011
1006
···
1318
1303
{
1319
1304
struct pp_hwmgr *hwmgr = handle;
1320
1305
1321
-
if (!hwmgr || !hwmgr->pm_en)
1306
+
if (!hwmgr)
1322
1307
return -EINVAL;
1323
1308
1324
-
if (hwmgr->hwmgr_func->enable_mgpu_fan_boost == NULL) {
1309
+
if (!hwmgr->pm_en ||
1310
+
hwmgr->hwmgr_func->enable_mgpu_fan_boost == NULL)
1325
1311
return 0;
1326
-
}
1327
1312
1328
1313
mutex_lock(&hwmgr->smu_lock);
1329
1314
hwmgr->hwmgr_func->enable_mgpu_fan_boost(hwmgr);
+6
-4
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+6
-4
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
···
3588
3588
break;
3589
3589
}
3590
3590
3591
-
if (i >= sclk_table->count)
3591
+
if (i >= sclk_table->count) {
3592
3592
data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3593
-
else {
3593
+
sclk_table->dpm_levels[i-1].value = sclk;
3594
+
} else {
3594
3595
/* TODO: Check SCLK in DAL's minimum clocks
3595
3596
* in case DeepSleep divider update is required.
3596
3597
*/
···
3606
3605
break;
3607
3606
}
3608
3607
3609
-
if (i >= mclk_table->count)
3608
+
if (i >= mclk_table->count) {
3610
3609
data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3611
-
3610
+
mclk_table->dpm_levels[i-1].value = mclk;
3611
+
}
3612
3612
3613
3613
if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
3614
3614
data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
+1
-1
drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
+1
-1
drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
···
718
718
table->WatermarkRow[1][i].MaxClock =
719
719
cpu_to_le16((uint16_t)
720
720
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz) /
721
-
100);
721
+
1000);
722
722
table->WatermarkRow[1][i].MinUclk =
723
723
cpu_to_le16((uint16_t)
724
724
(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz) /
+39
-4
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+39
-4
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
···
1333
1333
if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0)
1334
1334
hwmgr->platform_descriptor.overdriveLimit.memoryClock =
1335
1335
dpm_table->dpm_levels[dpm_table->count-1].value;
1336
-
1337
1336
vega10_init_dpm_state(&(dpm_table->dpm_state));
1338
1337
1339
1338
data->dpm_table.eclk_table.count = 0;
···
3248
3249
static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
3249
3250
{
3250
3251
struct vega10_hwmgr *data = hwmgr->backend;
3252
+
const struct phm_set_power_state_input *states =
3253
+
(const struct phm_set_power_state_input *)input;
3254
+
const struct vega10_power_state *vega10_ps =
3255
+
cast_const_phw_vega10_power_state(states->pnew_state);
3256
+
struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
3257
+
uint32_t sclk = vega10_ps->performance_levels
3258
+
[vega10_ps->performance_level_count - 1].gfx_clock;
3259
+
struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
3260
+
uint32_t mclk = vega10_ps->performance_levels
3261
+
[vega10_ps->performance_level_count - 1].mem_clock;
3262
+
uint32_t i;
3263
+
3264
+
for (i = 0; i < sclk_table->count; i++) {
3265
+
if (sclk == sclk_table->dpm_levels[i].value)
3266
+
break;
3267
+
}
3268
+
3269
+
if (i >= sclk_table->count) {
3270
+
data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3271
+
sclk_table->dpm_levels[i-1].value = sclk;
3272
+
}
3273
+
3274
+
for (i = 0; i < mclk_table->count; i++) {
3275
+
if (mclk == mclk_table->dpm_levels[i].value)
3276
+
break;
3277
+
}
3278
+
3279
+
if (i >= mclk_table->count) {
3280
+
data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3281
+
mclk_table->dpm_levels[i-1].value = mclk;
3282
+
}
3251
3283
3252
3284
if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
3253
3285
data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK;
···
4559
4529
4560
4530
if (vega10_ps->performance_levels
4561
4531
[vega10_ps->performance_level_count - 1].gfx_clock >
4562
-
hwmgr->platform_descriptor.overdriveLimit.engineClock)
4532
+
hwmgr->platform_descriptor.overdriveLimit.engineClock) {
4563
4533
vega10_ps->performance_levels
4564
4534
[vega10_ps->performance_level_count - 1].gfx_clock =
4565
4535
hwmgr->platform_descriptor.overdriveLimit.engineClock;
4566
-
4536
+
pr_warn("max sclk supported by vbios is %d\n",
4537
+
hwmgr->platform_descriptor.overdriveLimit.engineClock);
4538
+
}
4567
4539
return 0;
4568
4540
}
4569
4541
···
4613
4581
4614
4582
if (vega10_ps->performance_levels
4615
4583
[vega10_ps->performance_level_count - 1].mem_clock >
4616
-
hwmgr->platform_descriptor.overdriveLimit.memoryClock)
4584
+
hwmgr->platform_descriptor.overdriveLimit.memoryClock) {
4617
4585
vega10_ps->performance_levels
4618
4586
[vega10_ps->performance_level_count - 1].mem_clock =
4619
4587
hwmgr->platform_descriptor.overdriveLimit.memoryClock;
4588
+
pr_warn("max mclk supported by vbios is %d\n",
4589
+
hwmgr->platform_descriptor.overdriveLimit.memoryClock);
4590
+
}
4620
4591
4621
4592
return 0;
4622
4593
}
+8
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+8
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
···
2356
2356
return vega12_disable_gfx_off(hwmgr);
2357
2357
}
2358
2358
2359
+
static int vega12_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
2360
+
PHM_PerformanceLevelDesignation designation, uint32_t index,
2361
+
PHM_PerformanceLevel *level)
2362
+
{
2363
+
return 0;
2364
+
}
2365
+
2359
2366
static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
2360
2367
.backend_init = vega12_hwmgr_backend_init,
2361
2368
.backend_fini = vega12_hwmgr_backend_fini,
···
2413
2406
.register_irq_handlers = smu9_register_irq_handlers,
2414
2407
.start_thermal_controller = vega12_start_thermal_controller,
2415
2408
.powergate_gfx = vega12_gfx_off_control,
2409
+
.get_performance_level = vega12_get_performance_level,
2416
2410
};
2417
2411
2418
2412
int vega12_hwmgr_init(struct pp_hwmgr *hwmgr)
+45
-40
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+45
-40
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
···
1875
1875
return ret;
1876
1876
}
1877
1877
1878
-
static int vega20_get_current_gfx_clk_freq(struct pp_hwmgr *hwmgr, uint32_t *gfx_freq)
1878
+
static int vega20_get_current_clk_freq(struct pp_hwmgr *hwmgr,
1879
+
PPCLK_e clk_id, uint32_t *clk_freq)
1879
1880
{
1880
-
uint32_t gfx_clk = 0;
1881
1881
int ret = 0;
1882
1882
1883
-
*gfx_freq = 0;
1883
+
*clk_freq = 0;
1884
1884
1885
1885
PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1886
-
PPSMC_MSG_GetDpmClockFreq, (PPCLK_GFXCLK << 16))) == 0,
1887
-
"[GetCurrentGfxClkFreq] Attempt to get Current GFXCLK Frequency Failed!",
1886
+
PPSMC_MSG_GetDpmClockFreq, (clk_id << 16))) == 0,
1887
+
"[GetCurrentClkFreq] Attempt to get Current Frequency Failed!",
1888
1888
return ret);
1889
-
gfx_clk = smum_get_argument(hwmgr);
1889
+
*clk_freq = smum_get_argument(hwmgr);
1890
1890
1891
-
*gfx_freq = gfx_clk * 100;
1892
-
1893
-
return 0;
1894
-
}
1895
-
1896
-
static int vega20_get_current_mclk_freq(struct pp_hwmgr *hwmgr, uint32_t *mclk_freq)
1897
-
{
1898
-
uint32_t mem_clk = 0;
1899
-
int ret = 0;
1900
-
1901
-
*mclk_freq = 0;
1902
-
1903
-
PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1904
-
PPSMC_MSG_GetDpmClockFreq, (PPCLK_UCLK << 16))) == 0,
1905
-
"[GetCurrentMClkFreq] Attempt to get Current MCLK Frequency Failed!",
1906
-
return ret);
1907
-
mem_clk = smum_get_argument(hwmgr);
1908
-
1909
-
*mclk_freq = mem_clk * 100;
1891
+
*clk_freq = *clk_freq * 100;
1910
1892
1911
1893
return 0;
1912
1894
}
···
1919
1937
1920
1938
switch (idx) {
1921
1939
case AMDGPU_PP_SENSOR_GFX_SCLK:
1922
-
ret = vega20_get_current_gfx_clk_freq(hwmgr, (uint32_t *)value);
1940
+
ret = vega20_get_current_clk_freq(hwmgr,
1941
+
PPCLK_GFXCLK,
1942
+
(uint32_t *)value);
1923
1943
if (!ret)
1924
1944
*size = 4;
1925
1945
break;
1926
1946
case AMDGPU_PP_SENSOR_GFX_MCLK:
1927
-
ret = vega20_get_current_mclk_freq(hwmgr, (uint32_t *)value);
1947
+
ret = vega20_get_current_clk_freq(hwmgr,
1948
+
PPCLK_UCLK,
1949
+
(uint32_t *)value);
1928
1950
if (!ret)
1929
1951
*size = 4;
1930
1952
break;
···
1998
2012
if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
1999
2013
switch (clk_type) {
2000
2014
case amd_pp_dcef_clock:
2001
-
clk_freq = clock_req->clock_freq_in_khz / 100;
2002
2015
clk_select = PPCLK_DCEFCLK;
2003
2016
break;
2004
2017
case amd_pp_disp_clock:
···
2026
2041
return result;
2027
2042
}
2028
2043
2044
+
static int vega20_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
2045
+
PHM_PerformanceLevelDesignation designation, uint32_t index,
2046
+
PHM_PerformanceLevel *level)
2047
+
{
2048
+
return 0;
2049
+
}
2050
+
2029
2051
static int vega20_notify_smc_display_config_after_ps_adjustment(
2030
2052
struct pp_hwmgr *hwmgr)
2031
2053
{
2032
2054
struct vega20_hwmgr *data =
2033
2055
(struct vega20_hwmgr *)(hwmgr->backend);
2056
+
struct vega20_single_dpm_table *dpm_table =
2057
+
&data->dpm_table.mem_table;
2034
2058
struct PP_Clocks min_clocks = {0};
2035
2059
struct pp_display_clock_request clock_req;
2036
2060
int ret = 0;
···
2057
2063
2058
2064
if (data->smu_features[GNLD_DPM_DCEFCLK].supported) {
2059
2065
clock_req.clock_type = amd_pp_dcef_clock;
2060
-
clock_req.clock_freq_in_khz = min_clocks.dcefClock;
2066
+
clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10;
2061
2067
if (!vega20_display_clock_voltage_request(hwmgr, &clock_req)) {
2062
2068
if (data->smu_features[GNLD_DS_DCEFCLK].supported)
2063
2069
PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(
···
2068
2074
} else {
2069
2075
pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
2070
2076
}
2077
+
}
2078
+
2079
+
if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2080
+
dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100;
2081
+
PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2082
+
PPSMC_MSG_SetHardMinByFreq,
2083
+
(PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
2084
+
"[SetHardMinFreq] Set hard min uclk failed!",
2085
+
return ret);
2071
2086
}
2072
2087
2073
2088
return 0;
···
2356
2353
2357
2354
for (i = 0; i < count; i++) {
2358
2355
clocks->data[i].clocks_in_khz =
2359
-
dpm_table->dpm_levels[i].value * 100;
2356
+
dpm_table->dpm_levels[i].value * 1000;
2360
2357
clocks->data[i].latency_in_us = 0;
2361
2358
}
2362
2359
···
2386
2383
for (i = 0; i < count; i++) {
2387
2384
clocks->data[i].clocks_in_khz =
2388
2385
data->mclk_latency_table.entries[i].frequency =
2389
-
dpm_table->dpm_levels[i].value * 100;
2386
+
dpm_table->dpm_levels[i].value * 1000;
2390
2387
clocks->data[i].latency_in_us =
2391
2388
data->mclk_latency_table.entries[i].latency =
2392
2389
vega20_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value);
···
2411
2408
2412
2409
for (i = 0; i < count; i++) {
2413
2410
clocks->data[i].clocks_in_khz =
2414
-
dpm_table->dpm_levels[i].value * 100;
2411
+
dpm_table->dpm_levels[i].value * 1000;
2415
2412
clocks->data[i].latency_in_us = 0;
2416
2413
}
2417
2414
···
2434
2431
2435
2432
for (i = 0; i < count; i++) {
2436
2433
clocks->data[i].clocks_in_khz =
2437
-
dpm_table->dpm_levels[i].value * 100;
2434
+
dpm_table->dpm_levels[i].value * 1000;
2438
2435
clocks->data[i].latency_in_us = 0;
2439
2436
}
2440
2437
···
2585
2582
return -EINVAL;
2586
2583
}
2587
2584
2588
-
if (input_clk < clocks.data[0].clocks_in_khz / 100 ||
2585
+
if (input_clk < clocks.data[0].clocks_in_khz / 1000 ||
2589
2586
input_clk > od8_settings[OD8_SETTING_UCLK_FMAX].max_value) {
2590
2587
pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2591
2588
input_clk,
2592
-
clocks.data[0].clocks_in_khz / 100,
2589
+
clocks.data[0].clocks_in_khz / 1000,
2593
2590
od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
2594
2591
return -EINVAL;
2595
2592
}
···
2729
2726
2730
2727
switch (type) {
2731
2728
case PP_SCLK:
2732
-
ret = vega20_get_current_gfx_clk_freq(hwmgr, &now);
2729
+
ret = vega20_get_current_clk_freq(hwmgr, PPCLK_GFXCLK, &now);
2733
2730
PP_ASSERT_WITH_CODE(!ret,
2734
2731
"Attempt to get current gfx clk Failed!",
2735
2732
return ret);
···
2741
2738
2742
2739
for (i = 0; i < clocks.num_levels; i++)
2743
2740
size += sprintf(buf + size, "%d: %uMhz %s\n",
2744
-
i, clocks.data[i].clocks_in_khz / 100,
2741
+
i, clocks.data[i].clocks_in_khz / 1000,
2745
2742
(clocks.data[i].clocks_in_khz == now) ? "*" : "");
2746
2743
break;
2747
2744
2748
2745
case PP_MCLK:
2749
-
ret = vega20_get_current_mclk_freq(hwmgr, &now);
2746
+
ret = vega20_get_current_clk_freq(hwmgr, PPCLK_UCLK, &now);
2750
2747
PP_ASSERT_WITH_CODE(!ret,
2751
2748
"Attempt to get current mclk freq Failed!",
2752
2749
return ret);
···
2758
2755
2759
2756
for (i = 0; i < clocks.num_levels; i++)
2760
2757
size += sprintf(buf + size, "%d: %uMhz %s\n",
2761
-
i, clocks.data[i].clocks_in_khz / 100,
2758
+
i, clocks.data[i].clocks_in_khz / 1000,
2762
2759
(clocks.data[i].clocks_in_khz == now) ? "*" : "");
2763
2760
break;
2764
2761
···
2823
2820
return ret);
2824
2821
2825
2822
size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
2826
-
clocks.data[0].clocks_in_khz / 100,
2823
+
clocks.data[0].clocks_in_khz / 1000,
2827
2824
od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
2828
2825
}
2829
2826
···
3479
3476
vega20_set_watermarks_for_clocks_ranges,
3480
3477
.display_clock_voltage_request =
3481
3478
vega20_display_clock_voltage_request,
3479
+
.get_performance_level =
3480
+
vega20_get_performance_level,
3482
3481
/* UMD pstate, profile related */
3483
3482
.force_dpm_level =
3484
3483
vega20_dpm_force_dpm_level,
+25
-31
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c
+25
-31
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c
···
642
642
"Unsupported PPTable format!", return -1);
643
643
PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0,
644
644
"Invalid PowerPlay Table!", return -1);
645
-
PP_ASSERT_WITH_CODE(powerplay_table->smcPPTable.Version == PPTABLE_V20_SMU_VERSION,
646
-
"Unmatch PPTable version, vbios update may be needed!", return -1);
645
+
646
+
if (powerplay_table->smcPPTable.Version != PPTABLE_V20_SMU_VERSION) {
647
+
pr_info("Unmatch PPTable version: "
648
+
"pptable from VBIOS is V%d while driver supported is V%d!",
649
+
powerplay_table->smcPPTable.Version,
650
+
PPTABLE_V20_SMU_VERSION);
651
+
return -EINVAL;
652
+
}
647
653
648
654
//dump_pptable(&powerplay_table->smcPPTable);
649
655
···
722
716
"[appendVbiosPPTable] Failed to retrieve Smc Dpm Table from VBIOS!",
723
717
return -1);
724
718
725
-
memset(ppsmc_pptable->Padding32,
726
-
0,
727
-
sizeof(struct atom_smc_dpm_info_v4_4) -
728
-
sizeof(struct atom_common_table_header));
729
719
ppsmc_pptable->MaxVoltageStepGfx = smc_dpm_table->maxvoltagestepgfx;
730
720
ppsmc_pptable->MaxVoltageStepSoc = smc_dpm_table->maxvoltagestepsoc;
731
721
···
780
778
ppsmc_pptable->FllGfxclkSpreadPercent = smc_dpm_table->fllgfxclkspreadpercent;
781
779
ppsmc_pptable->FllGfxclkSpreadFreq = smc_dpm_table->fllgfxclkspreadfreq;
782
780
783
-
if ((smc_dpm_table->table_header.format_revision == 4) &&
784
-
(smc_dpm_table->table_header.content_revision == 4)) {
785
-
for (i = 0; i < I2C_CONTROLLER_NAME_COUNT; i++) {
786
-
ppsmc_pptable->I2cControllers[i].Enabled =
787
-
smc_dpm_table->i2ccontrollers[i].enabled;
788
-
ppsmc_pptable->I2cControllers[i].SlaveAddress =
789
-
smc_dpm_table->i2ccontrollers[i].slaveaddress;
790
-
ppsmc_pptable->I2cControllers[i].ControllerPort =
791
-
smc_dpm_table->i2ccontrollers[i].controllerport;
792
-
ppsmc_pptable->I2cControllers[i].ThermalThrottler =
793
-
smc_dpm_table->i2ccontrollers[i].thermalthrottler;
794
-
ppsmc_pptable->I2cControllers[i].I2cProtocol =
795
-
smc_dpm_table->i2ccontrollers[i].i2cprotocol;
796
-
ppsmc_pptable->I2cControllers[i].I2cSpeed =
797
-
smc_dpm_table->i2ccontrollers[i].i2cspeed;
798
-
}
781
+
for (i = 0; i < I2C_CONTROLLER_NAME_COUNT; i++) {
782
+
ppsmc_pptable->I2cControllers[i].Enabled =
783
+
smc_dpm_table->i2ccontrollers[i].enabled;
784
+
ppsmc_pptable->I2cControllers[i].SlaveAddress =
785
+
smc_dpm_table->i2ccontrollers[i].slaveaddress;
786
+
ppsmc_pptable->I2cControllers[i].ControllerPort =
787
+
smc_dpm_table->i2ccontrollers[i].controllerport;
788
+
ppsmc_pptable->I2cControllers[i].ThermalThrottler =
789
+
smc_dpm_table->i2ccontrollers[i].thermalthrottler;
790
+
ppsmc_pptable->I2cControllers[i].I2cProtocol =
791
+
smc_dpm_table->i2ccontrollers[i].i2cprotocol;
792
+
ppsmc_pptable->I2cControllers[i].I2cSpeed =
793
+
smc_dpm_table->i2ccontrollers[i].i2cspeed;
799
794
}
800
795
801
796
return 0;
···
881
882
if (pptable_information->smc_pptable == NULL)
882
883
return -ENOMEM;
883
884
884
-
if (powerplay_table->smcPPTable.Version <= 2)
885
-
memcpy(pptable_information->smc_pptable,
886
-
&(powerplay_table->smcPPTable),
887
-
sizeof(PPTable_t) -
888
-
sizeof(I2cControllerConfig_t) * I2C_CONTROLLER_NAME_COUNT);
889
-
else
890
-
memcpy(pptable_information->smc_pptable,
891
-
&(powerplay_table->smcPPTable),
892
-
sizeof(PPTable_t));
885
+
memcpy(pptable_information->smc_pptable,
886
+
&(powerplay_table->smcPPTable),
887
+
sizeof(PPTable_t));
888
+
893
889
894
890
result = append_vbios_pptable(hwmgr, (pptable_information->smc_pptable));
895
891
+1
-1
drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
+1
-1
drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
+4
drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
+4
drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
···
71
71
result = PHM_WAIT_FIELD_UNEQUAL(hwmgr,
72
72
SMU_MP1_SRBM2P_RESP_0, CONTENT, 0);
73
73
if (result != 0) {
74
+
/* Read the last message to SMU, to report actual cause */
75
+
uint32_t val = cgs_read_register(hwmgr->device,
76
+
mmSMU_MP1_SRBM2P_MSG_0);
74
77
pr_err("smu8_send_msg_to_smc_async (0x%04x) failed\n", msg);
78
+
pr_err("SMU still servicing msg (0x%04x)\n", val);
75
79
return result;
76
80
}
77
81
+16
-13
drivers/gpu/drm/bridge/ti-sn65dsi86.c
+16
-13
drivers/gpu/drm/bridge/ti-sn65dsi86.c
···
458
458
unsigned int val;
459
459
int ret;
460
460
461
-
/*
462
-
* FIXME:
463
-
* This 70ms was found necessary by experimentation. If it's not
464
-
* present, link training fails. It seems like it can go anywhere from
465
-
* pre_enable() up to semi-auto link training initiation below.
466
-
*
467
-
* Neither the datasheet for the bridge nor the panel tested mention a
468
-
* delay of this magnitude in the timing requirements. So for now, add
469
-
* the mystery delay until someone figures out a better fix.
470
-
*/
471
-
msleep(70);
472
-
473
461
/* DSI_A lane config */
474
462
val = CHA_DSI_LANES(4 - pdata->dsi->lanes);
475
463
regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
···
524
536
/* configure bridge ref_clk */
525
537
ti_sn_bridge_set_refclk_freq(pdata);
526
538
527
-
/* in case drm_panel is connected then HPD is not supported */
539
+
/*
540
+
* HPD on this bridge chip is a bit useless. This is an eDP bridge
541
+
* so the HPD is an internal signal that's only there to signal that
542
+
* the panel is done powering up. ...but the bridge chip debounces
543
+
* this signal by between 100 ms and 400 ms (depending on process,
544
+
* voltage, and temperate--I measured it at about 200 ms). One
545
+
* particular panel asserted HPD 84 ms after it was powered on meaning
546
+
* that we saw HPD 284 ms after power on. ...but the same panel said
547
+
* that instead of looking at HPD you could just hardcode a delay of
548
+
* 200 ms. We'll assume that the panel driver will have the hardcoded
549
+
* delay in its prepare and always disable HPD.
550
+
*
551
+
* If HPD somehow makes sense on some future panel we'll have to
552
+
* change this to be conditional on someone specifying that HPD should
553
+
* be used.
554
+
*/
528
555
regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE,
529
556
HPD_DISABLE);
530
557
+20
-1
drivers/gpu/drm/drm_atomic_helper.c
+20
-1
drivers/gpu/drm/drm_atomic_helper.c
···
308
308
return 0;
309
309
}
310
310
311
+
crtc_state = drm_atomic_get_new_crtc_state(state,
312
+
new_connector_state->crtc);
313
+
/*
314
+
* For compatibility with legacy users, we want to make sure that
315
+
* we allow DPMS On->Off modesets on unregistered connectors. Modesets
316
+
* which would result in anything else must be considered invalid, to
317
+
* avoid turning on new displays on dead connectors.
318
+
*
319
+
* Since the connector can be unregistered at any point during an
320
+
* atomic check or commit, this is racy. But that's OK: all we care
321
+
* about is ensuring that userspace can't do anything but shut off the
322
+
* display on a connector that was destroyed after its been notified,
323
+
* not before.
324
+
*/
325
+
if (drm_connector_is_unregistered(connector) && crtc_state->active) {
326
+
DRM_DEBUG_ATOMIC("[CONNECTOR:%d:%s] is not registered\n",
327
+
connector->base.id, connector->name);
328
+
return -EINVAL;
329
+
}
330
+
311
331
funcs = connector->helper_private;
312
332
313
333
if (funcs->atomic_best_encoder)
···
372
352
373
353
set_best_encoder(state, new_connector_state, new_encoder);
374
354
375
-
crtc_state = drm_atomic_get_new_crtc_state(state, new_connector_state->crtc);
376
355
crtc_state->connectors_changed = true;
377
356
378
357
DRM_DEBUG_ATOMIC("[CONNECTOR:%d:%s] using [ENCODER:%d:%s] on [CRTC:%d:%s]\n",
+6
-5
drivers/gpu/drm/drm_connector.c
+6
-5
drivers/gpu/drm/drm_connector.c
···
379
379
/* The connector should have been removed from userspace long before
380
380
* it is finally destroyed.
381
381
*/
382
-
if (WARN_ON(connector->registered))
382
+
if (WARN_ON(connector->registration_state ==
383
+
DRM_CONNECTOR_REGISTERED))
383
384
drm_connector_unregister(connector);
384
385
385
386
if (connector->tile_group) {
···
437
436
return 0;
438
437
439
438
mutex_lock(&connector->mutex);
440
-
if (connector->registered)
439
+
if (connector->registration_state != DRM_CONNECTOR_INITIALIZING)
441
440
goto unlock;
442
441
443
442
ret = drm_sysfs_connector_add(connector);
···
457
456
458
457
drm_mode_object_register(connector->dev, &connector->base);
459
458
460
-
connector->registered = true;
459
+
connector->registration_state = DRM_CONNECTOR_REGISTERED;
461
460
goto unlock;
462
461
463
462
err_debugfs:
···
479
478
void drm_connector_unregister(struct drm_connector *connector)
480
479
{
481
480
mutex_lock(&connector->mutex);
482
-
if (!connector->registered) {
481
+
if (connector->registration_state != DRM_CONNECTOR_REGISTERED) {
483
482
mutex_unlock(&connector->mutex);
484
483
return;
485
484
}
···
490
489
drm_sysfs_connector_remove(connector);
491
490
drm_debugfs_connector_remove(connector);
492
491
493
-
connector->registered = false;
492
+
connector->registration_state = DRM_CONNECTOR_UNREGISTERED;
494
493
mutex_unlock(&connector->mutex);
495
494
}
496
495
EXPORT_SYMBOL(drm_connector_unregister);
+3
drivers/gpu/drm/drm_edid.c
+3
drivers/gpu/drm/drm_edid.c
···
122
122
/* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
123
123
{ "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
124
124
125
+
/* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
126
+
{ "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC },
127
+
125
128
/* Belinea 10 15 55 */
126
129
{ "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
127
130
{ "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
+7
-13
drivers/gpu/drm/i915/intel_dp.c
+7
-13
drivers/gpu/drm/i915/intel_dp.c
···
5102
5102
*/
5103
5103
status = connector_status_disconnected;
5104
5104
goto out;
5105
-
} else {
5106
-
/*
5107
-
* If display is now connected check links status,
5108
-
* there has been known issues of link loss triggering
5109
-
* long pulse.
5110
-
*
5111
-
* Some sinks (eg. ASUS PB287Q) seem to perform some
5112
-
* weird HPD ping pong during modesets. So we can apparently
5113
-
* end up with HPD going low during a modeset, and then
5114
-
* going back up soon after. And once that happens we must
5115
-
* retrain the link to get a picture. That's in case no
5116
-
* userspace component reacted to intermittent HPD dip.
5117
-
*/
5105
+
}
5106
+
5107
+
/*
5108
+
* Some external monitors do not signal loss of link synchronization
5109
+
* with an IRQ_HPD, so force a link status check.
5110
+
*/
5111
+
if (!intel_dp_is_edp(intel_dp)) {
5118
5112
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5119
5113
5120
5114
intel_dp_retrain_link(encoder, ctx);
+4
-4
drivers/gpu/drm/i915/intel_dp_mst.c
+4
-4
drivers/gpu/drm/i915/intel_dp_mst.c
···
77
77
pipe_config->pbn = mst_pbn;
78
78
79
79
/* Zombie connectors can't have VCPI slots */
80
-
if (READ_ONCE(connector->registered)) {
80
+
if (!drm_connector_is_unregistered(connector)) {
81
81
slots = drm_dp_atomic_find_vcpi_slots(state,
82
82
&intel_dp->mst_mgr,
83
83
port,
···
313
313
struct edid *edid;
314
314
int ret;
315
315
316
-
if (!READ_ONCE(connector->registered))
316
+
if (drm_connector_is_unregistered(connector))
317
317
return intel_connector_update_modes(connector, NULL);
318
318
319
319
edid = drm_dp_mst_get_edid(connector, &intel_dp->mst_mgr, intel_connector->port);
···
329
329
struct intel_connector *intel_connector = to_intel_connector(connector);
330
330
struct intel_dp *intel_dp = intel_connector->mst_port;
331
331
332
-
if (!READ_ONCE(connector->registered))
332
+
if (drm_connector_is_unregistered(connector))
333
333
return connector_status_disconnected;
334
334
return drm_dp_mst_detect_port(connector, &intel_dp->mst_mgr,
335
335
intel_connector->port);
···
372
372
int bpp = 24; /* MST uses fixed bpp */
373
373
int max_rate, mode_rate, max_lanes, max_link_clock;
374
374
375
-
if (!READ_ONCE(connector->registered))
375
+
if (drm_connector_is_unregistered(connector))
376
376
return MODE_ERROR;
377
377
378
378
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
+4
-10
drivers/gpu/drm/nouveau/dispnv50/disp.c
+4
-10
drivers/gpu/drm/nouveau/dispnv50/disp.c
···
881
881
{
882
882
struct nv50_head *head = nv50_head(connector_state->crtc);
883
883
struct nv50_mstc *mstc = nv50_mstc(connector);
884
-
if (mstc->port) {
885
-
struct nv50_mstm *mstm = mstc->mstm;
886
-
return &mstm->msto[head->base.index]->encoder;
887
-
}
888
-
return NULL;
884
+
885
+
return &mstc->mstm->msto[head->base.index]->encoder;
889
886
}
890
887
891
888
static struct drm_encoder *
892
889
nv50_mstc_best_encoder(struct drm_connector *connector)
893
890
{
894
891
struct nv50_mstc *mstc = nv50_mstc(connector);
895
-
if (mstc->port) {
896
-
struct nv50_mstm *mstm = mstc->mstm;
897
-
return &mstm->msto[0]->encoder;
898
-
}
899
-
return NULL;
892
+
893
+
return &mstc->mstm->msto[0]->encoder;
900
894
}
901
895
902
896
static enum drm_mode_status
+20
-9
drivers/gpu/drm/panel/panel-simple.c
+20
-9
drivers/gpu/drm/panel/panel-simple.c
···
56
56
/**
57
57
* @prepare: the time (in milliseconds) that it takes for the panel to
58
58
* become ready and start receiving video data
59
+
* @hpd_absent_delay: Add this to the prepare delay if we know Hot
60
+
* Plug Detect isn't used.
59
61
* @enable: the time (in milliseconds) that it takes for the panel to
60
62
* display the first valid frame after starting to receive
61
63
* video data
···
68
66
*/
69
67
struct {
70
68
unsigned int prepare;
69
+
unsigned int hpd_absent_delay;
71
70
unsigned int enable;
72
71
unsigned int disable;
73
72
unsigned int unprepare;
···
82
79
struct drm_panel base;
83
80
bool prepared;
84
81
bool enabled;
82
+
bool no_hpd;
85
83
86
84
const struct panel_desc *desc;
87
85
···
206
202
static int panel_simple_prepare(struct drm_panel *panel)
207
203
{
208
204
struct panel_simple *p = to_panel_simple(panel);
205
+
unsigned int delay;
209
206
int err;
210
207
211
208
if (p->prepared)
···
220
215
221
216
gpiod_set_value_cansleep(p->enable_gpio, 1);
222
217
223
-
if (p->desc->delay.prepare)
224
-
msleep(p->desc->delay.prepare);
218
+
delay = p->desc->delay.prepare;
219
+
if (p->no_hpd)
220
+
delay += p->desc->delay.hpd_absent_delay;
221
+
if (delay)
222
+
msleep(delay);
225
223
226
224
p->prepared = true;
227
225
···
312
304
panel->enabled = false;
313
305
panel->prepared = false;
314
306
panel->desc = desc;
307
+
308
+
panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
315
309
316
310
panel->supply = devm_regulator_get(dev, "power");
317
311
if (IS_ERR(panel->supply))
···
1373
1363
},
1374
1364
};
1375
1365
1376
-
static const struct drm_display_mode innolux_tv123wam_mode = {
1366
+
static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
1377
1367
.clock = 206016,
1378
1368
.hdisplay = 2160,
1379
1369
.hsync_start = 2160 + 48,
···
1387
1377
.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
1388
1378
};
1389
1379
1390
-
static const struct panel_desc innolux_tv123wam = {
1391
-
.modes = &innolux_tv123wam_mode,
1380
+
static const struct panel_desc innolux_p120zdg_bf1 = {
1381
+
.modes = &innolux_p120zdg_bf1_mode,
1392
1382
.num_modes = 1,
1393
1383
.bpc = 8,
1394
1384
.size = {
1395
-
.width = 259,
1396
-
.height = 173,
1385
+
.width = 254,
1386
+
.height = 169,
1397
1387
},
1398
1388
.delay = {
1389
+
.hpd_absent_delay = 200,
1399
1390
.unprepare = 500,
1400
1391
},
1401
1392
};
···
2456
2445
.compatible = "innolux,n156bge-l21",
2457
2446
.data = &innolux_n156bge_l21,
2458
2447
}, {
2459
-
.compatible = "innolux,tv123wam",
2460
-
.data = &innolux_tv123wam,
2448
+
.compatible = "innolux,p120zdg-bf1",
2449
+
.data = &innolux_p120zdg_bf1,
2461
2450
}, {
2462
2451
.compatible = "innolux,zj070na-01p",
2463
2452
.data = &innolux_zj070na_01p,
+69
-2
include/drm/drm_connector.h
+69
-2
include/drm/drm_connector.h
···
82
82
connector_status_unknown = 3,
83
83
};
84
84
85
+
/**
86
+
* enum drm_connector_registration_status - userspace registration status for
87
+
* a &drm_connector
88
+
*
89
+
* This enum is used to track the status of initializing a connector and
90
+
* registering it with userspace, so that DRM can prevent bogus modesets on
91
+
* connectors that no longer exist.
92
+
*/
93
+
enum drm_connector_registration_state {
94
+
/**
95
+
* @DRM_CONNECTOR_INITIALIZING: The connector has just been created,
96
+
* but has yet to be exposed to userspace. There should be no
97
+
* additional restrictions to how the state of this connector may be
98
+
* modified.
99
+
*/
100
+
DRM_CONNECTOR_INITIALIZING = 0,
101
+
102
+
/**
103
+
* @DRM_CONNECTOR_REGISTERED: The connector has been fully initialized
104
+
* and registered with sysfs, as such it has been exposed to
105
+
* userspace. There should be no additional restrictions to how the
106
+
* state of this connector may be modified.
107
+
*/
108
+
DRM_CONNECTOR_REGISTERED = 1,
109
+
110
+
/**
111
+
* @DRM_CONNECTOR_UNREGISTERED: The connector has either been exposed
112
+
* to userspace and has since been unregistered and removed from
113
+
* userspace, or the connector was unregistered before it had a chance
114
+
* to be exposed to userspace (e.g. still in the
115
+
* @DRM_CONNECTOR_INITIALIZING state). When a connector is
116
+
* unregistered, there are additional restrictions to how its state
117
+
* may be modified:
118
+
*
119
+
* - An unregistered connector may only have its DPMS changed from
120
+
* On->Off. Once DPMS is changed to Off, it may not be switched back
121
+
* to On.
122
+
* - Modesets are not allowed on unregistered connectors, unless they
123
+
* would result in disabling its assigned CRTCs. This means
124
+
* disabling a CRTC on an unregistered connector is OK, but enabling
125
+
* one is not.
126
+
* - Removing a CRTC from an unregistered connector is OK, but new
127
+
* CRTCs may never be assigned to an unregistered connector.
128
+
*/
129
+
DRM_CONNECTOR_UNREGISTERED = 2,
130
+
};
131
+
85
132
enum subpixel_order {
86
133
SubPixelUnknown = 0,
87
134
SubPixelHorizontalRGB,
···
900
853
bool ycbcr_420_allowed;
901
854
902
855
/**
903
-
* @registered: Is this connector exposed (registered) with userspace?
856
+
* @registration_state: Is this connector initializing, exposed
857
+
* (registered) with userspace, or unregistered?
858
+
*
904
859
* Protected by @mutex.
905
860
*/
906
-
bool registered;
861
+
enum drm_connector_registration_state registration_state;
907
862
908
863
/**
909
864
* @modes:
···
1213
1164
static inline void drm_connector_unreference(struct drm_connector *connector)
1214
1165
{
1215
1166
drm_connector_put(connector);
1167
+
}
1168
+
1169
+
/**
1170
+
* drm_connector_is_unregistered - has the connector been unregistered from
1171
+
* userspace?
1172
+
* @connector: DRM connector
1173
+
*
1174
+
* Checks whether or not @connector has been unregistered from userspace.
1175
+
*
1176
+
* Returns:
1177
+
* True if the connector was unregistered, false if the connector is
1178
+
* registered or has not yet been registered with userspace.
1179
+
*/
1180
+
static inline bool
1181
+
drm_connector_is_unregistered(struct drm_connector *connector)
1182
+
{
1183
+
return READ_ONCE(connector->registration_state) ==
1184
+
DRM_CONNECTOR_UNREGISTERED;
1216
1185
}
1217
1186
1218
1187
const char *drm_get_connector_status_name(enum drm_connector_status status);