tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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crypto: qat - add pfvf_ops

Add pfvf_ops structure to isolate PFVF related functions inside the
adf_hw_device_data structure.

For GEN2, the structure is populated using one of the two helper
functions, adf_gen2_init_pf_pfvf_ops() or adf_gen2_init_vf_pfvf_ops(),
for the PF and VF driver respectively.

For the DH895XCC PF driver, the structure is populated using
adf_gen2_init_pf_pfvf_ops() but some of the functions are then
overwritten.

Signed-off-by: Marco Chiappero <marco.chiappero@intel.com>
Co-developed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

authored by

Marco Chiappero and committed by
Herbert Xu bc63dabe 6f2e2801

+76 -61
+2 -2
drivers/crypto/qat/qat_4xxx/adf_4xxx_hw_data.c
··· 254 254 hw_data->uof_get_ae_mask = uof_get_ae_mask; 255 255 hw_data->set_msix_rttable = set_msix_default_rttable; 256 256 hw_data->set_ssm_wdtimer = adf_gen4_set_ssm_wdtimer; 257 - hw_data->enable_pfvf_comms = adf_pfvf_comms_disabled; 258 - hw_data->get_vf2pf_sources = get_vf2pf_sources; 257 + hw_data->pfvf_ops.enable_comms = adf_pfvf_comms_disabled; 258 + hw_data->pfvf_ops.get_vf2pf_sources = get_vf2pf_sources; 259 259 hw_data->disable_iov = adf_disable_sriov; 260 260 hw_data->min_iov_compat_ver = ADF_PFVF_COMPAT_THIS_VERSION; 261 261
+1 -5
drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c
··· 136 136 hw_data->enable_ints = adf_enable_ints; 137 137 hw_data->reset_device = adf_reset_flr; 138 138 hw_data->set_ssm_wdtimer = adf_gen2_set_ssm_wdtimer; 139 - hw_data->get_pf2vf_offset = adf_gen2_pf_get_pf2vf_offset; 140 - hw_data->get_vf2pf_sources = adf_gen2_get_vf2pf_sources; 141 - hw_data->enable_vf2pf_interrupts = adf_gen2_enable_vf2pf_interrupts; 142 - hw_data->disable_vf2pf_interrupts = adf_gen2_disable_vf2pf_interrupts; 143 - hw_data->enable_pfvf_comms = adf_enable_pf2vf_comms; 144 139 hw_data->disable_iov = adf_disable_sriov; 145 140 hw_data->min_iov_compat_ver = ADF_PFVF_COMPAT_THIS_VERSION; 146 141 142 + adf_gen2_init_pf_pfvf_ops(&hw_data->pfvf_ops); 147 143 adf_gen2_init_hw_csr_ops(&hw_data->csr_ops); 148 144 } 149 145
+1 -2
drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c
··· 82 82 hw_data->get_num_aes = get_num_aes; 83 83 hw_data->get_etr_bar_id = get_etr_bar_id; 84 84 hw_data->get_misc_bar_id = get_misc_bar_id; 85 - hw_data->get_pf2vf_offset = adf_gen2_vf_get_pf2vf_offset; 86 85 hw_data->get_sku = get_sku; 87 86 hw_data->enable_ints = adf_vf_void_noop; 88 - hw_data->enable_pfvf_comms = adf_enable_vf2pf_comms; 89 87 hw_data->min_iov_compat_ver = ADF_PFVF_COMPAT_THIS_VERSION; 90 88 hw_data->dev_class->instances++; 91 89 adf_devmgr_update_class_index(hw_data); 90 + adf_gen2_init_vf_pfvf_ops(&hw_data->pfvf_ops); 92 91 adf_gen2_init_hw_csr_ops(&hw_data->csr_ops); 93 92 } 94 93
+1 -5
drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c
··· 138 138 hw_data->enable_ints = adf_enable_ints; 139 139 hw_data->reset_device = adf_reset_flr; 140 140 hw_data->set_ssm_wdtimer = adf_gen2_set_ssm_wdtimer; 141 - hw_data->get_pf2vf_offset = adf_gen2_pf_get_pf2vf_offset; 142 - hw_data->get_vf2pf_sources = adf_gen2_get_vf2pf_sources; 143 - hw_data->enable_vf2pf_interrupts = adf_gen2_enable_vf2pf_interrupts; 144 - hw_data->disable_vf2pf_interrupts = adf_gen2_disable_vf2pf_interrupts; 145 - hw_data->enable_pfvf_comms = adf_enable_pf2vf_comms; 146 141 hw_data->disable_iov = adf_disable_sriov; 147 142 hw_data->min_iov_compat_ver = ADF_PFVF_COMPAT_THIS_VERSION; 148 143 144 + adf_gen2_init_pf_pfvf_ops(&hw_data->pfvf_ops); 149 145 adf_gen2_init_hw_csr_ops(&hw_data->csr_ops); 150 146 } 151 147
+1 -2
drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c
··· 82 82 hw_data->get_num_aes = get_num_aes; 83 83 hw_data->get_etr_bar_id = get_etr_bar_id; 84 84 hw_data->get_misc_bar_id = get_misc_bar_id; 85 - hw_data->get_pf2vf_offset = adf_gen2_vf_get_pf2vf_offset; 86 85 hw_data->get_sku = get_sku; 87 86 hw_data->enable_ints = adf_vf_void_noop; 88 - hw_data->enable_pfvf_comms = adf_enable_vf2pf_comms; 89 87 hw_data->min_iov_compat_ver = ADF_PFVF_COMPAT_THIS_VERSION; 90 88 hw_data->dev_class->instances++; 91 89 adf_devmgr_update_class_index(hw_data); 90 + adf_gen2_init_vf_pfvf_ops(&hw_data->pfvf_ops); 92 91 adf_gen2_init_hw_csr_ops(&hw_data->csr_ops); 93 92 } 94 93
+3 -3
drivers/crypto/qat/qat_common/Makefile
··· 16 16 qat_algs.o \ 17 17 qat_asym_algs.o \ 18 18 qat_uclo.o \ 19 - qat_hal.o \ 20 - adf_gen2_pfvf.o 19 + qat_hal.o 21 20 22 21 intel_qat-$(CONFIG_DEBUG_FS) += adf_transport_debug.o 23 22 intel_qat-$(CONFIG_PCI_IOV) += adf_sriov.o adf_pf2vf_msg.o \ 24 - adf_vf2pf_msg.o adf_vf_isr.o 23 + adf_vf2pf_msg.o adf_vf_isr.o \ 24 + adf_gen2_pfvf.o
+10 -7
drivers/crypto/qat/qat_common/adf_accel_devices.h
··· 147 147 struct adf_etr_data; 148 148 struct adf_etr_ring_data; 149 149 150 + struct adf_pfvf_ops { 151 + int (*enable_comms)(struct adf_accel_dev *accel_dev); 152 + u32 (*get_pf2vf_offset)(u32 i); 153 + u32 (*get_vf2pf_sources)(void __iomem *pmisc_addr); 154 + void (*enable_vf2pf_interrupts)(void __iomem *pmisc_addr, u32 vf_mask); 155 + void (*disable_vf2pf_interrupts)(void __iomem *pmisc_addr, u32 vf_mask); 156 + }; 157 + 150 158 struct adf_hw_device_data { 151 159 struct adf_hw_device_class *dev_class; 152 160 u32 (*get_accel_mask)(struct adf_hw_device_data *self); ··· 165 157 u32 (*get_etr_bar_id)(struct adf_hw_device_data *self); 166 158 u32 (*get_num_aes)(struct adf_hw_device_data *self); 167 159 u32 (*get_num_accels)(struct adf_hw_device_data *self); 168 - u32 (*get_pf2vf_offset)(u32 i); 169 160 void (*get_arb_info)(struct arb_info *arb_csrs_info); 170 161 void (*get_admin_info)(struct admin_info *admin_csrs_info); 171 162 enum dev_sku_info (*get_sku)(struct adf_hw_device_data *self); ··· 183 176 bool enable); 184 177 void (*enable_ints)(struct adf_accel_dev *accel_dev); 185 178 void (*set_ssm_wdtimer)(struct adf_accel_dev *accel_dev); 186 - int (*enable_pfvf_comms)(struct adf_accel_dev *accel_dev); 187 - u32 (*get_vf2pf_sources)(void __iomem *pmisc_addr); 188 - void (*enable_vf2pf_interrupts)(void __iomem *pmisc_bar_addr, 189 - u32 vf_mask); 190 - void (*disable_vf2pf_interrupts)(void __iomem *pmisc_bar_addr, 191 - u32 vf_mask); 192 179 void (*reset_device)(struct adf_accel_dev *accel_dev); 193 180 void (*set_msix_rttable)(struct adf_accel_dev *accel_dev); 194 181 char *(*uof_get_name)(u32 obj_num); 195 182 u32 (*uof_get_num_objs)(void); 196 183 u32 (*uof_get_ae_mask)(u32 obj_num); 184 + struct adf_pfvf_ops pfvf_ops; 197 185 struct adf_hw_csr_ops csr_ops; 198 186 const char *fw_name; 199 187 const char *fw_mmp_name; ··· 224 222 GET_HW_DATA(accel_dev)->num_rings_per_bank 225 223 #define GET_MAX_ACCELENGINES(accel_dev) (GET_HW_DATA(accel_dev)->num_engines) 226 224 #define GET_CSR_OPS(accel_dev) (&(accel_dev)->hw_device->csr_ops) 225 + #define GET_PFVF_OPS(accel_dev) (&(accel_dev)->hw_device->pfvf_ops) 227 226 #define accel_to_pci_dev(accel_ptr) accel_ptr->accel_pci_dev.pci_dev 228 227 229 228 struct adf_admin_comms;
+25 -10
drivers/crypto/qat/qat_common/adf_gen2_pfvf.c
··· 2 2 /* Copyright(c) 2021 Intel Corporation */ 3 3 #include <linux/types.h> 4 4 #include "adf_accel_devices.h" 5 + #include "adf_common_drv.h" 5 6 #include "adf_gen2_pfvf.h" 6 7 7 8 /* VF2PF interrupts */ ··· 12 11 #define ADF_GEN2_PF_PF2VF_OFFSET(i) (0x3A000 + 0x280 + ((i) * 0x04)) 13 12 #define ADF_GEN2_VF_PF2VF_OFFSET 0x200 14 13 15 - u32 adf_gen2_pf_get_pf2vf_offset(u32 i) 14 + static u32 adf_gen2_pf_get_pf2vf_offset(u32 i) 16 15 { 17 16 return ADF_GEN2_PF_PF2VF_OFFSET(i); 18 17 } 19 - EXPORT_SYMBOL_GPL(adf_gen2_pf_get_pf2vf_offset); 20 18 21 - u32 adf_gen2_vf_get_pf2vf_offset(u32 i) 19 + static u32 adf_gen2_vf_get_pf2vf_offset(u32 i) 22 20 { 23 21 return ADF_GEN2_VF_PF2VF_OFFSET; 24 22 } 25 - EXPORT_SYMBOL_GPL(adf_gen2_vf_get_pf2vf_offset); 26 23 27 - u32 adf_gen2_get_vf2pf_sources(void __iomem *pmisc_addr) 24 + static u32 adf_gen2_get_vf2pf_sources(void __iomem *pmisc_addr) 28 25 { 29 26 u32 errsou3, errmsk3, vf_int_mask; 30 27 ··· 38 39 39 40 return vf_int_mask; 40 41 } 41 - EXPORT_SYMBOL_GPL(adf_gen2_get_vf2pf_sources); 42 42 43 - void adf_gen2_enable_vf2pf_interrupts(void __iomem *pmisc_addr, u32 vf_mask) 43 + static void adf_gen2_enable_vf2pf_interrupts(void __iomem *pmisc_addr, 44 + u32 vf_mask) 44 45 { 45 46 /* Enable VF2PF Messaging Ints - VFs 0 through 15 per vf_mask[15:0] */ 46 47 if (vf_mask & 0xFFFF) { ··· 49 50 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val); 50 51 } 51 52 } 52 - EXPORT_SYMBOL_GPL(adf_gen2_enable_vf2pf_interrupts); 53 53 54 - void adf_gen2_disable_vf2pf_interrupts(void __iomem *pmisc_addr, u32 vf_mask) 54 + static void adf_gen2_disable_vf2pf_interrupts(void __iomem *pmisc_addr, 55 + u32 vf_mask) 55 56 { 56 57 /* Disable VF2PF interrupts for VFs 0 through 15 per vf_mask[15:0] */ 57 58 if (vf_mask & 0xFFFF) { ··· 60 61 ADF_CSR_WR(pmisc_addr, ADF_GEN2_ERRMSK3, val); 61 62 } 62 63 } 63 - EXPORT_SYMBOL_GPL(adf_gen2_disable_vf2pf_interrupts); 64 + 65 + void adf_gen2_init_pf_pfvf_ops(struct adf_pfvf_ops *pfvf_ops) 66 + { 67 + pfvf_ops->enable_comms = adf_enable_pf2vf_comms; 68 + pfvf_ops->get_pf2vf_offset = adf_gen2_pf_get_pf2vf_offset; 69 + pfvf_ops->get_vf2pf_sources = adf_gen2_get_vf2pf_sources; 70 + pfvf_ops->enable_vf2pf_interrupts = adf_gen2_enable_vf2pf_interrupts; 71 + pfvf_ops->disable_vf2pf_interrupts = adf_gen2_disable_vf2pf_interrupts; 72 + } 73 + EXPORT_SYMBOL_GPL(adf_gen2_init_pf_pfvf_ops); 74 + 75 + void adf_gen2_init_vf_pfvf_ops(struct adf_pfvf_ops *pfvf_ops) 76 + { 77 + pfvf_ops->enable_comms = adf_enable_vf2pf_comms; 78 + pfvf_ops->get_pf2vf_offset = adf_gen2_vf_get_pf2vf_offset; 79 + } 80 + EXPORT_SYMBOL_GPL(adf_gen2_init_vf_pfvf_ops);
+14 -5
drivers/crypto/qat/qat_common/adf_gen2_pfvf.h
··· 11 11 #define ADF_GEN2_ERRMSK3 (0x3A000 + 0x1C) 12 12 #define ADF_GEN2_ERRMSK5 (0x3A000 + 0xDC) 13 13 14 - u32 adf_gen2_pf_get_pf2vf_offset(u32 i); 15 - u32 adf_gen2_vf_get_pf2vf_offset(u32 i); 16 - u32 adf_gen2_get_vf2pf_sources(void __iomem *pmisc_bar); 17 - void adf_gen2_enable_vf2pf_interrupts(void __iomem *pmisc_addr, u32 vf_mask); 18 - void adf_gen2_disable_vf2pf_interrupts(void __iomem *pmisc_addr, u32 vf_mask); 14 + #if defined(CONFIG_PCI_IOV) 15 + void adf_gen2_init_pf_pfvf_ops(struct adf_pfvf_ops *pfvf_ops); 16 + void adf_gen2_init_vf_pfvf_ops(struct adf_pfvf_ops *pfvf_ops); 17 + #else 18 + static inline void adf_gen2_init_pf_pfvf_ops(struct adf_pfvf_ops *pfvf_ops) 19 + { 20 + pfvf_ops->enable_comms = adf_pfvf_comms_disabled; 21 + } 22 + 23 + static inline void adf_gen2_init_vf_pfvf_ops(struct adf_pfvf_ops *pfvf_ops) 24 + { 25 + pfvf_ops->enable_comms = adf_pfvf_comms_disabled; 26 + } 27 + #endif 19 28 20 29 #endif /* ADF_GEN2_PFVF_H */
+1 -1
drivers/crypto/qat/qat_common/adf_init.c
··· 117 117 hw_data->enable_ints(accel_dev); 118 118 hw_data->enable_error_correction(accel_dev); 119 119 120 - ret = hw_data->enable_pfvf_comms(accel_dev); 120 + ret = hw_data->pfvf_ops.enable_comms(accel_dev); 121 121 if (ret) 122 122 return ret; 123 123
+4 -4
drivers/crypto/qat/qat_common/adf_isr.c
··· 64 64 unsigned long flags; 65 65 66 66 spin_lock_irqsave(&accel_dev->pf.vf2pf_ints_lock, flags); 67 - hw_data->enable_vf2pf_interrupts(pmisc_addr, vf_mask); 67 + hw_data->pfvf_ops.enable_vf2pf_interrupts(pmisc_addr, vf_mask); 68 68 spin_unlock_irqrestore(&accel_dev->pf.vf2pf_ints_lock, flags); 69 69 } 70 70 ··· 77 77 unsigned long flags; 78 78 79 79 spin_lock_irqsave(&accel_dev->pf.vf2pf_ints_lock, flags); 80 - hw_data->disable_vf2pf_interrupts(pmisc_addr, vf_mask); 80 + hw_data->pfvf_ops.disable_vf2pf_interrupts(pmisc_addr, vf_mask); 81 81 spin_unlock_irqrestore(&accel_dev->pf.vf2pf_ints_lock, flags); 82 82 } 83 83 ··· 90 90 void __iomem *pmisc_addr = pmisc->virt_addr; 91 91 92 92 spin_lock(&accel_dev->pf.vf2pf_ints_lock); 93 - hw_data->disable_vf2pf_interrupts(pmisc_addr, vf_mask); 93 + hw_data->pfvf_ops.disable_vf2pf_interrupts(pmisc_addr, vf_mask); 94 94 spin_unlock(&accel_dev->pf.vf2pf_ints_lock); 95 95 } 96 96 ··· 104 104 unsigned long vf_mask; 105 105 106 106 /* Get the interrupt sources triggered by VFs */ 107 - vf_mask = hw_data->get_vf2pf_sources(pmisc_addr); 107 + vf_mask = hw_data->pfvf_ops.get_vf2pf_sources(pmisc_addr); 108 108 109 109 if (vf_mask) { 110 110 struct adf_accel_vf_info *vf_info;
+4 -4
drivers/crypto/qat/qat_common/adf_pf2vf_msg.c
··· 29 29 int ret; 30 30 31 31 if (accel_dev->is_vf) { 32 - pf2vf_offset = hw_data->get_pf2vf_offset(0); 32 + pf2vf_offset = hw_data->pfvf_ops.get_pf2vf_offset(0); 33 33 lock = &accel_dev->vf.vf2pf_lock; 34 34 local_in_use_mask = ADF_VF2PF_IN_USE_BY_VF_MASK; 35 35 local_in_use_pattern = ADF_VF2PF_IN_USE_BY_VF; ··· 37 37 remote_in_use_pattern = ADF_PF2VF_IN_USE_BY_PF; 38 38 int_bit = ADF_VF2PF_INT; 39 39 } else { 40 - pf2vf_offset = hw_data->get_pf2vf_offset(vf_nr); 40 + pf2vf_offset = hw_data->pfvf_ops.get_pf2vf_offset(vf_nr); 41 41 lock = &accel_dev->pf.vf_info[vf_nr].pf2vf_lock; 42 42 local_in_use_mask = ADF_PF2VF_IN_USE_BY_PF_MASK; 43 43 local_in_use_pattern = ADF_PF2VF_IN_USE_BY_PF; ··· 258 258 u32 msg, resp = 0; 259 259 260 260 /* Read message from the VF */ 261 - msg = ADF_CSR_RD(pmisc_addr, hw_data->get_pf2vf_offset(vf_nr)); 261 + msg = ADF_CSR_RD(pmisc_addr, hw_data->pfvf_ops.get_pf2vf_offset(vf_nr)); 262 262 if (!(msg & ADF_VF2PF_INT)) { 263 263 dev_info(&GET_DEV(accel_dev), 264 264 "Spurious VF2PF interrupt, msg %X. Ignored\n", msg); ··· 275 275 276 276 /* To ACK, clear the VF2PFINT bit */ 277 277 msg &= ~ADF_VF2PF_INT; 278 - ADF_CSR_WR(pmisc_addr, hw_data->get_pf2vf_offset(vf_nr), msg); 278 + ADF_CSR_WR(pmisc_addr, hw_data->pfvf_ops.get_pf2vf_offset(vf_nr), msg); 279 279 280 280 if (adf_handle_vf2pf_msg(accel_dev, vf_nr, msg, &resp)) 281 281 return false;
+3 -3
drivers/crypto/qat/qat_common/adf_sriov.c
··· 70 70 hw_data->configure_iov_threads(accel_dev, true); 71 71 72 72 /* Enable VF to PF interrupts for all VFs */ 73 - if (hw_data->get_pf2vf_offset) 73 + if (hw_data->pfvf_ops.get_pf2vf_offset) 74 74 adf_enable_vf2pf_interrupts(accel_dev, BIT_ULL(totalvfs) - 1); 75 75 76 76 /* ··· 100 100 if (!accel_dev->pf.vf_info) 101 101 return; 102 102 103 - if (hw_data->get_pf2vf_offset) 103 + if (hw_data->pfvf_ops.get_pf2vf_offset) 104 104 adf_pf2vf_notify_restarting(accel_dev); 105 105 106 106 pci_disable_sriov(accel_to_pci_dev(accel_dev)); 107 107 108 108 /* Disable VF to PF interrupts */ 109 - if (hw_data->get_pf2vf_offset) 109 + if (hw_data->pfvf_ops.get_pf2vf_offset) 110 110 adf_disable_vf2pf_interrupts(accel_dev, GENMASK(31, 0)); 111 111 112 112 /* Clear Valid bits in AE Thread to PCIe Function Mapping */
+1 -1
drivers/crypto/qat/qat_common/adf_vf2pf_msg.c
··· 81 81 struct adf_bar *pmisc = 82 82 &GET_BARS(accel_dev)[hw_data->get_misc_bar_id(hw_data)]; 83 83 void __iomem *pmisc_bar_addr = pmisc->virt_addr; 84 - u32 offset = hw_data->get_pf2vf_offset(0); 84 + u32 offset = hw_data->pfvf_ops.get_pf2vf_offset(0); 85 85 u32 msg; 86 86 87 87 /* Read the message from PF */
+4 -5
drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
··· 215 215 hw_data->get_arb_mapping = adf_get_arbiter_mapping; 216 216 hw_data->enable_ints = adf_enable_ints; 217 217 hw_data->reset_device = adf_reset_sbr; 218 - hw_data->get_pf2vf_offset = adf_gen2_pf_get_pf2vf_offset; 219 - hw_data->get_vf2pf_sources = get_vf2pf_sources; 220 - hw_data->enable_vf2pf_interrupts = enable_vf2pf_interrupts; 221 - hw_data->disable_vf2pf_interrupts = disable_vf2pf_interrupts; 222 - hw_data->enable_pfvf_comms = adf_enable_pf2vf_comms; 223 218 hw_data->disable_iov = adf_disable_sriov; 224 219 hw_data->min_iov_compat_ver = ADF_PFVF_COMPAT_THIS_VERSION; 225 220 221 + adf_gen2_init_pf_pfvf_ops(&hw_data->pfvf_ops); 222 + hw_data->pfvf_ops.get_vf2pf_sources = get_vf2pf_sources; 223 + hw_data->pfvf_ops.enable_vf2pf_interrupts = enable_vf2pf_interrupts; 224 + hw_data->pfvf_ops.disable_vf2pf_interrupts = disable_vf2pf_interrupts; 226 225 adf_gen2_init_hw_csr_ops(&hw_data->csr_ops); 227 226 } 228 227
+1 -2
drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c
··· 82 82 hw_data->get_num_aes = get_num_aes; 83 83 hw_data->get_etr_bar_id = get_etr_bar_id; 84 84 hw_data->get_misc_bar_id = get_misc_bar_id; 85 - hw_data->get_pf2vf_offset = adf_gen2_vf_get_pf2vf_offset; 86 85 hw_data->get_sku = get_sku; 87 86 hw_data->enable_ints = adf_vf_void_noop; 88 - hw_data->enable_pfvf_comms = adf_enable_vf2pf_comms; 89 87 hw_data->min_iov_compat_ver = ADF_PFVF_COMPAT_THIS_VERSION; 90 88 hw_data->dev_class->instances++; 91 89 adf_devmgr_update_class_index(hw_data); 90 + adf_gen2_init_vf_pfvf_ops(&hw_data->pfvf_ops); 92 91 adf_gen2_init_hw_csr_ops(&hw_data->csr_ops); 93 92 } 94 93