tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'various-cleanups'

Rosen Penev says:

====================
various cleanups

Allow CI to build. Also a bugfix for dual GMAC devices.
====================

Link: https://patch.msgid.link/20240905194938.8453-1-rosenp@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

Jakub Kicinski bcd138b1 228fa9b1

+42 -38
+2 -2
drivers/net/ethernet/atheros/Kconfig
··· 6 6 config NET_VENDOR_ATHEROS 7 7 bool "Atheros devices" 8 8 default y 9 - depends on (PCI || ATH79) 9 + depends on PCI || ATH79 || COMPILE_TEST 10 10 help 11 11 If you have a network (Ethernet) card belonging to this class, say Y. 12 12 ··· 19 19 20 20 config AG71XX 21 21 tristate "Atheros AR7XXX/AR9XXX built-in ethernet mac support" 22 - depends on ATH79 22 + depends on ATH79 || COMPILE_TEST 23 23 select PHYLINK 24 24 imply NET_SELFTESTS 25 25 help
+40 -36
drivers/net/ethernet/atheros/ag71xx.c
··· 149 149 #define FIFO_CFG4_MC BIT(8) /* Multicast Packet */ 150 150 #define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */ 151 151 #define FIFO_CFG4_DR BIT(10) /* Dribble */ 152 - #define FIFO_CFG4_LE BIT(11) /* Long Event */ 153 - #define FIFO_CFG4_CF BIT(12) /* Control Frame */ 154 - #define FIFO_CFG4_PF BIT(13) /* Pause Frame */ 155 - #define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */ 156 - #define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */ 152 + #define FIFO_CFG4_CF BIT(11) /* Control Frame */ 153 + #define FIFO_CFG4_PF BIT(12) /* Pause Frame */ 154 + #define FIFO_CFG4_UO BIT(13) /* Unsupported Opcode */ 155 + #define FIFO_CFG4_VT BIT(14) /* VLAN tag detected */ 156 + #define FIFO_CFG4_LE BIT(15) /* Long Event */ 157 157 #define FIFO_CFG4_FT BIT(16) /* Frame Truncated */ 158 158 #define FIFO_CFG4_UC BIT(17) /* Unicast Packet */ 159 159 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \ ··· 168 168 #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */ 169 169 #define FIFO_CFG5_FC BIT(2) /* False Carrier */ 170 170 #define FIFO_CFG5_CE BIT(3) /* Code Error */ 171 - #define FIFO_CFG5_LM BIT(4) /* Length Mismatch */ 172 - #define FIFO_CFG5_LO BIT(5) /* Length Out of Range */ 173 - #define FIFO_CFG5_OK BIT(6) /* Packet is OK */ 174 - #define FIFO_CFG5_MC BIT(7) /* Multicast Packet */ 175 - #define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */ 176 - #define FIFO_CFG5_DR BIT(9) /* Dribble */ 177 - #define FIFO_CFG5_CF BIT(10) /* Control Frame */ 178 - #define FIFO_CFG5_PF BIT(11) /* Pause Frame */ 179 - #define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */ 180 - #define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */ 181 - #define FIFO_CFG5_LE BIT(14) /* Long Event */ 182 - #define FIFO_CFG5_FT BIT(15) /* Frame Truncated */ 183 - #define FIFO_CFG5_16 BIT(16) /* unknown */ 184 - #define FIFO_CFG5_17 BIT(17) /* unknown */ 171 + #define FIFO_CFG5_CR BIT(4) /* CRC error */ 172 + #define FIFO_CFG5_LM BIT(5) /* Length Mismatch */ 173 + #define FIFO_CFG5_LO BIT(6) /* Length Out of Range */ 174 + #define FIFO_CFG5_OK BIT(7) /* Packet is OK */ 175 + #define FIFO_CFG5_MC BIT(8) /* Multicast Packet */ 176 + #define FIFO_CFG5_BC BIT(9) /* Broadcast Packet */ 177 + #define FIFO_CFG5_DR BIT(10) /* Dribble */ 178 + #define FIFO_CFG5_CF BIT(11) /* Control Frame */ 179 + #define FIFO_CFG5_PF BIT(12) /* Pause Frame */ 180 + #define FIFO_CFG5_UO BIT(13) /* Unsupported Opcode */ 181 + #define FIFO_CFG5_VT BIT(14) /* VLAN tag detected */ 182 + #define FIFO_CFG5_LE BIT(15) /* Long Event */ 183 + #define FIFO_CFG5_FT BIT(16) /* Frame Truncated */ 184 + #define FIFO_CFG5_UC BIT(17) /* Unicast Packet */ 185 185 #define FIFO_CFG5_SF BIT(18) /* Short Frame */ 186 186 #define FIFO_CFG5_BM BIT(19) /* Byte Mode */ 187 187 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \ 188 - FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \ 189 - FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \ 190 - FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \ 191 - FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \ 192 - FIFO_CFG5_17 | FIFO_CFG5_SF) 188 + FIFO_CFG5_CE | FIFO_CFG5_LM | FIFO_CFG5_LO | \ 189 + FIFO_CFG5_OK | FIFO_CFG5_MC | FIFO_CFG5_BC | \ 190 + FIFO_CFG5_DR | FIFO_CFG5_CF | FIFO_CFG5_UO | \ 191 + FIFO_CFG5_VT | FIFO_CFG5_LE | FIFO_CFG5_FT | \ 192 + FIFO_CFG5_UC | FIFO_CFG5_SF) 193 193 194 194 #define AG71XX_REG_TX_CTRL 0x0180 195 195 #define TX_CTRL_TXE BIT(0) /* Tx Enable */ ··· 379 379 u32 fifodata[3]; 380 380 int mac_idx; 381 381 382 - struct reset_control *mdio_reset; 383 382 struct clk *clk_mdio; 384 383 }; 385 384 ··· 508 509 switch (sset) { 509 510 case ETH_SS_STATS: 510 511 for (i = 0; i < ARRAY_SIZE(ag71xx_statistics); i++) 511 - memcpy(data + i * ETH_GSTRING_LEN, 512 - ag71xx_statistics[i].name, ETH_GSTRING_LEN); 512 + ethtool_puts(&data, ag71xx_statistics[i].name); 513 513 break; 514 514 case ETH_SS_TEST: 515 515 net_selftest_get_strings(data); ··· 688 690 { 689 691 struct device *dev = &ag->pdev->dev; 690 692 struct net_device *ndev = ag->ndev; 693 + struct reset_control *mdio_reset; 691 694 static struct mii_bus *mii_bus; 692 695 struct device_node *np, *mnp; 693 696 int err; ··· 705 706 if (!mii_bus) 706 707 return -ENOMEM; 707 708 708 - ag->mdio_reset = of_reset_control_get_exclusive(np, "mdio"); 709 - if (IS_ERR(ag->mdio_reset)) { 709 + mdio_reset = devm_reset_control_get_exclusive(dev, "mdio"); 710 + if (IS_ERR(mdio_reset)) { 710 711 netif_err(ag, probe, ndev, "Failed to get reset mdio.\n"); 711 - return PTR_ERR(ag->mdio_reset); 712 + return PTR_ERR(mdio_reset); 712 713 } 713 714 714 715 mii_bus->name = "ag71xx_mdio"; ··· 719 720 mii_bus->parent = dev; 720 721 snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s.%d", np->name, ag->mac_idx); 721 722 722 - if (!IS_ERR(ag->mdio_reset)) { 723 - reset_control_assert(ag->mdio_reset); 724 - msleep(100); 725 - reset_control_deassert(ag->mdio_reset); 726 - msleep(200); 727 - } 723 + reset_control_assert(mdio_reset); 724 + msleep(100); 725 + reset_control_deassert(mdio_reset); 726 + msleep(200); 728 727 729 728 mnp = of_get_child_by_name(np, "mdio"); 730 729 err = devm_of_mdiobus_register(dev, mii_bus, mnp); ··· 1850 1853 if (!ag->mac_base) 1851 1854 return -ENOMEM; 1852 1855 1856 + /* ensure that HW is in manual polling mode before interrupts are 1857 + * activated. Otherwise ag71xx_interrupt might call napi_schedule 1858 + * before it is initialized by netif_napi_add. 1859 + */ 1860 + ag71xx_int_disable(ag, AG71XX_INT_POLL); 1861 + 1853 1862 ndev->irq = platform_get_irq(pdev, 0); 1854 1863 err = devm_request_irq(&pdev->dev, ndev->irq, ag71xx_interrupt, 1855 1864 0x0, dev_name(&pdev->dev), ndev); ··· 2036 2033 }; 2037 2034 2038 2035 module_platform_driver(ag71xx_driver); 2036 + MODULE_DESCRIPTION("Atheros AR71xx built-in ethernet mac driver"); 2039 2037 MODULE_LICENSE("GPL v2");