+29

drivers/gpu/drm/amd/amdgpu/amdgpu.h

reviewed

··· 103 103 extern char *amdgpu_virtual_display; 104 104 extern unsigned amdgpu_pp_feature_mask; 105 105 extern int amdgpu_vram_page_split; 106 106 + extern int amdgpu_ngg; 107 107 + extern int amdgpu_prim_buf_per_se; 108 108 + extern int amdgpu_pos_buf_per_se; 109 109 + extern int amdgpu_cntl_sb_buf_per_se; 110 110 + extern int amdgpu_param_buf_per_se; 106 111 107 112 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 108 113 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ ··· 962 957 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst); 963 958 }; 964 959 960 960 + struct amdgpu_ngg_buf { 961 961 + struct amdgpu_bo *bo; 962 962 + uint64_t gpu_addr; 963 963 + uint32_t size; 964 964 + uint32_t bo_size; 965 965 + }; 966 966 + 967 967 + enum { 968 968 + PRIM = 0, 969 969 + POS, 970 970 + CNTL, 971 971 + PARAM, 972 972 + NGG_BUF_MAX 973 973 + }; 974 974 + 975 975 + struct amdgpu_ngg { 976 976 + struct amdgpu_ngg_buf buf[NGG_BUF_MAX]; 977 977 + uint32_t gds_reserve_addr; 978 978 + uint32_t gds_reserve_size; 979 979 + bool init; 980 980 + }; 981 981 + 965 982 struct amdgpu_gfx { 966 983 struct mutex gpu_clock_mutex; 967 984 struct amdgpu_gfx_config config; ··· 1027 1000 uint32_t grbm_soft_reset; 1028 1001 uint32_t srbm_soft_reset; 1029 1002 bool in_reset; 1003 1003 + /* NGG */ 1004 1004 + struct amdgpu_ngg ngg; 1030 1005 }; 1031 1006 1032 1007 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,

+21

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

reviewed

··· 103 103 char *amdgpu_disable_cu = NULL; 104 104 char *amdgpu_virtual_display = NULL; 105 105 unsigned amdgpu_pp_feature_mask = 0xffffffff; 106 106 + int amdgpu_ngg = 0; 107 107 + int amdgpu_prim_buf_per_se = 0; 108 108 + int amdgpu_pos_buf_per_se = 0; 109 109 + int amdgpu_cntl_sb_buf_per_se = 0; 110 110 + int amdgpu_param_buf_per_se = 0; 106 111 107 112 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 108 113 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); ··· 214 209 MODULE_PARM_DESC(virtual_display, 215 210 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 216 211 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 212 212 + 213 213 + MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))"); 214 214 + module_param_named(ngg, amdgpu_ngg, int, 0444); 215 215 + 216 216 + MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)"); 217 217 + module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444); 218 218 + 219 219 + MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)"); 220 220 + module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444); 221 221 + 222 222 + MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)"); 223 223 + module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444); 224 224 + 225 225 + MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Pramater Cache per Shader Engine (default depending on gfx)"); 226 226 + module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444); 227 227 + 217 228 218 229 static const struct pci_device_id pciidlist[] = { 219 230 #ifdef CONFIG_DRM_AMDGPU_SI

+7

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

reviewed

··· 541 541 dev_info.gc_double_offchip_lds_buf = 542 542 adev->gfx.config.double_offchip_lds_buf; 543 543 544 544 + if (amdgpu_ngg) { 545 545 + dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[PRIM].gpu_addr; 546 546 + dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[POS].gpu_addr; 547 547 + dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[CNTL].gpu_addr; 548 548 + dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[PARAM].gpu_addr; 549 549 + } 550 550 + 544 551 return copy_to_user(out, &dev_info, 545 552 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; 546 553 }

+8

include/uapi/drm/amdgpu_drm.h

reviewed

··· 743 743 __u32 vce_harvest_config; 744 744 /* gfx double offchip LDS buffers */ 745 745 __u32 gc_double_offchip_lds_buf; 746 746 + /* NGG Primitive Buffer */ 747 747 + __u64 prim_buf_gpu_addr; 748 748 + /* NGG Position Buffer */ 749 749 + __u64 pos_buf_gpu_addr; 750 750 + /* NGG Control Sideband */ 751 751 + __u64 cntl_sb_buf_gpu_addr; 752 752 + /* NGG Parameter Cache */ 753 753 + __u64 param_buf_gpu_addr; 746 754 }; 747 755 748 756 struct drm_amdgpu_info_hw_ip {