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drm/panfrost: Commonize Mediatek power domain array definitions

In the panfrost driver, the platform data of several Mediatek SoC
declares and uses several different power domains arrays according to
GPU core number present in the SoC:
- mediatek_mt8186_pm_domains (2 cores)
- mediatek_mt8183_pm_domains (3 cores)
- mediatek_mt8192_pm_domains (5 cores)

As they all are fixed arrays, starting with the same entries and the
platform data also has a power domains array length field
(num_pm_domains), they can be replaced by a single array, containing
all entries, if the num_pm_domains field of the platform data is also
set to the matching core number.

So, create a generic power domain array (mediatek_pm_domains) and use
it in the mt8183(b), mt8186, mt8188 and mt8192 platform data instead.

Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
Reviewed-by: Steven Price <steven.price@arm.com>
Signed-off-by: Steven Price <steven.price@arm.com>
Link: https://lore.kernel.org/r/20250509-mt8370-enable-gpu-v6-3-2833888cb1d3@collabora.com

authored by

Louis-Alexis Eyraud and committed by
Steven Price bd77b870 6905b0d9

+12 -15
+12 -15
drivers/gpu/drm/panfrost/panfrost_drv.c
··· 866 866 .vendor_quirk = panfrost_gpu_amlogic_quirk, 867 867 }; 868 868 869 + static const char * const mediatek_pm_domains[] = { "core0", "core1", "core2", 870 + "core3", "core4" }; 869 871 /* 870 872 * The old data with two power supplies for MT8183 is here only to 871 873 * keep retro-compatibility with older devicetrees, as DVFS will ··· 877 875 * coupled regulators instead. 878 876 */ 879 877 static const char * const legacy_supplies[] = { "mali", "sram", NULL }; 880 - static const char * const mediatek_mt8183_pm_domains[] = { "core0", "core1", "core2" }; 881 878 static const struct panfrost_compatible mediatek_mt8183_data = { 882 879 .num_supplies = ARRAY_SIZE(legacy_supplies) - 1, 883 880 .supply_names = legacy_supplies, 884 - .num_pm_domains = ARRAY_SIZE(mediatek_mt8183_pm_domains), 885 - .pm_domain_names = mediatek_mt8183_pm_domains, 881 + .num_pm_domains = 3, 882 + .pm_domain_names = mediatek_pm_domains, 886 883 }; 887 884 888 885 static const struct panfrost_compatible mediatek_mt8183_b_data = { 889 886 .num_supplies = ARRAY_SIZE(default_supplies) - 1, 890 887 .supply_names = default_supplies, 891 - .num_pm_domains = ARRAY_SIZE(mediatek_mt8183_pm_domains), 892 - .pm_domain_names = mediatek_mt8183_pm_domains, 888 + .num_pm_domains = 3, 889 + .pm_domain_names = mediatek_pm_domains, 893 890 .pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF), 894 891 }; 895 892 896 - static const char * const mediatek_mt8186_pm_domains[] = { "core0", "core1" }; 897 893 static const struct panfrost_compatible mediatek_mt8186_data = { 898 894 .num_supplies = ARRAY_SIZE(default_supplies) - 1, 899 895 .supply_names = default_supplies, 900 - .num_pm_domains = ARRAY_SIZE(mediatek_mt8186_pm_domains), 901 - .pm_domain_names = mediatek_mt8186_pm_domains, 896 + .num_pm_domains = 2, 897 + .pm_domain_names = mediatek_pm_domains, 902 898 .pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF), 903 899 }; 904 900 905 - /* MT8188 uses the same power domains and power supplies as MT8183 */ 906 901 static const struct panfrost_compatible mediatek_mt8188_data = { 907 902 .num_supplies = ARRAY_SIZE(default_supplies) - 1, 908 903 .supply_names = default_supplies, 909 - .num_pm_domains = ARRAY_SIZE(mediatek_mt8183_pm_domains), 910 - .pm_domain_names = mediatek_mt8183_pm_domains, 904 + .num_pm_domains = 3, 905 + .pm_domain_names = mediatek_pm_domains, 911 906 .pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF), 912 907 .gpu_quirks = BIT(GPU_QUIRK_FORCE_AARCH64_PGTABLE), 913 908 }; 914 909 915 - static const char * const mediatek_mt8192_pm_domains[] = { "core0", "core1", "core2", 916 - "core3", "core4" }; 917 910 static const struct panfrost_compatible mediatek_mt8192_data = { 918 911 .num_supplies = ARRAY_SIZE(default_supplies) - 1, 919 912 .supply_names = default_supplies, 920 - .num_pm_domains = ARRAY_SIZE(mediatek_mt8192_pm_domains), 921 - .pm_domain_names = mediatek_mt8192_pm_domains, 913 + .num_pm_domains = 5, 914 + .pm_domain_names = mediatek_pm_domains, 922 915 .pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF), 923 916 .gpu_quirks = BIT(GPU_QUIRK_FORCE_AARCH64_PGTABLE), 924 917 };