Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'x86_microcode_for_v6.18_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 microcode loading updates from Borislav Petkov:
- Add infrastructure to be able to debug the microcode loader in a guest
- Refresh Intel old microcode revisions
* tag 'x86_microcode_for_v6.18_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/microcode: Add microcode loader debugging functionality
x86/microcode: Add microcode= cmdline parsing
x86/microcode/intel: Refresh the revisions that determine old_microcode
+174
-69
+10
-2
Documentation/admin-guide/kernel-parameters.txt
+10
-2
Documentation/admin-guide/kernel-parameters.txt
···
3767
3767
3768
3768
mga= [HW,DRM]
3769
3769
3770
-
microcode.force_minrev= [X86]
3771
-
Format: <bool>
3770
+
microcode= [X86] Control the behavior of the microcode loader.
3771
+
Available options, comma separated:
3772
+
3773
+
base_rev=X - with <X> with format: <u32>
3774
+
Set the base microcode revision of each thread when in
3775
+
debug mode.
3776
+
3777
+
dis_ucode_ldr: disable the microcode loader
3778
+
3779
+
force_minrev:
3772
3780
Enable or disable the microcode minimal revision
3773
3781
enforcement for the runtime microcode loader.
3774
3782
+14
-2
arch/x86/Kconfig
+14
-2
arch/x86/Kconfig
···
1321
1321
use this at your own risk. Late loading taints the kernel unless the
1322
1322
microcode header indicates that it is safe for late loading via the
1323
1323
minimal revision check. This minimal revision check can be enforced on
1324
-
the kernel command line with "microcode.minrev=Y".
1324
+
the kernel command line with "microcode=force_minrev".
1325
1325
1326
1326
config MICROCODE_LATE_FORCE_MINREV
1327
1327
bool "Enforce late microcode loading minimal revision check"
···
1337
1337
revision check fails.
1338
1338
1339
1339
This minimal revision check can also be controlled via the
1340
-
"microcode.minrev" parameter on the kernel command line.
1340
+
"microcode=force_minrev" parameter on the kernel command line.
1341
1341
1342
1342
If unsure say Y.
1343
+
1344
+
config MICROCODE_DBG
1345
+
bool "Enable microcode loader debugging"
1346
+
default n
1347
+
depends on MICROCODE
1348
+
help
1349
+
Enable code which allows for debugging the microcode loader in
1350
+
a guest. Meaning the patch loading is simulated but everything else
1351
+
related to patch parsing and handling is done as on baremetal with
1352
+
the purpose of debugging solely the software side of things.
1353
+
1354
+
You almost certainly want to say n here.
1343
1355
1344
1356
config X86_MSR
1345
1357
tristate "/dev/cpu/*/msr - Model-specific register support"
+51
-22
arch/x86/kernel/cpu/microcode/amd.c
+51
-22
arch/x86/kernel/cpu/microcode/amd.c
···
269
269
return true;
270
270
}
271
271
272
-
static u32 get_patch_level(void)
273
-
{
274
-
u32 rev, dummy __always_unused;
275
-
276
-
native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
277
-
278
-
return rev;
279
-
}
280
-
281
272
static union cpuid_1_eax ucode_rev_to_cpuid(unsigned int val)
282
273
{
283
274
union zen_patch_rev p;
···
284
293
c.ext_fam = p.ext_fam;
285
294
286
295
return c;
296
+
}
297
+
298
+
static u32 get_patch_level(void)
299
+
{
300
+
u32 rev, dummy __always_unused;
301
+
302
+
if (IS_ENABLED(CONFIG_MICROCODE_DBG)) {
303
+
int cpu = smp_processor_id();
304
+
305
+
if (!microcode_rev[cpu]) {
306
+
if (!base_rev)
307
+
base_rev = cpuid_to_ucode_rev(bsp_cpuid_1_eax);
308
+
309
+
microcode_rev[cpu] = base_rev;
310
+
311
+
ucode_dbg("CPU%d, base_rev: 0x%x\n", cpu, base_rev);
312
+
}
313
+
314
+
return microcode_rev[cpu];
315
+
}
316
+
317
+
native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
318
+
319
+
return rev;
287
320
}
288
321
289
322
static u16 find_equiv_id(struct equiv_cpu_table *et, u32 sig)
···
339
324
u32 cont_magic;
340
325
341
326
if (buf_size <= CONTAINER_HDR_SZ) {
342
-
pr_debug("Truncated microcode container header.\n");
327
+
ucode_dbg("Truncated microcode container header.\n");
343
328
return false;
344
329
}
345
330
346
331
cont_magic = *(const u32 *)buf;
347
332
if (cont_magic != UCODE_MAGIC) {
348
-
pr_debug("Invalid magic value (0x%08x).\n", cont_magic);
333
+
ucode_dbg("Invalid magic value (0x%08x).\n", cont_magic);
349
334
return false;
350
335
}
351
336
···
370
355
371
356
cont_type = hdr[1];
372
357
if (cont_type != UCODE_EQUIV_CPU_TABLE_TYPE) {
373
-
pr_debug("Wrong microcode container equivalence table type: %u.\n",
374
-
cont_type);
358
+
ucode_dbg("Wrong microcode container equivalence table type: %u.\n",
359
+
cont_type);
375
360
return false;
376
361
}
377
362
···
380
365
equiv_tbl_len = hdr[2];
381
366
if (equiv_tbl_len < sizeof(struct equiv_cpu_entry) ||
382
367
buf_size < equiv_tbl_len) {
383
-
pr_debug("Truncated equivalence table.\n");
368
+
ucode_dbg("Truncated equivalence table.\n");
384
369
return false;
385
370
}
386
371
···
400
385
const u32 *hdr;
401
386
402
387
if (buf_size < SECTION_HDR_SIZE) {
403
-
pr_debug("Truncated patch section.\n");
388
+
ucode_dbg("Truncated patch section.\n");
404
389
return false;
405
390
}
406
391
···
409
394
p_size = hdr[1];
410
395
411
396
if (p_type != UCODE_UCODE_TYPE) {
412
-
pr_debug("Invalid type field (0x%x) in container file section header.\n",
413
-
p_type);
397
+
ucode_dbg("Invalid type field (0x%x) in container file section header.\n",
398
+
p_type);
414
399
return false;
415
400
}
416
401
417
402
if (p_size < sizeof(struct microcode_header_amd)) {
418
-
pr_debug("Patch of size %u too short.\n", p_size);
403
+
ucode_dbg("Patch of size %u too short.\n", p_size);
419
404
return false;
420
405
}
421
406
···
492
477
* size sh_psize, as the section claims.
493
478
*/
494
479
if (buf_size < sh_psize) {
495
-
pr_debug("Patch of size %u truncated.\n", sh_psize);
480
+
ucode_dbg("Patch of size %u truncated.\n", sh_psize);
496
481
return -1;
497
482
}
498
483
499
484
if (!__verify_patch_size(sh_psize, buf_size)) {
500
-
pr_debug("Per-family patch size mismatch.\n");
485
+
ucode_dbg("Per-family patch size mismatch.\n");
501
486
return -1;
502
487
}
503
488
···
511
496
512
497
proc_id = mc_hdr->processor_rev_id;
513
498
patch_fam = 0xf + (proc_id >> 12);
499
+
500
+
ucode_dbg("Patch-ID 0x%08x: family: 0x%x\n", mc_hdr->patch_id, patch_fam);
501
+
514
502
if (patch_fam != family)
515
503
return 1;
516
504
···
584
566
}
585
567
586
568
mc = (struct microcode_amd *)(buf + SECTION_HDR_SIZE);
569
+
570
+
ucode_dbg("patch_id: 0x%x\n", mc->hdr.patch_id);
571
+
587
572
if (mc_patch_matches(mc, eq_id)) {
588
573
desc->psize = patch_size;
589
574
desc->mc = mc;
575
+
576
+
ucode_dbg(" match: size: %d\n", patch_size);
590
577
}
591
578
592
579
skip:
···
662
639
invlpg(p_addr_end);
663
640
}
664
641
642
+
if (IS_ENABLED(CONFIG_MICROCODE_DBG))
643
+
microcode_rev[smp_processor_id()] = mc->hdr.patch_id;
644
+
665
645
/* verify patch application was successful */
666
646
*cur_rev = get_patch_level();
647
+
648
+
ucode_dbg("updated rev: 0x%x\n", *cur_rev);
649
+
667
650
if (*cur_rev != mc->hdr.patch_id)
668
651
return false;
669
652
···
1055
1026
patch->patch_id = mc_hdr->patch_id;
1056
1027
patch->equiv_cpu = proc_id;
1057
1028
1058
-
pr_debug("%s: Adding patch_id: 0x%08x, proc_id: 0x%04x\n",
1029
+
ucode_dbg("%s: Adding patch_id: 0x%08x, proc_id: 0x%04x\n",
1059
1030
__func__, patch->patch_id, proc_id);
1060
1031
1061
1032
/* ... and add to cache. */
···
1198
1169
snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86);
1199
1170
1200
1171
if (request_firmware_direct(&fw, (const char *)fw_name, device)) {
1201
-
pr_debug("failed to load file %s\n", fw_name);
1172
+
ucode_dbg("failed to load file %s\n", fw_name);
1202
1173
goto out;
1203
1174
}
1204
1175
+42
-5
arch/x86/kernel/cpu/microcode/core.c
+42
-5
arch/x86/kernel/cpu/microcode/core.c
···
43
43
#include "internal.h"
44
44
45
45
static struct microcode_ops *microcode_ops;
46
-
static bool dis_ucode_ldr = false;
46
+
static bool dis_ucode_ldr;
47
47
48
48
bool force_minrev = IS_ENABLED(CONFIG_MICROCODE_LATE_FORCE_MINREV);
49
-
module_param(force_minrev, bool, S_IRUSR | S_IWUSR);
49
+
50
+
/*
51
+
* Those below should be behind CONFIG_MICROCODE_DBG ifdeffery but in
52
+
* order to not uglify the code with ifdeffery and use IS_ENABLED()
53
+
* instead, leave them in. When microcode debugging is not enabled,
54
+
* those are meaningless anyway.
55
+
*/
56
+
/* base microcode revision for debugging */
57
+
u32 base_rev;
58
+
u32 microcode_rev[NR_CPUS] = {};
50
59
51
60
/*
52
61
* Synchronization.
···
128
119
* overwritten.
129
120
*/
130
121
if (!cpuid_feature() ||
131
-
native_cpuid_ecx(1) & BIT(31) ||
122
+
((native_cpuid_ecx(1) & BIT(31)) &&
123
+
!IS_ENABLED(CONFIG_MICROCODE_DBG)) ||
132
124
amd_check_current_patch_level())
133
125
dis_ucode_ldr = true;
134
126
135
127
return dis_ucode_ldr;
128
+
}
129
+
130
+
static void early_parse_cmdline(void)
131
+
{
132
+
char cmd_buf[64] = {};
133
+
char *s, *p = cmd_buf;
134
+
135
+
if (cmdline_find_option(boot_command_line, "microcode", cmd_buf, sizeof(cmd_buf)) > 0) {
136
+
while ((s = strsep(&p, ","))) {
137
+
if (IS_ENABLED(CONFIG_MICROCODE_DBG)) {
138
+
if (strstr(s, "base_rev=")) {
139
+
/* advance to the option arg */
140
+
strsep(&s, "=");
141
+
if (kstrtouint(s, 16, &base_rev)) { ; }
142
+
}
143
+
}
144
+
145
+
if (!strcmp("force_minrev", s))
146
+
force_minrev = true;
147
+
148
+
if (!strcmp(s, "dis_ucode_ldr"))
149
+
dis_ucode_ldr = true;
150
+
}
151
+
}
152
+
153
+
/* old, compat option */
154
+
if (cmdline_find_option_bool(boot_command_line, "dis_ucode_ldr") > 0)
155
+
dis_ucode_ldr = true;
136
156
}
137
157
138
158
void __init load_ucode_bsp(void)
···
169
131
unsigned int cpuid_1_eax;
170
132
bool intel = true;
171
133
172
-
if (cmdline_find_option_bool(boot_command_line, "dis_ucode_ldr") > 0)
173
-
dis_ucode_ldr = true;
134
+
early_parse_cmdline();
174
135
175
136
if (microcode_loader_disabled())
176
137
return;
+48
-38
arch/x86/kernel/cpu/microcode/intel-ucode-defs.h
+48
-38
arch/x86/kernel/cpu/microcode/intel-ucode-defs.h
···
67
67
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x55, .steppings = 0x0008, .driver_data = 0x1000191 },
68
68
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x55, .steppings = 0x0010, .driver_data = 0x2007006 },
69
69
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x55, .steppings = 0x0020, .driver_data = 0x3000010 },
70
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x55, .steppings = 0x0040, .driver_data = 0x4003605 },
71
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x55, .steppings = 0x0080, .driver_data = 0x5003707 },
72
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x55, .steppings = 0x0800, .driver_data = 0x7002904 },
70
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x55, .steppings = 0x0080, .driver_data = 0x5003901 },
71
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x55, .steppings = 0x0800, .driver_data = 0x7002b01 },
73
72
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x56, .steppings = 0x0004, .driver_data = 0x1c },
74
73
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x56, .steppings = 0x0008, .driver_data = 0x700001c },
75
74
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x56, .steppings = 0x0010, .driver_data = 0xf00001a },
···
80
81
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x5f, .steppings = 0x0002, .driver_data = 0x3e },
81
82
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x66, .steppings = 0x0008, .driver_data = 0x2a },
82
83
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x6a, .steppings = 0x0020, .driver_data = 0xc0002f0 },
83
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x6a, .steppings = 0x0040, .driver_data = 0xd0003e7 },
84
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x6c, .steppings = 0x0002, .driver_data = 0x10002b0 },
84
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x6a, .steppings = 0x0040, .driver_data = 0xd000404 },
85
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x6c, .steppings = 0x0002, .driver_data = 0x10002d0 },
85
86
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x7a, .steppings = 0x0002, .driver_data = 0x42 },
86
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x7a, .steppings = 0x0100, .driver_data = 0x24 },
87
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x7e, .steppings = 0x0020, .driver_data = 0xc6 },
87
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x7a, .steppings = 0x0100, .driver_data = 0x26 },
88
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x7e, .steppings = 0x0020, .driver_data = 0xca },
88
89
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8a, .steppings = 0x0002, .driver_data = 0x33 },
89
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8c, .steppings = 0x0002, .driver_data = 0xb8 },
90
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8c, .steppings = 0x0004, .driver_data = 0x38 },
91
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8d, .steppings = 0x0002, .driver_data = 0x52 },
90
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8c, .steppings = 0x0002, .driver_data = 0xbc },
91
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8c, .steppings = 0x0004, .driver_data = 0x3c },
92
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8d, .steppings = 0x0002, .driver_data = 0x56 },
92
93
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8e, .steppings = 0x0200, .driver_data = 0xf6 },
93
94
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8e, .steppings = 0x0400, .driver_data = 0xf6 },
94
95
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8e, .steppings = 0x0800, .driver_data = 0xf6 },
95
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8e, .steppings = 0x1000, .driver_data = 0xfc },
96
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8f, .steppings = 0x0100, .driver_data = 0x2c000390 },
97
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8f, .steppings = 0x0080, .driver_data = 0x2b000603 },
98
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8f, .steppings = 0x0040, .driver_data = 0x2c000390 },
99
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8f, .steppings = 0x0020, .driver_data = 0x2c000390 },
100
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8f, .steppings = 0x0010, .driver_data = 0x2c000390 },
96
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8e, .steppings = 0x1000, .driver_data = 0x100 },
97
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8f, .steppings = 0x0010, .driver_data = 0x2c0003f7 },
98
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8f, .steppings = 0x0020, .driver_data = 0x2c0003f7 },
99
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8f, .steppings = 0x0040, .driver_data = 0x2c0003f7 },
100
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8f, .steppings = 0x0080, .driver_data = 0x2b000639 },
101
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8f, .steppings = 0x0100, .driver_data = 0x2c0003f7 },
101
102
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x96, .steppings = 0x0002, .driver_data = 0x1a },
102
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x97, .steppings = 0x0004, .driver_data = 0x37 },
103
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x97, .steppings = 0x0020, .driver_data = 0x37 },
104
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xbf, .steppings = 0x0004, .driver_data = 0x37 },
105
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xbf, .steppings = 0x0020, .driver_data = 0x37 },
106
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x9a, .steppings = 0x0008, .driver_data = 0x435 },
107
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x9a, .steppings = 0x0010, .driver_data = 0x435 },
103
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x97, .steppings = 0x0004, .driver_data = 0x3a },
104
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x97, .steppings = 0x0020, .driver_data = 0x3a },
105
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x9a, .steppings = 0x0008, .driver_data = 0x437 },
106
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x9a, .steppings = 0x0010, .driver_data = 0x437 },
108
107
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x9c, .steppings = 0x0001, .driver_data = 0x24000026 },
109
108
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x9e, .steppings = 0x0200, .driver_data = 0xf8 },
110
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x9e, .steppings = 0x0400, .driver_data = 0xf8 },
109
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x9e, .steppings = 0x0400, .driver_data = 0xfa },
111
110
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x9e, .steppings = 0x0800, .driver_data = 0xf6 },
112
111
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x9e, .steppings = 0x1000, .driver_data = 0xf8 },
113
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x9e, .steppings = 0x2000, .driver_data = 0x100 },
114
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xa5, .steppings = 0x0004, .driver_data = 0xfc },
115
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xa5, .steppings = 0x0008, .driver_data = 0xfc },
116
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xa5, .steppings = 0x0020, .driver_data = 0xfc },
117
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xa6, .steppings = 0x0001, .driver_data = 0xfe },
118
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xa6, .steppings = 0x0002, .driver_data = 0xfc },
119
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xa7, .steppings = 0x0002, .driver_data = 0x62 },
120
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xaa, .steppings = 0x0010, .driver_data = 0x20 },
121
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xb7, .steppings = 0x0002, .driver_data = 0x12b },
122
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xba, .steppings = 0x0004, .driver_data = 0x4123 },
123
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xba, .steppings = 0x0008, .driver_data = 0x4123 },
124
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xba, .steppings = 0x0100, .driver_data = 0x4123 },
125
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xbe, .steppings = 0x0001, .driver_data = 0x1a },
126
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xcf, .steppings = 0x0004, .driver_data = 0x21000283 },
127
-
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xcf, .steppings = 0x0002, .driver_data = 0x21000283 },
112
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x9e, .steppings = 0x2000, .driver_data = 0x104 },
113
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xa5, .steppings = 0x0004, .driver_data = 0x100 },
114
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xa5, .steppings = 0x0008, .driver_data = 0x100 },
115
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xa5, .steppings = 0x0020, .driver_data = 0x100 },
116
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xa6, .steppings = 0x0001, .driver_data = 0x102 },
117
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xa6, .steppings = 0x0002, .driver_data = 0x100 },
118
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xa7, .steppings = 0x0002, .driver_data = 0x64 },
119
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xaa, .steppings = 0x0010, .driver_data = 0x24 },
120
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xad, .steppings = 0x0002, .driver_data = 0xa0000d1 },
121
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xaf, .steppings = 0x0008, .driver_data = 0x3000341 },
122
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xb5, .steppings = 0x0001, .driver_data = 0xa },
123
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xb7, .steppings = 0x0002, .driver_data = 0x12f },
124
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xb7, .steppings = 0x0010, .driver_data = 0x12f },
125
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xba, .steppings = 0x0004, .driver_data = 0x4128 },
126
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xba, .steppings = 0x0008, .driver_data = 0x4128 },
127
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xba, .steppings = 0x0100, .driver_data = 0x4128 },
128
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xbd, .steppings = 0x0002, .driver_data = 0x11f },
129
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xbe, .steppings = 0x0001, .driver_data = 0x1d },
130
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xbf, .steppings = 0x0004, .driver_data = 0x3a },
131
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xbf, .steppings = 0x0020, .driver_data = 0x3a },
132
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xbf, .steppings = 0x0040, .driver_data = 0x3a },
133
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xbf, .steppings = 0x0080, .driver_data = 0x3a },
134
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xc5, .steppings = 0x0004, .driver_data = 0x118 },
135
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xc6, .steppings = 0x0004, .driver_data = 0x118 },
136
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xc6, .steppings = 0x0010, .driver_data = 0x118 },
137
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xca, .steppings = 0x0004, .driver_data = 0x118 },
138
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xcf, .steppings = 0x0002, .driver_data = 0x210002a9 },
139
+
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xcf, .steppings = 0x0004, .driver_data = 0x210002a9 },
128
140
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0xf, .model = 0x00, .steppings = 0x0080, .driver_data = 0x12 },
129
141
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0xf, .model = 0x00, .steppings = 0x0400, .driver_data = 0x15 },
130
142
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0xf, .model = 0x01, .steppings = 0x0004, .driver_data = 0x2e },
+9
arch/x86/kernel/cpu/microcode/internal.h
+9
arch/x86/kernel/cpu/microcode/internal.h
···
44
44
45
45
extern struct early_load_data early_data;
46
46
extern struct ucode_cpu_info ucode_cpu_info[];
47
+
extern u32 microcode_rev[NR_CPUS];
48
+
extern u32 base_rev;
49
+
47
50
struct cpio_data find_microcode_in_initrd(const char *path);
48
51
49
52
#define MAX_UCODE_COUNT 128
···
124
121
static inline void reload_ucode_intel(void) { }
125
122
static inline struct microcode_ops *init_intel_microcode(void) { return NULL; }
126
123
#endif /* !CONFIG_CPU_SUP_INTEL */
124
+
125
+
#define ucode_dbg(fmt, ...) \
126
+
({ \
127
+
if (IS_ENABLED(CONFIG_MICROCODE_DBG)) \
128
+
pr_info(fmt, ##__VA_ARGS__); \
129
+
})
127
130
128
131
#endif /* _X86_MICROCODE_INTERNAL_H */