Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6: (37 commits)
[NETFILTER]: fix ebtable targets return
[IP_TUNNEL]: Don't limit the number of tunnels with generic name explicitly.
[NET]: Restore sanity wrt. print_mac().
[NEIGH]: Fix race between neighbor lookup and table's hash_rnd update.
[RTNL]: Validate hardware and broadcast address attribute for RTM_NEWLINK
tg3: ethtool phys_id default
[BNX2]: Update version to 1.7.4.
[BNX2]: Disable parallel detect on an HP blade.
[BNX2]: More 5706S link down workaround.
ssb: Fix support for PCI devices behind a SSB->PCI bridge
zd1211rw: fix sparse warnings
rtl818x: fix sparse warnings
ssb: Fix pcicore cardbus mode
ssb: Make the GPIO API reentrancy safe
ssb: Fix the GPIO API
ssb: Fix watchdog access for devices without a chipcommon
ssb: Fix serial console on new bcm47xx devices
ath5k: Fix build warnings on some 64-bit platforms.
WDEV, ath5k, don't return int from bool function
WDEV: ath5k, fix lock imbalance
...
+524
-183
+32
-18
drivers/net/bnx2.c
+32
-18
drivers/net/bnx2.c
···
56
56
57
57
#define DRV_MODULE_NAME "bnx2"
58
58
#define PFX DRV_MODULE_NAME ": "
59
-
#define DRV_MODULE_VERSION "1.7.3"
60
-
#define DRV_MODULE_RELDATE "January 29, 2008"
59
+
#define DRV_MODULE_VERSION "1.7.4"
60
+
#define DRV_MODULE_RELDATE "February 18, 2008"
61
61
62
62
#define RUN_AT(x) (jiffies + (x))
63
63
···
1273
1273
1274
1274
if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1275
1275
(CHIP_NUM(bp) == CHIP_NUM_5706)) {
1276
-
u32 val;
1276
+
u32 val, an_dbg;
1277
1277
1278
1278
if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1279
1279
bnx2_5706s_force_link_dn(bp, 0);
1280
1280
bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1281
1281
}
1282
1282
val = REG_RD(bp, BNX2_EMAC_STATUS);
1283
-
if (val & BNX2_EMAC_STATUS_LINK)
1283
+
1284
+
bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1285
+
bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1286
+
bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1287
+
1288
+
if ((val & BNX2_EMAC_STATUS_LINK) &&
1289
+
!(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1284
1290
bmsr |= BMSR_LSTATUS;
1285
1291
else
1286
1292
bmsr &= ~BMSR_LSTATUS;
···
5362
5356
return -ENODEV;
5363
5357
}
5364
5358
5359
+
/* Determining link for parallel detection. */
5365
5360
static int
5366
5361
bnx2_5706_serdes_has_link(struct bnx2 *bp)
5367
5362
{
5368
5363
u32 mode_ctl, an_dbg, exp;
5364
+
5365
+
if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5366
+
return 0;
5369
5367
5370
5368
bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5371
5369
bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
···
5400
5390
int check_link = 1;
5401
5391
5402
5392
spin_lock(&bp->phy_lock);
5403
-
if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
5404
-
bnx2_5706s_force_link_dn(bp, 0);
5405
-
bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
5406
-
spin_unlock(&bp->phy_lock);
5407
-
return;
5408
-
}
5409
-
5410
5393
if (bp->serdes_an_pending) {
5411
5394
bp->serdes_an_pending--;
5412
5395
check_link = 0;
···
5423
5420
(bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
5424
5421
u32 phy2;
5425
5422
5426
-
check_link = 0;
5427
5423
bnx2_write_phy(bp, 0x17, 0x0f01);
5428
5424
bnx2_read_phy(bp, 0x15, &phy2);
5429
5425
if (phy2 & 0x20) {
···
5437
5435
} else
5438
5436
bp->current_interval = bp->timer_interval;
5439
5437
5440
-
if (bp->link_up && (bp->autoneg & AUTONEG_SPEED) && check_link) {
5438
+
if (check_link) {
5441
5439
u32 val;
5442
5440
5443
5441
bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5444
5442
bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5445
5443
bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5446
5444
5447
-
if (val & MISC_SHDW_AN_DBG_NOSYNC) {
5448
-
bnx2_5706s_force_link_dn(bp, 1);
5449
-
bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
5450
-
}
5445
+
if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
5446
+
if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
5447
+
bnx2_5706s_force_link_dn(bp, 1);
5448
+
bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
5449
+
} else
5450
+
bnx2_set_link(bp);
5451
+
} else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
5452
+
bnx2_set_link(bp);
5451
5453
}
5452
5454
spin_unlock(&bp->phy_lock);
5453
5455
}
···
7332
7326
bp->flags |= BNX2_FLAG_NO_WOL;
7333
7327
bp->wol = 0;
7334
7328
}
7335
-
if (CHIP_NUM(bp) != CHIP_NUM_5706) {
7329
+
if (CHIP_NUM(bp) == CHIP_NUM_5706) {
7330
+
/* Don't do parallel detect on this board because of
7331
+
* some board problems. The link will not go down
7332
+
* if we do parallel detect.
7333
+
*/
7334
+
if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
7335
+
pdev->subsystem_device == 0x310c)
7336
+
bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
7337
+
} else {
7336
7338
bp->phy_addr = 2;
7337
7339
if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
7338
7340
bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
+1
drivers/net/bnx2.h
+1
drivers/net/bnx2.h
+5
-4
drivers/net/niu.c
+5
-4
drivers/net/niu.c
···
1616
1616
if (index >= niu_num_alt_addr(np))
1617
1617
return -EINVAL;
1618
1618
1619
-
if (np->flags & NIU_FLAGS_XMAC)
1619
+
if (np->flags & NIU_FLAGS_XMAC) {
1620
1620
reg = XMAC_ADDR_CMPEN;
1621
-
else
1621
+
mask = 1 << index;
1622
+
} else {
1622
1623
reg = BMAC_ADDR_CMPEN;
1623
-
1624
-
mask = 1 << index;
1624
+
mask = 1 << (index + 1);
1625
+
}
1625
1626
1626
1627
val = nr64_mac(reg);
1627
1628
if (on)
+1
-1
drivers/net/niu.h
+1
-1
drivers/net/niu.h
···
499
499
#define BMAC_ADDR2 0x00110UL
500
500
#define BMAC_ADDR2_ADDR2 0x000000000000ffffULL
501
501
502
-
#define BMAC_NUM_ALT_ADDR 7
502
+
#define BMAC_NUM_ALT_ADDR 6
503
503
504
504
#define BMAC_ALT_ADDR0(NUM) (0x00118UL + (NUM)*0x18UL)
505
505
#define BMAC_ALT_ADDR0_ADDR0 0x000000000000ffffULL
+1
-1
drivers/net/tg3.c
+1
-1
drivers/net/tg3.c
+40
-13
drivers/net/veth.c
+40
-13
drivers/net/veth.c
···
244
244
return 0;
245
245
}
246
246
247
-
static int veth_close(struct net_device *dev)
248
-
{
249
-
struct veth_priv *priv;
250
-
251
-
if (netif_carrier_ok(dev)) {
252
-
priv = netdev_priv(dev);
253
-
netif_carrier_off(dev);
254
-
netif_carrier_off(priv->peer);
255
-
}
256
-
return 0;
257
-
}
258
-
259
247
static int veth_dev_init(struct net_device *dev)
260
248
{
261
249
struct veth_net_stats *stats;
···
274
286
dev->hard_start_xmit = veth_xmit;
275
287
dev->get_stats = veth_get_stats;
276
288
dev->open = veth_open;
277
-
dev->stop = veth_close;
278
289
dev->ethtool_ops = &veth_ethtool_ops;
279
290
dev->features |= NETIF_F_LLTX;
280
291
dev->init = veth_dev_init;
281
292
dev->destructor = veth_dev_free;
282
293
}
294
+
295
+
static void veth_change_state(struct net_device *dev)
296
+
{
297
+
struct net_device *peer;
298
+
struct veth_priv *priv;
299
+
300
+
priv = netdev_priv(dev);
301
+
peer = priv->peer;
302
+
303
+
if (netif_carrier_ok(peer)) {
304
+
if (!netif_carrier_ok(dev))
305
+
netif_carrier_on(dev);
306
+
} else {
307
+
if (netif_carrier_ok(dev))
308
+
netif_carrier_off(dev);
309
+
}
310
+
}
311
+
312
+
static int veth_device_event(struct notifier_block *unused,
313
+
unsigned long event, void *ptr)
314
+
{
315
+
struct net_device *dev = ptr;
316
+
317
+
if (dev->open != veth_open)
318
+
goto out;
319
+
320
+
switch (event) {
321
+
case NETDEV_CHANGE:
322
+
veth_change_state(dev);
323
+
break;
324
+
}
325
+
out:
326
+
return NOTIFY_DONE;
327
+
}
328
+
329
+
static struct notifier_block veth_notifier_block __read_mostly = {
330
+
.notifier_call = veth_device_event,
331
+
};
283
332
284
333
/*
285
334
* netlink interface
···
479
454
480
455
static __init int veth_init(void)
481
456
{
457
+
register_netdevice_notifier(&veth_notifier_block);
482
458
return rtnl_link_register(&veth_link_ops);
483
459
}
484
460
485
461
static __exit void veth_exit(void)
486
462
{
487
463
rtnl_link_unregister(&veth_link_ops);
464
+
unregister_netdevice_notifier(&veth_notifier_block);
488
465
}
489
466
490
467
module_init(veth_init);
+1
-1
drivers/net/wireless/ath5k/ath5k.h
+1
-1
drivers/net/wireless/ath5k/ath5k.h
···
1035
1035
unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
1036
1036
unsigned int, unsigned int, unsigned int, unsigned int,
1037
1037
unsigned int, unsigned int, unsigned int);
1038
-
bool (*ah_setup_xtx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1038
+
int (*ah_setup_xtx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1039
1039
unsigned int, unsigned int, unsigned int, unsigned int,
1040
1040
unsigned int, unsigned int);
1041
1041
int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *);
+13
-7
drivers/net/wireless/ath5k/base.c
+13
-7
drivers/net/wireless/ath5k/base.c
···
668
668
* return false w/o doing anything. MAC's that do
669
669
* support it will return true w/o doing anything.
670
670
*/
671
-
if (ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0))
671
+
ret = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
672
+
if (ret < 0)
673
+
goto err;
674
+
if (ret > 0)
672
675
__set_bit(ATH_STAT_MRRETRY, sc->status);
673
676
674
677
/*
···
1718
1715
break;
1719
1716
else if (unlikely(ret)) {
1720
1717
ATH5K_ERR(sc, "error in processing rx descriptor\n");
1718
+
spin_unlock(&sc->rxbuflock);
1721
1719
return;
1722
1720
}
1723
1721
···
2130
2126
"updated timers based on beacon TSF\n");
2131
2127
2132
2128
ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2133
-
"bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2134
-
bc_tsf, hw_tsf, bc_tu, hw_tu, nexttbtt);
2129
+
"bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2130
+
(unsigned long long) bc_tsf,
2131
+
(unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2135
2132
ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2136
2133
intval & AR5K_BEACON_PERIOD,
2137
2134
intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
···
2390
2385
u64 tsf = ath5k_hw_get_tsf64(ah);
2391
2386
sc->nexttbtt += sc->bintval;
2392
2387
ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2393
-
"SWBA nexttbtt: %x hw_tu: %x "
2394
-
"TSF: %llx\n",
2395
-
sc->nexttbtt,
2396
-
TSF_TO_TU(tsf), tsf);
2388
+
"SWBA nexttbtt: %x hw_tu: %x "
2389
+
"TSF: %llx\n",
2390
+
sc->nexttbtt,
2391
+
TSF_TO_TU(tsf),
2392
+
(unsigned long long) tsf);
2397
2393
} else {
2398
2394
ath5k_beacon_send(sc);
2399
2395
}
+4
-4
drivers/net/wireless/ath5k/hw.c
+4
-4
drivers/net/wireless/ath5k/hw.c
···
45
45
unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
46
46
unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
47
47
unsigned int, unsigned int);
48
-
static bool ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
48
+
static int ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
49
49
unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
50
50
unsigned int);
51
51
static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *, struct ath5k_desc *);
···
3743
3743
/*
3744
3744
* Initialize a 4-word multirate tx descriptor on 5212
3745
3745
*/
3746
-
static bool
3746
+
static int
3747
3747
ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3748
3748
unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2,
3749
3749
unsigned int tx_rate3, u_int tx_tries3)
···
3783
3783
3784
3784
#undef _XTX_TRIES
3785
3785
3786
-
return true;
3786
+
return 1;
3787
3787
}
3788
3788
3789
-
return false;
3789
+
return 0;
3790
3790
}
3791
3791
3792
3792
/*
+2
drivers/net/wireless/p54usb.c
+2
drivers/net/wireless/p54usb.c
···
35
35
{USB_DEVICE(0x0707, 0xee06)}, /* SMC 2862W-G */
36
36
{USB_DEVICE(0x083a, 0x4501)}, /* Accton 802.11g WN4501 USB */
37
37
{USB_DEVICE(0x083a, 0x4502)}, /* Siemens Gigaset USB Adapter */
38
+
{USB_DEVICE(0x083a, 0x5501)}, /* Phillips CPWUA054 */
38
39
{USB_DEVICE(0x0846, 0x4200)}, /* Netgear WG121 */
39
40
{USB_DEVICE(0x0846, 0x4210)}, /* Netgear WG121 the second ? */
40
41
{USB_DEVICE(0x0846, 0x4220)}, /* Netgear WG111 */
···
63
62
{USB_DEVICE(0x0cde, 0x0008)}, /* Sagem XG703A */
64
63
{USB_DEVICE(0x0d8e, 0x3762)}, /* DLink DWL-G120 Cohiba */
65
64
{USB_DEVICE(0x09aa, 0x1000)}, /* Spinnaker Proto board */
65
+
{USB_DEVICE(0x13b1, 0x000a)}, /* Linksys WUSB54G ver 2 */
66
66
{USB_DEVICE(0x13B1, 0x000C)}, /* Linksys WUSB54AG */
67
67
{USB_DEVICE(0x1435, 0x0427)}, /* Inventel UR054G */
68
68
{USB_DEVICE(0x2001, 0x3704)}, /* DLink DWL-G122 rev A2 */
+3
-1
drivers/net/wireless/rtl8180_dev.c
+3
-1
drivers/net/wireless/rtl8180_dev.c
···
135
135
while (skb_queue_len(&ring->queue)) {
136
136
struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
137
137
struct sk_buff *skb;
138
-
struct ieee80211_tx_status status = { {0} };
138
+
struct ieee80211_tx_status status;
139
139
struct ieee80211_tx_control *control;
140
140
u32 flags = le32_to_cpu(entry->flags);
141
141
142
142
if (flags & RTL8180_TX_DESC_FLAG_OWN)
143
143
return;
144
+
145
+
memset(&status, 0, sizeof(status));
144
146
145
147
ring->idx = (ring->idx + 1) % ring->entries;
146
148
skb = __skb_dequeue(&ring->queue);
+3
-1
drivers/net/wireless/rtl8187_dev.c
+3
-1
drivers/net/wireless/rtl8187_dev.c
···
113
113
114
114
static void rtl8187_tx_cb(struct urb *urb)
115
115
{
116
-
struct ieee80211_tx_status status = { {0} };
116
+
struct ieee80211_tx_status status;
117
117
struct sk_buff *skb = (struct sk_buff *)urb->context;
118
118
struct rtl8187_tx_info *info = (struct rtl8187_tx_info *)skb->cb;
119
+
120
+
memset(&status, 0, sizeof(status));
119
121
120
122
usb_free_urb(info->urb);
121
123
if (info->control)
+9
-3
drivers/net/wireless/zd1211rw/zd_mac.c
+9
-3
drivers/net/wireless/zd1211rw/zd_mac.c
···
360
360
{
361
361
struct sk_buff_head *q = &zd_hw_mac(hw)->ack_wait_queue;
362
362
struct sk_buff *skb;
363
-
struct ieee80211_tx_status status = {{0}};
363
+
struct ieee80211_tx_status status;
364
364
365
365
skb = skb_dequeue(q);
366
366
if (skb == NULL)
367
367
return;
368
+
369
+
memset(&status, 0, sizeof(status));
370
+
368
371
tx_status(hw, skb, &status, 0);
369
372
}
370
373
···
392
389
if (unlikely(error ||
393
390
(cb->control->flags & IEEE80211_TXCTL_NO_ACK)))
394
391
{
395
-
struct ieee80211_tx_status status = {{0}};
392
+
struct ieee80211_tx_status status;
393
+
memset(&status, 0, sizeof(status));
396
394
tx_status(hw, skb, &status, !error);
397
395
} else {
398
396
struct sk_buff_head *q =
···
607
603
tx_hdr = (struct ieee80211_hdr *)skb->data;
608
604
if (likely(!compare_ether_addr(tx_hdr->addr2, rx_hdr->addr1)))
609
605
{
610
-
struct ieee80211_tx_status status = {{0}};
606
+
struct ieee80211_tx_status status;
607
+
608
+
memset(&status, 0, sizeof(status));
611
609
status.flags = IEEE80211_TX_STATUS_ACK;
612
610
status.ack_signal = stats->ssi;
613
611
__skb_unlink(skb, q);
+6
drivers/ssb/Kconfig
+6
drivers/ssb/Kconfig
···
105
105
106
106
If unsure, say N
107
107
108
+
# Assumption: We are on embedded, if we compile the MIPS core.
109
+
config SSB_EMBEDDED
110
+
bool
111
+
depends on SSB_DRIVER_MIPS
112
+
default y
113
+
108
114
config SSB_DRIVER_EXTIF
109
115
bool "SSB Broadcom EXTIF core driver (EXPERIMENTAL)"
110
116
depends on SSB_DRIVER_MIPS && EXPERIMENTAL
+1
drivers/ssb/Makefile
+1
drivers/ssb/Makefile
+57
-14
drivers/ssb/driver_chipcommon.c
+57
-14
drivers/ssb/driver_chipcommon.c
···
39
39
ssb_write32(cc->dev, offset, value);
40
40
}
41
41
42
-
static inline void chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
43
-
u32 mask, u32 value)
42
+
static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
43
+
u32 mask, u32 value)
44
44
{
45
45
value &= mask;
46
46
value |= chipco_read32(cc, offset) & ~mask;
47
47
chipco_write32(cc, offset, value);
48
+
49
+
return value;
48
50
}
49
51
50
52
void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
···
358
356
return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask;
359
357
}
360
358
361
-
void ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
359
+
u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
362
360
{
363
-
chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
361
+
return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
364
362
}
365
363
366
-
void ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
364
+
u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
367
365
{
368
-
chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
366
+
return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
367
+
}
368
+
369
+
u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
370
+
{
371
+
return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
372
+
}
373
+
374
+
u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
375
+
{
376
+
return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
377
+
}
378
+
379
+
u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
380
+
{
381
+
return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
369
382
}
370
383
371
384
#ifdef CONFIG_SSB_SERIAL
···
393
376
unsigned int irq;
394
377
u32 baud_base, div;
395
378
u32 i, n;
379
+
unsigned int ccrev = cc->dev->id.revision;
396
380
397
381
plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
398
382
irq = ssb_mips_irq(cc->dev);
···
405
387
chipco_read32(cc, SSB_CHIPCO_CLOCK_M2));
406
388
div = 1;
407
389
} else {
408
-
if (cc->dev->id.revision >= 11) {
409
-
/* Fixed ALP clock */
410
-
baud_base = 20000000;
411
-
div = 1;
390
+
if (ccrev == 20) {
391
+
/* BCM5354 uses constant 25MHz clock */
392
+
baud_base = 25000000;
393
+
div = 48;
412
394
/* Set the override bit so we don't divide it */
413
395
chipco_write32(cc, SSB_CHIPCO_CORECTL,
414
-
SSB_CHIPCO_CORECTL_UARTCLK0);
415
-
} else if (cc->dev->id.revision >= 3) {
396
+
chipco_read32(cc, SSB_CHIPCO_CORECTL)
397
+
| SSB_CHIPCO_CORECTL_UARTCLK0);
398
+
} else if ((ccrev >= 11) && (ccrev != 15)) {
399
+
/* Fixed ALP clock */
400
+
baud_base = 20000000;
401
+
if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
402
+
/* FIXME: baud_base is different for devices with a PMU */
403
+
SSB_WARN_ON(1);
404
+
}
405
+
div = 1;
406
+
if (ccrev >= 21) {
407
+
/* Turn off UART clock before switching clocksource. */
408
+
chipco_write32(cc, SSB_CHIPCO_CORECTL,
409
+
chipco_read32(cc, SSB_CHIPCO_CORECTL)
410
+
& ~SSB_CHIPCO_CORECTL_UARTCLKEN);
411
+
}
412
+
/* Set the override bit so we don't divide it */
413
+
chipco_write32(cc, SSB_CHIPCO_CORECTL,
414
+
chipco_read32(cc, SSB_CHIPCO_CORECTL)
415
+
| SSB_CHIPCO_CORECTL_UARTCLK0);
416
+
if (ccrev >= 21) {
417
+
/* Re-enable the UART clock. */
418
+
chipco_write32(cc, SSB_CHIPCO_CORECTL,
419
+
chipco_read32(cc, SSB_CHIPCO_CORECTL)
420
+
| SSB_CHIPCO_CORECTL_UARTCLKEN);
421
+
}
422
+
} else if (ccrev >= 3) {
416
423
/* Internal backplane clock */
417
424
baud_base = ssb_clockspeed(bus);
418
425
div = chipco_read32(cc, SSB_CHIPCO_CLKDIV)
···
449
406
}
450
407
451
408
/* Clock source depends on strapping if UartClkOverride is unset */
452
-
if ((cc->dev->id.revision > 0) &&
409
+
if ((ccrev > 0) &&
453
410
!(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) {
454
411
if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) ==
455
412
SSB_CHIPCO_CAP_UARTCLK_INT) {
···
471
428
cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE);
472
429
uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA;
473
430
/* Offset changed at after rev 0 */
474
-
if (cc->dev->id.revision == 0)
431
+
if (ccrev == 0)
475
432
uart_regs += (i * 8);
476
433
else
477
434
uart_regs += (i * 256);
+21
-4
drivers/ssb/driver_extif.c
+21
-4
drivers/ssb/driver_extif.c
···
27
27
ssb_write32(extif->dev, offset, value);
28
28
}
29
29
30
-
static inline void extif_write32_masked(struct ssb_extif *extif, u16 offset,
31
-
u32 mask, u32 value)
30
+
static inline u32 extif_write32_masked(struct ssb_extif *extif, u16 offset,
31
+
u32 mask, u32 value)
32
32
{
33
33
value &= mask;
34
34
value |= extif_read32(extif, offset) & ~mask;
35
35
extif_write32(extif, offset, value);
36
+
37
+
return value;
36
38
}
37
39
38
40
#ifdef CONFIG_SSB_SERIAL
···
112
110
*m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
113
111
}
114
112
113
+
void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
114
+
u32 ticks)
115
+
{
116
+
extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks);
117
+
}
118
+
115
119
u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
116
120
{
117
121
return extif_read32(extif, SSB_EXTIF_GPIO_IN) & mask;
118
122
}
119
123
120
-
void ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value)
124
+
u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value)
121
125
{
122
126
return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0),
123
127
mask, value);
124
128
}
125
129
126
-
void ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value)
130
+
u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value)
127
131
{
128
132
return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0),
129
133
mask, value);
130
134
}
131
135
136
+
u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value)
137
+
{
138
+
return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value);
139
+
}
140
+
141
+
u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value)
142
+
{
143
+
return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value);
144
+
}
+38
-7
drivers/ssb/driver_pcicore.c
+38
-7
drivers/ssb/driver_pcicore.c
···
11
11
#include <linux/ssb/ssb.h>
12
12
#include <linux/pci.h>
13
13
#include <linux/delay.h>
14
+
#include <linux/ssb/ssb_embedded.h>
14
15
15
16
#include "ssb_private.h"
16
17
···
26
25
void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value)
27
26
{
28
27
ssb_write32(pc->dev, offset, value);
28
+
}
29
+
30
+
static inline
31
+
u16 pcicore_read16(struct ssb_pcicore *pc, u16 offset)
32
+
{
33
+
return ssb_read16(pc->dev, offset);
34
+
}
35
+
36
+
static inline
37
+
void pcicore_write16(struct ssb_pcicore *pc, u16 offset, u16 value)
38
+
{
39
+
ssb_write16(pc->dev, offset, value);
29
40
}
30
41
31
42
/**************************************************
···
79
66
base = &ssb_pcicore_pcibus_iobase;
80
67
else
81
68
base = &ssb_pcicore_pcibus_membase;
69
+
res->flags |= IORESOURCE_PCI_FIXED;
82
70
if (res->end) {
83
71
size = res->end - res->start + 1;
84
72
if (*base & (size - 1))
···
102
88
103
89
static void __init ssb_fixup_pcibridge(struct pci_dev *dev)
104
90
{
91
+
u8 lat;
92
+
105
93
if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
106
94
return;
107
95
108
-
ssb_printk(KERN_INFO "PCI: fixing up bridge\n");
96
+
ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
109
97
110
98
/* Enable PCI bridge bus mastering and memory space */
111
99
pci_set_master(dev);
···
117
101
pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
118
102
119
103
/* Make sure our latency is high enough to handle the devices behind us */
120
-
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xa8);
104
+
lat = 168;
105
+
ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
106
+
pci_name(dev), lat);
107
+
pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
121
108
}
122
109
DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
123
110
···
136
117
u32 addr = 0;
137
118
u32 tmp;
138
119
139
-
if (unlikely(pc->cardbusmode && dev > 1))
120
+
/* We do only have one cardbus device behind the bridge. */
121
+
if (pc->cardbusmode && (dev >= 1))
140
122
goto out;
123
+
141
124
if (bus == 0) {
142
125
/* Type 0 transaction */
143
126
if (unlikely(dev >= SSB_PCI_SLOT_MAX))
···
300
279
.name = "SSB PCIcore external memory",
301
280
.start = SSB_PCI_DMA,
302
281
.end = SSB_PCI_DMA + SSB_PCI_DMA_SZ - 1,
303
-
.flags = IORESOURCE_MEM,
282
+
.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED,
304
283
};
305
284
306
285
static struct resource ssb_pcicore_io_resource = {
307
286
.name = "SSB PCIcore external I/O",
308
287
.start = 0x100,
309
288
.end = 0x7FF,
310
-
.flags = IORESOURCE_IO,
289
+
.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED,
311
290
};
312
291
313
292
static struct pci_controller ssb_pcicore_controller = {
···
339
318
pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
340
319
udelay(1); /* Assertion time demanded by the PCI standard */
341
320
342
-
/*TODO cardbus mode */
321
+
if (pc->dev->bus->has_cardbus_slot) {
322
+
ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n");
323
+
pc->cardbusmode = 1;
324
+
/* GPIO 1 resets the bridge */
325
+
ssb_gpio_out(pc->dev->bus, 1, 1);
326
+
ssb_gpio_outen(pc->dev->bus, 1, 1);
327
+
pcicore_write16(pc, SSB_PCICORE_SPROM(0),
328
+
pcicore_read16(pc, SSB_PCICORE_SPROM(0))
329
+
| 0x0400);
330
+
}
343
331
344
332
/* 64MB I/O window */
345
333
pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
···
374
344
/* Ok, ready to run, register it to the system.
375
345
* The following needs change, if we want to port hostmode
376
346
* to non-MIPS platform. */
377
-
set_io_port_base((unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000));
347
+
ssb_pcicore_controller.io_map_base = (unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000);
348
+
set_io_port_base(ssb_pcicore_controller.io_map_base);
378
349
/* Give some time to the PCI controller to configure itself with the new
379
350
* values. Not waiting at this point causes crashes of the machine. */
380
351
mdelay(10);
+132
drivers/ssb/embedded.c
+132
drivers/ssb/embedded.c
···
1
+
/*
2
+
* Sonics Silicon Backplane
3
+
* Embedded systems support code
4
+
*
5
+
* Copyright 2005-2008, Broadcom Corporation
6
+
* Copyright 2006-2008, Michael Buesch <mb@bu3sch.de>
7
+
*
8
+
* Licensed under the GNU/GPL. See COPYING for details.
9
+
*/
10
+
11
+
#include <linux/ssb/ssb.h>
12
+
#include <linux/ssb/ssb_embedded.h>
13
+
14
+
#include "ssb_private.h"
15
+
16
+
17
+
int ssb_watchdog_timer_set(struct ssb_bus *bus, u32 ticks)
18
+
{
19
+
if (ssb_chipco_available(&bus->chipco)) {
20
+
ssb_chipco_watchdog_timer_set(&bus->chipco, ticks);
21
+
return 0;
22
+
}
23
+
if (ssb_extif_available(&bus->extif)) {
24
+
ssb_extif_watchdog_timer_set(&bus->extif, ticks);
25
+
return 0;
26
+
}
27
+
return -ENODEV;
28
+
}
29
+
30
+
u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask)
31
+
{
32
+
unsigned long flags;
33
+
u32 res = 0;
34
+
35
+
spin_lock_irqsave(&bus->gpio_lock, flags);
36
+
if (ssb_chipco_available(&bus->chipco))
37
+
res = ssb_chipco_gpio_in(&bus->chipco, mask);
38
+
else if (ssb_extif_available(&bus->extif))
39
+
res = ssb_extif_gpio_in(&bus->extif, mask);
40
+
else
41
+
SSB_WARN_ON(1);
42
+
spin_unlock_irqrestore(&bus->gpio_lock, flags);
43
+
44
+
return res;
45
+
}
46
+
EXPORT_SYMBOL(ssb_gpio_in);
47
+
48
+
u32 ssb_gpio_out(struct ssb_bus *bus, u32 mask, u32 value)
49
+
{
50
+
unsigned long flags;
51
+
u32 res = 0;
52
+
53
+
spin_lock_irqsave(&bus->gpio_lock, flags);
54
+
if (ssb_chipco_available(&bus->chipco))
55
+
res = ssb_chipco_gpio_out(&bus->chipco, mask, value);
56
+
else if (ssb_extif_available(&bus->extif))
57
+
res = ssb_extif_gpio_out(&bus->extif, mask, value);
58
+
else
59
+
SSB_WARN_ON(1);
60
+
spin_unlock_irqrestore(&bus->gpio_lock, flags);
61
+
62
+
return res;
63
+
}
64
+
EXPORT_SYMBOL(ssb_gpio_out);
65
+
66
+
u32 ssb_gpio_outen(struct ssb_bus *bus, u32 mask, u32 value)
67
+
{
68
+
unsigned long flags;
69
+
u32 res = 0;
70
+
71
+
spin_lock_irqsave(&bus->gpio_lock, flags);
72
+
if (ssb_chipco_available(&bus->chipco))
73
+
res = ssb_chipco_gpio_outen(&bus->chipco, mask, value);
74
+
else if (ssb_extif_available(&bus->extif))
75
+
res = ssb_extif_gpio_outen(&bus->extif, mask, value);
76
+
else
77
+
SSB_WARN_ON(1);
78
+
spin_unlock_irqrestore(&bus->gpio_lock, flags);
79
+
80
+
return res;
81
+
}
82
+
EXPORT_SYMBOL(ssb_gpio_outen);
83
+
84
+
u32 ssb_gpio_control(struct ssb_bus *bus, u32 mask, u32 value)
85
+
{
86
+
unsigned long flags;
87
+
u32 res = 0;
88
+
89
+
spin_lock_irqsave(&bus->gpio_lock, flags);
90
+
if (ssb_chipco_available(&bus->chipco))
91
+
res = ssb_chipco_gpio_control(&bus->chipco, mask, value);
92
+
spin_unlock_irqrestore(&bus->gpio_lock, flags);
93
+
94
+
return res;
95
+
}
96
+
EXPORT_SYMBOL(ssb_gpio_control);
97
+
98
+
u32 ssb_gpio_intmask(struct ssb_bus *bus, u32 mask, u32 value)
99
+
{
100
+
unsigned long flags;
101
+
u32 res = 0;
102
+
103
+
spin_lock_irqsave(&bus->gpio_lock, flags);
104
+
if (ssb_chipco_available(&bus->chipco))
105
+
res = ssb_chipco_gpio_intmask(&bus->chipco, mask, value);
106
+
else if (ssb_extif_available(&bus->extif))
107
+
res = ssb_extif_gpio_intmask(&bus->extif, mask, value);
108
+
else
109
+
SSB_WARN_ON(1);
110
+
spin_unlock_irqrestore(&bus->gpio_lock, flags);
111
+
112
+
return res;
113
+
}
114
+
EXPORT_SYMBOL(ssb_gpio_intmask);
115
+
116
+
u32 ssb_gpio_polarity(struct ssb_bus *bus, u32 mask, u32 value)
117
+
{
118
+
unsigned long flags;
119
+
u32 res = 0;
120
+
121
+
spin_lock_irqsave(&bus->gpio_lock, flags);
122
+
if (ssb_chipco_available(&bus->chipco))
123
+
res = ssb_chipco_gpio_polarity(&bus->chipco, mask, value);
124
+
else if (ssb_extif_available(&bus->extif))
125
+
res = ssb_extif_gpio_polarity(&bus->extif, mask, value);
126
+
else
127
+
SSB_WARN_ON(1);
128
+
spin_unlock_irqrestore(&bus->gpio_lock, flags);
129
+
130
+
return res;
131
+
}
132
+
EXPORT_SYMBOL(ssb_gpio_polarity);
+4
drivers/ssb/main.c
+4
drivers/ssb/main.c
···
557
557
goto out;
558
558
memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo));
559
559
memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom));
560
+
bus->has_cardbus_slot = iv.has_cardbus_slot;
560
561
out:
561
562
return err;
562
563
}
···
570
569
571
570
spin_lock_init(&bus->bar_lock);
572
571
INIT_LIST_HEAD(&bus->list);
572
+
#ifdef CONFIG_SSB_EMBEDDED
573
+
spin_lock_init(&bus->gpio_lock);
574
+
#endif
573
575
574
576
/* Powerup the bus */
575
577
err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
+2
-1
include/linux/if_ether.h
+2
-1
include/linux/if_ether.h
···
129
129
/*
130
130
* Display a 6 byte device address (MAC) in a readable format.
131
131
*/
132
-
extern __pure char *print_mac(char *buf, const unsigned char *addr);
132
+
extern char *print_mac(char *buf, const unsigned char *addr);
133
+
#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x"
133
134
#define MAC_BUF_SIZE 18
134
135
#define DECLARE_MAC_BUF(var) char var[MAC_BUF_SIZE] __maybe_unused
135
136
+1
-1
include/linux/netfilter.h
+1
-1
include/linux/netfilter.h
+1
-1
include/linux/netfilter/Kbuild
+1
-1
include/linux/netfilter/Kbuild
···
30
30
header-y += xt_multiport.h
31
31
header-y += xt_owner.h
32
32
header-y += xt_pkttype.h
33
-
header-y += xt_policy.h
34
33
header-y += xt_rateest.h
35
34
header-y += xt_realm.h
36
35
header-y += xt_sctp.h
···
46
47
unifdef-y += nfnetlink_compat.h
47
48
unifdef-y += x_tables.h
48
49
unifdef-y += xt_physdev.h
50
+
unifdef-y += xt_policy.h
-1
include/linux/netfilter/xt_hashlimit.h
-1
include/linux/netfilter/xt_hashlimit.h
+12
include/linux/ssb/ssb.h
+12
include/linux/ssb/ssb.h
···
282
282
struct ssb_boardinfo boardinfo;
283
283
/* Contents of the SPROM. */
284
284
struct ssb_sprom sprom;
285
+
/* If the board has a cardbus slot, this is set to true. */
286
+
bool has_cardbus_slot;
287
+
288
+
#ifdef CONFIG_SSB_EMBEDDED
289
+
/* Lock for GPIO register access. */
290
+
spinlock_t gpio_lock;
291
+
#endif /* EMBEDDED */
285
292
286
293
/* Internal-only stuff follows. Do not touch. */
287
294
struct list_head list;
···
301
294
302
295
/* The initialization-invariants. */
303
296
struct ssb_init_invariants {
297
+
/* Versioning information about the PCB. */
304
298
struct ssb_boardinfo boardinfo;
299
+
/* The SPROM information. That's either stored in an
300
+
* EEPROM or NVRAM on the board. */
305
301
struct ssb_sprom sprom;
302
+
/* If the board has a cardbus slot, this is set to true. */
303
+
bool has_cardbus_slot;
306
304
};
307
305
/* Type of function to fetch the invariants. */
308
306
typedef int (*ssb_invariants_func_t)(struct ssb_bus *bus,
+14
-4
include/linux/ssb/ssb_driver_chipcommon.h
+14
-4
include/linux/ssb/ssb_driver_chipcommon.h
···
51
51
#define SSB_CHIPCO_CAP_JTAGM 0x00400000 /* JTAG master present */
52
52
#define SSB_CHIPCO_CAP_BROM 0x00800000 /* Internal boot ROM active */
53
53
#define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
54
+
#define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
55
+
#define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
54
56
#define SSB_CHIPCO_CORECTL 0x0008
55
57
#define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
56
58
#define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
59
+
#define SSB_CHIPCO_CORECTL_UARTCLKEN 0x00000008 /* UART clock enable (rev >= 21) */
57
60
#define SSB_CHIPCO_BIST 0x000C
58
61
#define SSB_CHIPCO_OTPS 0x0010 /* OTP status */
59
62
#define SSB_CHIPCO_OTPS_PROGFAIL 0x80000000
···
360
357
u16 fast_pwrup_delay;
361
358
};
362
359
360
+
static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
361
+
{
362
+
return (cc->dev != NULL);
363
+
}
364
+
363
365
extern void ssb_chipcommon_init(struct ssb_chipcommon *cc);
364
366
365
367
#include <linux/pm.h>
···
390
382
extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc,
391
383
u32 ticks);
392
384
385
+
/* Chipcommon GPIO pin access. */
393
386
u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask);
394
-
395
-
void ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value);
396
-
397
-
void ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value);
387
+
u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value);
388
+
u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value);
389
+
u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value);
390
+
u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value);
391
+
u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value);
398
392
399
393
#ifdef CONFIG_SSB_SERIAL
400
394
extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
+14
-4
include/linux/ssb/ssb_driver_extif.h
+14
-4
include/linux/ssb/ssb_driver_extif.h
···
171
171
extern void ssb_extif_timing_init(struct ssb_extif *extif,
172
172
unsigned long ns);
173
173
174
+
extern void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
175
+
u32 ticks);
176
+
177
+
/* Extif GPIO pin access */
174
178
u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask);
175
-
176
-
void ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value);
177
-
178
-
void ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value);
179
+
u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value);
180
+
u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value);
181
+
u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value);
182
+
u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value);
179
183
180
184
#ifdef CONFIG_SSB_SERIAL
181
185
extern int ssb_extif_serial_init(struct ssb_extif *extif,
···
201
197
static inline
202
198
void ssb_extif_get_clockcontrol(struct ssb_extif *extif,
203
199
u32 *plltype, u32 *n, u32 *m)
200
+
{
201
+
}
202
+
203
+
static inline
204
+
void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
205
+
u32 ticks)
204
206
{
205
207
}
206
208
+5
include/linux/ssb/ssb_driver_pci.h
+5
include/linux/ssb/ssb_driver_pci.h
···
51
51
#define SSB_PCICORE_SBTOPCI1_MASK 0xFC000000
52
52
#define SSB_PCICORE_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */
53
53
#define SSB_PCICORE_SBTOPCI2_MASK 0xC0000000
54
+
#define SSB_PCICORE_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
55
+
#define SSB_PCICORE_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */
56
+
#define SSB_PCICORE_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
57
+
#define SSB_PCICORE_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */
58
+
#define SSB_PCICORE_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
54
59
55
60
/* SBtoPCIx */
56
61
#define SSB_PCICORE_SBTOPCI_MEM 0x00000000
+18
include/linux/ssb/ssb_embedded.h
+18
include/linux/ssb/ssb_embedded.h
···
1
+
#ifndef LINUX_SSB_EMBEDDED_H_
2
+
#define LINUX_SSB_EMBEDDED_H_
3
+
4
+
#include <linux/types.h>
5
+
#include <linux/ssb/ssb.h>
6
+
7
+
8
+
extern int ssb_watchdog_timer_set(struct ssb_bus *bus, u32 ticks);
9
+
10
+
/* Generic GPIO API */
11
+
u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask);
12
+
u32 ssb_gpio_out(struct ssb_bus *bus, u32 mask, u32 value);
13
+
u32 ssb_gpio_outen(struct ssb_bus *bus, u32 mask, u32 value);
14
+
u32 ssb_gpio_control(struct ssb_bus *bus, u32 mask, u32 value);
15
+
u32 ssb_gpio_intmask(struct ssb_bus *bus, u32 mask, u32 value);
16
+
u32 ssb_gpio_polarity(struct ssb_bus *bus, u32 mask, u32 value);
17
+
18
+
#endif /* LINUX_SSB_EMBEDDED_H_ */
-2
include/net/ip6_tunnel.h
-2
include/net/ip6_tunnel.h
+6
-4
net/8021q/vlan_dev.c
+6
-4
net/8021q/vlan_dev.c
···
366
366
{
367
367
struct net_device_stats *stats = &dev->stats;
368
368
struct vlan_ethhdr *veth = (struct vlan_ethhdr *)(skb->data);
369
-
DECLARE_MAC_BUF(mac);
370
-
DECLARE_MAC_BUF(mac2);
369
+
371
370
/* Handle non-VLAN frames if they are sent to us, for example by DHCP.
372
371
*
373
372
* NOTE: THIS ASSUMES DIX ETHERNET, SPECIFICALLY NOT SUPPORTING
···
404
405
405
406
pr_debug("%s: about to send skb: %p to dev: %s\n",
406
407
__FUNCTION__, skb, skb->dev->name);
407
-
pr_debug(" %s %s %4hx %4hx %4hx\n",
408
-
print_mac(mac, veth->h_dest), print_mac(mac2, veth->h_source),
408
+
pr_debug(" " MAC_FMT " " MAC_FMT " %4hx %4hx %4hx\n",
409
+
veth->h_dest[0], veth->h_dest[1], veth->h_dest[2],
410
+
veth->h_dest[3], veth->h_dest[4], veth->h_dest[5],
411
+
veth->h_source[0], veth->h_source[1], veth->h_source[2],
412
+
veth->h_source[3], veth->h_source[4], veth->h_source[5],
409
413
veth->h_vlan_proto, veth->h_vlan_TCI,
410
414
veth->h_vlan_encapsulated_proto);
411
415
+1
-1
net/9p/trans_virtio.c
+1
-1
net/9p/trans_virtio.c
···
110
110
}
111
111
for (count = old_max; count < c->max_tag; count++) {
112
112
c->reqs[count].status = REQ_STATUS_IDLE;
113
-
c->reqs[count].wq = kmalloc(sizeof(wait_queue_t),
113
+
c->reqs[count].wq = kmalloc(sizeof(wait_queue_head_t),
114
114
GFP_ATOMIC);
115
115
if (!c->reqs[count].wq) {
116
116
printk(KERN_ERR "Couldn't grow tag array\n");
+2
-2
net/bridge/netfilter/ebt_dnat.c
+2
-2
net/bridge/netfilter/ebt_dnat.c
+2
-2
net/bridge/netfilter/ebt_redirect.c
+2
-2
net/bridge/netfilter/ebt_redirect.c
+2
-2
net/bridge/netfilter/ebt_snat.c
+2
-2
net/bridge/netfilter/ebt_snat.c
+1
-1
net/core/dev.c
+1
-1
net/core/dev.c
+5
-2
net/core/neighbour.c
+5
-2
net/core/neighbour.c
···
358
358
{
359
359
struct neighbour *n;
360
360
int key_len = tbl->key_len;
361
-
u32 hash_val = tbl->hash(pkey, dev);
361
+
u32 hash_val;
362
362
363
363
NEIGH_CACHE_STAT_INC(tbl, lookups);
364
364
365
365
read_lock_bh(&tbl->lock);
366
+
hash_val = tbl->hash(pkey, dev);
366
367
for (n = tbl->hash_buckets[hash_val & tbl->hash_mask]; n; n = n->next) {
367
368
if (dev == n->dev && !memcmp(n->primary_key, pkey, key_len)) {
368
369
neigh_hold(n);
···
380
379
{
381
380
struct neighbour *n;
382
381
int key_len = tbl->key_len;
383
-
u32 hash_val = tbl->hash(pkey, NULL);
382
+
u32 hash_val;
384
383
385
384
NEIGH_CACHE_STAT_INC(tbl, lookups);
386
385
387
386
read_lock_bh(&tbl->lock);
387
+
hash_val = tbl->hash(pkey, NULL);
388
388
for (n = tbl->hash_buckets[hash_val & tbl->hash_mask]; n; n = n->next) {
389
389
if (!memcmp(n->primary_key, pkey, key_len) &&
390
390
(net == n->dev->nd_net)) {
···
509
507
if (tbl->pconstructor && tbl->pconstructor(n)) {
510
508
if (dev)
511
509
dev_put(dev);
510
+
release_net(net);
512
511
kfree(n);
513
512
n = NULL;
514
513
goto out;
+21
-6
net/core/rtnetlink.c
+21
-6
net/core/rtnetlink.c
···
689
689
[IFLA_BROADCAST] = { .type = NLA_BINARY, .len = MAX_ADDR_LEN },
690
690
[IFLA_MAP] = { .len = sizeof(struct rtnl_link_ifmap) },
691
691
[IFLA_MTU] = { .type = NLA_U32 },
692
+
[IFLA_LINK] = { .type = NLA_U32 },
692
693
[IFLA_TXQLEN] = { .type = NLA_U32 },
693
694
[IFLA_WEIGHT] = { .type = NLA_U32 },
694
695
[IFLA_OPERSTATE] = { .type = NLA_U8 },
695
696
[IFLA_LINKMODE] = { .type = NLA_U8 },
697
+
[IFLA_LINKINFO] = { .type = NLA_NESTED },
696
698
[IFLA_NET_NS_PID] = { .type = NLA_U32 },
697
699
};
698
700
···
720
718
}
721
719
rcu_read_unlock();
722
720
return net;
721
+
}
722
+
723
+
static int validate_linkmsg(struct net_device *dev, struct nlattr *tb[])
724
+
{
725
+
if (dev) {
726
+
if (tb[IFLA_ADDRESS] &&
727
+
nla_len(tb[IFLA_ADDRESS]) < dev->addr_len)
728
+
return -EINVAL;
729
+
730
+
if (tb[IFLA_BROADCAST] &&
731
+
nla_len(tb[IFLA_BROADCAST]) < dev->addr_len)
732
+
return -EINVAL;
733
+
}
734
+
735
+
return 0;
723
736
}
724
737
725
738
static int do_setlink(struct net_device *dev, struct ifinfomsg *ifm,
···
909
892
goto errout;
910
893
}
911
894
912
-
if (tb[IFLA_ADDRESS] &&
913
-
nla_len(tb[IFLA_ADDRESS]) < dev->addr_len)
914
-
goto errout_dev;
915
-
916
-
if (tb[IFLA_BROADCAST] &&
917
-
nla_len(tb[IFLA_BROADCAST]) < dev->addr_len)
895
+
if ((err = validate_linkmsg(dev, tb)) < 0)
918
896
goto errout_dev;
919
897
920
898
err = do_setlink(dev, ifm, tb, ifname, 0);
···
1029
1017
dev = __dev_get_by_name(net, ifname);
1030
1018
else
1031
1019
dev = NULL;
1020
+
1021
+
if ((err = validate_linkmsg(dev, tb)) < 0)
1022
+
return err;
1032
1023
1033
1024
if (tb[IFLA_LINKINFO]) {
1034
1025
err = nla_parse_nested(linkinfo, IFLA_INFO_MAX,
+5
-5
net/ipv4/fib_hash.c
+5
-5
net/ipv4/fib_hash.c
···
372
372
static int fn_hash_insert(struct fib_table *tb, struct fib_config *cfg)
373
373
{
374
374
struct fn_hash *table = (struct fn_hash *) tb->tb_data;
375
-
struct fib_node *new_f, *f;
375
+
struct fib_node *new_f = NULL;
376
+
struct fib_node *f;
376
377
struct fib_alias *fa, *new_fa;
377
378
struct fn_zone *fz;
378
379
struct fib_info *fi;
···
497
496
498
497
err = -ENOBUFS;
499
498
500
-
new_f = NULL;
501
499
if (!f) {
502
500
new_f = kmem_cache_zalloc(fn_hash_kmem, GFP_KERNEL);
503
501
if (new_f == NULL)
···
512
512
if (new_fa->fa_info != NULL) {
513
513
new_fa = kmem_cache_alloc(fn_alias_kmem, GFP_KERNEL);
514
514
if (new_fa == NULL)
515
-
goto out_free_new_f;
515
+
goto out;
516
516
}
517
517
new_fa->fa_info = fi;
518
518
new_fa->fa_tos = tos;
···
540
540
&cfg->fc_nlinfo, 0);
541
541
return 0;
542
542
543
-
out_free_new_f:
544
-
kmem_cache_free(fn_hash_kmem, new_f);
545
543
out:
544
+
if (new_f)
545
+
kmem_cache_free(fn_hash_kmem, new_f);
546
546
fib_release_info(fi);
547
547
return err;
548
548
}
+2
-10
net/ipv4/ip_gre.c
+2
-10
net/ipv4/ip_gre.c
···
259
259
260
260
if (parms->name[0])
261
261
strlcpy(name, parms->name, IFNAMSIZ);
262
-
else {
263
-
int i;
264
-
for (i=1; i<100; i++) {
265
-
sprintf(name, "gre%d", i);
266
-
if (__dev_get_by_name(&init_net, name) == NULL)
267
-
break;
268
-
}
269
-
if (i==100)
270
-
goto failed;
271
-
}
262
+
else
263
+
sprintf(name, "gre%%d");
272
264
273
265
dev = alloc_netdev(sizeof(*t), name, ipgre_tunnel_setup);
274
266
if (!dev)
+2
-10
net/ipv4/ipip.c
+2
-10
net/ipv4/ipip.c
···
221
221
222
222
if (parms->name[0])
223
223
strlcpy(name, parms->name, IFNAMSIZ);
224
-
else {
225
-
int i;
226
-
for (i=1; i<100; i++) {
227
-
sprintf(name, "tunl%d", i);
228
-
if (__dev_get_by_name(&init_net, name) == NULL)
229
-
break;
230
-
}
231
-
if (i==100)
232
-
goto failed;
233
-
}
224
+
else
225
+
sprintf(name, "tunl%%d");
234
226
235
227
dev = alloc_netdev(sizeof(*t), name, ipip_tunnel_setup);
236
228
if (dev == NULL)
+1
-1
net/ipv4/netfilter/arpt_mangle.c
+1
-1
net/ipv4/netfilter/arpt_mangle.c
+7
-5
net/ipv4/netfilter/ip_queue.c
+7
-5
net/ipv4/netfilter/ip_queue.c
···
283
283
ipq_mangle_ipv4(ipq_verdict_msg_t *v, struct nf_queue_entry *e)
284
284
{
285
285
int diff;
286
-
int err;
287
286
struct iphdr *user_iph = (struct iphdr *)v->payload;
287
+
struct sk_buff *nskb;
288
288
289
289
if (v->data_len < sizeof(*user_iph))
290
290
return 0;
···
296
296
if (v->data_len > 0xFFFF)
297
297
return -EINVAL;
298
298
if (diff > skb_tailroom(e->skb)) {
299
-
err = pskb_expand_head(e->skb, 0,
299
+
nskb = skb_copy_expand(e->skb, 0,
300
300
diff - skb_tailroom(e->skb),
301
301
GFP_ATOMIC);
302
-
if (err) {
302
+
if (!nskb) {
303
303
printk(KERN_WARNING "ip_queue: error "
304
-
"in mangle, dropping packet: %d\n", -err);
305
-
return err;
304
+
"in mangle, dropping packet\n");
305
+
return -ENOMEM;
306
306
}
307
+
kfree_skb(e->skb);
308
+
e->skb = nskb;
307
309
}
308
310
skb_put(e->skb, diff);
309
311
}
+4
-11
net/ipv6/ip6_tunnel.c
+4
-11
net/ipv6/ip6_tunnel.c
···
229
229
char name[IFNAMSIZ];
230
230
int err;
231
231
232
-
if (p->name[0]) {
232
+
if (p->name[0])
233
233
strlcpy(name, p->name, IFNAMSIZ);
234
-
} else {
235
-
int i;
236
-
for (i = 1; i < IP6_TNL_MAX; i++) {
237
-
sprintf(name, "ip6tnl%d", i);
238
-
if (__dev_get_by_name(&init_net, name) == NULL)
239
-
break;
240
-
}
241
-
if (i == IP6_TNL_MAX)
242
-
goto failed;
243
-
}
234
+
else
235
+
sprintf(name, "ip6tnl%%d");
236
+
244
237
dev = alloc_netdev(sizeof (*t), name, ip6_tnl_dev_setup);
245
238
if (dev == NULL)
246
239
goto failed;
+6
-4
net/ipv6/netfilter/ip6_queue.c
+6
-4
net/ipv6/netfilter/ip6_queue.c
···
285
285
ipq_mangle_ipv6(ipq_verdict_msg_t *v, struct nf_queue_entry *e)
286
286
{
287
287
int diff;
288
-
int err;
289
288
struct ipv6hdr *user_iph = (struct ipv6hdr *)v->payload;
289
+
struct sk_buff *nskb;
290
290
291
291
if (v->data_len < sizeof(*user_iph))
292
292
return 0;
···
298
298
if (v->data_len > 0xFFFF)
299
299
return -EINVAL;
300
300
if (diff > skb_tailroom(e->skb)) {
301
-
err = pskb_expand_head(e->skb, 0,
301
+
nskb = skb_copy_expand(e->skb, 0,
302
302
diff - skb_tailroom(e->skb),
303
303
GFP_ATOMIC);
304
-
if (err) {
304
+
if (!nskb) {
305
305
printk(KERN_WARNING "ip6_queue: OOM "
306
306
"in mangle, dropping packet\n");
307
-
return err;
307
+
return -ENOMEM;
308
308
}
309
+
kfree_skb(e->skb);
310
+
e->skb = nskb;
309
311
}
310
312
skb_put(e->skb, diff);
311
313
}
+2
-10
net/ipv6/sit.c
+2
-10
net/ipv6/sit.c
···
164
164
165
165
if (parms->name[0])
166
166
strlcpy(name, parms->name, IFNAMSIZ);
167
-
else {
168
-
int i;
169
-
for (i=1; i<100; i++) {
170
-
sprintf(name, "sit%d", i);
171
-
if (__dev_get_by_name(&init_net, name) == NULL)
172
-
break;
173
-
}
174
-
if (i==100)
175
-
goto failed;
176
-
}
167
+
else
168
+
sprintf(name, "sit%%d");
177
169
178
170
dev = alloc_netdev(sizeof(*t), name, ipip6_tunnel_setup);
179
171
if (dev == NULL)
+6
-4
net/netfilter/nfnetlink_queue.c
+6
-4
net/netfilter/nfnetlink_queue.c
···
443
443
static int
444
444
nfqnl_mangle(void *data, int data_len, struct nf_queue_entry *e)
445
445
{
446
+
struct sk_buff *nskb;
446
447
int diff;
447
-
int err;
448
448
449
449
diff = data_len - e->skb->len;
450
450
if (diff < 0) {
···
454
454
if (data_len > 0xFFFF)
455
455
return -EINVAL;
456
456
if (diff > skb_tailroom(e->skb)) {
457
-
err = pskb_expand_head(e->skb, 0,
457
+
nskb = skb_copy_expand(e->skb, 0,
458
458
diff - skb_tailroom(e->skb),
459
459
GFP_ATOMIC);
460
-
if (err) {
460
+
if (!nskb) {
461
461
printk(KERN_WARNING "nf_queue: OOM "
462
462
"in mangle, dropping packet\n");
463
-
return err;
463
+
return -ENOMEM;
464
464
}
465
+
kfree_skb(e->skb);
466
+
e->skb = nskb;
465
467
}
466
468
skb_put(e->skb, diff);
467
469
}
-3
net/netfilter/xt_hashlimit.c
-3
net/netfilter/xt_hashlimit.c
+1
-1
net/netfilter/xt_iprange.c
+1
-1
net/netfilter/xt_iprange.c
+5
-6
net/netfilter/xt_u32.c
+5
-6
net/netfilter/xt_u32.c
···
26
26
u_int32_t pos;
27
27
u_int32_t val;
28
28
u_int32_t at;
29
-
int ret;
30
29
31
30
/*
32
31
* Small example: "0 >> 28 == 4 && 8 & 0xFF0000 >> 16 = 6, 17"
···
39
40
if (skb->len < 4 || pos > skb->len - 4)
40
41
return false;
41
42
42
-
ret = skb_copy_bits(skb, pos, &n, sizeof(n));
43
-
BUG_ON(ret < 0);
43
+
if (skb_copy_bits(skb, pos, &n, sizeof(n)) < 0)
44
+
BUG();
44
45
val = ntohl(n);
45
46
nnums = ct->nnums;
46
47
···
66
67
pos > skb->len - at - 4)
67
68
return false;
68
69
69
-
ret = skb_copy_bits(skb, at + pos, &n,
70
-
sizeof(n));
71
-
BUG_ON(ret < 0);
70
+
if (skb_copy_bits(skb, at + pos, &n,
71
+
sizeof(n)) < 0)
72
+
BUG();
72
73
val = ntohl(n);
73
74
break;
74
75
}
+2
net/sctp/socket.c
+2
net/sctp/socket.c
···
6488
6488
.memory_pressure = &sctp_memory_pressure,
6489
6489
.enter_memory_pressure = sctp_enter_memory_pressure,
6490
6490
.memory_allocated = &sctp_memory_allocated,
6491
+
.sockets_allocated = &sctp_sockets_allocated,
6491
6492
REF_PROTO_INUSE(sctp)
6492
6493
};
6493
6494
···
6522
6521
.memory_pressure = &sctp_memory_pressure,
6523
6522
.enter_memory_pressure = sctp_enter_memory_pressure,
6524
6523
.memory_allocated = &sctp_memory_allocated,
6524
+
.sockets_allocated = &sctp_sockets_allocated,
6525
6525
REF_PROTO_INUSE(sctpv6)
6526
6526
};
6527
6527
#endif /* defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) */