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Merge tag 'riscv-for-linus-5.9-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fixes from Palmer Dabbelt:

- A fix for a lockdep issue to avoid an asserting triggering during
early boot. There shouldn't be any incorrect behavior as the system
isn't concurrent at the time.

- The addition of a missing fence when installing early fixmap
mappings.

- A corretion to the K210 device tree's interrupt map.

- A fix for M-mode timer handling on the K210.

* tag 'riscv-for-linus-5.9-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
RISC-V: Resurrect the MMIO timer implementation for M-mode systems
riscv: Fix Kendryte K210 device tree
riscv: Add sfence.vma after early page table changes
RISC-V: Take text_mutex in ftrace_init_nop()

+104 -6
+1
arch/riscv/Kconfig
··· 32 32 select ARCH_WANT_FRAME_POINTERS 33 33 select ARCH_WANT_HUGE_PMD_SHARE if 64BIT 34 34 select CLONE_BACKWARDS 35 + select CLINT_TIMER if !MMU 35 36 select COMMON_CLK 36 37 select EDAC_SUPPORT 37 38 select GENERIC_ARCH_TOPOLOGY if SMP
+4 -2
arch/riscv/boot/dts/kendryte/k210.dtsi
··· 95 95 #clock-cells = <1>; 96 96 }; 97 97 98 - clint0: interrupt-controller@2000000 { 98 + clint0: clint@2000000 { 99 + #interrupt-cells = <1>; 99 100 compatible = "riscv,clint0"; 100 101 reg = <0x2000000 0xC000>; 101 - interrupts-extended = <&cpu0_intc 3>, <&cpu1_intc 3>; 102 + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 103 + &cpu1_intc 3 &cpu1_intc 7>; 102 104 clocks = <&sysctl K210_CLK_ACLK>; 103 105 }; 104 106
+26
arch/riscv/include/asm/clint.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0-only */ 2 + /* 3 + * Copyright (C) 2020 Google, Inc 4 + */ 5 + 6 + #ifndef _ASM_RISCV_CLINT_H 7 + #define _ASM_RISCV_CLINT_H 8 + 9 + #include <linux/types.h> 10 + #include <asm/mmio.h> 11 + 12 + #ifdef CONFIG_RISCV_M_MODE 13 + /* 14 + * This lives in the CLINT driver, but is accessed directly by timex.h to avoid 15 + * any overhead when accessing the MMIO timer. 16 + * 17 + * The ISA defines mtime as a 64-bit memory-mapped register that increments at 18 + * a constant frequency, but it doesn't define some other constraints we depend 19 + * on (most notably ordering constraints, but also some simpler stuff like the 20 + * memory layout). Thus, this is called "clint_time_val" instead of something 21 + * like "riscv_mtime", to signify that these non-ISA assumptions must hold. 22 + */ 23 + extern u64 __iomem *clint_time_val; 24 + #endif 25 + 26 + #endif
+7
arch/riscv/include/asm/ftrace.h
··· 66 66 * Let auipc+jalr be the basic *mcount unit*, so we make it 8 bytes here. 67 67 */ 68 68 #define MCOUNT_INSN_SIZE 8 69 + 70 + #ifndef __ASSEMBLY__ 71 + struct dyn_ftrace; 72 + int ftrace_init_nop(struct module *mod, struct dyn_ftrace *rec); 73 + #define ftrace_init_nop ftrace_init_nop 74 + #endif 75 + 69 76 #endif 70 77 71 78 #endif /* _ASM_RISCV_FTRACE_H */
+27
arch/riscv/include/asm/timex.h
··· 10 10 11 11 typedef unsigned long cycles_t; 12 12 13 + #ifdef CONFIG_RISCV_M_MODE 14 + 15 + #include <asm/clint.h> 16 + 17 + #ifdef CONFIG_64BIT 18 + static inline cycles_t get_cycles(void) 19 + { 20 + return readq_relaxed(clint_time_val); 21 + } 22 + #else /* !CONFIG_64BIT */ 23 + static inline u32 get_cycles(void) 24 + { 25 + return readl_relaxed(((u32 *)clint_time_val)); 26 + } 27 + #define get_cycles get_cycles 28 + 29 + static inline u32 get_cycles_hi(void) 30 + { 31 + return readl_relaxed(((u32 *)clint_time_val) + 1); 32 + } 33 + #define get_cycles_hi get_cycles_hi 34 + #endif /* CONFIG_64BIT */ 35 + 36 + #else /* CONFIG_RISCV_M_MODE */ 37 + 13 38 static inline cycles_t get_cycles(void) 14 39 { 15 40 return csr_read(CSR_TIME); ··· 65 40 return ((u64)hi << 32) | lo; 66 41 } 67 42 #endif /* CONFIG_64BIT */ 43 + 44 + #endif /* !CONFIG_RISCV_M_MODE */ 68 45 69 46 #define ARCH_HAS_READ_CURRENT_TIMER 70 47 static inline int read_current_timer(unsigned long *timer_val)
+19
arch/riscv/kernel/ftrace.c
··· 97 97 return __ftrace_modify_call(rec->ip, addr, false); 98 98 } 99 99 100 + 101 + /* 102 + * This is called early on, and isn't wrapped by 103 + * ftrace_arch_code_modify_{prepare,post_process}() and therefor doesn't hold 104 + * text_mutex, which triggers a lockdep failure. SMP isn't running so we could 105 + * just directly poke the text, but it's simpler to just take the lock 106 + * ourselves. 107 + */ 108 + int ftrace_init_nop(struct module *mod, struct dyn_ftrace *rec) 109 + { 110 + int out; 111 + 112 + ftrace_arch_code_modify_prepare(); 113 + out = ftrace_make_nop(mod, rec, MCOUNT_ADDR); 114 + ftrace_arch_code_modify_post_process(); 115 + 116 + return out; 117 + } 118 + 100 119 int ftrace_update_ftrace_func(ftrace_func_t func) 101 120 { 102 121 int ret = __ftrace_modify_call((unsigned long)&ftrace_call,
+3 -4
arch/riscv/mm/init.c
··· 226 226 227 227 ptep = &fixmap_pte[pte_index(addr)]; 228 228 229 - if (pgprot_val(prot)) { 229 + if (pgprot_val(prot)) 230 230 set_pte(ptep, pfn_pte(phys >> PAGE_SHIFT, prot)); 231 - } else { 231 + else 232 232 pte_clear(&init_mm, addr, ptep); 233 - local_flush_tlb_page(addr); 234 - } 233 + local_flush_tlb_page(addr); 235 234 } 236 235 237 236 static pte_t *__init get_pte_virt(phys_addr_t pa)
+17
drivers/clocksource/timer-clint.c
··· 19 19 #include <linux/interrupt.h> 20 20 #include <linux/of_irq.h> 21 21 #include <linux/smp.h> 22 + #include <linux/timex.h> 23 + 24 + #ifndef CONFIG_RISCV_M_MODE 25 + #include <asm/clint.h> 26 + #endif 22 27 23 28 #define CLINT_IPI_OFF 0 24 29 #define CLINT_TIMER_CMP_OFF 0x4000 ··· 35 30 static u64 __iomem *clint_timer_val; 36 31 static unsigned long clint_timer_freq; 37 32 static unsigned int clint_timer_irq; 33 + 34 + #ifdef CONFIG_RISCV_M_MODE 35 + u64 __iomem *clint_time_val; 36 + #endif 38 37 39 38 static void clint_send_ipi(const struct cpumask *target) 40 39 { ··· 192 183 clint_timer_cmp = base + CLINT_TIMER_CMP_OFF; 193 184 clint_timer_val = base + CLINT_TIMER_VAL_OFF; 194 185 clint_timer_freq = riscv_timebase; 186 + 187 + #ifdef CONFIG_RISCV_M_MODE 188 + /* 189 + * Yes, that's an odd naming scheme. time_val is public, but hopefully 190 + * will die in favor of something cleaner. 191 + */ 192 + clint_time_val = clint_timer_val; 193 + #endif 195 194 196 195 pr_info("%pOFP: timer running at %ld Hz\n", np, clint_timer_freq); 197 196