tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

Merge tag 'fixes-3.3-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

These are the bug fixes that have accumulated since 3.3-rc3 in arm-soc.
The majority of them are regression fixes for stuff that broke during
the merge 3.3 window.

The notable ones are:

* The at91 ata drivers both broke because of an earlier cleanup patch that
some other patches were based on. Jean-Christophe decided to remove
the legacy at91_ide driver and fix the new-style at91-pata driver while
keeping the cleanup patch. I almost rejected the patches for being too
late and too big but in the end decided to accept them because they
fix a regression.

* A patch fixing build breakage from the sysdev-to-device conversion
colliding with other changes touches a number of mach-s3c files.

* b0654037 "ARM: orion: Fix Orion5x GPIO regression from MPP cleanup"
is a mechanical change that unfortunately touches a lot of lines
that should up in the diffstat.

* tag 'fixes-3.3-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (28 commits)
ARM: at91: drop ide driver in favor of the pata one
pata/at91: use newly introduced SMC accessors
ARM: at91: add accessor to manage SMC
ARM: at91:rtc/rtc-at91sam9: ioremap register bank
ARM: at91: USB AT91 gadget registration for module
ep93xx: fix build of vision_ep93xx.c
ARM: OMAP2xxx: PM: fix OMAP2xxx-specific UART idle bug in v3.3
ARM: orion: Fix USB phy for orion5x.
ARM: orion: Fix Orion5x GPIO regression from MPP cleanup
ARM: EXYNOS: Add cpu-offset property in gic device tree node
ARM: EXYNOS: Bring exynos4-dt up to date
ARM: OMAP3: cm-t35: fix section mismatch warning
ARM: OMAP2: Fix the OMAP2 only build break seen with 2011+ ARM tool-chains
ARM: tegra: paz00: fix wrong UART port on mini-pcie plug
ARM: tegra: paz00: fix wrong SD1 power gpio
i2c: tegra: Add devexit_p() for remove
ARM: EXYNOS: Correct M-5MOLS sensor clock frequency on Universal C210 board
ARM: EXYNOS: Correct framebuffer window size on Nuri board
ARM: SAMSUNG: Fix missing api-change from subsys_interface change
ARM: EXYNOS: Fix "warning: initialization from incompatible pointer type"
...

Linus Torvalds be2874cb 584216b7

+523 -785
+1
arch/arm/boot/dts/exynos4210.dtsi
··· 29 29 compatible = "arm,cortex-a9-gic"; 30 30 #interrupt-cells = <3>; 31 31 interrupt-controller; 32 + cpu-offset = <0x8000>; 32 33 reg = <0x10490000 0x1000>, <0x10480000 0x100>; 33 34 }; 34 35
+3 -3
arch/arm/boot/dts/tegra-paz00.dts
··· 46 46 }; 47 47 48 48 serial@70006200 { 49 - status = "disable"; 49 + clock-frequency = <216000000>; 50 50 }; 51 51 52 52 serial@70006300 { 53 - clock-frequency = <216000000>; 53 + status = "disable"; 54 54 }; 55 55 56 56 serial@70006400 { ··· 60 60 sdhci@c8000000 { 61 61 cd-gpios = <&gpio 173 0>; /* gpio PV5 */ 62 62 wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 63 - power-gpios = <&gpio 155 0>; /* gpio PT3 */ 63 + power-gpios = <&gpio 169 0>; /* gpio PV1 */ 64 64 }; 65 65 66 66 sdhci@c8000200 {
+1 -1
arch/arm/mach-at91/at91rm9200_devices.c
··· 83 83 * USB Device (Gadget) 84 84 * -------------------------------------------------------------------- */ 85 85 86 - #ifdef CONFIG_USB_AT91 86 + #if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE) 87 87 static struct at91_udc_data udc_data; 88 88 89 89 static struct resource udc_resources[] = {
+3 -6
arch/arm/mach-at91/at91sam9260_devices.c
··· 84 84 * USB Device (Gadget) 85 85 * -------------------------------------------------------------------- */ 86 86 87 - #ifdef CONFIG_USB_AT91 87 + #if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE) 88 88 static struct at91_udc_data udc_data; 89 89 90 90 static struct resource udc_resources[] = { ··· 1215 1215 * CF/IDE 1216 1216 * -------------------------------------------------------------------- */ 1217 1217 1218 - #if defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE) || \ 1219 - defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \ 1218 + #if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \ 1220 1219 defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) 1221 1220 1222 1221 static struct at91_cf_data cf0_data; ··· 1312 1313 if (data->flags & AT91_CF_TRUE_IDE) 1313 1314 #if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) 1314 1315 pdev->name = "pata_at91"; 1315 - #elif defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE) 1316 - pdev->name = "at91_ide"; 1317 1316 #else 1318 - #warning "board requires AT91_CF_TRUE_IDE: enable either at91_ide or pata_at91" 1317 + #warning "board requires AT91_CF_TRUE_IDE: enable pata_at91" 1319 1318 #endif 1320 1319 else 1321 1320 pdev->name = "at91_cf";
+1 -1
arch/arm/mach-at91/at91sam9261_devices.c
··· 87 87 * USB Device (Gadget) 88 88 * -------------------------------------------------------------------- */ 89 89 90 - #ifdef CONFIG_USB_AT91 90 + #if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE) 91 91 static struct at91_udc_data udc_data; 92 92 93 93 static struct resource udc_resources[] = {
+4 -4
arch/arm/mach-at91/at91sam9263_devices.c
··· 92 92 * USB Device (Gadget) 93 93 * -------------------------------------------------------------------- */ 94 94 95 - #ifdef CONFIG_USB_AT91 95 + #if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE) 96 96 static struct at91_udc_data udc_data; 97 97 98 98 static struct resource udc_resources[] = { ··· 355 355 * Compact Flash (PCMCIA or IDE) 356 356 * -------------------------------------------------------------------- */ 357 357 358 - #if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) || \ 359 - defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE) 358 + #if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \ 359 + defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) 360 360 361 361 static struct at91_cf_data cf0_data; 362 362 ··· 450 450 at91_set_A_periph(AT91_PIN_PD9, 0); /* CFCE2 */ 451 451 at91_set_A_periph(AT91_PIN_PD14, 0); /* CFNRW */ 452 452 453 - pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "at91_ide" : "at91_cf"; 453 + pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "pata_at91" : "at91_cf"; 454 454 platform_device_register(pdev); 455 455 } 456 456 #else
+29
arch/arm/mach-at91/include/mach/at91sam9_smc.h
··· 18 18 19 19 #include <mach/cpu.h> 20 20 21 + #ifndef __ASSEMBLY__ 22 + struct sam9_smc_config { 23 + /* Setup register */ 24 + u8 ncs_read_setup; 25 + u8 nrd_setup; 26 + u8 ncs_write_setup; 27 + u8 nwe_setup; 28 + 29 + /* Pulse register */ 30 + u8 ncs_read_pulse; 31 + u8 nrd_pulse; 32 + u8 ncs_write_pulse; 33 + u8 nwe_pulse; 34 + 35 + /* Cycle register */ 36 + u16 read_cycle; 37 + u16 write_cycle; 38 + 39 + /* Mode register */ 40 + u32 mode; 41 + u8 tdf_cycles:4; 42 + }; 43 + 44 + extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config); 45 + extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config); 46 + extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config *config); 47 + extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config); 48 + #endif 49 + 21 50 #define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */ 22 51 #define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ 23 52 #define AT91_SMC_NWESETUP_(x) ((x) << 0)
+71 -5
arch/arm/mach-at91/sam9_smc.c
··· 2 2 * linux/arch/arm/mach-at91/sam9_smc.c 3 3 * 4 4 * Copyright (C) 2008 Andrew Victor 5 + * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 5 6 * 6 7 * This program is free software; you can redistribute it and/or modify 7 8 * it under the terms of the GNU General Public License version 2 as ··· 23 22 24 23 static void __iomem *smc_base_addr[2]; 25 24 26 - static void __init sam9_smc_cs_configure(void __iomem *base, struct sam9_smc_config* config) 25 + static void sam9_smc_cs_write_mode(void __iomem *base, 26 + struct sam9_smc_config *config) 27 + { 28 + __raw_writel(config->mode 29 + | AT91_SMC_TDF_(config->tdf_cycles), 30 + base + AT91_SMC_MODE); 31 + } 32 + 33 + void sam9_smc_write_mode(int id, int cs, 34 + struct sam9_smc_config *config) 35 + { 36 + sam9_smc_cs_write_mode(AT91_SMC_CS(id, cs), config); 37 + } 38 + 39 + static void sam9_smc_cs_configure(void __iomem *base, 40 + struct sam9_smc_config *config) 27 41 { 28 42 29 43 /* Setup register */ ··· 61 45 base + AT91_SMC_CYCLE); 62 46 63 47 /* Mode register */ 64 - __raw_writel(config->mode 65 - | AT91_SMC_TDF_(config->tdf_cycles), 66 - base + AT91_SMC_MODE); 48 + sam9_smc_cs_write_mode(base, config); 67 49 } 68 50 69 - void __init sam9_smc_configure(int id, int cs, struct sam9_smc_config* config) 51 + void sam9_smc_configure(int id, int cs, 52 + struct sam9_smc_config *config) 70 53 { 71 54 sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config); 55 + } 56 + 57 + static void sam9_smc_cs_read_mode(void __iomem *base, 58 + struct sam9_smc_config *config) 59 + { 60 + u32 val = __raw_readl(base + AT91_SMC_MODE); 61 + 62 + config->mode = (val & ~AT91_SMC_NWECYCLE); 63 + config->tdf_cycles = (val & AT91_SMC_NWECYCLE) >> 16 ; 64 + } 65 + 66 + void sam9_smc_read_mode(int id, int cs, 67 + struct sam9_smc_config *config) 68 + { 69 + sam9_smc_cs_read_mode(AT91_SMC_CS(id, cs), config); 70 + } 71 + 72 + static void sam9_smc_cs_read(void __iomem *base, 73 + struct sam9_smc_config *config) 74 + { 75 + u32 val; 76 + 77 + /* Setup register */ 78 + val = __raw_readl(base + AT91_SMC_SETUP); 79 + 80 + config->nwe_setup = val & AT91_SMC_NWESETUP; 81 + config->ncs_write_setup = (val & AT91_SMC_NCS_WRSETUP) >> 8; 82 + config->nrd_setup = (val & AT91_SMC_NRDSETUP) >> 16; 83 + config->ncs_read_setup = (val & AT91_SMC_NCS_RDSETUP) >> 24; 84 + 85 + /* Pulse register */ 86 + val = __raw_readl(base + AT91_SMC_PULSE); 87 + 88 + config->nwe_setup = val & AT91_SMC_NWEPULSE; 89 + config->ncs_write_pulse = (val & AT91_SMC_NCS_WRPULSE) >> 8; 90 + config->nrd_pulse = (val & AT91_SMC_NRDPULSE) >> 16; 91 + config->ncs_read_pulse = (val & AT91_SMC_NCS_RDPULSE) >> 24; 92 + 93 + /* Cycle register */ 94 + val = __raw_readl(base + AT91_SMC_CYCLE); 95 + 96 + config->write_cycle = val & AT91_SMC_NWECYCLE; 97 + config->read_cycle = (val & AT91_SMC_NRDCYCLE) >> 16; 98 + 99 + /* Mode register */ 100 + sam9_smc_cs_read_mode(base, config); 101 + } 102 + 103 + void sam9_smc_read(int id, int cs, struct sam9_smc_config *config) 104 + { 105 + sam9_smc_cs_read(AT91_SMC_CS(id, cs), config); 72 106 } 73 107 74 108 void __init at91sam9_ioremap_smc(int id, u32 addr)
-23
arch/arm/mach-at91/sam9_smc.h
··· 8 8 * published by the Free Software Foundation. 9 9 */ 10 10 11 - struct sam9_smc_config { 12 - /* Setup register */ 13 - u8 ncs_read_setup; 14 - u8 nrd_setup; 15 - u8 ncs_write_setup; 16 - u8 nwe_setup; 17 - 18 - /* Pulse register */ 19 - u8 ncs_read_pulse; 20 - u8 nrd_pulse; 21 - u8 ncs_write_pulse; 22 - u8 nwe_pulse; 23 - 24 - /* Cycle register */ 25 - u16 read_cycle; 26 - u16 write_cycle; 27 - 28 - /* Mode register */ 29 - u32 mode; 30 - u8 tdf_cycles:4; 31 - }; 32 - 33 - extern void __init sam9_smc_configure(int id, int cs, struct sam9_smc_config* config); 34 11 extern void __init at91sam9_ioremap_smc(int id, u32 addr);
+2 -1
arch/arm/mach-dove/common.c
··· 28 28 #include <asm/mach/arch.h> 29 29 #include <linux/irq.h> 30 30 #include <plat/time.h> 31 + #include <plat/ehci-orion.h> 31 32 #include <plat/common.h> 32 33 #include <plat/addr-map.h> 33 34 #include "common.h" ··· 72 71 ****************************************************************************/ 73 72 void __init dove_ehci0_init(void) 74 73 { 75 - orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0); 74 + orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA); 76 75 } 77 76 78 77 /*****************************************************************************
+3 -1
arch/arm/mach-ep93xx/vision_ep9307.c
··· 32 32 #include <mach/hardware.h> 33 33 #include <mach/fb.h> 34 34 #include <mach/ep93xx_spi.h> 35 + #include <mach/gpio-ep93xx.h> 35 36 36 37 #include <asm/mach-types.h> 37 38 #include <asm/mach/map.h> ··· 154 153 }, { 155 154 I2C_BOARD_INFO("pca9539", 0x74), 156 155 .platform_data = &pca953x_74_gpio_data, 157 - .irq = gpio_to_irq(EP93XX_GPIO_LINE_F(7)), 158 156 }, { 159 157 I2C_BOARD_INFO("pca9539", 0x75), 160 158 .platform_data = &pca953x_75_gpio_data, ··· 347 347 if (gpio_request_one(EP93XX_GPIO_LINE_F(7), GPIOF_DIR_IN, 348 348 "pca9539:74")) 349 349 pr_warn("cannot request interrupt gpio for pca9539:74\n"); 350 + 351 + vision_i2c_info[1].irq = gpio_to_irq(EP93XX_GPIO_LINE_F(7)); 350 352 351 353 ep93xx_register_i2c(&vision_i2c_gpio_data, vision_i2c_info, 352 354 ARRAY_SIZE(vision_i2c_info));
+2
arch/arm/mach-exynos/clock-exynos4210.c
··· 32 32 33 33 #include "common.h" 34 34 35 + #ifdef CONFIG_PM_SLEEP 35 36 static struct sleep_save exynos4210_clock_save[] = { 36 37 SAVE_ITEM(S5P_CLKSRC_IMAGE), 37 38 SAVE_ITEM(S5P_CLKSRC_LCD1), ··· 43 42 SAVE_ITEM(S5P_CLKGATE_IP_LCD1), 44 43 SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210), 45 44 }; 45 + #endif 46 46 47 47 static struct clksrc_clk *sysclks[] = { 48 48 /* nothing here yet */
+2
arch/arm/mach-exynos/clock-exynos4212.c
··· 32 32 33 33 #include "common.h" 34 34 35 + #ifdef CONFIG_PM_SLEEP 35 36 static struct sleep_save exynos4212_clock_save[] = { 36 37 SAVE_ITEM(S5P_CLKSRC_IMAGE), 37 38 SAVE_ITEM(S5P_CLKDIV_IMAGE), 38 39 SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212), 39 40 SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212), 40 41 }; 42 + #endif 41 43 42 44 static struct clk *clk_src_mpll_user_list[] = { 43 45 [0] = &clk_fin_mpll,
+2
arch/arm/mach-exynos/clock.c
··· 30 30 31 31 #include "common.h" 32 32 33 + #ifdef CONFIG_PM_SLEEP 33 34 static struct sleep_save exynos4_clock_save[] = { 34 35 SAVE_ITEM(S5P_CLKDIV_LEFTBUS), 35 36 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS), ··· 94 93 SAVE_ITEM(S5P_CLKGATE_SCLKCPU), 95 94 SAVE_ITEM(S5P_CLKGATE_IP_CPU), 96 95 }; 96 + #endif 97 97 98 98 struct clk clk_sclk_hdmi27m = { 99 99 .name = "sclk_hdmi27m",
+6 -2
arch/arm/mach-exynos/mach-exynos4-dt.c
··· 15 15 #include <linux/serial_core.h> 16 16 17 17 #include <asm/mach/arch.h> 18 + #include <asm/hardware/gic.h> 18 19 #include <mach/map.h> 19 20 20 21 #include <plat/cpu.h> 21 22 #include <plat/regs-serial.h> 22 - #include <plat/exynos4.h> 23 + 24 + #include "common.h" 23 25 24 26 /* 25 27 * The following lookup table is used to override device names when devices ··· 62 60 63 61 static void __init exynos4210_dt_map_io(void) 64 62 { 65 - s5p_init_io(NULL, 0, S5P_VA_CHIPID); 63 + exynos_init_io(NULL, 0); 66 64 s3c24xx_init_clocks(24000000); 67 65 } 68 66 ··· 81 79 /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */ 82 80 .init_irq = exynos4_init_irq, 83 81 .map_io = exynos4210_dt_map_io, 82 + .handle_irq = gic_handle_irq, 84 83 .init_machine = exynos4210_dt_machine_init, 85 84 .timer = &exynos4_timer, 86 85 .dt_compat = exynos4210_dt_compat, 86 + .restart = exynos4_restart, 87 87 MACHINE_END
+4 -4
arch/arm/mach-exynos/mach-nuri.c
··· 220 220 .lower_margin = 1, 221 221 .hsync_len = 48, 222 222 .vsync_len = 3, 223 - .xres = 1280, 224 - .yres = 800, 223 + .xres = 1024, 224 + .yres = 600, 225 225 .refresh = 60, 226 226 }, 227 227 .max_bpp = 24, 228 228 .default_bpp = 16, 229 - .virtual_x = 1280, 230 - .virtual_y = 800, 229 + .virtual_x = 1024, 230 + .virtual_y = 2 * 600, 231 231 }; 232 232 233 233 static struct s3c_fb_platdata nuri_fb_pdata __initdata = {
+1 -1
arch/arm/mach-exynos/mach-universal_c210.c
··· 910 910 .bus_type = FIMC_MIPI_CSI2, 911 911 .board_info = &m5mols_board_info, 912 912 .i2c_bus_num = 0, 913 - .clk_frequency = 21600000UL, 913 + .clk_frequency = 24000000UL, 914 914 .csi_data_align = 32, 915 915 }, 916 916 };
+3 -1
arch/arm/mach-exynos/pm.c
··· 206 206 207 207 } 208 208 209 - static int exynos4_pm_add(struct device *dev) 209 + static int exynos4_pm_add(struct device *dev, struct subsys_interface *sif) 210 210 { 211 211 pm_cpu_prep = exynos4_pm_prepare; 212 212 pm_cpu_sleep = exynos4_cpu_suspend; ··· 384 384 385 385 exynos4_restore_pll(); 386 386 387 + #ifdef CONFIG_SMP 387 388 scu_enable(S5P_VA_SCU); 389 + #endif 388 390 389 391 #ifdef CONFIG_CACHE_L2X0 390 392 s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
+2 -1
arch/arm/mach-kirkwood/common.c
··· 27 27 #include <plat/cache-feroceon-l2.h> 28 28 #include <plat/mvsdio.h> 29 29 #include <plat/orion_nand.h> 30 + #include <plat/ehci-orion.h> 30 31 #include <plat/common.h> 31 32 #include <plat/time.h> 32 33 #include <plat/addr-map.h> ··· 74 73 void __init kirkwood_ehci_init(void) 75 74 { 76 75 kirkwood_clk_ctrl |= CGC_USB0; 77 - orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB); 76 + orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA); 78 77 } 79 78 80 79
+160 -160
arch/arm/mach-kirkwood/mpp.h
··· 31 31 #define MPP_F6282_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 0, 1 ) 32 32 33 33 #define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 34 - #define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 35 - #define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 34 + #define MPP0_NF_IO2 MPP( 0, 0x1, 0, 0, 1, 1, 1, 1, 1 ) 35 + #define MPP0_SPI_SCn MPP( 0, 0x2, 0, 0, 1, 1, 1, 1, 1 ) 36 36 37 37 #define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 38 - #define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 39 - #define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 38 + #define MPP1_NF_IO3 MPP( 1, 0x1, 0, 0, 1, 1, 1, 1, 1 ) 39 + #define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 0, 1, 1, 1, 1, 1 ) 40 40 41 41 #define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 42 - #define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 43 - #define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 42 + #define MPP2_NF_IO4 MPP( 2, 0x1, 0, 0, 1, 1, 1, 1, 1 ) 43 + #define MPP2_SPI_SCK MPP( 2, 0x2, 0, 0, 1, 1, 1, 1, 1 ) 44 44 45 45 #define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 46 - #define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 47 - #define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1, 1 ) 46 + #define MPP3_NF_IO5 MPP( 3, 0x1, 0, 0, 1, 1, 1, 1, 1 ) 47 + #define MPP3_SPI_MISO MPP( 3, 0x2, 0, 0, 1, 1, 1, 1, 1 ) 48 48 49 49 #define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 50 - #define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 51 - #define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1, 1 ) 52 - #define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1, 1 ) 50 + #define MPP4_NF_IO6 MPP( 4, 0x1, 0, 0, 1, 1, 1, 1, 1 ) 51 + #define MPP4_UART0_RXD MPP( 4, 0x2, 0, 0, 1, 1, 1, 1, 1 ) 52 + #define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 0, 0, 0, 1, 1, 1 ) 53 53 #define MPP4_LCD_VGA_HSYNC MPP( 4, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 54 - #define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1, 0 ) 54 + #define MPP4_PTP_CLK MPP( 4, 0xd, 0, 0, 1, 1, 1, 1, 0 ) 55 55 56 56 #define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 57 - #define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 58 - #define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 59 - #define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1, 0 ) 60 - #define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1, 1 ) 57 + #define MPP5_NF_IO7 MPP( 5, 0x1, 0, 0, 1, 1, 1, 1, 1 ) 58 + #define MPP5_UART0_TXD MPP( 5, 0x2, 0, 0, 1, 1, 1, 1, 1 ) 59 + #define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 0, 1, 1, 1, 1, 0 ) 60 + #define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 0, 0, 1, 1, 1, 1 ) 61 61 #define MPP5_LCD_VGA_VSYNC MPP( 5, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 62 62 63 - #define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1, 1 ) 64 - #define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 65 - #define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1, 0 ) 63 + #define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 0, 1, 1, 1, 1, 1 ) 64 + #define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 0, 1, 1, 1, 1, 1 ) 65 + #define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 0, 1, 1, 1, 1, 0 ) 66 66 67 67 #define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 68 - #define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1, 0 ) 69 - #define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 70 - #define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1, 0 ) 71 - #define MPP7_LCD_PWM MPP( 7, 0xb, 0, 1, 0, 0, 0, 0, 1 ) 68 + #define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 0, 1, 1, 1, 1, 0 ) 69 + #define MPP7_SPI_SCn MPP( 7, 0x2, 0, 0, 1, 1, 1, 1, 1 ) 70 + #define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 0, 1, 1, 1, 1, 0 ) 71 + #define MPP7_LCD_PWM MPP( 7, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 72 72 73 73 #define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 74 - #define MPP8_TW0_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 75 - #define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 76 - #define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1, 1 ) 77 - #define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1, 1 ) 78 - #define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1, 1 ) 79 - #define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1, 0 ) 80 - #define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1, 1 ) 74 + #define MPP8_TW0_SDA MPP( 8, 0x1, 0, 0, 1, 1, 1, 1, 1 ) 75 + #define MPP8_UART0_RTS MPP( 8, 0x2, 0, 0, 1, 1, 1, 1, 1 ) 76 + #define MPP8_UART1_RTS MPP( 8, 0x3, 0, 0, 1, 1, 1, 1, 1 ) 77 + #define MPP8_MII0_RXERR MPP( 8, 0x4, 0, 0, 0, 1, 1, 1, 1 ) 78 + #define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 0, 0, 0, 1, 1, 1 ) 79 + #define MPP8_PTP_CLK MPP( 8, 0xc, 0, 0, 1, 1, 1, 1, 0 ) 80 + #define MPP8_MII0_COL MPP( 8, 0xd, 0, 0, 1, 1, 1, 1, 1 ) 81 81 82 82 #define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 83 - #define MPP9_TW0_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 84 - #define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1, 1 ) 85 - #define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1, 1 ) 86 - #define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1, 1 ) 87 - #define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1, 0 ) 88 - #define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1, 1 ) 83 + #define MPP9_TW0_SCK MPP( 9, 0x1, 0, 0, 1, 1, 1, 1, 1 ) 84 + #define MPP9_UART0_CTS MPP( 9, 0x2, 0, 0, 1, 1, 1, 1, 1 ) 85 + #define MPP9_UART1_CTS MPP( 9, 0x3, 0, 0, 1, 1, 1, 1, 1 ) 86 + #define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 0, 0, 1, 1, 1, 1 ) 87 + #define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 0, 0, 1, 1, 1, 1, 0 ) 88 + #define MPP9_MII0_CRS MPP( 9, 0xd, 0, 0, 1, 1, 1, 1, 1 ) 89 89 90 90 #define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 91 - #define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 92 - #define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1, 1 ) 93 - #define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1, 1 ) 94 - #define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1, 0 ) 91 + #define MPP10_SPI_SCK MPP( 10, 0x2, 0, 0, 1, 1, 1, 1, 1 ) 92 + #define MPP10_UART0_TXD MPP( 10, 0X3, 0, 0, 1, 1, 1, 1, 1 ) 93 + #define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 0, 0, 0, 1, 1, 1 ) 94 + #define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 0, 1, 1, 1, 1, 0 ) 95 95 96 96 #define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 97 - #define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1, 1 ) 98 - #define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1, 1 ) 99 - #define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1, 0 ) 100 - #define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1, 0 ) 101 - #define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1, 0 ) 102 - #define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1, 1 ) 97 + #define MPP11_SPI_MISO MPP( 11, 0x2, 0, 0, 1, 1, 1, 1, 1 ) 98 + #define MPP11_UART0_RXD MPP( 11, 0x3, 0, 0, 1, 1, 1, 1, 1 ) 99 + #define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 0, 0, 1, 1, 1, 1, 0 ) 100 + #define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 0, 1, 1, 1, 1, 0 ) 101 + #define MPP11_PTP_CLK MPP( 11, 0xd, 0, 0, 1, 1, 1, 1, 0 ) 102 + #define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 0, 0, 1, 1, 1, 1 ) 103 103 104 104 #define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 105 105 #define MPP12_GPIO MPP( 12, 0x0, 1, 1, 0, 0, 0, 1, 0 ) 106 - #define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1, 1 ) 107 - #define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 1, 0, 0, 0, 0, 1 ) 108 - #define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 1, 0, 0, 0, 0, 1 ) 109 - #define MPP12_TW1_SDA MPP( 12, 0xd, 1, 0, 0, 0, 0, 0, 1 ) 106 + #define MPP12_SD_CLK MPP( 12, 0x1, 0, 0, 1, 1, 1, 1, 1 ) 107 + #define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 0, 0, 0, 0, 0, 1 ) 108 + #define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 109 + #define MPP12_TW1_SDA MPP( 12, 0xd, 0, 0, 0, 0, 0, 0, 1 ) 110 110 111 111 #define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 112 - #define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 113 - #define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1, 1 ) 114 - #define MPP13_AU_SPDIFRMCLK MPP( 13, 0xa, 0, 1, 0, 0, 0, 0, 1 ) 115 - #define MPP13_LCDPWM MPP( 13, 0xb, 0, 1, 0, 0, 0, 0, 1 ) 112 + #define MPP13_SD_CMD MPP( 13, 0x1, 0, 0, 1, 1, 1, 1, 1 ) 113 + #define MPP13_UART1_TXD MPP( 13, 0x3, 0, 0, 1, 1, 1, 1, 1 ) 114 + #define MPP13_AU_SPDIFRMCLK MPP( 13, 0xa, 0, 0, 0, 0, 0, 0, 1 ) 115 + #define MPP13_LCDPWM MPP( 13, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 116 116 117 117 #define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 118 - #define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 119 - #define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1, 1 ) 120 - #define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 121 - #define MPP14_AU_SPDIFI MPP( 14, 0xa, 1, 0, 0, 0, 0, 0, 1 ) 122 - #define MPP14_AU_I2SDI MPP( 14, 0xb, 1, 0, 0, 0, 0, 0, 1 ) 123 - #define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1, 1 ) 118 + #define MPP14_SD_D0 MPP( 14, 0x1, 0, 0, 1, 1, 1, 1, 1 ) 119 + #define MPP14_UART1_RXD MPP( 14, 0x3, 0, 0, 1, 1, 1, 1, 1 ) 120 + #define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 0, 0, 0, 1, 1, 1 ) 121 + #define MPP14_AU_SPDIFI MPP( 14, 0xa, 0, 0, 0, 0, 0, 0, 1 ) 122 + #define MPP14_AU_I2SDI MPP( 14, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 123 + #define MPP14_MII0_COL MPP( 14, 0xd, 0, 0, 1, 1, 1, 1, 1 ) 124 124 125 125 #define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 126 - #define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 127 - #define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 128 - #define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1, 1 ) 129 - #define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1, 1 ) 130 - #define MPP15_SPI_CSn MPP( 15, 0xb, 0, 1, 0, 0, 0, 0, 1 ) 126 + #define MPP15_SD_D1 MPP( 15, 0x1, 0, 0, 1, 1, 1, 1, 1 ) 127 + #define MPP15_UART0_RTS MPP( 15, 0x2, 0, 0, 1, 1, 1, 1, 1 ) 128 + #define MPP15_UART1_TXD MPP( 15, 0x3, 0, 0, 1, 1, 1, 1, 1 ) 129 + #define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 0, 0, 1, 1, 1, 1 ) 130 + #define MPP15_SPI_CSn MPP( 15, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 131 131 132 132 #define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 133 - #define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 134 - #define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1, 1 ) 135 - #define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1, 1 ) 136 - #define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 137 - #define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 1, 0, 0, 0, 0, 0, 1 ) 138 - #define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1, 1 ) 133 + #define MPP16_SD_D2 MPP( 16, 0x1, 0, 0, 1, 1, 1, 1, 1 ) 134 + #define MPP16_UART0_CTS MPP( 16, 0x2, 0, 0, 1, 1, 1, 1, 1 ) 135 + #define MPP16_UART1_RXD MPP( 16, 0x3, 0, 0, 1, 1, 1, 1, 1 ) 136 + #define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 0, 0, 0, 1, 1, 1 ) 137 + #define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 138 + #define MPP16_MII0_CRS MPP( 16, 0xd, 0, 0, 1, 1, 1, 1, 1 ) 139 139 140 140 #define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 141 - #define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 142 - #define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1, 1 ) 143 - #define MPP17_SATA1_ACTn MPP( 17, 0xa, 0, 1, 0, 0, 0, 0, 1 ) 144 - #define MPP17_TW1_SCK MPP( 17, 0xd, 1, 1, 0, 0, 0, 0, 1 ) 141 + #define MPP17_SD_D3 MPP( 17, 0x1, 0, 0, 1, 1, 1, 1, 1 ) 142 + #define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 0, 0, 1, 1, 1, 1 ) 143 + #define MPP17_SATA1_ACTn MPP( 17, 0xa, 0, 0, 0, 0, 0, 0, 1 ) 144 + #define MPP17_TW1_SCK MPP( 17, 0xd, 0, 0, 0, 0, 0, 0, 1 ) 145 145 146 146 #define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 147 - #define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 148 - #define MPP18_PEX0_CLKREQ MPP( 18, 0x2, 0, 1, 0, 0, 0, 0, 1 ) 147 + #define MPP18_NF_IO0 MPP( 18, 0x1, 0, 0, 1, 1, 1, 1, 1 ) 148 + #define MPP18_PEX0_CLKREQ MPP( 18, 0x2, 0, 0, 0, 0, 0, 0, 1 ) 149 149 150 150 #define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 151 - #define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 151 + #define MPP19_NF_IO1 MPP( 19, 0x1, 0, 0, 1, 1, 1, 1, 1 ) 152 152 153 153 #define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 154 - #define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 155 - #define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 154 + #define MPP20_TSMP0 MPP( 20, 0x1, 0, 0, 0, 0, 1, 1, 1 ) 155 + #define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 0, 0, 0, 1, 1, 1 ) 156 156 #define MPP20_GE1_TXD0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 157 - #define MPP20_AU_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1, 1 ) 158 - #define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1, 1 ) 157 + #define MPP20_AU_SPDIFI MPP( 20, 0x4, 0, 0, 0, 0, 1, 1, 1 ) 158 + #define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 0, 0, 0, 1, 1, 1 ) 159 159 #define MPP20_LCD_D0 MPP( 20, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 160 160 161 161 #define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 162 - #define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 163 - #define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 162 + #define MPP21_TSMP1 MPP( 21, 0x1, 0, 0, 0, 0, 1, 1, 1 ) 163 + #define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 0, 0, 0, 1, 1, 1 ) 164 164 #define MPP21_GE1_TXD1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 165 - #define MPP21_AU_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 166 - #define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1, 1 ) 165 + #define MPP21_AU_SPDIFO MPP( 21, 0x4, 0, 0, 0, 0, 1, 1, 1 ) 166 + #define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 0, 0, 1, 1, 1, 1 ) 167 167 #define MPP21_LCD_D1 MPP( 21, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 168 168 169 169 #define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 170 - #define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 171 - #define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 170 + #define MPP22_TSMP2 MPP( 22, 0x1, 0, 0, 0, 0, 1, 1, 1 ) 171 + #define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 0, 0, 0, 1, 1, 1 ) 172 172 #define MPP22_GE1_TXD2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 173 - #define MPP22_AU_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 174 - #define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1, 1 ) 173 + #define MPP22_AU_SPDIFRMKCLK MPP( 22, 0x4, 0, 0, 0, 0, 1, 1, 1 ) 174 + #define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 0, 0, 0, 1, 1, 1 ) 175 175 #define MPP22_LCD_D2 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 176 176 177 177 #define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 178 - #define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 179 - #define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1, 1 ) 178 + #define MPP23_TSMP3 MPP( 23, 0x1, 0, 0, 0, 0, 1, 1, 1 ) 179 + #define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 0, 0, 0, 0, 1, 1, 1 ) 180 180 #define MPP23_GE1_TXD3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 181 - #define MPP23_AU_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 182 - #define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1, 1 ) 181 + #define MPP23_AU_I2SBCLK MPP( 23, 0x4, 0, 0, 0, 0, 1, 1, 1 ) 182 + #define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 0, 0, 1, 1, 1, 1 ) 183 183 #define MPP23_LCD_D3 MPP( 23, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 184 184 185 185 #define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 186 - #define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 187 - #define MPP24_TDM_SPI_CS0 MPP( 24, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 186 + #define MPP24_TSMP4 MPP( 24, 0x1, 0, 0, 0, 0, 1, 1, 1 ) 187 + #define MPP24_TDM_SPI_CS0 MPP( 24, 0x2, 0, 0, 0, 0, 1, 1, 1 ) 188 188 #define MPP24_GE1_RXD0 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 189 - #define MPP24_AU_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 189 + #define MPP24_AU_I2SDO MPP( 24, 0x4, 0, 0, 0, 0, 1, 1, 1 ) 190 190 #define MPP24_LCD_D4 MPP( 24, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 191 191 192 192 #define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 193 - #define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 194 - #define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 193 + #define MPP25_TSMP5 MPP( 25, 0x1, 0, 0, 0, 0, 1, 1, 1 ) 194 + #define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 0, 0, 0, 1, 1, 1 ) 195 195 #define MPP25_GE1_RXD1 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 196 - #define MPP25_AU_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 196 + #define MPP25_AU_I2SLRCLK MPP( 25, 0x4, 0, 0, 0, 0, 1, 1, 1 ) 197 197 #define MPP25_LCD_D5 MPP( 25, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 198 198 199 199 #define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 200 - #define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 201 - #define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1, 1 ) 200 + #define MPP26_TSMP6 MPP( 26, 0x1, 0, 0, 0, 0, 1, 1, 1 ) 201 + #define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 0, 0, 0, 0, 1, 1, 1 ) 202 202 #define MPP26_GE1_RXD2 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 203 - #define MPP26_AU_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 203 + #define MPP26_AU_I2SMCLK MPP( 26, 0x4, 0, 0, 0, 0, 1, 1, 1 ) 204 204 #define MPP26_LCD_D6 MPP( 26, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 205 205 206 206 #define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 207 - #define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 208 - #define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 207 + #define MPP27_TSMP7 MPP( 27, 0x1, 0, 0, 0, 0, 1, 1, 1 ) 208 + #define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 0, 0, 0, 1, 1, 1 ) 209 209 #define MPP27_GE1_RXD3 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 210 - #define MPP27_AU_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1, 1 ) 210 + #define MPP27_AU_I2SDI MPP( 27, 0x4, 0, 0, 0, 0, 1, 1, 1 ) 211 211 #define MPP27_LCD_D7 MPP( 27, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 212 212 213 213 #define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 214 - #define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 214 + #define MPP28_TSMP8 MPP( 28, 0x1, 0, 0, 0, 0, 1, 1, 1 ) 215 215 #define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1, 1 ) 216 216 #define MPP28_GE1_COL MPP( 28, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 217 - #define MPP28_AU_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1, 1 ) 217 + #define MPP28_AU_EXTCLK MPP( 28, 0x4, 0, 0, 0, 0, 1, 1, 1 ) 218 218 #define MPP28_LCD_D8 MPP( 28, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 219 219 220 220 #define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 221 - #define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 221 + #define MPP29_TSMP9 MPP( 29, 0x1, 0, 0, 0, 0, 1, 1, 1 ) 222 222 #define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1, 1 ) 223 223 #define MPP29_GE1_TCLK MPP( 29, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 224 224 #define MPP29_LCD_D9 MPP( 29, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 225 225 226 226 #define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 227 - #define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 228 - #define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1, 1 ) 227 + #define MPP30_TSMP10 MPP( 30, 0x1, 0, 0, 0, 0, 1, 1, 1 ) 228 + #define MPP30_TDM_PCLK MPP( 30, 0x2, 0, 0, 0, 0, 1, 1, 1 ) 229 229 #define MPP30_GE1_RXCTL MPP( 30, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 230 230 #define MPP30_LCD_D10 MPP( 30, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 231 231 232 232 #define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 233 - #define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 234 - #define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1, 1 ) 233 + #define MPP31_TSMP11 MPP( 31, 0x1, 0, 0, 0, 0, 1, 1, 1 ) 234 + #define MPP31_TDM_FS MPP( 31, 0x2, 0, 0, 0, 0, 1, 1, 1 ) 235 235 #define MPP31_GE1_RXCLK MPP( 31, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 236 236 #define MPP31_LCD_D11 MPP( 31, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 237 237 238 238 #define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 239 - #define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 240 - #define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1, 1 ) 239 + #define MPP32_TSMP12 MPP( 32, 0x1, 0, 0, 0, 0, 1, 1, 1 ) 240 + #define MPP32_TDM_DRX MPP( 32, 0x2, 0, 0, 0, 0, 1, 1, 1 ) 241 241 #define MPP32_GE1_TCLKOUT MPP( 32, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 242 242 #define MPP32_LCD_D12 MPP( 32, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 243 243 244 244 #define MPP33_GPO MPP( 33, 0x0, 0, 1, 0, 1, 1, 1, 1 ) 245 - #define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 245 + #define MPP33_TDM_DTX MPP( 33, 0x2, 0, 0, 0, 0, 1, 1, 1 ) 246 246 #define MPP33_GE1_TXCTL MPP( 33, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 247 247 #define MPP33_LCD_D13 MPP( 33, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 248 248 249 249 #define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 250 - #define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 250 + #define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 0, 0, 0, 1, 1, 1 ) 251 251 #define MPP34_GE1_TXEN MPP( 34, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 252 - #define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 1, 0, 0, 0, 1, 1 ) 252 + #define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 0, 0, 0, 0, 1, 1 ) 253 253 #define MPP34_LCD_D14 MPP( 34, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 254 254 255 255 #define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 256 - #define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 256 + #define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 0, 0, 0, 1, 1, 1 ) 257 257 #define MPP35_GE1_RXERR MPP( 35, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 258 - #define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1, 1 ) 258 + #define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 0, 0, 1, 1, 1, 1 ) 259 259 #define MPP35_LCD_D15 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 260 - #define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1, 1 ) 260 + #define MPP35_MII0_RXERR MPP( 35, 0xc, 0, 0, 1, 1, 1, 1, 1 ) 261 261 262 262 #define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 263 - #define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 264 - #define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 265 - #define MPP36_AU_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1, 1 ) 266 - #define MPP36_TW1_SDA MPP( 36, 0xb, 1, 1, 0, 0, 0, 0, 1 ) 263 + #define MPP36_TSMP0 MPP( 36, 0x1, 0, 0, 0, 0, 0, 1, 1 ) 264 + #define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 0, 0, 0, 0, 1, 1 ) 265 + #define MPP36_AU_SPDIFI MPP( 36, 0x4, 0, 0, 1, 0, 0, 1, 1 ) 266 + #define MPP36_TW1_SDA MPP( 36, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 267 267 268 268 #define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 269 - #define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 270 - #define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 271 - #define MPP37_AU_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1, 1 ) 272 - #define MPP37_TW1_SCK MPP( 37, 0xb, 1, 1, 0, 0, 0, 0, 1 ) 269 + #define MPP37_TSMP1 MPP( 37, 0x1, 0, 0, 0, 0, 0, 1, 1 ) 270 + #define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 0, 0, 0, 0, 1, 1 ) 271 + #define MPP37_AU_SPDIFO MPP( 37, 0x4, 0, 0, 1, 0, 0, 1, 1 ) 272 + #define MPP37_TW1_SCK MPP( 37, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 273 273 274 274 #define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 275 - #define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 276 - #define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 277 - #define MPP38_AU_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1, 1 ) 275 + #define MPP38_TSMP2 MPP( 38, 0x1, 0, 0, 0, 0, 0, 1, 1 ) 276 + #define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 0, 0, 0, 0, 1, 1 ) 277 + #define MPP38_AU_SPDIFRMLCLK MPP( 38, 0x4, 0, 0, 1, 0, 0, 1, 1 ) 278 278 #define MPP38_LCD_D18 MPP( 38, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 279 279 280 280 #define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 281 - #define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 282 - #define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 283 - #define MPP39_AU_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1, 1 ) 281 + #define MPP39_TSMP3 MPP( 39, 0x1, 0, 0, 0, 0, 0, 1, 1 ) 282 + #define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 0, 0, 0, 0, 1, 1 ) 283 + #define MPP39_AU_I2SBCLK MPP( 39, 0x4, 0, 0, 1, 0, 0, 1, 1 ) 284 284 #define MPP39_LCD_D19 MPP( 39, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 285 285 286 286 #define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 287 - #define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 288 - #define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 289 - #define MPP40_AU_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1, 1 ) 287 + #define MPP40_TSMP4 MPP( 40, 0x1, 0, 0, 0, 0, 0, 1, 1 ) 288 + #define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 0, 0, 0, 0, 1, 1 ) 289 + #define MPP40_AU_I2SDO MPP( 40, 0x4, 0, 0, 1, 0, 0, 1, 1 ) 290 290 #define MPP40_LCD_D20 MPP( 40, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 291 291 292 292 #define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 293 - #define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 294 - #define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1, 1 ) 295 - #define MPP41_AU_I2SLRCLK MPP( 41, 0x4, 0, 1, 1, 0, 0, 1, 1 ) 293 + #define MPP41_TSMP5 MPP( 41, 0x1, 0, 0, 0, 0, 0, 1, 1 ) 294 + #define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 0, 0, 0, 0, 0, 1, 1 ) 295 + #define MPP41_AU_I2SLRCLK MPP( 41, 0x4, 0, 0, 1, 0, 0, 1, 1 ) 296 296 #define MPP41_LCD_D21 MPP( 41, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 297 297 298 298 #define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 299 - #define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 300 - #define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 301 - #define MPP42_AU_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1, 1 ) 299 + #define MPP42_TSMP6 MPP( 42, 0x1, 0, 0, 0, 0, 0, 1, 1 ) 300 + #define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 0, 0, 0, 0, 1, 1 ) 301 + #define MPP42_AU_I2SMCLK MPP( 42, 0x4, 0, 0, 1, 0, 0, 1, 1 ) 302 302 #define MPP42_LCD_D22 MPP( 42, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 303 303 304 304 #define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 305 - #define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 305 + #define MPP43_TSMP7 MPP( 43, 0x1, 0, 0, 0, 0, 0, 1, 1 ) 306 306 #define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1, 1 ) 307 - #define MPP43_AU_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1, 1 ) 307 + #define MPP43_AU_I2SDI MPP( 43, 0x4, 0, 0, 1, 0, 0, 1, 1 ) 308 308 #define MPP43_LCD_D23 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 309 309 310 310 #define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 311 - #define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 311 + #define MPP44_TSMP8 MPP( 44, 0x1, 0, 0, 0, 0, 0, 1, 1 ) 312 312 #define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1, 1 ) 313 - #define MPP44_AU_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1, 1 ) 313 + #define MPP44_AU_EXTCLK MPP( 44, 0x4, 0, 0, 1, 0, 0, 1, 1 ) 314 314 #define MPP44_LCD_CLK MPP( 44, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 315 315 316 316 #define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1, 1 ) 317 - #define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 318 - #define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1, 1 ) 317 + #define MPP45_TSMP9 MPP( 45, 0x1, 0, 0, 0, 0, 0, 1, 1 ) 318 + #define MPP45_TDM_PCLK MPP( 45, 0x2, 0, 0, 0, 0, 0, 1, 1 ) 319 319 #define MPP245_LCD_E MPP( 45, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 320 320 321 321 #define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1, 1 ) 322 - #define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 323 - #define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1, 1 ) 322 + #define MPP46_TSMP10 MPP( 46, 0x1, 0, 0, 0, 0, 0, 1, 1 ) 323 + #define MPP46_TDM_FS MPP( 46, 0x2, 0, 0, 0, 0, 0, 1, 1 ) 324 324 #define MPP46_LCD_HSYNC MPP( 46, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 325 325 326 326 #define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1, 1 ) 327 - #define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 328 - #define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1, 1 ) 327 + #define MPP47_TSMP11 MPP( 47, 0x1, 0, 0, 0, 0, 0, 1, 1 ) 328 + #define MPP47_TDM_DRX MPP( 47, 0x2, 0, 0, 0, 0, 0, 1, 1 ) 329 329 #define MPP47_LCD_VSYNC MPP( 47, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 330 330 331 331 #define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1, 1 ) 332 - #define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 333 - #define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 332 + #define MPP48_TSMP12 MPP( 48, 0x1, 0, 0, 0, 0, 0, 1, 1 ) 333 + #define MPP48_TDM_DTX MPP( 48, 0x2, 0, 0, 0, 0, 0, 1, 1 ) 334 334 #define MPP48_LCD_D16 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 335 335 336 336 #define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1, 0 ) 337 337 #define MPP49_GPO MPP( 49, 0x0, 0, 1, 0, 0, 0, 0, 1 ) 338 - #define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1, 0 ) 339 - #define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 340 - #define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1, 0 ) 341 - #define MPP49_PEX0_CLKREQ MPP( 49, 0xa, 0, 1, 0, 0, 0, 0, 1 ) 338 + #define MPP49_TSMP9 MPP( 49, 0x1, 0, 0, 0, 0, 0, 1, 0 ) 339 + #define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 0, 0, 0, 0, 1, 1 ) 340 + #define MPP49_PTP_CLK MPP( 49, 0x5, 0, 0, 0, 0, 0, 1, 0 ) 341 + #define MPP49_PEX0_CLKREQ MPP( 49, 0xa, 0, 0, 0, 0, 0, 0, 1 ) 342 342 #define MPP49_LCD_D17 MPP( 49, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 343 343 344 344 #define MPP_MAX 49
+2 -1
arch/arm/mach-mv78xx0/common.c
··· 19 19 #include <mach/mv78xx0.h> 20 20 #include <mach/bridge-regs.h> 21 21 #include <plat/cache-feroceon-l2.h> 22 + #include <plat/ehci-orion.h> 22 23 #include <plat/orion_nand.h> 23 24 #include <plat/time.h> 24 25 #include <plat/common.h> ··· 170 169 ****************************************************************************/ 171 170 void __init mv78xx0_ehci0_init(void) 172 171 { 173 - orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0); 172 + orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA); 174 173 } 175 174 176 175
+113 -113
arch/arm/mach-mv78xx0/mpp.h
··· 24 24 #define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1) 25 25 26 26 #define MPP0_GPIO MPP(0, 0x0, 1, 1, 1) 27 - #define MPP0_GE0_COL MPP(0, 0x1, 1, 0, 1) 28 - #define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 1, 1) 27 + #define MPP0_GE0_COL MPP(0, 0x1, 0, 0, 1) 28 + #define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 0, 1) 29 29 #define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1) 30 30 31 31 #define MPP1_GPIO MPP(1, 0x0, 1, 1, 1) 32 - #define MPP1_GE0_RXERR MPP(1, 0x1, 1, 0, 1) 33 - #define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 1, 1) 32 + #define MPP1_GE0_RXERR MPP(1, 0x1, 0, 0, 1) 33 + #define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 0, 1) 34 34 #define MPP1_UNUSED MPP(1, 0x3, 0, 0, 1) 35 35 36 36 #define MPP2_GPIO MPP(2, 0x0, 1, 1, 1) 37 - #define MPP2_GE0_CRS MPP(2, 0x1, 1, 0, 1) 38 - #define MPP2_GE1_RXCTL MPP(2, 0x2, 1, 0, 1) 37 + #define MPP2_GE0_CRS MPP(2, 0x1, 0, 0, 1) 38 + #define MPP2_GE1_RXCTL MPP(2, 0x2, 0, 0, 1) 39 39 #define MPP2_UNUSED MPP(2, 0x3, 0, 0, 1) 40 40 41 41 #define MPP3_GPIO MPP(3, 0x0, 1, 1, 1) 42 - #define MPP3_GE0_TXERR MPP(3, 0x1, 0, 1, 1) 43 - #define MPP3_GE1_RXCLK MPP(3, 0x2, 1, 0, 1) 42 + #define MPP3_GE0_TXERR MPP(3, 0x1, 0, 0, 1) 43 + #define MPP3_GE1_RXCLK MPP(3, 0x2, 0, 0, 1) 44 44 #define MPP3_UNUSED MPP(3, 0x3, 0, 0, 1) 45 45 46 46 #define MPP4_GPIO MPP(4, 0x0, 1, 1, 1) 47 - #define MPP4_GE0_TXD4 MPP(4, 0x1, 0, 1, 1) 48 - #define MPP4_GE1_TXD0 MPP(4, 0x2, 0, 1, 1) 47 + #define MPP4_GE0_TXD4 MPP(4, 0x1, 0, 0, 1) 48 + #define MPP4_GE1_TXD0 MPP(4, 0x2, 0, 0, 1) 49 49 #define MPP4_UNUSED MPP(4, 0x3, 0, 0, 1) 50 50 51 51 #define MPP5_GPIO MPP(5, 0x0, 1, 1, 1) 52 - #define MPP5_GE0_TXD5 MPP(5, 0x1, 0, 1, 1) 53 - #define MPP5_GE1_TXD1 MPP(5, 0x2, 0, 1, 1) 52 + #define MPP5_GE0_TXD5 MPP(5, 0x1, 0, 0, 1) 53 + #define MPP5_GE1_TXD1 MPP(5, 0x2, 0, 0, 1) 54 54 #define MPP5_UNUSED MPP(5, 0x3, 0, 0, 1) 55 55 56 56 #define MPP6_GPIO MPP(6, 0x0, 1, 1, 1) 57 - #define MPP6_GE0_TXD6 MPP(6, 0x1, 0, 1, 1) 58 - #define MPP6_GE1_TXD2 MPP(6, 0x2, 0, 1, 1) 57 + #define MPP6_GE0_TXD6 MPP(6, 0x1, 0, 0, 1) 58 + #define MPP6_GE1_TXD2 MPP(6, 0x2, 0, 0, 1) 59 59 #define MPP6_UNUSED MPP(6, 0x3, 0, 0, 1) 60 60 61 61 #define MPP7_GPIO MPP(7, 0x0, 1, 1, 1) 62 - #define MPP7_GE0_TXD7 MPP(7, 0x1, 0, 1, 1) 63 - #define MPP7_GE1_TXD3 MPP(7, 0x2, 0, 1, 1) 62 + #define MPP7_GE0_TXD7 MPP(7, 0x1, 0, 0, 1) 63 + #define MPP7_GE1_TXD3 MPP(7, 0x2, 0, 0, 1) 64 64 #define MPP7_UNUSED MPP(7, 0x3, 0, 0, 1) 65 65 66 66 #define MPP8_GPIO MPP(8, 0x0, 1, 1, 1) 67 - #define MPP8_GE0_RXD4 MPP(8, 0x1, 1, 0, 1) 68 - #define MPP8_GE1_RXD0 MPP(8, 0x2, 1, 0, 1) 67 + #define MPP8_GE0_RXD4 MPP(8, 0x1, 0, 0, 1) 68 + #define MPP8_GE1_RXD0 MPP(8, 0x2, 0, 0, 1) 69 69 #define MPP8_UNUSED MPP(8, 0x3, 0, 0, 1) 70 70 71 71 #define MPP9_GPIO MPP(9, 0x0, 1, 1, 1) 72 - #define MPP9_GE0_RXD5 MPP(9, 0x1, 1, 0, 1) 73 - #define MPP9_GE1_RXD1 MPP(9, 0x2, 1, 0, 1) 72 + #define MPP9_GE0_RXD5 MPP(9, 0x1, 0, 0, 1) 73 + #define MPP9_GE1_RXD1 MPP(9, 0x2, 0, 0, 1) 74 74 #define MPP9_UNUSED MPP(9, 0x3, 0, 0, 1) 75 75 76 76 #define MPP10_GPIO MPP(10, 0x0, 1, 1, 1) 77 - #define MPP10_GE0_RXD6 MPP(10, 0x1, 1, 0, 1) 78 - #define MPP10_GE1_RXD2 MPP(10, 0x2, 1, 0, 1) 77 + #define MPP10_GE0_RXD6 MPP(10, 0x1, 0, 0, 1) 78 + #define MPP10_GE1_RXD2 MPP(10, 0x2, 0, 0, 1) 79 79 #define MPP10_UNUSED MPP(10, 0x3, 0, 0, 1) 80 80 81 81 #define MPP11_GPIO MPP(11, 0x0, 1, 1, 1) 82 - #define MPP11_GE0_RXD7 MPP(11, 0x1, 1, 0, 1) 83 - #define MPP11_GE1_RXD3 MPP(11, 0x2, 1, 0, 1) 82 + #define MPP11_GE0_RXD7 MPP(11, 0x1, 0, 0, 1) 83 + #define MPP11_GE1_RXD3 MPP(11, 0x2, 0, 0, 1) 84 84 #define MPP11_UNUSED MPP(11, 0x3, 0, 0, 1) 85 85 86 86 #define MPP12_GPIO MPP(12, 0x0, 1, 1, 1) 87 - #define MPP12_M_BB MPP(12, 0x3, 1, 0, 1) 88 - #define MPP12_UA0_CTSn MPP(12, 0x4, 1, 0, 1) 89 - #define MPP12_NAND_FLASH_REn0 MPP(12, 0x5, 0, 1, 1) 90 - #define MPP12_TDM0_SCSn MPP(12, 0X6, 0, 1, 1) 87 + #define MPP12_M_BB MPP(12, 0x3, 0, 0, 1) 88 + #define MPP12_UA0_CTSn MPP(12, 0x4, 0, 0, 1) 89 + #define MPP12_NAND_FLASH_REn0 MPP(12, 0x5, 0, 0, 1) 90 + #define MPP12_TDM0_SCSn MPP(12, 0X6, 0, 0, 1) 91 91 #define MPP12_UNUSED MPP(12, 0x1, 0, 0, 1) 92 92 93 93 #define MPP13_GPIO MPP(13, 0x0, 1, 1, 1) 94 - #define MPP13_SYSRST_OUTn MPP(13, 0x3, 0, 1, 1) 95 - #define MPP13_UA0_RTSn MPP(13, 0x4, 0, 1, 1) 96 - #define MPP13_NAN_FLASH_WEn0 MPP(13, 0x5, 0, 1, 1) 97 - #define MPP13_TDM_SCLK MPP(13, 0x6, 0, 1, 1) 94 + #define MPP13_SYSRST_OUTn MPP(13, 0x3, 0, 0, 1) 95 + #define MPP13_UA0_RTSn MPP(13, 0x4, 0, 0, 1) 96 + #define MPP13_NAN_FLASH_WEn0 MPP(13, 0x5, 0, 0, 1) 97 + #define MPP13_TDM_SCLK MPP(13, 0x6, 0, 0, 1) 98 98 #define MPP13_UNUSED MPP(13, 0x1, 0, 0, 1) 99 99 100 100 #define MPP14_GPIO MPP(14, 0x0, 1, 1, 1) 101 - #define MPP14_SATA1_ACTn MPP(14, 0x3, 0, 1, 1) 102 - #define MPP14_UA1_CTSn MPP(14, 0x4, 1, 0, 1) 103 - #define MPP14_NAND_FLASH_REn1 MPP(14, 0x5, 0, 1, 1) 104 - #define MPP14_TDM_SMOSI MPP(14, 0x6, 0, 1, 1) 101 + #define MPP14_SATA1_ACTn MPP(14, 0x3, 0, 0, 1) 102 + #define MPP14_UA1_CTSn MPP(14, 0x4, 0, 0, 1) 103 + #define MPP14_NAND_FLASH_REn1 MPP(14, 0x5, 0, 0, 1) 104 + #define MPP14_TDM_SMOSI MPP(14, 0x6, 0, 0, 1) 105 105 #define MPP14_UNUSED MPP(14, 0x1, 0, 0, 1) 106 106 107 107 #define MPP15_GPIO MPP(15, 0x0, 1, 1, 1) 108 - #define MPP15_SATA0_ACTn MPP(15, 0x3, 0, 1, 1) 109 - #define MPP15_UA1_RTSn MPP(15, 0x4, 0, 1, 1) 110 - #define MPP15_NAND_FLASH_WEn1 MPP(15, 0x5, 0, 1, 1) 111 - #define MPP15_TDM_SMISO MPP(15, 0x6, 1, 0, 1) 108 + #define MPP15_SATA0_ACTn MPP(15, 0x3, 0, 0, 1) 109 + #define MPP15_UA1_RTSn MPP(15, 0x4, 0, 0, 1) 110 + #define MPP15_NAND_FLASH_WEn1 MPP(15, 0x5, 0, 0, 1) 111 + #define MPP15_TDM_SMISO MPP(15, 0x6, 0, 0, 1) 112 112 #define MPP15_UNUSED MPP(15, 0x1, 0, 0, 1) 113 113 114 114 #define MPP16_GPIO MPP(16, 0x0, 1, 1, 1) 115 - #define MPP16_SATA1_PRESENTn MPP(16, 0x3, 0, 1, 1) 116 - #define MPP16_UA2_TXD MPP(16, 0x4, 0, 1, 1) 117 - #define MPP16_NAND_FLASH_REn3 MPP(16, 0x5, 0, 1, 1) 118 - #define MPP16_TDM_INTn MPP(16, 0x6, 1, 0, 1) 115 + #define MPP16_SATA1_PRESENTn MPP(16, 0x3, 0, 0, 1) 116 + #define MPP16_UA2_TXD MPP(16, 0x4, 0, 0, 1) 117 + #define MPP16_NAND_FLASH_REn3 MPP(16, 0x5, 0, 0, 1) 118 + #define MPP16_TDM_INTn MPP(16, 0x6, 0, 0, 1) 119 119 #define MPP16_UNUSED MPP(16, 0x1, 0, 0, 1) 120 120 121 121 122 122 #define MPP17_GPIO MPP(17, 0x0, 1, 1, 1) 123 - #define MPP17_SATA0_PRESENTn MPP(17, 0x3, 0, 1, 1) 124 - #define MPP17_UA2_RXD MPP(17, 0x4, 1, 0, 1) 125 - #define MPP17_NAND_FLASH_WEn3 MPP(17, 0x5, 0, 1, 1) 126 - #define MPP17_TDM_RSTn MPP(17, 0x6, 0, 1, 1) 123 + #define MPP17_SATA0_PRESENTn MPP(17, 0x3, 0, 0, 1) 124 + #define MPP17_UA2_RXD MPP(17, 0x4, 0, 0, 1) 125 + #define MPP17_NAND_FLASH_WEn3 MPP(17, 0x5, 0, 0, 1) 126 + #define MPP17_TDM_RSTn MPP(17, 0x6, 0, 0, 1) 127 127 #define MPP17_UNUSED MPP(17, 0x1, 0, 0, 1) 128 128 129 129 130 130 #define MPP18_GPIO MPP(18, 0x0, 1, 1, 1) 131 - #define MPP18_UA0_CTSn MPP(18, 0x4, 1, 0, 1) 132 - #define MPP18_BOOT_FLASH_REn MPP(18, 0x5, 0, 1, 1) 131 + #define MPP18_UA0_CTSn MPP(18, 0x4, 0, 0, 1) 132 + #define MPP18_BOOT_FLASH_REn MPP(18, 0x5, 0, 0, 1) 133 133 #define MPP18_UNUSED MPP(18, 0x1, 0, 0, 1) 134 134 135 135 136 136 137 137 #define MPP19_GPIO MPP(19, 0x0, 1, 1, 1) 138 - #define MPP19_UA0_CTSn MPP(19, 0x4, 0, 1, 1) 139 - #define MPP19_BOOT_FLASH_WEn MPP(19, 0x5, 0, 1, 1) 138 + #define MPP19_UA0_CTSn MPP(19, 0x4, 0, 0, 1) 139 + #define MPP19_BOOT_FLASH_WEn MPP(19, 0x5, 0, 0, 1) 140 140 #define MPP19_UNUSED MPP(19, 0x1, 0, 0, 1) 141 141 142 142 143 143 #define MPP20_GPIO MPP(20, 0x0, 1, 1, 1) 144 - #define MPP20_UA1_CTSs MPP(20, 0x4, 1, 0, 1) 145 - #define MPP20_TDM_PCLK MPP(20, 0x6, 1, 1, 0) 144 + #define MPP20_UA1_CTSs MPP(20, 0x4, 0, 0, 1) 145 + #define MPP20_TDM_PCLK MPP(20, 0x6, 0, 0, 0) 146 146 #define MPP20_UNUSED MPP(20, 0x1, 0, 0, 1) 147 147 148 148 149 149 150 150 #define MPP21_GPIO MPP(21, 0x0, 1, 1, 1) 151 - #define MPP21_UA1_CTSs MPP(21, 0x4, 0, 1, 1) 152 - #define MPP21_TDM_FSYNC MPP(21, 0x6, 1, 1, 0) 151 + #define MPP21_UA1_CTSs MPP(21, 0x4, 0, 0, 1) 152 + #define MPP21_TDM_FSYNC MPP(21, 0x6, 0, 0, 0) 153 153 #define MPP21_UNUSED MPP(21, 0x1, 0, 0, 1) 154 154 155 155 156 156 157 157 #define MPP22_GPIO MPP(22, 0x0, 1, 1, 1) 158 - #define MPP22_UA3_TDX MPP(22, 0x4, 0, 1, 1) 159 - #define MPP22_NAND_FLASH_REn2 MPP(22, 0x5, 0, 1, 1) 160 - #define MPP22_TDM_DRX MPP(22, 0x6, 1, 0, 1) 158 + #define MPP22_UA3_TDX MPP(22, 0x4, 0, 0, 1) 159 + #define MPP22_NAND_FLASH_REn2 MPP(22, 0x5, 0, 0, 1) 160 + #define MPP22_TDM_DRX MPP(22, 0x6, 0, 0, 1) 161 161 #define MPP22_UNUSED MPP(22, 0x1, 0, 0, 1) 162 162 163 163 164 164 165 165 #define MPP23_GPIO MPP(23, 0x0, 1, 1, 1) 166 - #define MPP23_UA3_RDX MPP(23, 0x4, 1, 0, 1) 167 - #define MPP23_NAND_FLASH_WEn2 MPP(23, 0x5, 0, 1, 1) 168 - #define MPP23_TDM_DTX MPP(23, 0x6, 0, 1, 1) 166 + #define MPP23_UA3_RDX MPP(23, 0x4, 0, 0, 1) 167 + #define MPP23_NAND_FLASH_WEn2 MPP(23, 0x5, 0, 0, 1) 168 + #define MPP23_TDM_DTX MPP(23, 0x6, 0, 0, 1) 169 169 #define MPP23_UNUSED MPP(23, 0x1, 0, 0, 1) 170 170 171 171 172 172 #define MPP24_GPIO MPP(24, 0x0, 1, 1, 1) 173 - #define MPP24_UA2_TXD MPP(24, 0x4, 0, 1, 1) 174 - #define MPP24_TDM_INTn MPP(24, 0x6, 1, 0, 1) 173 + #define MPP24_UA2_TXD MPP(24, 0x4, 0, 0, 1) 174 + #define MPP24_TDM_INTn MPP(24, 0x6, 0, 0, 1) 175 175 #define MPP24_UNUSED MPP(24, 0x1, 0, 0, 1) 176 176 177 177 178 178 #define MPP25_GPIO MPP(25, 0x0, 1, 1, 1) 179 - #define MPP25_UA2_RXD MPP(25, 0x4, 1, 0, 1) 180 - #define MPP25_TDM_RSTn MPP(25, 0x6, 0, 1, 1) 179 + #define MPP25_UA2_RXD MPP(25, 0x4, 0, 0, 1) 180 + #define MPP25_TDM_RSTn MPP(25, 0x6, 0, 0, 1) 181 181 #define MPP25_UNUSED MPP(25, 0x1, 0, 0, 1) 182 182 183 183 184 184 #define MPP26_GPIO MPP(26, 0x0, 1, 1, 1) 185 - #define MPP26_UA2_CTSn MPP(26, 0x4, 1, 0, 1) 186 - #define MPP26_TDM_PCLK MPP(26, 0x6, 1, 1, 1) 185 + #define MPP26_UA2_CTSn MPP(26, 0x4, 0, 0, 1) 186 + #define MPP26_TDM_PCLK MPP(26, 0x6, 0, 0, 1) 187 187 #define MPP26_UNUSED MPP(26, 0x1, 0, 0, 1) 188 188 189 189 190 190 #define MPP27_GPIO MPP(27, 0x0, 1, 1, 1) 191 - #define MPP27_UA2_RTSn MPP(27, 0x4, 0, 1, 1) 192 - #define MPP27_TDM_FSYNC MPP(27, 0x6, 1, 1, 1) 191 + #define MPP27_UA2_RTSn MPP(27, 0x4, 0, 0, 1) 192 + #define MPP27_TDM_FSYNC MPP(27, 0x6, 0, 0, 1) 193 193 #define MPP27_UNUSED MPP(27, 0x1, 0, 0, 1) 194 194 195 195 196 196 #define MPP28_GPIO MPP(28, 0x0, 1, 1, 1) 197 - #define MPP28_UA3_TXD MPP(28, 0x4, 0, 1, 1) 198 - #define MPP28_TDM_DRX MPP(28, 0x6, 1, 0, 1) 197 + #define MPP28_UA3_TXD MPP(28, 0x4, 0, 0, 1) 198 + #define MPP28_TDM_DRX MPP(28, 0x6, 0, 0, 1) 199 199 #define MPP28_UNUSED MPP(28, 0x1, 0, 0, 1) 200 200 201 201 #define MPP29_GPIO MPP(29, 0x0, 1, 1, 1) 202 - #define MPP29_UA3_RXD MPP(29, 0x4, 1, 0, 1) 203 - #define MPP29_SYSRST_OUTn MPP(29, 0x5, 0, 1, 1) 204 - #define MPP29_TDM_DTX MPP(29, 0x6, 0, 1, 1) 202 + #define MPP29_UA3_RXD MPP(29, 0x4, 0, 0, 1) 203 + #define MPP29_SYSRST_OUTn MPP(29, 0x5, 0, 0, 1) 204 + #define MPP29_TDM_DTX MPP(29, 0x6, 0, 0, 1) 205 205 #define MPP29_UNUSED MPP(29, 0x1, 0, 0, 1) 206 206 207 207 #define MPP30_GPIO MPP(30, 0x0, 1, 1, 1) 208 - #define MPP30_UA3_CTSn MPP(30, 0x4, 1, 0, 1) 208 + #define MPP30_UA3_CTSn MPP(30, 0x4, 0, 0, 1) 209 209 #define MPP30_UNUSED MPP(30, 0x1, 0, 0, 1) 210 210 211 211 #define MPP31_GPIO MPP(31, 0x0, 1, 1, 1) 212 - #define MPP31_UA3_RTSn MPP(31, 0x4, 0, 1, 1) 213 - #define MPP31_TDM1_SCSn MPP(31, 0x6, 0, 1, 1) 212 + #define MPP31_UA3_RTSn MPP(31, 0x4, 0, 0, 1) 213 + #define MPP31_TDM1_SCSn MPP(31, 0x6, 0, 0, 1) 214 214 #define MPP31_UNUSED MPP(31, 0x1, 0, 0, 1) 215 215 216 216 217 217 #define MPP32_GPIO MPP(32, 0x1, 1, 1, 1) 218 - #define MPP32_UA3_TDX MPP(32, 0x4, 0, 1, 1) 219 - #define MPP32_SYSRST_OUTn MPP(32, 0x5, 0, 1, 1) 220 - #define MPP32_TDM0_RXQ MPP(32, 0x6, 0, 1, 1) 218 + #define MPP32_UA3_TDX MPP(32, 0x4, 0, 0, 1) 219 + #define MPP32_SYSRST_OUTn MPP(32, 0x5, 0, 0, 1) 220 + #define MPP32_TDM0_RXQ MPP(32, 0x6, 0, 0, 1) 221 221 #define MPP32_UNUSED MPP(32, 0x3, 0, 0, 1) 222 222 223 223 224 224 #define MPP33_GPIO MPP(33, 0x1, 1, 1, 1) 225 - #define MPP33_UA3_RDX MPP(33, 0x4, 1, 0, 1) 226 - #define MPP33_TDM0_TXQ MPP(33, 0x6, 0, 1, 1) 225 + #define MPP33_UA3_RDX MPP(33, 0x4, 0, 0, 1) 226 + #define MPP33_TDM0_TXQ MPP(33, 0x6, 0, 0, 1) 227 227 #define MPP33_UNUSED MPP(33, 0x3, 0, 0, 1) 228 228 229 229 230 230 231 231 #define MPP34_GPIO MPP(34, 0x1, 1, 1, 1) 232 - #define MPP34_UA2_TDX MPP(34, 0x4, 0, 1, 1) 233 - #define MPP34_TDM1_RXQ MPP(34, 0x6, 0, 1, 1) 232 + #define MPP34_UA2_TDX MPP(34, 0x4, 0, 0, 1) 233 + #define MPP34_TDM1_RXQ MPP(34, 0x6, 0, 0, 1) 234 234 #define MPP34_UNUSED MPP(34, 0x3, 0, 0, 1) 235 235 236 236 237 237 238 238 #define MPP35_GPIO MPP(35, 0x1, 1, 1, 1) 239 - #define MPP35_UA2_RDX MPP(35, 0x4, 1, 0, 1) 240 - #define MPP35_TDM1_TXQ MPP(35, 0x6, 0, 1, 1) 239 + #define MPP35_UA2_RDX MPP(35, 0x4, 0, 0, 1) 240 + #define MPP35_TDM1_TXQ MPP(35, 0x6, 0, 0, 1) 241 241 #define MPP35_UNUSED MPP(35, 0x3, 0, 0, 1) 242 242 243 243 #define MPP36_GPIO MPP(36, 0x1, 1, 1, 1) 244 - #define MPP36_UA0_CTSn MPP(36, 0x2, 1, 0, 1) 245 - #define MPP36_UA2_TDX MPP(36, 0x4, 0, 1, 1) 246 - #define MPP36_TDM0_SCSn MPP(36, 0x6, 0, 1, 1) 244 + #define MPP36_UA0_CTSn MPP(36, 0x2, 0, 0, 1) 245 + #define MPP36_UA2_TDX MPP(36, 0x4, 0, 0, 1) 246 + #define MPP36_TDM0_SCSn MPP(36, 0x6, 0, 0, 1) 247 247 #define MPP36_UNUSED MPP(36, 0x3, 0, 0, 1) 248 248 249 249 250 250 #define MPP37_GPIO MPP(37, 0x1, 1, 1, 1) 251 - #define MPP37_UA0_RTSn MPP(37, 0x2, 0, 1, 1) 252 - #define MPP37_UA2_RXD MPP(37, 0x4, 1, 0, 1) 253 - #define MPP37_SYSRST_OUTn MPP(37, 0x5, 0, 1, 1) 254 - #define MPP37_TDM_SCLK MPP(37, 0x6, 0, 1, 1) 251 + #define MPP37_UA0_RTSn MPP(37, 0x2, 0, 0, 1) 252 + #define MPP37_UA2_RXD MPP(37, 0x4, 0, 0, 1) 253 + #define MPP37_SYSRST_OUTn MPP(37, 0x5, 0, 0, 1) 254 + #define MPP37_TDM_SCLK MPP(37, 0x6, 0, 0, 1) 255 255 #define MPP37_UNUSED MPP(37, 0x3, 0, 0, 1) 256 256 257 257 258 258 259 259 260 260 #define MPP38_GPIO MPP(38, 0x1, 1, 1, 1) 261 - #define MPP38_UA1_CTSn MPP(38, 0x2, 1, 0, 1) 262 - #define MPP38_UA3_TXD MPP(38, 0x4, 0, 1, 1) 263 - #define MPP38_SYSRST_OUTn MPP(38, 0x5, 0, 1, 1) 264 - #define MPP38_TDM_SMOSI MPP(38, 0x6, 0, 1, 1) 261 + #define MPP38_UA1_CTSn MPP(38, 0x2, 0, 0, 1) 262 + #define MPP38_UA3_TXD MPP(38, 0x4, 0, 0, 1) 263 + #define MPP38_SYSRST_OUTn MPP(38, 0x5, 0, 0, 1) 264 + #define MPP38_TDM_SMOSI MPP(38, 0x6, 0, 0, 1) 265 265 #define MPP38_UNUSED MPP(38, 0x3, 0, 0, 1) 266 266 267 267 268 268 269 269 270 270 #define MPP39_GPIO MPP(39, 0x1, 1, 1, 1) 271 - #define MPP39_UA1_RTSn MPP(39, 0x2, 0, 1, 1) 272 - #define MPP39_UA3_RXD MPP(39, 0x4, 1, 0, 1) 273 - #define MPP39_SYSRST_OUTn MPP(39, 0x5, 0, 1, 1) 274 - #define MPP39_TDM_SMISO MPP(39, 0x6, 1, 0, 1) 271 + #define MPP39_UA1_RTSn MPP(39, 0x2, 0, 0, 1) 272 + #define MPP39_UA3_RXD MPP(39, 0x4, 0, 0, 1) 273 + #define MPP39_SYSRST_OUTn MPP(39, 0x5, 0, 0, 1) 274 + #define MPP39_TDM_SMISO MPP(39, 0x6, 0, 0, 1) 275 275 #define MPP39_UNUSED MPP(39, 0x3, 0, 0, 1) 276 276 277 277 278 278 279 279 #define MPP40_GPIO MPP(40, 0x1, 1, 1, 1) 280 - #define MPP40_TDM_INTn MPP(40, 0x6, 1, 0, 1) 280 + #define MPP40_TDM_INTn MPP(40, 0x6, 0, 0, 1) 281 281 #define MPP40_UNUSED MPP(40, 0x0, 0, 0, 1) 282 282 283 283 284 284 285 285 #define MPP41_GPIO MPP(41, 0x1, 1, 1, 1) 286 - #define MPP41_TDM_RSTn MPP(41, 0x6, 0, 1, 1) 286 + #define MPP41_TDM_RSTn MPP(41, 0x6, 0, 0, 1) 287 287 #define MPP41_UNUSED MPP(41, 0x0, 0, 0, 1) 288 288 289 289 290 290 291 291 #define MPP42_GPIO MPP(42, 0x1, 1, 1, 1) 292 - #define MPP42_TDM_PCLK MPP(42, 0x6, 1, 1, 1) 292 + #define MPP42_TDM_PCLK MPP(42, 0x6, 0, 0, 1) 293 293 #define MPP42_UNUSED MPP(42, 0x0, 0, 0, 1) 294 294 295 295 296 296 297 297 #define MPP43_GPIO MPP(43, 0x1, 1, 1, 1) 298 - #define MPP43_TDM_FSYNC MPP(43, 0x6, 1, 1, 1) 298 + #define MPP43_TDM_FSYNC MPP(43, 0x6, 0, 0, 1) 299 299 #define MPP43_UNUSED MPP(43, 0x0, 0, 0, 1) 300 300 301 301 302 302 303 303 #define MPP44_GPIO MPP(44, 0x1, 1, 1, 1) 304 - #define MPP44_TDM_DRX MPP(44, 0x6, 1, 0, 1) 304 + #define MPP44_TDM_DRX MPP(44, 0x6, 0, 0, 1) 305 305 #define MPP44_UNUSED MPP(44, 0x0, 0, 0, 1) 306 306 307 307 308 308 309 309 #define MPP45_GPIO MPP(45, 0x1, 1, 1, 1) 310 - #define MPP45_SATA0_ACTn MPP(45, 0x3, 0, 1, 1) 311 - #define MPP45_TDM_DRX MPP(45, 0x6, 0, 1, 1) 310 + #define MPP45_SATA0_ACTn MPP(45, 0x3, 0, 0, 1) 311 + #define MPP45_TDM_DRX MPP(45, 0x6, 0, 0, 1) 312 312 #define MPP45_UNUSED MPP(45, 0x0, 0, 0, 1) 313 313 314 314 315 315 #define MPP46_GPIO MPP(46, 0x1, 1, 1, 1) 316 - #define MPP46_TDM_SCSn MPP(46, 0x6, 0, 1, 1) 316 + #define MPP46_TDM_SCSn MPP(46, 0x6, 0, 0, 1) 317 317 #define MPP46_UNUSED MPP(46, 0x0, 0, 0, 1) 318 318 319 319 ··· 323 323 324 324 325 325 #define MPP48_GPIO MPP(48, 0x1, 1, 1, 1) 326 - #define MPP48_SATA1_ACTn MPP(48, 0x3, 0, 1, 1) 326 + #define MPP48_SATA1_ACTn MPP(48, 0x3, 0, 0, 1) 327 327 #define MPP48_UNUSED MPP(48, 0x2, 0, 0, 1) 328 328 329 329 330 330 331 331 #define MPP49_GPIO MPP(49, 0x1, 1, 1, 1) 332 - #define MPP49_SATA0_ACTn MPP(49, 0x3, 0, 1, 1) 333 - #define MPP49_M_BB MPP(49, 0x4, 1, 0, 1) 332 + #define MPP49_SATA0_ACTn MPP(49, 0x3, 0, 0, 1) 333 + #define MPP49_M_BB MPP(49, 0x4, 0, 0, 1) 334 334 #define MPP49_UNUSED MPP(49, 0x2, 0, 0, 1) 335 335 336 336
+2 -2
arch/arm/mach-omap2/Makefile
··· 11 11 omap_hwmod_common_data.o 12 12 clock-common = clock.o clock_common_data.o \ 13 13 clkt_dpll.o clkt_clksel.o 14 - secure-common = omap-smc.o omap-secure.o 14 + secure-common = omap-smc.o omap-secure.o 15 15 16 - obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) $(secure-common) 16 + obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) 17 17 obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) 18 18 obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common) 19 19
+1 -1
arch/arm/mach-omap2/board-cm-t35.c
··· 437 437 .reset_gpio_port[2] = -EINVAL 438 438 }; 439 439 440 - static void cm_t35_init_usbh(void) 440 + static void __init cm_t35_init_usbh(void) 441 441 { 442 442 int err; 443 443
+4
arch/arm/mach-omap2/board-generic.c
··· 17 17 #include <linux/i2c/twl.h> 18 18 19 19 #include <mach/hardware.h> 20 + #include <asm/hardware/gic.h> 20 21 #include <asm/mach/arch.h> 21 22 22 23 #include <plat/board.h> ··· 103 102 .map_io = omap242x_map_io, 104 103 .init_early = omap2420_init_early, 105 104 .init_irq = omap2_init_irq, 105 + .handle_irq = omap2_intc_handle_irq, 106 106 .init_machine = omap_generic_init, 107 107 .timer = &omap2_timer, 108 108 .dt_compat = omap242x_boards_compat, ··· 143 141 .map_io = omap3_map_io, 144 142 .init_early = omap3430_init_early, 145 143 .init_irq = omap3_init_irq, 144 + .handle_irq = omap3_intc_handle_irq, 146 145 .init_machine = omap3_init, 147 146 .timer = &omap3_timer, 148 147 .dt_compat = omap3_boards_compat, ··· 163 160 .map_io = omap4_map_io, 164 161 .init_early = omap4430_init_early, 165 162 .init_irq = gic_init_irq, 163 + .handle_irq = gic_handle_irq, 166 164 .init_machine = omap4_init, 167 165 .timer = &omap4_timer, 168 166 .dt_compat = omap4_boards_compat,
+1 -7
arch/arm/mach-omap2/pm24xx.c
··· 82 82 f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); 83 83 f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); 84 84 85 - /* Ignore UART clocks. These are handled by UART core (serial.c) */ 86 - f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK); 87 - f2 &= ~OMAP24XX_EN_UART3_MASK; 88 - 89 - if (f1 | f2) 90 - return 1; 91 - return 0; 85 + return (f1 | f2) ? 1 : 0; 92 86 } 93 87 94 88 static void omap2_enter_full_retention(void)
+3 -1
arch/arm/mach-orion5x/common.c
··· 29 29 #include <mach/hardware.h> 30 30 #include <mach/orion5x.h> 31 31 #include <plat/orion_nand.h> 32 + #include <plat/ehci-orion.h> 32 33 #include <plat/time.h> 33 34 #include <plat/common.h> 34 35 #include <plat/addr-map.h> ··· 73 72 ****************************************************************************/ 74 73 void __init orion5x_ehci0_init(void) 75 74 { 76 - orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL); 75 + orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL, 76 + EHCI_PHY_ORION); 77 77 } 78 78 79 79
+5 -3
arch/arm/mach-s3c2410/cpu-freq.c
··· 115 115 .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs), 116 116 }; 117 117 118 - static int s3c2410_cpufreq_add(struct device *dev) 118 + static int s3c2410_cpufreq_add(struct device *dev, 119 + struct subsys_interface *sif) 119 120 { 120 121 return s3c_cpufreq_register(&s3c2410_cpufreq_info); 121 122 } ··· 134 133 135 134 arch_initcall(s3c2410_cpufreq_init); 136 135 137 - static int s3c2410a_cpufreq_add(struct device *dev) 136 + static int s3c2410a_cpufreq_add(struct device *dev, 137 + struct subsys_interface *sif) 138 138 { 139 139 /* alter the maximum freq settings for S3C2410A. If a board knows 140 140 * it only has a maximum of 200, then it should register its own ··· 146 144 s3c2410_cpufreq_info.max.pclk = 66500000; 147 145 s3c2410_cpufreq_info.name = "s3c2410a"; 148 146 149 - return s3c2410_cpufreq_add(dev); 147 + return s3c2410_cpufreq_add(dev, sif); 150 148 } 151 149 152 150 static struct subsys_interface s3c2410a_cpufreq_interface = {
+3 -2
arch/arm/mach-s3c2410/dma.c
··· 132 132 }, 133 133 }; 134 134 135 - static int __init s3c2410_dma_add(struct device *dev) 135 + static int __init s3c2410_dma_add(struct device *dev, 136 + struct subsys_interface *sif) 136 137 { 137 138 s3c2410_dma_init(); 138 139 s3c24xx_dma_order_set(&s3c2410_dma_order); ··· 149 148 150 149 static int __init s3c2410_dma_drvinit(void) 151 150 { 152 - return subsys_interface_register(&s3c2410_interface); 151 + return subsys_interface_register(&s3c2410_dma_interface); 153 152 } 154 153 155 154 arch_initcall(s3c2410_dma_drvinit);
+1 -1
arch/arm/mach-s3c2410/pll.c
··· 66 66 { .frequency = 270000000, .index = PLLVAL(127, 1, 1), }, 67 67 }; 68 68 69 - static int s3c2410_plls_add(struct device *dev) 69 + static int s3c2410_plls_add(struct device *dev, struct subsys_interface *sif) 70 70 { 71 71 return s3c_plltab_register(pll_vals_12MHz, ARRAY_SIZE(pll_vals_12MHz)); 72 72 }
+1 -1
arch/arm/mach-s3c2410/pm.c
··· 111 111 .resume = s3c2410_pm_resume, 112 112 }; 113 113 114 - static int s3c2410_pm_add(struct device *dev) 114 + static int s3c2410_pm_add(struct device *dev, struct subsys_interface *sif) 115 115 { 116 116 pm_cpu_prep = s3c2410_pm_prepare; 117 117 pm_cpu_sleep = s3c2410_cpu_suspend;
+2 -1
arch/arm/mach-s3c2412/cpu-freq.c
··· 194 194 .debug_io_show = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs), 195 195 }; 196 196 197 - static int s3c2412_cpufreq_add(struct device *dev) 197 + static int s3c2412_cpufreq_add(struct device *dev, 198 + struct subsys_interface *sif) 198 199 { 199 200 unsigned long fclk_rate; 200 201
+2 -1
arch/arm/mach-s3c2412/dma.c
··· 159 159 .map_size = ARRAY_SIZE(s3c2412_dma_mappings), 160 160 }; 161 161 162 - static int __init s3c2412_dma_add(struct device *dev) 162 + static int __init s3c2412_dma_add(struct device *dev, 163 + struct subsys_interface *sif) 163 164 { 164 165 s3c2410_dma_init(); 165 166 return s3c24xx_dma_init_map(&s3c2412_dma_sel);
+1 -1
arch/arm/mach-s3c2412/irq.c
··· 170 170 171 171 static struct irq_chip s3c2412_irq_rtc_chip; 172 172 173 - static int s3c2412_irq_add(struct device *dev) 173 + static int s3c2412_irq_add(struct device *dev, struct subsys_interface *sif) 174 174 { 175 175 unsigned int irqno; 176 176
+1 -1
arch/arm/mach-s3c2412/pm.c
··· 56 56 { 57 57 } 58 58 59 - static int s3c2412_pm_add(struct device *dev) 59 + static int s3c2412_pm_add(struct device *dev, struct subsys_interface *sif) 60 60 { 61 61 pm_cpu_prep = s3c2412_pm_prepare; 62 62 pm_cpu_sleep = s3c2412_cpu_suspend;
+2 -1
arch/arm/mach-s3c2416/irq.c
··· 213 213 return 0; 214 214 } 215 215 216 - static int __init s3c2416_irq_add(struct device *dev) 216 + static int __init s3c2416_irq_add(struct device *dev, 217 + struct subsys_interface *sif) 217 218 { 218 219 printk(KERN_INFO "S3C2416: IRQ Support\n"); 219 220
+1 -1
arch/arm/mach-s3c2416/pm.c
··· 48 48 __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1); 49 49 } 50 50 51 - static int s3c2416_pm_add(struct device *dev) 51 + static int s3c2416_pm_add(struct device *dev, struct subsys_interface *sif) 52 52 { 53 53 pm_cpu_prep = s3c2416_pm_prepare; 54 54 pm_cpu_sleep = s3c2416_cpu_suspend;
+1 -1
arch/arm/mach-s3c2440/clock.c
··· 149 149 CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n), 150 150 }; 151 151 152 - static int s3c2440_clk_add(struct device *dev) 152 + static int s3c2440_clk_add(struct device *dev, struct subsys_interface *sif) 153 153 { 154 154 struct clk *clock_upll; 155 155 struct clk *clock_h;
+2 -1
arch/arm/mach-s3c2440/dma.c
··· 174 174 }, 175 175 }; 176 176 177 - static int __init s3c2440_dma_add(struct device *dev) 177 + static int __init s3c2440_dma_add(struct device *dev, 178 + struct subsys_interface *sif) 178 179 { 179 180 s3c2410_dma_init(); 180 181 s3c24xx_dma_order_set(&s3c2440_dma_order);
+1 -1
arch/arm/mach-s3c2440/irq.c
··· 92 92 .irq_ack = s3c_irq_wdtac97_ack, 93 93 }; 94 94 95 - static int s3c2440_irq_add(struct device *dev) 95 + static int s3c2440_irq_add(struct device *dev, struct subsys_interface *sif) 96 96 { 97 97 unsigned int irqno; 98 98
+2 -1
arch/arm/mach-s3c2440/s3c2440-cpufreq.c
··· 270 270 .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs), 271 271 }; 272 272 273 - static int s3c2440_cpufreq_add(struct device *dev) 273 + static int s3c2440_cpufreq_add(struct device *dev, 274 + struct subsys_interface *sif) 274 275 { 275 276 xtal = s3c_cpufreq_clk_get(NULL, "xtal"); 276 277 hclk = s3c_cpufreq_clk_get(NULL, "hclk");
+1 -1
arch/arm/mach-s3c2440/s3c2440-pll-12000000.c
··· 51 51 { .frequency = 400000000, .index = PLLVAL(0x5c, 1, 1), }, /* FVco 800.000000 */ 52 52 }; 53 53 54 - static int s3c2440_plls12_add(struct device *dev) 54 + static int s3c2440_plls12_add(struct device *dev, struct subsys_interface *sif) 55 55 { 56 56 struct clk *xtal_clk; 57 57 unsigned long xtal;
+2 -1
arch/arm/mach-s3c2440/s3c2440-pll-16934400.c
··· 79 79 { .frequency = 402192000, .index = PLLVAL(87, 2, 1), }, /* FVco 804.384000 */ 80 80 }; 81 81 82 - static int s3c2440_plls169344_add(struct device *dev) 82 + static int s3c2440_plls169344_add(struct device *dev, 83 + struct subsys_interface *sif) 83 84 { 84 85 struct clk *xtal_clk; 85 86 unsigned long xtal;
+1 -1
arch/arm/mach-s3c2440/s3c2442.c
··· 122 122 }, 123 123 }; 124 124 125 - static int s3c2442_clk_add(struct device *dev) 125 + static int s3c2442_clk_add(struct device *dev, struct subsys_interface *sif) 126 126 { 127 127 struct clk *clock_upll; 128 128 struct clk *clock_h;
+1 -1
arch/arm/mach-s3c2440/s3c244x-clock.c
··· 72 72 }, 73 73 }; 74 74 75 - static int s3c244x_clk_add(struct device *dev) 75 + static int s3c244x_clk_add(struct device *dev, struct subsys_interface *sif) 76 76 { 77 77 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); 78 78 unsigned long clkdivn;
+1 -1
arch/arm/mach-s3c2440/s3c244x-irq.c
··· 91 91 .irq_ack = s3c_irq_cam_ack, 92 92 }; 93 93 94 - static int s3c244x_irq_add(struct device *dev) 94 + static int s3c244x_irq_add(struct device *dev, struct subsys_interface *sif) 95 95 { 96 96 unsigned int irqno; 97 97
+2 -1
arch/arm/mach-s3c2443/dma.c
··· 135 135 .map_size = ARRAY_SIZE(s3c2443_dma_mappings), 136 136 }; 137 137 138 - static int __init s3c2443_dma_add(struct device *dev) 138 + static int __init s3c2443_dma_add(struct device *dev, 139 + struct subsys_interface *sif) 139 140 { 140 141 s3c24xx_dma_init(6, IRQ_S3C2443_DMA0, 0x100); 141 142 return s3c24xx_dma_init_map(&s3c2443_dma_sel);
+2 -1
arch/arm/mach-s3c2443/irq.c
··· 241 241 return 0; 242 242 } 243 243 244 - static int __init s3c2443_irq_add(struct device *dev) 244 + static int __init s3c2443_irq_add(struct device *dev, 245 + struct subsys_interface *sif) 245 246 { 246 247 printk("S3C2443: IRQ Support\n"); 247 248
+5
arch/arm/mach-s3c64xx/clock.c
··· 138 138 .ctrlbit = S3C_CLKCON_PCLK_TSADC, 139 139 }, { 140 140 .name = "i2c", 141 + #ifdef CONFIG_S3C_DEV_I2C1 142 + .devname = "s3c2440-i2c.0", 143 + #else 144 + .devname = "s3c2440-i2c", 145 + #endif 141 146 .parent = &clk_p, 142 147 .enable = s3c64xx_pclk_ctrl, 143 148 .ctrlbit = S3C_CLKCON_PCLK_IIC,
+1 -1
arch/arm/mach-s3c64xx/common.c
··· 49 49 50 50 /* uart registration process */ 51 51 52 - void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) 52 + static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) 53 53 { 54 54 s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no); 55 55 }
+1 -1
arch/arm/mach-s5p64x0/pm.c
··· 160 160 161 161 } 162 162 163 - static int s5p64x0_pm_add(struct device *dev) 163 + static int s5p64x0_pm_add(struct device *dev, struct subsys_interface *sif) 164 164 { 165 165 pm_cpu_prep = s5p64x0_pm_prepare; 166 166 pm_cpu_sleep = s5p64x0_cpu_suspend;
+2 -2
arch/arm/mach-s5pv210/clock.c
··· 175 175 return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable); 176 176 } 177 177 178 - static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable) 178 + static int s5pv210_clk_hdmiphy_ctrl(struct clk *clk, int enable) 179 179 { 180 180 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable); 181 181 } ··· 372 372 }, { 373 373 .name = "hdmiphy", 374 374 .devname = "s5pv210-hdmi", 375 - .enable = exynos4_clk_hdmiphy_ctrl, 375 + .enable = s5pv210_clk_hdmiphy_ctrl, 376 376 .ctrlbit = (1 << 0), 377 377 }, { 378 378 .name = "dacphy",
+1 -1
arch/arm/mach-s5pv210/pm.c
··· 133 133 s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save)); 134 134 } 135 135 136 - static int s5pv210_pm_add(struct device *dev) 136 + static int s5pv210_pm_add(struct device *dev, struct subsys_interface *sif) 137 137 { 138 138 pm_cpu_prep = s5pv210_pm_prepare; 139 139 pm_cpu_sleep = s5pv210_cpu_suspend;
+4 -4
arch/arm/mach-tegra/board-paz00.c
··· 60 60 .uartclk = 216000000, 61 61 }, { 62 62 /* serial port on mini-pcie */ 63 - .membase = IO_ADDRESS(TEGRA_UARTD_BASE), 64 - .mapbase = TEGRA_UARTD_BASE, 65 - .irq = INT_UARTD, 63 + .membase = IO_ADDRESS(TEGRA_UARTC_BASE), 64 + .mapbase = TEGRA_UARTC_BASE, 65 + .irq = INT_UARTC, 66 66 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE, 67 67 .type = PORT_TEGRA, 68 68 .iotype = UPIO_MEM, ··· 174 174 static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = { 175 175 /* name parent rate enabled */ 176 176 { "uarta", "pll_p", 216000000, true }, 177 - { "uartd", "pll_p", 216000000, true }, 177 + { "uartc", "pll_p", 216000000, true }, 178 178 179 179 { "pll_p_out4", "pll_p", 24000000, true }, 180 180 { "usbd", "clk_m", 12000000, false },
+1 -1
arch/arm/mach-tegra/board-paz00.h
··· 22 22 /* SDCARD */ 23 23 #define TEGRA_GPIO_SD1_CD TEGRA_GPIO_PV5 24 24 #define TEGRA_GPIO_SD1_WP TEGRA_GPIO_PH1 25 - #define TEGRA_GPIO_SD1_POWER TEGRA_GPIO_PT3 25 + #define TEGRA_GPIO_SD1_POWER TEGRA_GPIO_PV1 26 26 27 27 /* ULPI */ 28 28 #define TEGRA_ULPI_RST TEGRA_GPIO_PV0
+5 -5
arch/arm/mach-tegra/include/mach/dma.h
··· 23 23 24 24 #include <linux/list.h> 25 25 26 - #if defined(CONFIG_TEGRA_SYSTEM_DMA) 27 - 28 - struct tegra_dma_req; 29 - struct tegra_dma_channel; 30 - 31 26 #define TEGRA_DMA_REQ_SEL_CNTR 0 32 27 #define TEGRA_DMA_REQ_SEL_I2S_2 1 33 28 #define TEGRA_DMA_REQ_SEL_I2S_1 2 ··· 50 55 #define TEGRA_DMA_REQ_SEL_DVC_I2C 24 51 56 #define TEGRA_DMA_REQ_SEL_OWR 25 52 57 #define TEGRA_DMA_REQ_SEL_INVALID 31 58 + 59 + #if defined(CONFIG_TEGRA_SYSTEM_DMA) 60 + 61 + struct tegra_dma_req; 62 + struct tegra_dma_channel; 53 63 54 64 enum tegra_dma_mode { 55 65 TEGRA_DMA_SHARED = 1,
+1 -1
arch/arm/plat-omap/include/plat/omap-secure.h
··· 3 3 4 4 #include <linux/types.h> 5 5 6 - #ifdef CONFIG_ARCH_OMAP2PLUS 6 + #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) 7 7 extern int omap_secure_ram_reserve_memblock(void); 8 8 #else 9 9 static inline void omap_secure_ram_reserve_memblock(void)
+4 -5
arch/arm/plat-orion/common.c
··· 789 789 /***************************************************************************** 790 790 * EHCI 791 791 ****************************************************************************/ 792 - static struct orion_ehci_data orion_ehci_data = { 793 - .phy_version = EHCI_PHY_NA, 794 - }; 795 - 792 + static struct orion_ehci_data orion_ehci_data; 796 793 static u64 ehci_dmamask = DMA_BIT_MASK(32); 797 794 798 795 ··· 809 812 }; 810 813 811 814 void __init orion_ehci_init(unsigned long mapbase, 812 - unsigned long irq) 815 + unsigned long irq, 816 + enum orion_ehci_phy_ver phy_version) 813 817 { 818 + orion_ehci_data.phy_version = phy_version; 814 819 fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1, 815 820 irq); 816 821
+2 -1
arch/arm/plat-orion/include/plat/common.h
··· 89 89 unsigned long irq_1); 90 90 91 91 void __init orion_ehci_init(unsigned long mapbase, 92 - unsigned long irq); 92 + unsigned long irq, 93 + enum orion_ehci_phy_ver phy_version); 93 94 94 95 void __init orion_ehci_1_init(unsigned long mapbase, 95 96 unsigned long irq);
+1 -2
arch/arm/plat-orion/mpp.c
··· 64 64 gpio_mode |= GPIO_INPUT_OK; 65 65 if (*mpp_list & MPP_OUTPUT_MASK) 66 66 gpio_mode |= GPIO_OUTPUT_OK; 67 - if (sel != 0) 68 - gpio_mode = 0; 67 + 69 68 orion_gpio_set_valid(num, gpio_mode); 70 69 } 71 70
+3 -1
arch/arm/plat-samsung/devs.c
··· 468 468 { 469 469 struct s3c2410_platform_i2c *npd; 470 470 471 - if (!pd) 471 + if (!pd) { 472 472 pd = &default_i2c_data; 473 + pd->bus_num = 0; 474 + } 473 475 474 476 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), 475 477 &s3c_device_i2c0);
+20 -26
drivers/ata/pata_at91.c
··· 207 207 { 208 208 int ret = 0; 209 209 int use_iordy; 210 + struct sam9_smc_config smc; 210 211 unsigned int t6z; /* data tristate time in ns */ 211 212 unsigned int cycle; /* SMC Cycle width in MCK ticks */ 212 213 unsigned int setup; /* SMC Setup width in MCK ticks */ 213 214 unsigned int pulse; /* CFIOR and CFIOW pulse width in MCK ticks */ 214 - unsigned int cs_setup = 0;/* CS4 or CS5 setup width in MCK ticks */ 215 215 unsigned int cs_pulse; /* CS4 or CS5 pulse width in MCK ticks*/ 216 216 unsigned int tdf_cycles; /* SMC TDF MCK ticks */ 217 217 unsigned long mck_hz; /* MCK frequency in Hz */ ··· 244 244 } 245 245 246 246 dev_dbg(dev, "Use IORDY=%u, TDF Cycles=%u\n", use_iordy, tdf_cycles); 247 - info->mode |= AT91_SMC_TDF_(tdf_cycles); 248 247 249 - /* write SMC Setup Register */ 250 - at91_sys_write(AT91_SMC_SETUP(info->cs), 251 - AT91_SMC_NWESETUP_(setup) | 252 - AT91_SMC_NRDSETUP_(setup) | 253 - AT91_SMC_NCS_WRSETUP_(cs_setup) | 254 - AT91_SMC_NCS_RDSETUP_(cs_setup)); 255 - /* write SMC Pulse Register */ 256 - at91_sys_write(AT91_SMC_PULSE(info->cs), 257 - AT91_SMC_NWEPULSE_(pulse) | 258 - AT91_SMC_NRDPULSE_(pulse) | 259 - AT91_SMC_NCS_WRPULSE_(cs_pulse) | 260 - AT91_SMC_NCS_RDPULSE_(cs_pulse)); 261 - /* write SMC Cycle Register */ 262 - at91_sys_write(AT91_SMC_CYCLE(info->cs), 263 - AT91_SMC_NWECYCLE_(cycle) | 264 - AT91_SMC_NRDCYCLE_(cycle)); 265 - /* write SMC Mode Register*/ 266 - at91_sys_write(AT91_SMC_MODE(info->cs), info->mode); 248 + /* SMC Setup Register */ 249 + smc.nwe_setup = smc.nrd_setup = setup; 250 + smc.ncs_write_setup = smc.ncs_read_setup = 0; 251 + /* SMC Pulse Register */ 252 + smc.nwe_pulse = smc.nrd_pulse = pulse; 253 + smc.ncs_write_pulse = smc.ncs_read_pulse = cs_pulse; 254 + /* SMC Cycle Register */ 255 + smc.write_cycle = smc.read_cycle = cycle; 256 + /* SMC Mode Register*/ 257 + smc.tdf_cycles = tdf_cycles; 258 + smc.mode = info->mode; 259 + 260 + sam9_smc_configure(0, info->cs, &smc); 267 261 } 268 262 269 263 static void pata_at91_set_piomode(struct ata_port *ap, struct ata_device *adev) ··· 282 288 struct at91_ide_info *info = dev->link->ap->host->private_data; 283 289 unsigned int consumed; 284 290 unsigned long flags; 285 - unsigned int mode; 291 + struct sam9_smc_config smc; 286 292 287 293 local_irq_save(flags); 288 - mode = at91_sys_read(AT91_SMC_MODE(info->cs)); 294 + sam9_smc_read_mode(0, info->cs, &smc); 289 295 290 296 /* set 16bit mode before writing data */ 291 - at91_sys_write(AT91_SMC_MODE(info->cs), 292 - (mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_16); 297 + smc.mode = (smc.mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_16; 298 + sam9_smc_write_mode(0, info->cs, &smc); 293 299 294 300 consumed = ata_sff_data_xfer(dev, buf, buflen, rw); 295 301 296 302 /* restore 8bit mode after data is written */ 297 - at91_sys_write(AT91_SMC_MODE(info->cs), 298 - (mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_8); 303 + smc.mode = (smc.mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_8; 304 + sam9_smc_write_mode(0, info->cs, &smc); 299 305 300 306 local_irq_restore(flags); 301 307 return consumed;
+1 -1
drivers/i2c/busses/i2c-tegra.c
··· 755 755 756 756 static struct platform_driver tegra_i2c_driver = { 757 757 .probe = tegra_i2c_probe, 758 - .remove = tegra_i2c_remove, 758 + .remove = __devexit_p(tegra_i2c_remove), 759 759 #ifdef CONFIG_PM 760 760 .suspend = tegra_i2c_suspend, 761 761 .resume = tegra_i2c_resume,
-1
drivers/ide/Makefile
··· 116 116 117 117 obj-$(CONFIG_BLK_DEV_IDE_TX4938) += tx4938ide.o 118 118 obj-$(CONFIG_BLK_DEV_IDE_TX4939) += tx4939ide.o 119 - obj-$(CONFIG_BLK_DEV_IDE_AT91) += at91_ide.o
-366
drivers/ide/at91_ide.c
··· 1 - /* 2 - * IDE host driver for AT91 (SAM9, CAP9, AT572D940HF) Static Memory Controller 3 - * with Compact Flash True IDE logic 4 - * 5 - * Copyright (c) 2008, 2009 Kelvatek Ltd. 6 - * 7 - * This program is free software; you can redistribute it and/or modify 8 - * it under the terms of the GNU General Public License as published by 9 - * the Free Software Foundation; either version 2 of the License, or 10 - * (at your option) any later version. 11 - * 12 - * This program is distributed in the hope that it will be useful, 13 - * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 - * GNU General Public License for more details. 16 - * 17 - * You should have received a copy of the GNU General Public License 18 - * along with this program; if not, write to the Free Software 19 - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 - * 21 - */ 22 - 23 - #include <linux/kernel.h> 24 - #include <linux/module.h> 25 - #include <linux/clk.h> 26 - #include <linux/err.h> 27 - #include <linux/ide.h> 28 - #include <linux/platform_device.h> 29 - 30 - #include <mach/board.h> 31 - #include <asm/gpio.h> 32 - #include <mach/at91sam9_smc.h> 33 - 34 - #define DRV_NAME "at91_ide" 35 - 36 - #define perr(fmt, args...) pr_err(DRV_NAME ": " fmt, ##args) 37 - #define pdbg(fmt, args...) pr_debug("%s " fmt, __func__, ##args) 38 - 39 - /* 40 - * Access to IDE device is possible through EBI Static Memory Controller 41 - * with Compact Flash logic. For details see EBI and SMC datasheet sections 42 - * of any microcontroller from AT91SAM9 family. 43 - * 44 - * Within SMC chip select address space, lines A[23:21] distinguish Compact 45 - * Flash modes (I/O, common memory, attribute memory, True IDE). IDE modes are: 46 - * 0x00c0000 - True IDE 47 - * 0x00e0000 - Alternate True IDE (Alt Status Register) 48 - * 49 - * On True IDE mode Task File and Data Register are mapped at the same address. 50 - * To distinguish access between these two different bus data width is used: 51 - * 8Bit for Task File, 16Bit for Data I/O. 52 - * 53 - * After initialization we do 8/16 bit flipping (changes in SMC MODE register) 54 - * only inside IDE callback routines which are serialized by IDE layer, 55 - * so no additional locking needed. 56 - */ 57 - 58 - #define TASK_FILE 0x00c00000 59 - #define ALT_MODE 0x00e00000 60 - #define REGS_SIZE 8 61 - 62 - #define enter_16bit(cs, mode) do { \ 63 - mode = at91_sys_read(AT91_SMC_MODE(cs)); \ 64 - at91_sys_write(AT91_SMC_MODE(cs), mode | AT91_SMC_DBW_16); \ 65 - } while (0) 66 - 67 - #define leave_16bit(cs, mode) at91_sys_write(AT91_SMC_MODE(cs), mode); 68 - 69 - static void set_smc_timings(const u8 chipselect, const u16 cycle, 70 - const u16 setup, const u16 pulse, 71 - const u16 data_float, int use_iordy) 72 - { 73 - unsigned long mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | 74 - AT91_SMC_BAT_SELECT; 75 - 76 - /* disable or enable waiting for IORDY signal */ 77 - if (use_iordy) 78 - mode |= AT91_SMC_EXNWMODE_READY; 79 - 80 - /* add data float cycles if needed */ 81 - if (data_float) 82 - mode |= AT91_SMC_TDF_(data_float); 83 - 84 - at91_sys_write(AT91_SMC_MODE(chipselect), mode); 85 - 86 - /* setup timings in SMC */ 87 - at91_sys_write(AT91_SMC_SETUP(chipselect), AT91_SMC_NWESETUP_(setup) | 88 - AT91_SMC_NCS_WRSETUP_(0) | 89 - AT91_SMC_NRDSETUP_(setup) | 90 - AT91_SMC_NCS_RDSETUP_(0)); 91 - at91_sys_write(AT91_SMC_PULSE(chipselect), AT91_SMC_NWEPULSE_(pulse) | 92 - AT91_SMC_NCS_WRPULSE_(cycle) | 93 - AT91_SMC_NRDPULSE_(pulse) | 94 - AT91_SMC_NCS_RDPULSE_(cycle)); 95 - at91_sys_write(AT91_SMC_CYCLE(chipselect), AT91_SMC_NWECYCLE_(cycle) | 96 - AT91_SMC_NRDCYCLE_(cycle)); 97 - } 98 - 99 - static unsigned int calc_mck_cycles(unsigned int ns, unsigned int mck_hz) 100 - { 101 - u64 tmp = ns; 102 - 103 - tmp *= mck_hz; 104 - tmp += 1000*1000*1000 - 1; /* round up */ 105 - do_div(tmp, 1000*1000*1000); 106 - return (unsigned int) tmp; 107 - } 108 - 109 - static void apply_timings(const u8 chipselect, const u8 pio, 110 - const struct ide_timing *timing, int use_iordy) 111 - { 112 - unsigned int t0, t1, t2, t6z; 113 - unsigned int cycle, setup, pulse, data_float; 114 - unsigned int mck_hz; 115 - struct clk *mck; 116 - 117 - /* see table 22 of Compact Flash standard 4.1 for the meaning, 118 - * we do not stretch active (t2) time, so setup (t1) + hold time (th) 119 - * assure at least minimal recovery (t2i) time */ 120 - t0 = timing->cyc8b; 121 - t1 = timing->setup; 122 - t2 = timing->act8b; 123 - t6z = (pio < 5) ? 30 : 20; 124 - 125 - pdbg("t0=%u t1=%u t2=%u t6z=%u\n", t0, t1, t2, t6z); 126 - 127 - mck = clk_get(NULL, "mck"); 128 - BUG_ON(IS_ERR(mck)); 129 - mck_hz = clk_get_rate(mck); 130 - pdbg("mck_hz=%u\n", mck_hz); 131 - 132 - cycle = calc_mck_cycles(t0, mck_hz); 133 - setup = calc_mck_cycles(t1, mck_hz); 134 - pulse = calc_mck_cycles(t2, mck_hz); 135 - data_float = calc_mck_cycles(t6z, mck_hz); 136 - 137 - pdbg("cycle=%u setup=%u pulse=%u data_float=%u\n", 138 - cycle, setup, pulse, data_float); 139 - 140 - set_smc_timings(chipselect, cycle, setup, pulse, data_float, use_iordy); 141 - } 142 - 143 - static void at91_ide_input_data(ide_drive_t *drive, struct ide_cmd *cmd, 144 - void *buf, unsigned int len) 145 - { 146 - ide_hwif_t *hwif = drive->hwif; 147 - struct ide_io_ports *io_ports = &hwif->io_ports; 148 - u8 chipselect = hwif->select_data; 149 - unsigned long mode; 150 - 151 - pdbg("cs %u buf %p len %d\n", chipselect, buf, len); 152 - 153 - len++; 154 - 155 - enter_16bit(chipselect, mode); 156 - readsw((void __iomem *)io_ports->data_addr, buf, len / 2); 157 - leave_16bit(chipselect, mode); 158 - } 159 - 160 - static void at91_ide_output_data(ide_drive_t *drive, struct ide_cmd *cmd, 161 - void *buf, unsigned int len) 162 - { 163 - ide_hwif_t *hwif = drive->hwif; 164 - struct ide_io_ports *io_ports = &hwif->io_ports; 165 - u8 chipselect = hwif->select_data; 166 - unsigned long mode; 167 - 168 - pdbg("cs %u buf %p len %d\n", chipselect, buf, len); 169 - 170 - enter_16bit(chipselect, mode); 171 - writesw((void __iomem *)io_ports->data_addr, buf, len / 2); 172 - leave_16bit(chipselect, mode); 173 - } 174 - 175 - static void at91_ide_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) 176 - { 177 - struct ide_timing *timing; 178 - u8 chipselect = hwif->select_data; 179 - int use_iordy = 0; 180 - const u8 pio = drive->pio_mode - XFER_PIO_0; 181 - 182 - pdbg("chipselect %u pio %u\n", chipselect, pio); 183 - 184 - timing = ide_timing_find_mode(XFER_PIO_0 + pio); 185 - BUG_ON(!timing); 186 - 187 - if (ide_pio_need_iordy(drive, pio)) 188 - use_iordy = 1; 189 - 190 - apply_timings(chipselect, pio, timing, use_iordy); 191 - } 192 - 193 - static const struct ide_tp_ops at91_ide_tp_ops = { 194 - .exec_command = ide_exec_command, 195 - .read_status = ide_read_status, 196 - .read_altstatus = ide_read_altstatus, 197 - .write_devctl = ide_write_devctl, 198 - 199 - .dev_select = ide_dev_select, 200 - .tf_load = ide_tf_load, 201 - .tf_read = ide_tf_read, 202 - 203 - .input_data = at91_ide_input_data, 204 - .output_data = at91_ide_output_data, 205 - }; 206 - 207 - static const struct ide_port_ops at91_ide_port_ops = { 208 - .set_pio_mode = at91_ide_set_pio_mode, 209 - }; 210 - 211 - static const struct ide_port_info at91_ide_port_info __initdata = { 212 - .port_ops = &at91_ide_port_ops, 213 - .tp_ops = &at91_ide_tp_ops, 214 - .host_flags = IDE_HFLAG_MMIO | IDE_HFLAG_NO_DMA | IDE_HFLAG_SINGLE | 215 - IDE_HFLAG_NO_IO_32BIT | IDE_HFLAG_UNMASK_IRQS, 216 - .pio_mask = ATA_PIO6, 217 - .chipset = ide_generic, 218 - }; 219 - 220 - /* 221 - * If interrupt is delivered through GPIO, IRQ are triggered on falling 222 - * and rising edge of signal. Whereas IDE device request interrupt on high 223 - * level (rising edge in our case). This mean we have fake interrupts, so 224 - * we need to check interrupt pin and exit instantly from ISR when line 225 - * is on low level. 226 - */ 227 - 228 - irqreturn_t at91_irq_handler(int irq, void *dev_id) 229 - { 230 - int ntries = 8; 231 - int pin_val1, pin_val2; 232 - 233 - /* additional deglitch, line can be noisy in badly designed PCB */ 234 - do { 235 - pin_val1 = at91_get_gpio_value(irq); 236 - pin_val2 = at91_get_gpio_value(irq); 237 - } while (pin_val1 != pin_val2 && --ntries > 0); 238 - 239 - if (pin_val1 == 0 || ntries <= 0) 240 - return IRQ_HANDLED; 241 - 242 - return ide_intr(irq, dev_id); 243 - } 244 - 245 - static int __init at91_ide_probe(struct platform_device *pdev) 246 - { 247 - int ret; 248 - struct ide_hw hw, *hws[] = { &hw }; 249 - struct ide_host *host; 250 - struct resource *res; 251 - unsigned long tf_base = 0, ctl_base = 0; 252 - struct at91_cf_data *board = pdev->dev.platform_data; 253 - 254 - if (!board) 255 - return -ENODEV; 256 - 257 - if (board->det_pin && at91_get_gpio_value(board->det_pin) != 0) { 258 - perr("no device detected\n"); 259 - return -ENODEV; 260 - } 261 - 262 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 263 - if (!res) { 264 - perr("can't get memory resource\n"); 265 - return -ENODEV; 266 - } 267 - 268 - if (!devm_request_mem_region(&pdev->dev, res->start + TASK_FILE, 269 - REGS_SIZE, "ide") || 270 - !devm_request_mem_region(&pdev->dev, res->start + ALT_MODE, 271 - REGS_SIZE, "alt")) { 272 - perr("memory resources in use\n"); 273 - return -EBUSY; 274 - } 275 - 276 - pdbg("chipselect %u irq %u res %08lx\n", board->chipselect, 277 - board->irq_pin, (unsigned long) res->start); 278 - 279 - tf_base = (unsigned long) devm_ioremap(&pdev->dev, res->start + TASK_FILE, 280 - REGS_SIZE); 281 - ctl_base = (unsigned long) devm_ioremap(&pdev->dev, res->start + ALT_MODE, 282 - REGS_SIZE); 283 - if (!tf_base || !ctl_base) { 284 - perr("can't map memory regions\n"); 285 - return -EBUSY; 286 - } 287 - 288 - memset(&hw, 0, sizeof(hw)); 289 - 290 - if (board->flags & AT91_IDE_SWAP_A0_A2) { 291 - /* workaround for stupid hardware bug */ 292 - hw.io_ports.data_addr = tf_base + 0; 293 - hw.io_ports.error_addr = tf_base + 4; 294 - hw.io_ports.nsect_addr = tf_base + 2; 295 - hw.io_ports.lbal_addr = tf_base + 6; 296 - hw.io_ports.lbam_addr = tf_base + 1; 297 - hw.io_ports.lbah_addr = tf_base + 5; 298 - hw.io_ports.device_addr = tf_base + 3; 299 - hw.io_ports.command_addr = tf_base + 7; 300 - hw.io_ports.ctl_addr = ctl_base + 3; 301 - } else 302 - ide_std_init_ports(&hw, tf_base, ctl_base + 6); 303 - 304 - hw.irq = board->irq_pin; 305 - hw.dev = &pdev->dev; 306 - 307 - host = ide_host_alloc(&at91_ide_port_info, hws, 1); 308 - if (!host) { 309 - perr("failed to allocate ide host\n"); 310 - return -ENOMEM; 311 - } 312 - 313 - /* setup Static Memory Controller - PIO 0 as default */ 314 - apply_timings(board->chipselect, 0, ide_timing_find_mode(XFER_PIO_0), 0); 315 - 316 - /* with GPIO interrupt we have to do quirks in handler */ 317 - if (gpio_is_valid(board->irq_pin)) 318 - host->irq_handler = at91_irq_handler; 319 - 320 - host->ports[0]->select_data = board->chipselect; 321 - 322 - ret = ide_host_register(host, &at91_ide_port_info, hws); 323 - if (ret) { 324 - perr("failed to register ide host\n"); 325 - goto err_free_host; 326 - } 327 - platform_set_drvdata(pdev, host); 328 - return 0; 329 - 330 - err_free_host: 331 - ide_host_free(host); 332 - return ret; 333 - } 334 - 335 - static int __exit at91_ide_remove(struct platform_device *pdev) 336 - { 337 - struct ide_host *host = platform_get_drvdata(pdev); 338 - 339 - ide_host_remove(host); 340 - return 0; 341 - } 342 - 343 - static struct platform_driver at91_ide_driver = { 344 - .driver = { 345 - .name = DRV_NAME, 346 - .owner = THIS_MODULE, 347 - }, 348 - .remove = __exit_p(at91_ide_remove), 349 - }; 350 - 351 - static int __init at91_ide_init(void) 352 - { 353 - return platform_driver_probe(&at91_ide_driver, at91_ide_probe); 354 - } 355 - 356 - static void __exit at91_ide_exit(void) 357 - { 358 - platform_driver_unregister(&at91_ide_driver); 359 - } 360 - 361 - module_init(at91_ide_init); 362 - module_exit(at91_ide_exit); 363 - 364 - MODULE_LICENSE("GPL"); 365 - MODULE_AUTHOR("Stanislaw Gruszka <stf_xl@wp.pl>"); 366 -
+10 -3
drivers/rtc/rtc-at91sam9.c
··· 307 307 device_init_wakeup(&pdev->dev, 1); 308 308 309 309 platform_set_drvdata(pdev, rtc); 310 - rtc->rtt = (void __force __iomem *) (AT91_VA_BASE_SYS - AT91_BASE_SYS); 311 - rtc->rtt += r->start; 310 + rtc->rtt = ioremap(r->start, resource_size(r)); 311 + if (!rtc->rtt) { 312 + dev_err(&pdev->dev, "failed to map registers, aborting.\n"); 313 + ret = -ENOMEM; 314 + goto fail; 315 + } 312 316 313 317 mr = rtt_readl(rtc, MR); 314 318 ··· 330 326 &at91_rtc_ops, THIS_MODULE); 331 327 if (IS_ERR(rtc->rtcdev)) { 332 328 ret = PTR_ERR(rtc->rtcdev); 333 - goto fail; 329 + goto fail_register; 334 330 } 335 331 336 332 /* register irq handler after we know what name we'll use */ ··· 355 351 356 352 return 0; 357 353 354 + fail_register: 355 + iounmap(rtc->rtt); 358 356 fail: 359 357 platform_set_drvdata(pdev, NULL); 360 358 kfree(rtc); ··· 377 371 378 372 rtc_device_unregister(rtc->rtcdev); 379 373 374 + iounmap(rtc->rtt); 380 375 platform_set_drvdata(pdev, NULL); 381 376 kfree(rtc); 382 377 return 0;