tjh.dev / kernel
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clk: renesas: r9a07g043: Add SSIF-2 clock and reset entries

Add SSIF-2{0,1,2,3} clock and reset entries in CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220425095244.156720-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Biju Das and committed by
Geert Uytterhoeven be5b5fcb a9391e01

+20
+20
drivers/clk/renesas/r9a07g043-cpg.c
··· 144 144 0x554, 6), 145 145 DEF_MOD("sdhi1_aclk", R9A07G043_SDHI1_ACLK, R9A07G043_CLK_P1, 146 146 0x554, 7), 147 + DEF_MOD("ssi0_pclk", R9A07G043_SSI0_PCLK2, R9A07G043_CLK_P0, 148 + 0x570, 0), 149 + DEF_MOD("ssi0_sfr", R9A07G043_SSI0_PCLK_SFR, R9A07G043_CLK_P0, 150 + 0x570, 1), 151 + DEF_MOD("ssi1_pclk", R9A07G043_SSI1_PCLK2, R9A07G043_CLK_P0, 152 + 0x570, 2), 153 + DEF_MOD("ssi1_sfr", R9A07G043_SSI1_PCLK_SFR, R9A07G043_CLK_P0, 154 + 0x570, 3), 155 + DEF_MOD("ssi2_pclk", R9A07G043_SSI2_PCLK2, R9A07G043_CLK_P0, 156 + 0x570, 4), 157 + DEF_MOD("ssi2_sfr", R9A07G043_SSI2_PCLK_SFR, R9A07G043_CLK_P0, 158 + 0x570, 5), 159 + DEF_MOD("ssi3_pclk", R9A07G043_SSI3_PCLK2, R9A07G043_CLK_P0, 160 + 0x570, 6), 161 + DEF_MOD("ssi3_sfr", R9A07G043_SSI3_PCLK_SFR, R9A07G043_CLK_P0, 162 + 0x570, 7), 147 163 DEF_COUPLED("eth0_axi", R9A07G043_ETH0_CLK_AXI, R9A07G043_CLK_M0, 148 164 0x57c, 0), 149 165 DEF_COUPLED("eth0_chi", R9A07G043_ETH0_CLK_CHI, R9A07G043_CLK_ZT, ··· 202 186 DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1), 203 187 DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0), 204 188 DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1), 189 + DEF_RST(R9A07G043_SSI0_RST_M2_REG, 0x870, 0), 190 + DEF_RST(R9A07G043_SSI1_RST_M2_REG, 0x870, 1), 191 + DEF_RST(R9A07G043_SSI2_RST_M2_REG, 0x870, 2), 192 + DEF_RST(R9A07G043_SSI3_RST_M2_REG, 0x870, 3), 205 193 DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0), 206 194 DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1), 207 195 DEF_RST(R9A07G043_I2C0_MRST, 0x880, 0),