spi: cadence-qspi: Add Renesas RZ/N1 support

+88 -99

2 changed files

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Documentation

devicetree

bindings

spi

cdns,qspi-nor.yaml

drivers

spi

spi-cadence-quadspi.c

+17 -2

Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml

··· 61 61 cdns,fifo-depth: 62 62 enum: [ 128, 256 ] 63 63 default: 128 64 + - if: 65 + properties: 66 + compatible: 67 + contains: 68 + const: renesas,rzn1-qspi 69 + then: 70 + properties: 71 + cdns,trigger-address: false 72 + cdns,fifo-depth: false 73 + cdns,fifo-width: false 74 + else: 75 + required: 76 + - cdns,trigger-address 77 + - cdns,fifo-depth 64 78 65 79 properties: 66 80 compatible: ··· 94 80 # controllers are meant to be used with flashes of all kinds, 95 81 # ie. also NAND flashes, not only NOR flashes. 96 82 - const: cdns,qspi-nor 83 + - items: 84 + - const: renesas,r9a06g032-qspi 85 + - const: renesas,rzn1-qspi 97 86 - const: cdns,qspi-nor 98 87 deprecated: true 99 88 ··· 180 163 - reg 181 164 - interrupts 182 165 - clocks 183 - - cdns,fifo-width 184 - - cdns,trigger-address 185 166 - '#address-cells' 186 167 - '#size-cells' 187 168

+71 -97

drivers/spi/spi-cadence-quadspi.c

··· 57 57 #define CQSPI_OP_WIDTH(part) ((part).nbytes ? ilog2((part).buswidth) : 0) 58 58 59 59 enum { 60 - CLK_QSPI_APB = 0, 60 + CLK_QSPI_REF = 0, 61 + CLK_QSPI_APB, 61 62 CLK_QSPI_AHB, 62 63 CLK_QSPI_NUM, 63 64 }; ··· 79 78 struct cqspi_st { 80 79 struct platform_device *pdev; 81 80 struct spi_controller *host; 82 - struct clk *clk; 83 - struct clk *clks[CLK_QSPI_NUM]; 81 + struct clk_bulk_data clks[CLK_QSPI_NUM]; 84 82 unsigned int sclk; 85 83 86 84 void __iomem *iobase; ··· 110 110 bool apb_ahb_hazard; 111 111 112 112 bool is_jh7110; /* Flag for StarFive JH7110 SoC */ 113 + bool is_rzn1; /* Flag for Renesas RZ/N1 SoC */ 113 114 bool disable_stig_mode; 114 115 refcount_t refcount; 115 116 refcount_t inflight_ops; ··· 124 123 int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata, 125 124 u_char *rxbuf, loff_t from_addr, size_t n_rx); 126 125 u32 (*get_dma_status)(struct cqspi_st *cqspi); 127 - int (*jh7110_clk_init)(struct platform_device *pdev, 128 - struct cqspi_st *cqspi); 129 126 }; 130 127 131 128 /* Operation timeout value */ ··· 1338 1339 * mode. So, we can not use direct mode when in DTR mode for writing 1339 1340 * data. 1340 1341 */ 1341 - if (!op->cmd.dtr && cqspi->use_direct_mode && 1342 - cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) { 1342 + if ((!op->cmd.dtr && cqspi->use_direct_mode && 1343 + cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) || 1344 + (cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) { 1343 1345 memcpy_toio(cqspi->ahb_base + to, buf, len); 1344 1346 return cqspi_wait_idle(cqspi); 1345 1347 } ··· 1514 1514 static bool cqspi_supports_mem_op(struct spi_mem *mem, 1515 1515 const struct spi_mem_op *op) 1516 1516 { 1517 + struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller); 1517 1518 bool all_true, all_false; 1518 1519 1519 1520 /* ··· 1540 1539 1541 1540 /* A single opcode is supported, it will be repeated */ 1542 1541 if ((op->cmd.opcode >> 8) != (op->cmd.opcode & 0xFF)) 1542 + return false; 1543 + 1544 + if (cqspi->is_rzn1) 1543 1545 return false; 1544 1546 } else if (!all_false) { 1545 1547 /* Mixed DTR modes are not supported. */ ··· 1597 1593 1598 1594 cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); 1599 1595 1600 - if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { 1601 - /* Zero signals FIFO depth should be runtime detected. */ 1602 - cqspi->fifo_depth = 0; 1603 - } 1596 + if (!(cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) { 1597 + if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { 1598 + /* Zero signals FIFO depth should be runtime detected. */ 1599 + cqspi->fifo_depth = 0; 1600 + } 1604 1601 1605 - if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) 1606 - cqspi->fifo_width = 4; 1602 + if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) 1603 + cqspi->fifo_width = 4; 1607 1604 1608 - if (of_property_read_u32(np, "cdns,trigger-address", 1609 - &cqspi->trigger_address)) { 1610 - dev_err(dev, "couldn't determine trigger-address\n"); 1611 - return -ENXIO; 1605 + if (of_property_read_u32(np, "cdns,trigger-address", 1606 + &cqspi->trigger_address)) { 1607 + dev_err(dev, "couldn't determine trigger-address\n"); 1608 + return -ENXIO; 1609 + } 1612 1610 } 1613 1611 1614 1612 if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) ··· 1673 1667 { 1674 1668 struct device *dev = &cqspi->pdev->dev; 1675 1669 u32 reg, fifo_depth; 1670 + 1671 + if (cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE) 1672 + return; 1676 1673 1677 1674 /* 1678 1675 * Bits N-1:0 are writable while bits 31:N are read as zero, with 2^N ··· 1780 1771 return 0; 1781 1772 } 1782 1773 1783 - static int cqspi_jh7110_clk_init(struct platform_device *pdev, struct cqspi_st *cqspi) 1784 - { 1785 - static struct clk_bulk_data qspiclk[] = { 1786 - { .id = "apb" }, 1787 - { .id = "ahb" }, 1788 - }; 1789 - 1790 - int ret = 0; 1791 - 1792 - ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(qspiclk), qspiclk); 1793 - if (ret) { 1794 - dev_err(&pdev->dev, "%s: failed to get qspi clocks\n", __func__); 1795 - return ret; 1796 - } 1797 - 1798 - cqspi->clks[CLK_QSPI_APB] = qspiclk[0].clk; 1799 - cqspi->clks[CLK_QSPI_AHB] = qspiclk[1].clk; 1800 - 1801 - ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_APB]); 1802 - if (ret) { 1803 - dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_APB\n", __func__); 1804 - return ret; 1805 - } 1806 - 1807 - ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_AHB]); 1808 - if (ret) { 1809 - dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_AHB\n", __func__); 1810 - goto disable_apb_clk; 1811 - } 1812 - 1813 - cqspi->is_jh7110 = true; 1814 - 1815 - return 0; 1816 - 1817 - disable_apb_clk: 1818 - clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]); 1819 - 1820 - return ret; 1821 - } 1822 - 1823 - static void cqspi_jh7110_disable_clk(struct platform_device *pdev, struct cqspi_st *cqspi) 1824 - { 1825 - clk_disable_unprepare(cqspi->clks[CLK_QSPI_AHB]); 1826 - clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]); 1827 - } 1828 1774 static int cqspi_probe(struct platform_device *pdev) 1829 1775 { 1830 1776 const struct cqspi_driver_platdata *ddata; ··· 1788 1824 struct spi_controller *host; 1789 1825 struct resource *res_ahb; 1790 1826 struct cqspi_st *cqspi; 1791 - int ret; 1792 - int irq; 1827 + int ret, irq; 1793 1828 1794 1829 host = devm_spi_alloc_host(&pdev->dev, sizeof(*cqspi)); 1795 1830 if (!host) ··· 1799 1836 host->mem_caps = &cqspi_mem_caps; 1800 1837 1801 1838 cqspi = spi_controller_get_devdata(host); 1839 + if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) 1840 + cqspi->is_jh7110 = true; 1841 + if (of_device_is_compatible(pdev->dev.of_node, "renesas,rzn1-qspi")) 1842 + cqspi->is_rzn1 = true; 1802 1843 1803 1844 cqspi->pdev = pdev; 1804 1845 cqspi->host = host; 1805 - cqspi->is_jh7110 = false; 1806 1846 cqspi->ddata = ddata = of_device_get_match_data(dev); 1807 1847 platform_set_drvdata(pdev, cqspi); 1808 1848 ··· 1822 1856 return ret; 1823 1857 } 1824 1858 1825 - /* Obtain QSPI clock. */ 1826 - cqspi->clk = devm_clk_get(dev, NULL); 1827 - if (IS_ERR(cqspi->clk)) { 1828 - dev_err(dev, "Cannot claim QSPI clock.\n"); 1829 - ret = PTR_ERR(cqspi->clk); 1830 - return ret; 1859 + /* Obtain QSPI clocks. */ 1860 + ret = devm_clk_bulk_get_optional(dev, CLK_QSPI_NUM, cqspi->clks); 1861 + if (ret) 1862 + return dev_err_probe(dev, ret, "Failed to get clocks\n"); 1863 + 1864 + if (!cqspi->clks[CLK_QSPI_REF].clk) { 1865 + dev_err(dev, "Cannot claim mandatory QSPI ref clock.\n"); 1866 + return -ENODEV; 1831 1867 } 1832 1868 1833 1869 /* Obtain and remap controller address. */ ··· 1861 1893 if (ret) 1862 1894 return ret; 1863 1895 1864 - 1865 - ret = clk_prepare_enable(cqspi->clk); 1896 + ret = clk_bulk_prepare_enable(CLK_QSPI_NUM, cqspi->clks); 1866 1897 if (ret) { 1867 - dev_err(dev, "Cannot enable QSPI clock.\n"); 1898 + dev_err(dev, "Cannot enable QSPI clocks.\n"); 1868 1899 goto disable_rpm; 1869 1900 } 1870 1901 ··· 1872 1905 if (IS_ERR(rstc)) { 1873 1906 ret = PTR_ERR(rstc); 1874 1907 dev_err(dev, "Cannot get QSPI reset.\n"); 1875 - goto disable_clk; 1908 + goto disable_clks; 1876 1909 } 1877 1910 1878 1911 rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); 1879 1912 if (IS_ERR(rstc_ocp)) { 1880 1913 ret = PTR_ERR(rstc_ocp); 1881 1914 dev_err(dev, "Cannot get QSPI OCP reset.\n"); 1882 - goto disable_clk; 1915 + goto disable_clks; 1883 1916 } 1884 1917 1885 - if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) { 1918 + if (cqspi->is_jh7110) { 1886 1919 rstc_ref = devm_reset_control_get_optional_exclusive(dev, "rstc_ref"); 1887 1920 if (IS_ERR(rstc_ref)) { 1888 1921 ret = PTR_ERR(rstc_ref); 1889 1922 dev_err(dev, "Cannot get QSPI REF reset.\n"); 1890 - goto disable_clk; 1923 + goto disable_clks; 1891 1924 } 1892 1925 reset_control_assert(rstc_ref); 1893 1926 reset_control_deassert(rstc_ref); ··· 1899 1932 reset_control_assert(rstc_ocp); 1900 1933 reset_control_deassert(rstc_ocp); 1901 1934 1902 - cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); 1903 - host->max_speed_hz = cqspi->master_ref_clk_hz; 1935 + cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clks[CLK_QSPI_REF].clk); 1936 + if (!cqspi->is_rzn1) { 1937 + host->max_speed_hz = cqspi->master_ref_clk_hz; 1938 + } else { 1939 + host->max_speed_hz = cqspi->master_ref_clk_hz / 2; 1940 + host->min_speed_hz = cqspi->master_ref_clk_hz / 32; 1941 + } 1904 1942 1905 1943 /* write completion is supported by default */ 1906 1944 cqspi->wr_completion = true; ··· 1930 1958 cqspi->slow_sram = true; 1931 1959 if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) 1932 1960 cqspi->apb_ahb_hazard = true; 1933 - 1934 - if (ddata->jh7110_clk_init) { 1935 - ret = cqspi_jh7110_clk_init(pdev, cqspi); 1936 - if (ret) 1937 - goto disable_clk; 1938 - } 1939 1961 if (ddata->quirks & CQSPI_DISABLE_STIG_MODE) 1940 1962 cqspi->disable_stig_mode = true; 1941 1963 ··· 1970 2004 if (ddata && (ddata->quirks & CQSPI_SUPPORT_DEVICE_RESET)) 1971 2005 cqspi_device_reset(cqspi); 1972 2006 1973 - if (cqspi->use_direct_mode) { 2007 + if (cqspi->use_direct_mode && !cqspi->is_rzn1) { 1974 2008 ret = cqspi_request_mmap_dma(cqspi); 1975 2009 if (ret == -EPROBE_DEFER) { 1976 2010 dev_err_probe(&pdev->dev, ret, "Failed to request mmap DMA\n"); ··· 1995 2029 disable_controller: 1996 2030 cqspi_controller_enable(cqspi, 0); 1997 2031 disable_clks: 1998 - if (cqspi->is_jh7110) 1999 - cqspi_jh7110_disable_clk(pdev, cqspi); 2000 - disable_clk: 2001 2032 if (pm_runtime_get_sync(&pdev->dev) >= 0) 2002 - clk_disable_unprepare(cqspi->clk); 2033 + clk_bulk_disable_unprepare(CLK_QSPI_NUM, cqspi->clks); 2003 2034 disable_rpm: 2004 2035 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) 2005 2036 pm_runtime_disable(dev); ··· 2025 2062 2026 2063 cqspi_controller_enable(cqspi, 0); 2027 2064 2028 - if (cqspi->is_jh7110) 2029 - cqspi_jh7110_disable_clk(pdev, cqspi); 2030 2065 2031 2066 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) 2032 2067 ret = pm_runtime_get_sync(&pdev->dev); 2033 2068 2034 2069 if (ret >= 0) 2035 - clk_disable(cqspi->clk); 2070 + clk_bulk_disable_unprepare(CLK_QSPI_NUM, cqspi->clks); 2036 2071 2037 2072 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) { 2038 2073 pm_runtime_put_sync(&pdev->dev); ··· 2043 2082 struct cqspi_st *cqspi = dev_get_drvdata(dev); 2044 2083 2045 2084 cqspi_controller_enable(cqspi, 0); 2046 - clk_disable_unprepare(cqspi->clk); 2085 + clk_bulk_disable_unprepare(CLK_QSPI_NUM, cqspi->clks); 2047 2086 return 0; 2048 2087 } 2049 2088 2050 2089 static int cqspi_runtime_resume(struct device *dev) 2051 2090 { 2052 2091 struct cqspi_st *cqspi = dev_get_drvdata(dev); 2092 + int ret; 2053 2093 2054 - clk_prepare_enable(cqspi->clk); 2094 + ret = clk_bulk_prepare_enable(CLK_QSPI_NUM, cqspi->clks); 2095 + if (ret) 2096 + return ret; 2097 + 2055 2098 cqspi_wait_idle(cqspi); 2056 2099 cqspi_controller_enable(cqspi, 0); 2057 2100 cqspi_controller_init(cqspi); ··· 2138 2173 2139 2174 static const struct cqspi_driver_platdata jh7110_qspi = { 2140 2175 .quirks = CQSPI_DISABLE_DAC_MODE, 2141 - .jh7110_clk_init = cqspi_jh7110_clk_init, 2142 2176 }; 2143 2177 2144 2178 static const struct cqspi_driver_platdata pensando_cdns_qspi = { ··· 2148 2184 .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 2149 2185 .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_NO_SUPPORT_WR_COMPLETION | 2150 2186 CQSPI_RD_NO_IRQ, 2187 + }; 2188 + 2189 + static const struct cqspi_driver_platdata renesas_rzn1_qspi = { 2190 + .hwcaps_mask = CQSPI_SUPPORTS_QUAD, 2191 + .quirks = CQSPI_NO_SUPPORT_WR_COMPLETION | CQSPI_RD_NO_IRQ | 2192 + CQSPI_HAS_WR_PROTECT | CQSPI_NO_INDIRECT_MODE, 2151 2193 }; 2152 2194 2153 2195 static const struct of_device_id cqspi_dt_ids[] = { ··· 2196 2226 { 2197 2227 .compatible = "amd,versal2-ospi", 2198 2228 .data = &versal2_ospi, 2229 + }, 2230 + { 2231 + .compatible = "renesas,rzn1-qspi", 2232 + .data = &renesas_rzn1_qspi, 2199 2233 }, 2200 2234 { /* end of table */ } 2201 2235 };

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