Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
soc/tegra: fuse: Use SoC specific nvmem cells
Tegra FUSE block size, availability and offsets can vary from one SoC
generation to another.
Signed-off-by: Kartik <kkartik@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
authored by
Kartik
and committed by
Thierry Reding
bea06d77
28dbe823
+241
-111
+2
-108
drivers/soc/tegra/fuse/fuse-tegra.c
+2
-108
drivers/soc/tegra/fuse/fuse-tegra.c
···
94
94
return 0;
95
95
}
96
96
97
-
static const struct nvmem_cell_info tegra_fuse_cells[] = {
98
-
{
99
-
.name = "tsensor-cpu1",
100
-
.offset = 0x084,
101
-
.bytes = 4,
102
-
.bit_offset = 0,
103
-
.nbits = 32,
104
-
}, {
105
-
.name = "tsensor-cpu2",
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-
.offset = 0x088,
107
-
.bytes = 4,
108
-
.bit_offset = 0,
109
-
.nbits = 32,
110
-
}, {
111
-
.name = "tsensor-cpu0",
112
-
.offset = 0x098,
113
-
.bytes = 4,
114
-
.bit_offset = 0,
115
-
.nbits = 32,
116
-
}, {
117
-
.name = "xusb-pad-calibration",
118
-
.offset = 0x0f0,
119
-
.bytes = 4,
120
-
.bit_offset = 0,
121
-
.nbits = 32,
122
-
}, {
123
-
.name = "tsensor-cpu3",
124
-
.offset = 0x12c,
125
-
.bytes = 4,
126
-
.bit_offset = 0,
127
-
.nbits = 32,
128
-
}, {
129
-
.name = "sata-calibration",
130
-
.offset = 0x124,
131
-
.bytes = 1,
132
-
.bit_offset = 0,
133
-
.nbits = 2,
134
-
}, {
135
-
.name = "tsensor-gpu",
136
-
.offset = 0x154,
137
-
.bytes = 4,
138
-
.bit_offset = 0,
139
-
.nbits = 32,
140
-
}, {
141
-
.name = "tsensor-mem0",
142
-
.offset = 0x158,
143
-
.bytes = 4,
144
-
.bit_offset = 0,
145
-
.nbits = 32,
146
-
}, {
147
-
.name = "tsensor-mem1",
148
-
.offset = 0x15c,
149
-
.bytes = 4,
150
-
.bit_offset = 0,
151
-
.nbits = 32,
152
-
}, {
153
-
.name = "tsensor-pllx",
154
-
.offset = 0x160,
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-
.bytes = 4,
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-
.bit_offset = 0,
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-
.nbits = 32,
158
-
}, {
159
-
.name = "tsensor-common",
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-
.offset = 0x180,
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-
.bytes = 4,
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-
.bit_offset = 0,
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-
.nbits = 32,
164
-
}, {
165
-
.name = "gpu-gcplex-config-fuse",
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-
.offset = 0x1c8,
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-
.bytes = 4,
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-
.bit_offset = 0,
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-
.nbits = 32,
170
-
}, {
171
-
.name = "tsensor-realignment",
172
-
.offset = 0x1fc,
173
-
.bytes = 4,
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-
.bit_offset = 0,
175
-
.nbits = 32,
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-
}, {
177
-
.name = "gpu-calibration",
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.offset = 0x204,
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-
.bytes = 4,
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-
.bit_offset = 0,
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-
.nbits = 32,
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-
}, {
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-
.name = "xusb-pad-calibration-ext",
184
-
.offset = 0x250,
185
-
.bytes = 4,
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.bit_offset = 0,
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-
.nbits = 32,
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}, {
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-
.name = "gpu-pdi0",
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-
.offset = 0x300,
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.bytes = 4,
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-
.bit_offset = 0,
193
-
.nbits = 32,
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-
}, {
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-
.name = "gpu-pdi1",
196
-
.offset = 0x304,
197
-
.bytes = 4,
198
-
.bit_offset = 0,
199
-
.nbits = 32,
200
-
},
201
-
};
202
-
203
97
static void tegra_fuse_restore(void *base)
204
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{
205
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fuse->base = (void __iomem *)base;
···
147
253
nvmem.name = "fuse";
148
254
nvmem.id = -1;
149
255
nvmem.owner = THIS_MODULE;
150
-
nvmem.cells = tegra_fuse_cells;
151
-
nvmem.ncells = ARRAY_SIZE(tegra_fuse_cells);
256
+
nvmem.cells = fuse->soc->cells;
257
+
nvmem.ncells = fuse->soc->num_cells;
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nvmem.type = NVMEM_TYPE_OTP;
153
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nvmem.read_only = true;
154
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nvmem.root_only = true;
+237
-3
drivers/soc/tegra/fuse/fuse-tegra30.c
+237
-3
drivers/soc/tegra/fuse/fuse-tegra30.c
···
133
133
#endif
134
134
135
135
#if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
136
+
static const struct nvmem_cell_info tegra124_fuse_cells[] = {
137
+
{
138
+
.name = "tsensor-cpu1",
139
+
.offset = 0x084,
140
+
.bytes = 4,
141
+
.bit_offset = 0,
142
+
.nbits = 32,
143
+
}, {
144
+
.name = "tsensor-cpu2",
145
+
.offset = 0x088,
146
+
.bytes = 4,
147
+
.bit_offset = 0,
148
+
.nbits = 32,
149
+
}, {
150
+
.name = "tsensor-cpu0",
151
+
.offset = 0x098,
152
+
.bytes = 4,
153
+
.bit_offset = 0,
154
+
.nbits = 32,
155
+
}, {
156
+
.name = "xusb-pad-calibration",
157
+
.offset = 0x0f0,
158
+
.bytes = 4,
159
+
.bit_offset = 0,
160
+
.nbits = 32,
161
+
}, {
162
+
.name = "tsensor-cpu3",
163
+
.offset = 0x12c,
164
+
.bytes = 4,
165
+
.bit_offset = 0,
166
+
.nbits = 32,
167
+
}, {
168
+
.name = "sata-calibration",
169
+
.offset = 0x124,
170
+
.bytes = 4,
171
+
.bit_offset = 0,
172
+
.nbits = 32,
173
+
}, {
174
+
.name = "tsensor-gpu",
175
+
.offset = 0x154,
176
+
.bytes = 4,
177
+
.bit_offset = 0,
178
+
.nbits = 32,
179
+
}, {
180
+
.name = "tsensor-mem0",
181
+
.offset = 0x158,
182
+
.bytes = 4,
183
+
.bit_offset = 0,
184
+
.nbits = 32,
185
+
}, {
186
+
.name = "tsensor-mem1",
187
+
.offset = 0x15c,
188
+
.bytes = 4,
189
+
.bit_offset = 0,
190
+
.nbits = 32,
191
+
}, {
192
+
.name = "tsensor-pllx",
193
+
.offset = 0x160,
194
+
.bytes = 4,
195
+
.bit_offset = 0,
196
+
.nbits = 32,
197
+
}, {
198
+
.name = "tsensor-common",
199
+
.offset = 0x180,
200
+
.bytes = 4,
201
+
.bit_offset = 0,
202
+
.nbits = 32,
203
+
}, {
204
+
.name = "tsensor-realignment",
205
+
.offset = 0x1fc,
206
+
.bytes = 4,
207
+
.bit_offset = 0,
208
+
.nbits = 32,
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+
},
210
+
};
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+
136
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static const struct nvmem_cell_lookup tegra124_fuse_lookups[] = {
137
213
{
138
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.nvmem_name = "fuse",
···
285
209
.info = &tegra124_fuse_info,
286
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.lookups = tegra124_fuse_lookups,
287
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.num_lookups = ARRAY_SIZE(tegra124_fuse_lookups),
212
+
.cells = tegra124_fuse_cells,
213
+
.num_cells = ARRAY_SIZE(tegra124_fuse_cells),
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.soc_attr_group = &tegra_soc_attr_group,
289
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.clk_suspend_on = true,
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};
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#endif
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#if defined(CONFIG_ARCH_TEGRA_210_SOC)
220
+
static const struct nvmem_cell_info tegra210_fuse_cells[] = {
221
+
{
222
+
.name = "tsensor-cpu1",
223
+
.offset = 0x084,
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+
.bytes = 4,
225
+
.bit_offset = 0,
226
+
.nbits = 32,
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+
}, {
228
+
.name = "tsensor-cpu2",
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+
.offset = 0x088,
230
+
.bytes = 4,
231
+
.bit_offset = 0,
232
+
.nbits = 32,
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+
}, {
234
+
.name = "tsensor-cpu0",
235
+
.offset = 0x098,
236
+
.bytes = 4,
237
+
.bit_offset = 0,
238
+
.nbits = 32,
239
+
}, {
240
+
.name = "xusb-pad-calibration",
241
+
.offset = 0x0f0,
242
+
.bytes = 4,
243
+
.bit_offset = 0,
244
+
.nbits = 32,
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+
}, {
246
+
.name = "tsensor-cpu3",
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+
.offset = 0x12c,
248
+
.bytes = 4,
249
+
.bit_offset = 0,
250
+
.nbits = 32,
251
+
}, {
252
+
.name = "sata-calibration",
253
+
.offset = 0x124,
254
+
.bytes = 4,
255
+
.bit_offset = 0,
256
+
.nbits = 32,
257
+
}, {
258
+
.name = "tsensor-gpu",
259
+
.offset = 0x154,
260
+
.bytes = 4,
261
+
.bit_offset = 0,
262
+
.nbits = 32,
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+
}, {
264
+
.name = "tsensor-mem0",
265
+
.offset = 0x158,
266
+
.bytes = 4,
267
+
.bit_offset = 0,
268
+
.nbits = 32,
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+
}, {
270
+
.name = "tsensor-mem1",
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+
.offset = 0x15c,
272
+
.bytes = 4,
273
+
.bit_offset = 0,
274
+
.nbits = 32,
275
+
}, {
276
+
.name = "tsensor-pllx",
277
+
.offset = 0x160,
278
+
.bytes = 4,
279
+
.bit_offset = 0,
280
+
.nbits = 32,
281
+
}, {
282
+
.name = "tsensor-common",
283
+
.offset = 0x180,
284
+
.bytes = 4,
285
+
.bit_offset = 0,
286
+
.nbits = 32,
287
+
}, {
288
+
.name = "gpu-calibration",
289
+
.offset = 0x204,
290
+
.bytes = 4,
291
+
.bit_offset = 0,
292
+
.nbits = 32,
293
+
}, {
294
+
.name = "xusb-pad-calibration-ext",
295
+
.offset = 0x250,
296
+
.bytes = 4,
297
+
.bit_offset = 0,
298
+
.nbits = 32,
299
+
},
300
+
};
301
+
294
302
static const struct nvmem_cell_lookup tegra210_fuse_lookups[] = {
295
303
{
296
304
.nvmem_name = "fuse",
···
455
295
.speedo_init = tegra210_init_speedo_data,
456
296
.info = &tegra210_fuse_info,
457
297
.lookups = tegra210_fuse_lookups,
298
+
.cells = tegra210_fuse_cells,
299
+
.num_cells = ARRAY_SIZE(tegra210_fuse_cells),
458
300
.num_lookups = ARRAY_SIZE(tegra210_fuse_lookups),
459
301
.soc_attr_group = &tegra_soc_attr_group,
460
302
.clk_suspend_on = false,
···
464
302
#endif
465
303
466
304
#if defined(CONFIG_ARCH_TEGRA_186_SOC)
305
+
static const struct nvmem_cell_info tegra186_fuse_cells[] = {
306
+
{
307
+
.name = "xusb-pad-calibration",
308
+
.offset = 0x0f0,
309
+
.bytes = 4,
310
+
.bit_offset = 0,
311
+
.nbits = 32,
312
+
}, {
313
+
.name = "xusb-pad-calibration-ext",
314
+
.offset = 0x250,
315
+
.bytes = 4,
316
+
.bit_offset = 0,
317
+
.nbits = 32,
318
+
},
319
+
};
320
+
467
321
static const struct nvmem_cell_lookup tegra186_fuse_lookups[] = {
468
322
{
469
323
.nvmem_name = "fuse",
···
496
318
497
319
static const struct tegra_fuse_info tegra186_fuse_info = {
498
320
.read = tegra30_fuse_read,
499
-
.size = 0x300,
321
+
.size = 0x478,
500
322
.spare = 0x280,
501
323
};
502
324
···
505
327
.info = &tegra186_fuse_info,
506
328
.lookups = tegra186_fuse_lookups,
507
329
.num_lookups = ARRAY_SIZE(tegra186_fuse_lookups),
330
+
.cells = tegra186_fuse_cells,
331
+
.num_cells = ARRAY_SIZE(tegra186_fuse_cells),
508
332
.soc_attr_group = &tegra_soc_attr_group,
509
333
.clk_suspend_on = false,
510
334
};
511
335
#endif
512
336
513
337
#if defined(CONFIG_ARCH_TEGRA_194_SOC)
338
+
static const struct nvmem_cell_info tegra194_fuse_cells[] = {
339
+
{
340
+
.name = "xusb-pad-calibration",
341
+
.offset = 0x0f0,
342
+
.bytes = 4,
343
+
.bit_offset = 0,
344
+
.nbits = 32,
345
+
}, {
346
+
.name = "gpu-gcplex-config-fuse",
347
+
.offset = 0x1c8,
348
+
.bytes = 4,
349
+
.bit_offset = 0,
350
+
.nbits = 32,
351
+
}, {
352
+
.name = "xusb-pad-calibration-ext",
353
+
.offset = 0x250,
354
+
.bytes = 4,
355
+
.bit_offset = 0,
356
+
.nbits = 32,
357
+
}, {
358
+
.name = "gpu-pdi0",
359
+
.offset = 0x300,
360
+
.bytes = 4,
361
+
.bit_offset = 0,
362
+
.nbits = 32,
363
+
}, {
364
+
.name = "gpu-pdi1",
365
+
.offset = 0x304,
366
+
.bytes = 4,
367
+
.bit_offset = 0,
368
+
.nbits = 32,
369
+
},
370
+
};
371
+
514
372
static const struct nvmem_cell_lookup tegra194_fuse_lookups[] = {
515
373
{
516
374
.nvmem_name = "fuse",
···
578
364
579
365
static const struct tegra_fuse_info tegra194_fuse_info = {
580
366
.read = tegra30_fuse_read,
581
-
.size = 0x300,
367
+
.size = 0x650,
582
368
.spare = 0x280,
583
369
};
584
370
···
587
373
.info = &tegra194_fuse_info,
588
374
.lookups = tegra194_fuse_lookups,
589
375
.num_lookups = ARRAY_SIZE(tegra194_fuse_lookups),
376
+
.cells = tegra194_fuse_cells,
377
+
.num_cells = ARRAY_SIZE(tegra194_fuse_cells),
590
378
.soc_attr_group = &tegra194_soc_attr_group,
591
379
.clk_suspend_on = false,
592
380
};
593
381
#endif
594
382
595
383
#if defined(CONFIG_ARCH_TEGRA_234_SOC)
384
+
static const struct nvmem_cell_info tegra234_fuse_cells[] = {
385
+
{
386
+
.name = "xusb-pad-calibration",
387
+
.offset = 0x0f0,
388
+
.bytes = 4,
389
+
.bit_offset = 0,
390
+
.nbits = 32,
391
+
}, {
392
+
.name = "xusb-pad-calibration-ext",
393
+
.offset = 0x250,
394
+
.bytes = 4,
395
+
.bit_offset = 0,
396
+
.nbits = 32,
397
+
},
398
+
};
399
+
596
400
static const struct nvmem_cell_lookup tegra234_fuse_lookups[] = {
597
401
{
598
402
.nvmem_name = "fuse",
···
627
395
628
396
static const struct tegra_fuse_info tegra234_fuse_info = {
629
397
.read = tegra30_fuse_read,
630
-
.size = 0x300,
398
+
.size = 0x98c,
631
399
.spare = 0x280,
632
400
};
633
401
···
636
404
.info = &tegra234_fuse_info,
637
405
.lookups = tegra234_fuse_lookups,
638
406
.num_lookups = ARRAY_SIZE(tegra234_fuse_lookups),
407
+
.cells = tegra234_fuse_cells,
408
+
.num_cells = ARRAY_SIZE(tegra234_fuse_cells),
639
409
.soc_attr_group = &tegra194_soc_attr_group,
640
410
.clk_suspend_on = false,
641
411
};