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drm/rockchip: vop2: Support setting custom background color

The Rockchip VOP2 display controller allows configuring the background
color of each video output port.

Since a previous patch introduced the BACKGROUND_COLOR CRTC property,
which defaults to solid black, make use of it when programming the
hardware.

Note the maximum precision allowed by the display controller is 10bpc,
while the alpha component is not supported, hence ignored.

Tested-by: Diederik de Haas <diederik@cknow-tech.com>
Reviewed-by: Andy Yan <andyshrk@163.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://patch.msgid.link/20260303-rk3588-bgcolor-v8-4-fee377037ad1@collabora.com
Signed-off-by: Daniel Stone <daniels@collabora.com>

authored by

Cristian Ciocaltea and committed by
Daniel Stone bec7cbfa 0b9eff72

+27 -1
+23 -1
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
··· 1080 1080 return -EINVAL; 1081 1081 } 1082 1082 1083 + if ((cstate->background_color << 16) && 1084 + (fb->format->has_alpha || pstate->alpha != 0xffff)) { 1085 + drm_dbg_kms(vop2->drm, 1086 + "Alpha-blending with background color is unsupported\n"); 1087 + return -EINVAL; 1088 + } 1089 + 1083 1090 return 0; 1084 1091 } 1085 1092 ··· 1559 1552 struct vop2_video_port *vp = to_vop2_video_port(crtc); 1560 1553 struct vop2 *vop2 = vp->vop2; 1561 1554 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 1555 + u64 bgcolor = crtc->state->background_color; 1562 1556 u16 vtotal = mode->crtc_vtotal; 1563 1557 u16 hdisplay = mode->crtc_hdisplay; 1564 1558 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; ··· 1605 1597 vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO_F1, val); 1606 1598 } 1607 1599 1608 - vop2_vp_write(vp, RK3568_VP_DSP_BG, 0); 1600 + /* 1601 + * Background color is programmed with 10 bits of precision. 1602 + * Since performance is more important than accuracy here, 1603 + * make use of the DRM_ARGB64_GET*_BPCS() helpers. 1604 + */ 1605 + val = FIELD_PREP(RK3568_VP_DSP_BG__DSP_BG_RED, DRM_ARGB64_GETR_BPCS(bgcolor, 10)); 1606 + FIELD_MODIFY(RK3568_VP_DSP_BG__DSP_BG_GREEN, &val, DRM_ARGB64_GETG_BPCS(bgcolor, 10)); 1607 + FIELD_MODIFY(RK3568_VP_DSP_BG__DSP_BG_BLUE, &val, DRM_ARGB64_GETB_BPCS(bgcolor, 10)); 1608 + vop2_vp_write(vp, RK3568_VP_DSP_BG, val); 1609 1609 } 1610 1610 1611 1611 static int us_to_vertical_line(struct drm_display_mode *mode, int us) ··· 1999 1983 drm_get_bus_format_name(vcstate->bus_format)); 2000 1984 seq_printf(s, "\toutput_mode[%x]", vcstate->output_mode); 2001 1985 seq_printf(s, " color_space[%d]\n", vcstate->color_space); 1986 + seq_printf(s, "\tbackground color (10bpc): r=0x%x g=0x%x b=0x%x\n", 1987 + DRM_ARGB64_GETR_BPCS(cstate->background_color, 10), 1988 + DRM_ARGB64_GETG_BPCS(cstate->background_color, 10), 1989 + DRM_ARGB64_GETB_BPCS(cstate->background_color, 10)); 2002 1990 seq_printf(s, " Display mode: %dx%d%s%d\n", 2003 1991 mode->hdisplay, mode->vdisplay, interlaced ? "i" : "p", 2004 1992 drm_mode_vrefresh(mode)); ··· 2490 2470 if (ret) 2491 2471 return dev_err_probe(drm->dev, ret, 2492 2472 "crtc init for video_port%d failed\n", i); 2473 + 2474 + drm_crtc_attach_background_color_property(&vp->crtc); 2493 2475 2494 2476 drm_crtc_helper_add(&vp->crtc, &vop2_crtc_helper_funcs); 2495 2477 if (vop2->lut_regs) {
+4
drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
··· 658 658 #define RK3588_VP_CLK_CTRL__DCLK_OUT_DIV GENMASK(3, 2) 659 659 #define RK3588_VP_CLK_CTRL__DCLK_CORE_DIV GENMASK(1, 0) 660 660 661 + #define RK3568_VP_DSP_BG__DSP_BG_RED GENMASK(29, 20) 662 + #define RK3568_VP_DSP_BG__DSP_BG_GREEN GENMASK(19, 10) 663 + #define RK3568_VP_DSP_BG__DSP_BG_BLUE GENMASK(9, 0) 664 + 661 665 #define RK3568_VP_POST_SCL_CTRL__VSCALEDOWN BIT(1) 662 666 #define RK3568_VP_POST_SCL_CTRL__HSCALEDOWN BIT(0) 663 667