Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'iommu-updates-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux
Pull iommu updates from Joerg Roedel:
- Inte VT-d:
- IOMMU driver updated to the latest VT-d specification
- Don't enable PRS if PDS isn't supported
- Replace snprintf with scnprintf
- Fix legacy mode page table dump through debugfs
- Miscellaneous cleanups
- AMD-Vi:
- Support kdump boot when SNP is enabled
- Apple-DART:
- 4-level page-table support
- RISC-V IOMMU:
- ACPI support
- Small number of miscellaneous cleanups and fixes
* tag 'iommu-updates-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux: (22 commits)
iommu/vt-d: Disallow dirty tracking if incoherent page walk
iommu/vt-d: debugfs: Avoid dumping context command register
iommu/vt-d: Removal of Advanced Fault Logging
iommu/vt-d: PRS isn't usable if PDS isn't supported
iommu/vt-d: Remove LPIG from page group response descriptor
iommu/vt-d: Drop unused cap_super_offset()
iommu/vt-d: debugfs: Fix legacy mode page table dump logic
iommu/vt-d: Replace snprintf with scnprintf in dmar_latency_snapshot()
iommu/io-pgtable-dart: Fix off by one error in table index check
iommu/riscv: Add ACPI support
ACPI: scan: Add support for RISC-V in acpi_iommu_configure_id()
ACPI: RISC-V: Add support for RIMT
iommu/omap: Use int type to store negative error codes
iommu/apple-dart: Clear stream error indicator bits for T8110 DARTs
iommu/amd: Skip enabling command/event buffers for kdump
crypto: ccp: Skip SEV and SNP INIT for kdump boot
iommu/amd: Reuse device table for kdump
iommu/amd: Add support to remap/unmap IOMMU buffers for kdump
iommu/apple-dart: Add 4-level page table support
iommu/io-pgtable-dart: Add 4-level page table support
...
+961
-200
+1
MAINTAINERS
+1
MAINTAINERS
+1
arch/riscv/Kconfig
+1
arch/riscv/Kconfig
···
16
16
select ACPI_MCFG if (ACPI && PCI)
17
17
select ACPI_PPTT if ACPI
18
18
select ACPI_REDUCED_HARDWARE_ONLY if ACPI
19
+
select ACPI_RIMT if ACPI
19
20
select ACPI_SPCR_TABLE if ACPI
20
21
select ARCH_DMA_DEFAULT_COHERENT
21
22
select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
+4
drivers/acpi/Kconfig
+4
drivers/acpi/Kconfig
+7
drivers/acpi/riscv/Kconfig
+7
drivers/acpi/riscv/Kconfig
+1
drivers/acpi/riscv/Makefile
+1
drivers/acpi/riscv/Makefile
+2
drivers/acpi/riscv/init.c
+2
drivers/acpi/riscv/init.c
+1
drivers/acpi/riscv/init.h
+1
drivers/acpi/riscv/init.h
+520
drivers/acpi/riscv/rimt.c
+520
drivers/acpi/riscv/rimt.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (C) 2024-2025, Ventana Micro Systems Inc
4
+
* Author: Sunil V L <sunilvl@ventanamicro.com>
5
+
*
6
+
*/
7
+
8
+
#define pr_fmt(fmt) "ACPI: RIMT: " fmt
9
+
10
+
#include <linux/acpi.h>
11
+
#include <linux/acpi_rimt.h>
12
+
#include <linux/iommu.h>
13
+
#include <linux/list.h>
14
+
#include <linux/pci.h>
15
+
#include <linux/platform_device.h>
16
+
#include "init.h"
17
+
18
+
struct rimt_fwnode {
19
+
struct list_head list;
20
+
struct acpi_rimt_node *rimt_node;
21
+
struct fwnode_handle *fwnode;
22
+
};
23
+
24
+
static LIST_HEAD(rimt_fwnode_list);
25
+
static DEFINE_SPINLOCK(rimt_fwnode_lock);
26
+
27
+
#define RIMT_TYPE_MASK(type) (1 << (type))
28
+
#define RIMT_IOMMU_TYPE BIT(0)
29
+
30
+
/* Root pointer to the mapped RIMT table */
31
+
static struct acpi_table_header *rimt_table;
32
+
33
+
/**
34
+
* rimt_set_fwnode() - Create rimt_fwnode and use it to register
35
+
* iommu data in the rimt_fwnode_list
36
+
*
37
+
* @rimt_node: RIMT table node associated with the IOMMU
38
+
* @fwnode: fwnode associated with the RIMT node
39
+
*
40
+
* Returns: 0 on success
41
+
* <0 on failure
42
+
*/
43
+
static int rimt_set_fwnode(struct acpi_rimt_node *rimt_node,
44
+
struct fwnode_handle *fwnode)
45
+
{
46
+
struct rimt_fwnode *np;
47
+
48
+
np = kzalloc(sizeof(*np), GFP_ATOMIC);
49
+
50
+
if (WARN_ON(!np))
51
+
return -ENOMEM;
52
+
53
+
INIT_LIST_HEAD(&np->list);
54
+
np->rimt_node = rimt_node;
55
+
np->fwnode = fwnode;
56
+
57
+
spin_lock(&rimt_fwnode_lock);
58
+
list_add_tail(&np->list, &rimt_fwnode_list);
59
+
spin_unlock(&rimt_fwnode_lock);
60
+
61
+
return 0;
62
+
}
63
+
64
+
/**
65
+
* rimt_get_fwnode() - Retrieve fwnode associated with an RIMT node
66
+
*
67
+
* @node: RIMT table node to be looked-up
68
+
*
69
+
* Returns: fwnode_handle pointer on success, NULL on failure
70
+
*/
71
+
static struct fwnode_handle *rimt_get_fwnode(struct acpi_rimt_node *node)
72
+
{
73
+
struct fwnode_handle *fwnode = NULL;
74
+
struct rimt_fwnode *curr;
75
+
76
+
spin_lock(&rimt_fwnode_lock);
77
+
list_for_each_entry(curr, &rimt_fwnode_list, list) {
78
+
if (curr->rimt_node == node) {
79
+
fwnode = curr->fwnode;
80
+
break;
81
+
}
82
+
}
83
+
spin_unlock(&rimt_fwnode_lock);
84
+
85
+
return fwnode;
86
+
}
87
+
88
+
static acpi_status rimt_match_node_callback(struct acpi_rimt_node *node,
89
+
void *context)
90
+
{
91
+
acpi_status status = AE_NOT_FOUND;
92
+
struct device *dev = context;
93
+
94
+
if (node->type == ACPI_RIMT_NODE_TYPE_IOMMU) {
95
+
struct acpi_rimt_iommu *iommu_node = (struct acpi_rimt_iommu *)&node->node_data;
96
+
97
+
if (dev_is_pci(dev)) {
98
+
struct pci_dev *pdev;
99
+
u16 bdf;
100
+
101
+
pdev = to_pci_dev(dev);
102
+
bdf = PCI_DEVID(pdev->bus->number, pdev->devfn);
103
+
if ((pci_domain_nr(pdev->bus) == iommu_node->pcie_segment_number) &&
104
+
bdf == iommu_node->pcie_bdf) {
105
+
status = AE_OK;
106
+
} else {
107
+
status = AE_NOT_FOUND;
108
+
}
109
+
} else {
110
+
struct platform_device *pdev = to_platform_device(dev);
111
+
struct resource *res;
112
+
113
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
114
+
if (res && res->start == iommu_node->base_address)
115
+
status = AE_OK;
116
+
else
117
+
status = AE_NOT_FOUND;
118
+
}
119
+
} else if (node->type == ACPI_RIMT_NODE_TYPE_PCIE_ROOT_COMPLEX) {
120
+
struct acpi_rimt_pcie_rc *pci_rc;
121
+
struct pci_bus *bus;
122
+
123
+
bus = to_pci_bus(dev);
124
+
pci_rc = (struct acpi_rimt_pcie_rc *)node->node_data;
125
+
126
+
/*
127
+
* It is assumed that PCI segment numbers maps one-to-one
128
+
* with root complexes. Each segment number can represent only
129
+
* one root complex.
130
+
*/
131
+
status = pci_rc->pcie_segment_number == pci_domain_nr(bus) ?
132
+
AE_OK : AE_NOT_FOUND;
133
+
} else if (node->type == ACPI_RIMT_NODE_TYPE_PLAT_DEVICE) {
134
+
struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER, NULL };
135
+
struct acpi_rimt_platform_device *ncomp;
136
+
struct device *plat_dev = dev;
137
+
struct acpi_device *adev;
138
+
139
+
/*
140
+
* Walk the device tree to find a device with an
141
+
* ACPI companion; there is no point in scanning
142
+
* RIMT for a device matching a platform device if
143
+
* the device does not have an ACPI companion to
144
+
* start with.
145
+
*/
146
+
do {
147
+
adev = ACPI_COMPANION(plat_dev);
148
+
if (adev)
149
+
break;
150
+
151
+
plat_dev = plat_dev->parent;
152
+
} while (plat_dev);
153
+
154
+
if (!adev)
155
+
return status;
156
+
157
+
status = acpi_get_name(adev->handle, ACPI_FULL_PATHNAME, &buf);
158
+
if (ACPI_FAILURE(status)) {
159
+
dev_warn(plat_dev, "Can't get device full path name\n");
160
+
return status;
161
+
}
162
+
163
+
ncomp = (struct acpi_rimt_platform_device *)node->node_data;
164
+
status = !strcmp(ncomp->device_name, buf.pointer) ?
165
+
AE_OK : AE_NOT_FOUND;
166
+
acpi_os_free(buf.pointer);
167
+
}
168
+
169
+
return status;
170
+
}
171
+
172
+
static struct acpi_rimt_node *rimt_scan_node(enum acpi_rimt_node_type type,
173
+
void *context)
174
+
{
175
+
struct acpi_rimt_node *rimt_node, *rimt_end;
176
+
struct acpi_table_rimt *rimt;
177
+
int i;
178
+
179
+
if (!rimt_table)
180
+
return NULL;
181
+
182
+
/* Get the first RIMT node */
183
+
rimt = (struct acpi_table_rimt *)rimt_table;
184
+
rimt_node = ACPI_ADD_PTR(struct acpi_rimt_node, rimt,
185
+
rimt->node_offset);
186
+
rimt_end = ACPI_ADD_PTR(struct acpi_rimt_node, rimt_table,
187
+
rimt_table->length);
188
+
189
+
for (i = 0; i < rimt->num_nodes; i++) {
190
+
if (WARN_TAINT(rimt_node >= rimt_end, TAINT_FIRMWARE_WORKAROUND,
191
+
"RIMT node pointer overflows, bad table!\n"))
192
+
return NULL;
193
+
194
+
if (rimt_node->type == type &&
195
+
ACPI_SUCCESS(rimt_match_node_callback(rimt_node, context)))
196
+
return rimt_node;
197
+
198
+
rimt_node = ACPI_ADD_PTR(struct acpi_rimt_node, rimt_node,
199
+
rimt_node->length);
200
+
}
201
+
202
+
return NULL;
203
+
}
204
+
205
+
static bool rimt_pcie_rc_supports_ats(struct acpi_rimt_node *node)
206
+
{
207
+
struct acpi_rimt_pcie_rc *pci_rc;
208
+
209
+
pci_rc = (struct acpi_rimt_pcie_rc *)node->node_data;
210
+
return pci_rc->flags & ACPI_RIMT_PCIE_ATS_SUPPORTED;
211
+
}
212
+
213
+
static int rimt_iommu_xlate(struct device *dev, struct acpi_rimt_node *node, u32 deviceid)
214
+
{
215
+
struct fwnode_handle *rimt_fwnode;
216
+
217
+
if (!node)
218
+
return -ENODEV;
219
+
220
+
rimt_fwnode = rimt_get_fwnode(node);
221
+
222
+
/*
223
+
* The IOMMU drivers may not be probed yet.
224
+
* Defer the IOMMU configuration
225
+
*/
226
+
if (!rimt_fwnode)
227
+
return -EPROBE_DEFER;
228
+
229
+
return acpi_iommu_fwspec_init(dev, deviceid, rimt_fwnode);
230
+
}
231
+
232
+
struct rimt_pci_alias_info {
233
+
struct device *dev;
234
+
struct acpi_rimt_node *node;
235
+
const struct iommu_ops *ops;
236
+
};
237
+
238
+
static int rimt_id_map(struct acpi_rimt_id_mapping *map, u8 type, u32 rid_in, u32 *rid_out)
239
+
{
240
+
if (rid_in < map->source_id_base ||
241
+
(rid_in > map->source_id_base + map->num_ids))
242
+
return -ENXIO;
243
+
244
+
*rid_out = map->dest_id_base + (rid_in - map->source_id_base);
245
+
return 0;
246
+
}
247
+
248
+
static struct acpi_rimt_node *rimt_node_get_id(struct acpi_rimt_node *node,
249
+
u32 *id_out, int index)
250
+
{
251
+
struct acpi_rimt_platform_device *plat_node;
252
+
u32 id_mapping_offset, num_id_mapping;
253
+
struct acpi_rimt_pcie_rc *pci_node;
254
+
struct acpi_rimt_id_mapping *map;
255
+
struct acpi_rimt_node *parent;
256
+
257
+
if (node->type == ACPI_RIMT_NODE_TYPE_PCIE_ROOT_COMPLEX) {
258
+
pci_node = (struct acpi_rimt_pcie_rc *)&node->node_data;
259
+
id_mapping_offset = pci_node->id_mapping_offset;
260
+
num_id_mapping = pci_node->num_id_mappings;
261
+
} else if (node->type == ACPI_RIMT_NODE_TYPE_PLAT_DEVICE) {
262
+
plat_node = (struct acpi_rimt_platform_device *)&node->node_data;
263
+
id_mapping_offset = plat_node->id_mapping_offset;
264
+
num_id_mapping = plat_node->num_id_mappings;
265
+
} else {
266
+
return NULL;
267
+
}
268
+
269
+
if (!id_mapping_offset || !num_id_mapping || index >= num_id_mapping)
270
+
return NULL;
271
+
272
+
map = ACPI_ADD_PTR(struct acpi_rimt_id_mapping, node,
273
+
id_mapping_offset + index * sizeof(*map));
274
+
275
+
/* Firmware bug! */
276
+
if (!map->dest_offset) {
277
+
pr_err(FW_BUG "[node %p type %d] ID map has NULL parent reference\n",
278
+
node, node->type);
279
+
return NULL;
280
+
}
281
+
282
+
parent = ACPI_ADD_PTR(struct acpi_rimt_node, rimt_table, map->dest_offset);
283
+
284
+
if (node->type == ACPI_RIMT_NODE_TYPE_PLAT_DEVICE ||
285
+
node->type == ACPI_RIMT_NODE_TYPE_PCIE_ROOT_COMPLEX) {
286
+
*id_out = map->dest_id_base;
287
+
return parent;
288
+
}
289
+
290
+
return NULL;
291
+
}
292
+
293
+
/*
294
+
* RISC-V supports IOMMU as a PCI device or a platform device.
295
+
* When it is a platform device, there should be a namespace device as
296
+
* well along with RIMT. To create the link between RIMT information and
297
+
* the platform device, the IOMMU driver should register itself with the
298
+
* RIMT module. This is true for PCI based IOMMU as well.
299
+
*/
300
+
int rimt_iommu_register(struct device *dev)
301
+
{
302
+
struct fwnode_handle *rimt_fwnode;
303
+
struct acpi_rimt_node *node;
304
+
305
+
node = rimt_scan_node(ACPI_RIMT_NODE_TYPE_IOMMU, dev);
306
+
if (!node) {
307
+
pr_err("Could not find IOMMU node in RIMT\n");
308
+
return -ENODEV;
309
+
}
310
+
311
+
if (dev_is_pci(dev)) {
312
+
rimt_fwnode = acpi_alloc_fwnode_static();
313
+
if (!rimt_fwnode)
314
+
return -ENOMEM;
315
+
316
+
rimt_fwnode->dev = dev;
317
+
if (!dev->fwnode)
318
+
dev->fwnode = rimt_fwnode;
319
+
320
+
rimt_set_fwnode(node, rimt_fwnode);
321
+
} else {
322
+
rimt_set_fwnode(node, dev->fwnode);
323
+
}
324
+
325
+
return 0;
326
+
}
327
+
328
+
#ifdef CONFIG_IOMMU_API
329
+
330
+
static struct acpi_rimt_node *rimt_node_map_id(struct acpi_rimt_node *node,
331
+
u32 id_in, u32 *id_out,
332
+
u8 type_mask)
333
+
{
334
+
struct acpi_rimt_platform_device *plat_node;
335
+
u32 id_mapping_offset, num_id_mapping;
336
+
struct acpi_rimt_pcie_rc *pci_node;
337
+
u32 id = id_in;
338
+
339
+
/* Parse the ID mapping tree to find specified node type */
340
+
while (node) {
341
+
struct acpi_rimt_id_mapping *map;
342
+
int i, rc = 0;
343
+
u32 map_id = id;
344
+
345
+
if (RIMT_TYPE_MASK(node->type) & type_mask) {
346
+
if (id_out)
347
+
*id_out = id;
348
+
return node;
349
+
}
350
+
351
+
if (node->type == ACPI_RIMT_NODE_TYPE_PCIE_ROOT_COMPLEX) {
352
+
pci_node = (struct acpi_rimt_pcie_rc *)&node->node_data;
353
+
id_mapping_offset = pci_node->id_mapping_offset;
354
+
num_id_mapping = pci_node->num_id_mappings;
355
+
} else if (node->type == ACPI_RIMT_NODE_TYPE_PLAT_DEVICE) {
356
+
plat_node = (struct acpi_rimt_platform_device *)&node->node_data;
357
+
id_mapping_offset = plat_node->id_mapping_offset;
358
+
num_id_mapping = plat_node->num_id_mappings;
359
+
} else {
360
+
goto fail_map;
361
+
}
362
+
363
+
if (!id_mapping_offset || !num_id_mapping)
364
+
goto fail_map;
365
+
366
+
map = ACPI_ADD_PTR(struct acpi_rimt_id_mapping, node,
367
+
id_mapping_offset);
368
+
369
+
/* Firmware bug! */
370
+
if (!map->dest_offset) {
371
+
pr_err(FW_BUG "[node %p type %d] ID map has NULL parent reference\n",
372
+
node, node->type);
373
+
goto fail_map;
374
+
}
375
+
376
+
/* Do the ID translation */
377
+
for (i = 0; i < num_id_mapping; i++, map++) {
378
+
rc = rimt_id_map(map, node->type, map_id, &id);
379
+
if (!rc)
380
+
break;
381
+
}
382
+
383
+
if (i == num_id_mapping)
384
+
goto fail_map;
385
+
386
+
node = ACPI_ADD_PTR(struct acpi_rimt_node, rimt_table,
387
+
rc ? 0 : map->dest_offset);
388
+
}
389
+
390
+
fail_map:
391
+
/* Map input ID to output ID unchanged on mapping failure */
392
+
if (id_out)
393
+
*id_out = id_in;
394
+
395
+
return NULL;
396
+
}
397
+
398
+
static struct acpi_rimt_node *rimt_node_map_platform_id(struct acpi_rimt_node *node, u32 *id_out,
399
+
u8 type_mask, int index)
400
+
{
401
+
struct acpi_rimt_node *parent;
402
+
u32 id;
403
+
404
+
parent = rimt_node_get_id(node, &id, index);
405
+
if (!parent)
406
+
return NULL;
407
+
408
+
if (!(RIMT_TYPE_MASK(parent->type) & type_mask))
409
+
parent = rimt_node_map_id(parent, id, id_out, type_mask);
410
+
else
411
+
if (id_out)
412
+
*id_out = id;
413
+
414
+
return parent;
415
+
}
416
+
417
+
static int rimt_pci_iommu_init(struct pci_dev *pdev, u16 alias, void *data)
418
+
{
419
+
struct rimt_pci_alias_info *info = data;
420
+
struct acpi_rimt_node *parent;
421
+
u32 deviceid;
422
+
423
+
parent = rimt_node_map_id(info->node, alias, &deviceid, RIMT_IOMMU_TYPE);
424
+
return rimt_iommu_xlate(info->dev, parent, deviceid);
425
+
}
426
+
427
+
static int rimt_plat_iommu_map(struct device *dev, struct acpi_rimt_node *node)
428
+
{
429
+
struct acpi_rimt_node *parent;
430
+
int err = -ENODEV, i = 0;
431
+
u32 deviceid = 0;
432
+
433
+
do {
434
+
parent = rimt_node_map_platform_id(node, &deviceid,
435
+
RIMT_IOMMU_TYPE,
436
+
i++);
437
+
438
+
if (parent)
439
+
err = rimt_iommu_xlate(dev, parent, deviceid);
440
+
} while (parent && !err);
441
+
442
+
return err;
443
+
}
444
+
445
+
static int rimt_plat_iommu_map_id(struct device *dev,
446
+
struct acpi_rimt_node *node,
447
+
const u32 *in_id)
448
+
{
449
+
struct acpi_rimt_node *parent;
450
+
u32 deviceid;
451
+
452
+
parent = rimt_node_map_id(node, *in_id, &deviceid, RIMT_IOMMU_TYPE);
453
+
if (parent)
454
+
return rimt_iommu_xlate(dev, parent, deviceid);
455
+
456
+
return -ENODEV;
457
+
}
458
+
459
+
/**
460
+
* rimt_iommu_configure_id - Set-up IOMMU configuration for a device.
461
+
*
462
+
* @dev: device to configure
463
+
* @id_in: optional input id const value pointer
464
+
*
465
+
* Returns: 0 on success, <0 on failure
466
+
*/
467
+
int rimt_iommu_configure_id(struct device *dev, const u32 *id_in)
468
+
{
469
+
struct acpi_rimt_node *node;
470
+
int err = -ENODEV;
471
+
472
+
if (dev_is_pci(dev)) {
473
+
struct iommu_fwspec *fwspec;
474
+
struct pci_bus *bus = to_pci_dev(dev)->bus;
475
+
struct rimt_pci_alias_info info = { .dev = dev };
476
+
477
+
node = rimt_scan_node(ACPI_RIMT_NODE_TYPE_PCIE_ROOT_COMPLEX, &bus->dev);
478
+
if (!node)
479
+
return -ENODEV;
480
+
481
+
info.node = node;
482
+
err = pci_for_each_dma_alias(to_pci_dev(dev),
483
+
rimt_pci_iommu_init, &info);
484
+
485
+
fwspec = dev_iommu_fwspec_get(dev);
486
+
if (fwspec && rimt_pcie_rc_supports_ats(node))
487
+
fwspec->flags |= IOMMU_FWSPEC_PCI_RC_ATS;
488
+
} else {
489
+
node = rimt_scan_node(ACPI_RIMT_NODE_TYPE_PLAT_DEVICE, dev);
490
+
if (!node)
491
+
return -ENODEV;
492
+
493
+
err = id_in ? rimt_plat_iommu_map_id(dev, node, id_in) :
494
+
rimt_plat_iommu_map(dev, node);
495
+
}
496
+
497
+
return err;
498
+
}
499
+
500
+
#endif
501
+
502
+
void __init riscv_acpi_rimt_init(void)
503
+
{
504
+
acpi_status status;
505
+
506
+
/* rimt_table will be used at runtime after the rimt init,
507
+
* so we don't need to call acpi_put_table() to release
508
+
* the RIMT table mapping.
509
+
*/
510
+
status = acpi_get_table(ACPI_SIG_RIMT, 0, &rimt_table);
511
+
if (ACPI_FAILURE(status)) {
512
+
if (status != AE_NOT_FOUND) {
513
+
const char *msg = acpi_format_exception(status);
514
+
515
+
pr_err("Failed to get table, %s\n", msg);
516
+
}
517
+
518
+
return;
519
+
}
520
+
}
+4
drivers/acpi/scan.c
+4
drivers/acpi/scan.c
···
11
11
#include <linux/kernel.h>
12
12
#include <linux/acpi.h>
13
13
#include <linux/acpi_iort.h>
14
+
#include <linux/acpi_rimt.h>
14
15
#include <linux/acpi_viot.h>
15
16
#include <linux/iommu.h>
16
17
#include <linux/signal.h>
···
1632
1631
1633
1632
err = iort_iommu_configure_id(dev, id_in);
1634
1633
if (err && err != -EPROBE_DEFER)
1634
+
err = rimt_iommu_configure_id(dev, id_in);
1635
+
if (err && err != -EPROBE_DEFER)
1635
1636
err = viot_iommu_configure(dev);
1637
+
1636
1638
mutex_unlock(&iommu_probe_device_lock);
1637
1639
1638
1640
return err;
+10
drivers/crypto/ccp/sev-dev.c
+10
drivers/crypto/ccp/sev-dev.c
···
28
28
#include <linux/fs_struct.h>
29
29
#include <linux/psp.h>
30
30
#include <linux/amd-iommu.h>
31
+
#include <linux/crash_dump.h>
31
32
32
33
#include <asm/smp.h>
33
34
#include <asm/cacheflush.h>
···
1526
1525
1527
1526
if (!psp_master || !psp_master->sev_data)
1528
1527
return -ENODEV;
1528
+
1529
+
/*
1530
+
* Skip SNP/SEV initialization under a kdump kernel as SEV/SNP
1531
+
* may already be initialized in the previous kernel. Since no
1532
+
* SNP/SEV guests are run under a kdump kernel, there is no
1533
+
* need to initialize SNP or SEV during kdump boot.
1534
+
*/
1535
+
if (is_kdump_kernel())
1536
+
return 0;
1529
1537
1530
1538
sev = psp_master->sev_data;
1531
1539
+5
drivers/iommu/amd/amd_iommu_types.h
+5
drivers/iommu/amd/amd_iommu_types.h
···
792
792
u32 flags;
793
793
volatile u64 *cmd_sem;
794
794
atomic64_t cmd_sem_val;
795
+
/*
796
+
* Track physical address to directly use it in build_completion_wait()
797
+
* and avoid adding any special checks and handling for kdump.
798
+
*/
799
+
u64 cmd_sem_paddr;
795
800
796
801
#ifdef CONFIG_AMD_IOMMU_DEBUGFS
797
802
/* DebugFS Info */
+193
-91
drivers/iommu/amd/init.c
+193
-91
drivers/iommu/amd/init.c
···
406
406
407
407
BUG_ON(iommu->mmio_base == NULL);
408
408
409
+
if (is_kdump_kernel())
410
+
return;
411
+
409
412
entry = iommu_virt_to_phys(dev_table);
410
413
entry |= (dev_table_size >> 12) - 1;
411
414
memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
···
649
646
650
647
static inline void free_dev_table(struct amd_iommu_pci_seg *pci_seg)
651
648
{
652
-
iommu_free_pages(pci_seg->dev_table);
649
+
if (is_kdump_kernel())
650
+
memunmap((void *)pci_seg->dev_table);
651
+
else
652
+
iommu_free_pages(pci_seg->dev_table);
653
653
pci_seg->dev_table = NULL;
654
654
}
655
655
···
714
708
{
715
709
kvfree(pci_seg->alias_table);
716
710
pci_seg->alias_table = NULL;
711
+
}
712
+
713
+
static inline void *iommu_memremap(unsigned long paddr, size_t size)
714
+
{
715
+
phys_addr_t phys;
716
+
717
+
if (!paddr)
718
+
return NULL;
719
+
720
+
/*
721
+
* Obtain true physical address in kdump kernel when SME is enabled.
722
+
* Currently, previous kernel with SME enabled and kdump kernel
723
+
* with SME support disabled is not supported.
724
+
*/
725
+
phys = __sme_clr(paddr);
726
+
727
+
if (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT))
728
+
return (__force void *)ioremap_encrypted(phys, size);
729
+
else
730
+
return memremap(phys, size, MEMREMAP_WB);
717
731
}
718
732
719
733
/*
···
821
795
822
796
BUG_ON(iommu->cmd_buf == NULL);
823
797
824
-
entry = iommu_virt_to_phys(iommu->cmd_buf);
825
-
entry |= MMIO_CMD_SIZE_512;
826
-
827
-
memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
828
-
&entry, sizeof(entry));
798
+
if (!is_kdump_kernel()) {
799
+
/*
800
+
* Command buffer is re-used for kdump kernel and setting
801
+
* of MMIO register is not required.
802
+
*/
803
+
entry = iommu_virt_to_phys(iommu->cmd_buf);
804
+
entry |= MMIO_CMD_SIZE_512;
805
+
memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
806
+
&entry, sizeof(entry));
807
+
}
829
808
830
809
amd_iommu_reset_cmd_buffer(iommu);
831
810
}
···
881
850
882
851
BUG_ON(iommu->evt_buf == NULL);
883
852
884
-
entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
885
-
886
-
memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
887
-
&entry, sizeof(entry));
853
+
if (!is_kdump_kernel()) {
854
+
/*
855
+
* Event buffer is re-used for kdump kernel and setting
856
+
* of MMIO register is not required.
857
+
*/
858
+
entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
859
+
memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
860
+
&entry, sizeof(entry));
861
+
}
888
862
889
863
/* set head and tail to zero manually */
890
864
writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
···
978
942
static int __init alloc_cwwb_sem(struct amd_iommu *iommu)
979
943
{
980
944
iommu->cmd_sem = iommu_alloc_4k_pages(iommu, GFP_KERNEL, 1);
945
+
if (!iommu->cmd_sem)
946
+
return -ENOMEM;
947
+
iommu->cmd_sem_paddr = iommu_virt_to_phys((void *)iommu->cmd_sem);
948
+
return 0;
949
+
}
981
950
982
-
return iommu->cmd_sem ? 0 : -ENOMEM;
951
+
static int __init remap_event_buffer(struct amd_iommu *iommu)
952
+
{
953
+
u64 paddr;
954
+
955
+
pr_info_once("Re-using event buffer from the previous kernel\n");
956
+
paddr = readq(iommu->mmio_base + MMIO_EVT_BUF_OFFSET) & PM_ADDR_MASK;
957
+
iommu->evt_buf = iommu_memremap(paddr, EVT_BUFFER_SIZE);
958
+
959
+
return iommu->evt_buf ? 0 : -ENOMEM;
960
+
}
961
+
962
+
static int __init remap_command_buffer(struct amd_iommu *iommu)
963
+
{
964
+
u64 paddr;
965
+
966
+
pr_info_once("Re-using command buffer from the previous kernel\n");
967
+
paddr = readq(iommu->mmio_base + MMIO_CMD_BUF_OFFSET) & PM_ADDR_MASK;
968
+
iommu->cmd_buf = iommu_memremap(paddr, CMD_BUFFER_SIZE);
969
+
970
+
return iommu->cmd_buf ? 0 : -ENOMEM;
971
+
}
972
+
973
+
static int __init remap_or_alloc_cwwb_sem(struct amd_iommu *iommu)
974
+
{
975
+
u64 paddr;
976
+
977
+
if (check_feature(FEATURE_SNP)) {
978
+
/*
979
+
* When SNP is enabled, the exclusion base register is used for the
980
+
* completion wait buffer (CWB) address. Read and re-use it.
981
+
*/
982
+
pr_info_once("Re-using CWB buffers from the previous kernel\n");
983
+
paddr = readq(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET) & PM_ADDR_MASK;
984
+
iommu->cmd_sem = iommu_memremap(paddr, PAGE_SIZE);
985
+
if (!iommu->cmd_sem)
986
+
return -ENOMEM;
987
+
iommu->cmd_sem_paddr = paddr;
988
+
} else {
989
+
return alloc_cwwb_sem(iommu);
990
+
}
991
+
992
+
return 0;
993
+
}
994
+
995
+
static int __init alloc_iommu_buffers(struct amd_iommu *iommu)
996
+
{
997
+
int ret;
998
+
999
+
/*
1000
+
* Reuse/Remap the previous kernel's allocated completion wait
1001
+
* command and event buffers for kdump boot.
1002
+
*/
1003
+
if (is_kdump_kernel()) {
1004
+
ret = remap_or_alloc_cwwb_sem(iommu);
1005
+
if (ret)
1006
+
return ret;
1007
+
1008
+
ret = remap_command_buffer(iommu);
1009
+
if (ret)
1010
+
return ret;
1011
+
1012
+
ret = remap_event_buffer(iommu);
1013
+
if (ret)
1014
+
return ret;
1015
+
} else {
1016
+
ret = alloc_cwwb_sem(iommu);
1017
+
if (ret)
1018
+
return ret;
1019
+
1020
+
ret = alloc_command_buffer(iommu);
1021
+
if (ret)
1022
+
return ret;
1023
+
1024
+
ret = alloc_event_buffer(iommu);
1025
+
if (ret)
1026
+
return ret;
1027
+
}
1028
+
1029
+
return 0;
983
1030
}
984
1031
985
1032
static void __init free_cwwb_sem(struct amd_iommu *iommu)
986
1033
{
987
1034
if (iommu->cmd_sem)
988
1035
iommu_free_pages((void *)iommu->cmd_sem);
1036
+
}
1037
+
static void __init unmap_cwwb_sem(struct amd_iommu *iommu)
1038
+
{
1039
+
if (iommu->cmd_sem) {
1040
+
if (check_feature(FEATURE_SNP))
1041
+
memunmap((void *)iommu->cmd_sem);
1042
+
else
1043
+
iommu_free_pages((void *)iommu->cmd_sem);
1044
+
}
1045
+
}
1046
+
1047
+
static void __init unmap_command_buffer(struct amd_iommu *iommu)
1048
+
{
1049
+
memunmap((void *)iommu->cmd_buf);
1050
+
}
1051
+
1052
+
static void __init unmap_event_buffer(struct amd_iommu *iommu)
1053
+
{
1054
+
memunmap(iommu->evt_buf);
1055
+
}
1056
+
1057
+
static void __init free_iommu_buffers(struct amd_iommu *iommu)
1058
+
{
1059
+
if (is_kdump_kernel()) {
1060
+
unmap_cwwb_sem(iommu);
1061
+
unmap_command_buffer(iommu);
1062
+
unmap_event_buffer(iommu);
1063
+
} else {
1064
+
free_cwwb_sem(iommu);
1065
+
free_command_buffer(iommu);
1066
+
free_event_buffer(iommu);
1067
+
}
989
1068
}
990
1069
991
1070
static void iommu_enable_xt(struct amd_iommu *iommu)
···
1133
982
dte->data[i] |= (1UL << _bit);
1134
983
}
1135
984
1136
-
static bool __copy_device_table(struct amd_iommu *iommu)
985
+
static bool __reuse_device_table(struct amd_iommu *iommu)
1137
986
{
1138
-
u64 int_ctl, int_tab_len, entry = 0;
1139
987
struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg;
1140
-
struct dev_table_entry *old_devtb = NULL;
1141
-
u32 lo, hi, devid, old_devtb_size;
988
+
u32 lo, hi, old_devtb_size;
1142
989
phys_addr_t old_devtb_phys;
1143
-
u16 dom_id, dte_v, irq_v;
1144
-
u64 tmp;
990
+
u64 entry;
1145
991
1146
992
/* Each IOMMU use separate device table with the same size */
1147
993
lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET);
···
1163
1015
pr_err("The address of old device table is above 4G, not trustworthy!\n");
1164
1016
return false;
1165
1017
}
1166
-
old_devtb = (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT) && is_kdump_kernel())
1167
-
? (__force void *)ioremap_encrypted(old_devtb_phys,
1168
-
pci_seg->dev_table_size)
1169
-
: memremap(old_devtb_phys, pci_seg->dev_table_size, MEMREMAP_WB);
1170
1018
1171
-
if (!old_devtb)
1172
-
return false;
1173
-
1174
-
pci_seg->old_dev_tbl_cpy = iommu_alloc_pages_sz(
1175
-
GFP_KERNEL | GFP_DMA32, pci_seg->dev_table_size);
1019
+
/*
1020
+
* Re-use the previous kernel's device table for kdump.
1021
+
*/
1022
+
pci_seg->old_dev_tbl_cpy = iommu_memremap(old_devtb_phys, pci_seg->dev_table_size);
1176
1023
if (pci_seg->old_dev_tbl_cpy == NULL) {
1177
-
pr_err("Failed to allocate memory for copying old device table!\n");
1178
-
memunmap(old_devtb);
1024
+
pr_err("Failed to remap memory for reusing old device table!\n");
1179
1025
return false;
1180
1026
}
1181
-
1182
-
for (devid = 0; devid <= pci_seg->last_bdf; ++devid) {
1183
-
pci_seg->old_dev_tbl_cpy[devid] = old_devtb[devid];
1184
-
dom_id = old_devtb[devid].data[1] & DEV_DOMID_MASK;
1185
-
dte_v = old_devtb[devid].data[0] & DTE_FLAG_V;
1186
-
1187
-
if (dte_v && dom_id) {
1188
-
pci_seg->old_dev_tbl_cpy[devid].data[0] = old_devtb[devid].data[0];
1189
-
pci_seg->old_dev_tbl_cpy[devid].data[1] = old_devtb[devid].data[1];
1190
-
/* Reserve the Domain IDs used by previous kernel */
1191
-
if (ida_alloc_range(&pdom_ids, dom_id, dom_id, GFP_ATOMIC) != dom_id) {
1192
-
pr_err("Failed to reserve domain ID 0x%x\n", dom_id);
1193
-
memunmap(old_devtb);
1194
-
return false;
1195
-
}
1196
-
/* If gcr3 table existed, mask it out */
1197
-
if (old_devtb[devid].data[0] & DTE_FLAG_GV) {
1198
-
tmp = (DTE_GCR3_30_15 | DTE_GCR3_51_31);
1199
-
pci_seg->old_dev_tbl_cpy[devid].data[1] &= ~tmp;
1200
-
tmp = (DTE_GCR3_14_12 | DTE_FLAG_GV);
1201
-
pci_seg->old_dev_tbl_cpy[devid].data[0] &= ~tmp;
1202
-
}
1203
-
}
1204
-
1205
-
irq_v = old_devtb[devid].data[2] & DTE_IRQ_REMAP_ENABLE;
1206
-
int_ctl = old_devtb[devid].data[2] & DTE_IRQ_REMAP_INTCTL_MASK;
1207
-
int_tab_len = old_devtb[devid].data[2] & DTE_INTTABLEN_MASK;
1208
-
if (irq_v && (int_ctl || int_tab_len)) {
1209
-
if ((int_ctl != DTE_IRQ_REMAP_INTCTL) ||
1210
-
(int_tab_len != DTE_INTTABLEN_512 &&
1211
-
int_tab_len != DTE_INTTABLEN_2K)) {
1212
-
pr_err("Wrong old irq remapping flag: %#x\n", devid);
1213
-
memunmap(old_devtb);
1214
-
return false;
1215
-
}
1216
-
1217
-
pci_seg->old_dev_tbl_cpy[devid].data[2] = old_devtb[devid].data[2];
1218
-
}
1219
-
}
1220
-
memunmap(old_devtb);
1221
1027
1222
1028
return true;
1223
1029
}
1224
1030
1225
-
static bool copy_device_table(void)
1031
+
static bool reuse_device_table(void)
1226
1032
{
1227
1033
struct amd_iommu *iommu;
1228
1034
struct amd_iommu_pci_seg *pci_seg;
···
1184
1082
if (!amd_iommu_pre_enabled)
1185
1083
return false;
1186
1084
1187
-
pr_warn("Translation is already enabled - trying to copy translation structures\n");
1085
+
pr_warn("Translation is already enabled - trying to reuse translation structures\n");
1188
1086
1189
1087
/*
1190
1088
* All IOMMUs within PCI segment shares common device table.
1191
-
* Hence copy device table only once per PCI segment.
1089
+
* Hence reuse device table only once per PCI segment.
1192
1090
*/
1193
1091
for_each_pci_segment(pci_seg) {
1194
1092
for_each_iommu(iommu) {
1195
1093
if (pci_seg->id != iommu->pci_seg->id)
1196
1094
continue;
1197
-
if (!__copy_device_table(iommu))
1095
+
if (!__reuse_device_table(iommu))
1198
1096
return false;
1199
1097
break;
1200
1098
}
···
1757
1655
static void __init free_iommu_one(struct amd_iommu *iommu)
1758
1656
{
1759
1657
free_sysfs(iommu);
1760
-
free_cwwb_sem(iommu);
1761
-
free_command_buffer(iommu);
1762
-
free_event_buffer(iommu);
1658
+
free_iommu_buffers(iommu);
1763
1659
amd_iommu_free_ppr_log(iommu);
1764
1660
free_ga_log(iommu);
1765
1661
iommu_unmap_mmio_space(iommu);
···
1921
1821
{
1922
1822
int ret;
1923
1823
1924
-
if (alloc_cwwb_sem(iommu))
1925
-
return -ENOMEM;
1926
-
1927
-
if (alloc_command_buffer(iommu))
1928
-
return -ENOMEM;
1929
-
1930
-
if (alloc_event_buffer(iommu))
1931
-
return -ENOMEM;
1824
+
ret = alloc_iommu_buffers(iommu);
1825
+
if (ret)
1826
+
return ret;
1932
1827
1933
1828
iommu->int_enabled = false;
1934
1829
···
2873
2778
* This function finally enables all IOMMUs found in the system after
2874
2779
* they have been initialized.
2875
2780
*
2876
-
* Or if in kdump kernel and IOMMUs are all pre-enabled, try to copy
2877
-
* the old content of device table entries. Not this case or copy failed,
2781
+
* Or if in kdump kernel and IOMMUs are all pre-enabled, try to reuse
2782
+
* the old content of device table entries. Not this case or reuse failed,
2878
2783
* just continue as normal kernel does.
2879
2784
*/
2880
2785
static void early_enable_iommus(void)
···
2882
2787
struct amd_iommu *iommu;
2883
2788
struct amd_iommu_pci_seg *pci_seg;
2884
2789
2885
-
if (!copy_device_table()) {
2790
+
if (!reuse_device_table()) {
2886
2791
/*
2887
-
* If come here because of failure in copying device table from old
2792
+
* If come here because of failure in reusing device table from old
2888
2793
* kernel with all IOMMUs enabled, print error message and try to
2889
2794
* free allocated old_dev_tbl_cpy.
2890
2795
*/
2891
-
if (amd_iommu_pre_enabled)
2892
-
pr_err("Failed to copy DEV table from previous kernel.\n");
2796
+
if (amd_iommu_pre_enabled) {
2797
+
pr_err("Failed to reuse DEV table from previous kernel.\n");
2798
+
/*
2799
+
* Bail out early if unable to remap/reuse DEV table from
2800
+
* previous kernel if SNP enabled as IOMMU commands will
2801
+
* time out without DEV table and cause kdump boot panic.
2802
+
*/
2803
+
BUG_ON(check_feature(FEATURE_SNP));
2804
+
}
2893
2805
2894
2806
for_each_pci_segment(pci_seg) {
2895
2807
if (pci_seg->old_dev_tbl_cpy != NULL) {
2896
-
iommu_free_pages(pci_seg->old_dev_tbl_cpy);
2808
+
memunmap((void *)pci_seg->old_dev_tbl_cpy);
2897
2809
pci_seg->old_dev_tbl_cpy = NULL;
2898
2810
}
2899
2811
}
···
2910
2808
early_enable_iommu(iommu);
2911
2809
}
2912
2810
} else {
2913
-
pr_info("Copied DEV table from previous kernel.\n");
2811
+
pr_info("Reused DEV table from previous kernel.\n");
2914
2812
2915
2813
for_each_pci_segment(pci_seg) {
2916
2814
iommu_free_pages(pci_seg->dev_table);
+3
-2
drivers/iommu/amd/iommu.c
+3
-2
drivers/iommu/amd/iommu.c
···
14
14
#include <linux/pci-ats.h>
15
15
#include <linux/bitmap.h>
16
16
#include <linux/slab.h>
17
+
#include <linux/string_choices.h>
17
18
#include <linux/debugfs.h>
18
19
#include <linux/scatterlist.h>
19
20
#include <linux/dma-map-ops.h>
···
266
265
return -EINVAL;
267
266
if (fw_bug)
268
267
dev_err_once(dev, FW_BUG "No ACPI device matched UID, but %d device%s matched HID.\n",
269
-
hid_count, hid_count > 1 ? "s" : "");
268
+
hid_count, str_plural(hid_count));
270
269
if (hid_count > 1)
271
270
return -EINVAL;
272
271
if (entry)
···
1196
1195
struct amd_iommu *iommu,
1197
1196
u64 data)
1198
1197
{
1199
-
u64 paddr = iommu_virt_to_phys((void *)iommu->cmd_sem);
1198
+
u64 paddr = iommu->cmd_sem_paddr;
1200
1199
1201
1200
memset(cmd, 0, sizeof(*cmd));
1202
1201
cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
+37
-18
drivers/iommu/apple-dart.c
+37
-18
drivers/iommu/apple-dart.c
···
122
122
#define DART_T8110_ERROR_ADDR_LO 0x170
123
123
#define DART_T8110_ERROR_ADDR_HI 0x174
124
124
125
+
#define DART_T8110_ERROR_STREAMS 0x1c0
126
+
125
127
#define DART_T8110_PROTECT 0x200
126
128
#define DART_T8110_UNPROTECT 0x204
127
129
#define DART_T8110_PROTECT_LOCK 0x208
···
135
133
#define DART_T8110_TCR 0x1000
136
134
#define DART_T8110_TCR_REMAP GENMASK(11, 8)
137
135
#define DART_T8110_TCR_REMAP_EN BIT(7)
136
+
#define DART_T8110_TCR_FOUR_LEVEL BIT(3)
138
137
#define DART_T8110_TCR_BYPASS_DAPF BIT(2)
139
138
#define DART_T8110_TCR_BYPASS_DART BIT(1)
140
139
#define DART_T8110_TCR_TRANSLATE_ENABLE BIT(0)
···
169
166
170
167
int max_sid_count;
171
168
172
-
u64 lock;
173
-
u64 lock_bit;
169
+
u32 lock;
170
+
u32 lock_bit;
174
171
175
-
u64 error;
172
+
u32 error;
176
173
177
-
u64 enable_streams;
174
+
u32 enable_streams;
178
175
179
-
u64 tcr;
180
-
u64 tcr_enabled;
181
-
u64 tcr_disabled;
182
-
u64 tcr_bypass;
176
+
u32 tcr;
177
+
u32 tcr_enabled;
178
+
u32 tcr_disabled;
179
+
u32 tcr_bypass;
180
+
u32 tcr_4level;
183
181
184
-
u64 ttbr;
185
-
u64 ttbr_valid;
186
-
u64 ttbr_addr_field_shift;
187
-
u64 ttbr_shift;
182
+
u32 ttbr;
183
+
u32 ttbr_valid;
184
+
u32 ttbr_addr_field_shift;
185
+
u32 ttbr_shift;
188
186
int ttbr_count;
189
187
};
190
188
···
221
217
u32 pgsize;
222
218
u32 num_streams;
223
219
u32 supports_bypass : 1;
220
+
u32 four_level : 1;
224
221
225
222
struct iommu_group *sid2group[DART_MAX_STREAMS];
226
223
struct iommu_device iommu;
···
310
305
}
311
306
312
307
static void
313
-
apple_dart_hw_enable_translation(struct apple_dart_stream_map *stream_map)
308
+
apple_dart_hw_enable_translation(struct apple_dart_stream_map *stream_map, int levels)
314
309
{
315
310
struct apple_dart *dart = stream_map->dart;
311
+
u32 tcr = dart->hw->tcr_enabled;
316
312
int sid;
317
313
314
+
if (levels == 4)
315
+
tcr |= dart->hw->tcr_4level;
316
+
317
+
WARN_ON(levels != 3 && levels != 4);
318
+
WARN_ON(levels == 4 && !dart->four_level);
318
319
for_each_set_bit(sid, stream_map->sidmap, dart->num_streams)
319
-
writel(dart->hw->tcr_enabled, dart->regs + DART_TCR(dart, sid));
320
+
writel(tcr, dart->regs + DART_TCR(dart, sid));
320
321
}
321
322
322
323
static void apple_dart_hw_disable_dma(struct apple_dart_stream_map *stream_map)
···
580
569
for (; i < stream_map->dart->hw->ttbr_count; ++i)
581
570
apple_dart_hw_clear_ttbr(stream_map, i);
582
571
583
-
apple_dart_hw_enable_translation(stream_map);
572
+
apple_dart_hw_enable_translation(stream_map,
573
+
pgtbl_cfg->apple_dart_cfg.n_levels);
584
574
stream_map->dart->hw->invalidate_tlb(stream_map);
585
575
}
586
576
···
626
614
dart_domain->domain.pgsize_bitmap = pgtbl_cfg.pgsize_bitmap;
627
615
dart_domain->domain.geometry.aperture_start = 0;
628
616
dart_domain->domain.geometry.aperture_end =
629
-
(dma_addr_t)DMA_BIT_MASK(dart->ias);
617
+
(dma_addr_t)DMA_BIT_MASK(pgtbl_cfg.ias);
630
618
dart_domain->domain.geometry.force_aperture = true;
631
619
632
620
dart_domain->finalized = true;
···
818
806
cfg_dart = cfg->stream_maps[0].dart;
819
807
if (cfg_dart) {
820
808
if (cfg_dart->pgsize != dart->pgsize)
809
+
return -EINVAL;
810
+
if (cfg_dart->ias != dart->ias)
821
811
return -EINVAL;
822
812
}
823
813
···
1091
1077
error, stream_idx, error_code, fault_name, addr);
1092
1078
1093
1079
writel(error, dart->regs + DART_T8110_ERROR);
1080
+
for (int i = 0; i < BITS_TO_U32(dart->num_streams); i++)
1081
+
writel(U32_MAX, dart->regs + DART_T8110_ERROR_STREAMS + 4 * i);
1082
+
1094
1083
return IRQ_HANDLED;
1095
1084
}
1096
1085
···
1154
1137
dart->ias = FIELD_GET(DART_T8110_PARAMS3_VA_WIDTH, dart_params[2]);
1155
1138
dart->oas = FIELD_GET(DART_T8110_PARAMS3_PA_WIDTH, dart_params[2]);
1156
1139
dart->num_streams = FIELD_GET(DART_T8110_PARAMS4_NUM_SIDS, dart_params[3]);
1140
+
dart->four_level = dart->ias > 36;
1157
1141
break;
1158
1142
}
1159
1143
···
1187
1169
1188
1170
dev_info(
1189
1171
&pdev->dev,
1190
-
"DART [pagesize %x, %d streams, bypass support: %d, bypass forced: %d] initialized\n",
1172
+
"DART [pagesize %x, %d streams, bypass support: %d, bypass forced: %d, AS %d -> %d] initialized\n",
1191
1173
dart->pgsize, dart->num_streams, dart->supports_bypass,
1192
-
dart->pgsize > PAGE_SIZE);
1174
+
dart->pgsize > PAGE_SIZE, dart->ias, dart->oas);
1193
1175
return 0;
1194
1176
1195
1177
err_sysfs_remove:
···
1310
1292
.tcr_enabled = DART_T8110_TCR_TRANSLATE_ENABLE,
1311
1293
.tcr_disabled = 0,
1312
1294
.tcr_bypass = DART_T8110_TCR_BYPASS_DAPF | DART_T8110_TCR_BYPASS_DART,
1295
+
.tcr_4level = DART_T8110_TCR_FOUR_LEVEL,
1313
1296
1314
1297
.ttbr = DART_T8110_TTBR,
1315
1298
.ttbr_valid = DART_T8110_TTBR_VALID,
+17
-12
drivers/iommu/intel/debugfs.c
+17
-12
drivers/iommu/intel/debugfs.c
···
62
62
IOMMU_REGSET_ENTRY(CAP),
63
63
IOMMU_REGSET_ENTRY(ECAP),
64
64
IOMMU_REGSET_ENTRY(RTADDR),
65
-
IOMMU_REGSET_ENTRY(CCMD),
66
-
IOMMU_REGSET_ENTRY(AFLOG),
67
65
IOMMU_REGSET_ENTRY(PHMBASE),
68
66
IOMMU_REGSET_ENTRY(PHMLIMIT),
69
67
IOMMU_REGSET_ENTRY(IQH),
···
433
435
}
434
436
pgd &= VTD_PAGE_MASK;
435
437
} else { /* legacy mode */
436
-
pgd = context->lo & VTD_PAGE_MASK;
437
-
agaw = context->hi & 7;
438
+
u8 tt = (u8)(context->lo & GENMASK_ULL(3, 2)) >> 2;
439
+
440
+
/*
441
+
* According to Translation Type(TT),
442
+
* get the page table pointer(SSPTPTR).
443
+
*/
444
+
switch (tt) {
445
+
case CONTEXT_TT_MULTI_LEVEL:
446
+
case CONTEXT_TT_DEV_IOTLB:
447
+
pgd = context->lo & VTD_PAGE_MASK;
448
+
agaw = context->hi & 7;
449
+
break;
450
+
default:
451
+
goto iommu_unlock;
452
+
}
438
453
}
439
454
440
455
seq_printf(m, "Device %04x:%02x:%02x.%x ",
···
659
648
static void latency_show_one(struct seq_file *m, struct intel_iommu *iommu,
660
649
struct dmar_drhd_unit *drhd)
661
650
{
662
-
int ret;
663
-
664
651
seq_printf(m, "IOMMU: %s Register Base Address: %llx\n",
665
652
iommu->name, drhd->reg_base_addr);
666
653
667
-
ret = dmar_latency_snapshot(iommu, debug_buf, DEBUG_BUFFER_SIZE);
668
-
if (ret < 0)
669
-
seq_puts(m, "Failed to get latency snapshot");
670
-
else
671
-
seq_puts(m, debug_buf);
672
-
seq_puts(m, "\n");
654
+
dmar_latency_snapshot(iommu, debug_buf, DEBUG_BUFFER_SIZE);
655
+
seq_printf(m, "%s\n", debug_buf);
673
656
}
674
657
675
658
static int latency_show(struct seq_file *m, void *v)
+1
-1
drivers/iommu/intel/iommu.c
+1
-1
drivers/iommu/intel/iommu.c
+2
-5
drivers/iommu/intel/iommu.h
+2
-5
drivers/iommu/intel/iommu.h
···
77
77
#define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */
78
78
#define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */
79
79
#define DMAR_FEUADDR_REG 0x44 /* Upper address register */
80
-
#define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */
81
80
#define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */
82
81
#define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */
83
82
#define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */
···
172
173
#define cap_pgsel_inv(c) (((c) >> 39) & 1)
173
174
174
175
#define cap_super_page_val(c) (((c) >> 34) & 0xf)
175
-
#define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \
176
-
* OFFSET_STRIDE) + 21)
177
176
178
177
#define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16)
179
178
#define cap_max_fault_reg_offset(c) \
···
459
462
#define QI_PGRP_PASID(pasid) (((u64)(pasid)) << 32)
460
463
461
464
/* Page group response descriptor QW1 */
462
-
#define QI_PGRP_LPIG(x) (((u64)(x)) << 2)
463
465
#define QI_PGRP_IDX(idx) (((u64)(idx)) << 3)
464
466
465
467
···
537
541
#define pasid_supported(iommu) (sm_supported(iommu) && \
538
542
ecap_pasid((iommu)->ecap))
539
543
#define ssads_supported(iommu) (sm_supported(iommu) && \
540
-
ecap_slads((iommu)->ecap))
544
+
ecap_slads((iommu)->ecap) && \
545
+
ecap_smpwc(iommu->ecap))
541
546
#define nested_supported(iommu) (sm_supported(iommu) && \
542
547
ecap_nest((iommu)->ecap))
543
548
+4
-6
drivers/iommu/intel/perf.c
+4
-6
drivers/iommu/intel/perf.c
···
113
113
" svm_prq"
114
114
};
115
115
116
-
int dmar_latency_snapshot(struct intel_iommu *iommu, char *str, size_t size)
116
+
void dmar_latency_snapshot(struct intel_iommu *iommu, char *str, size_t size)
117
117
{
118
118
struct latency_statistic *lstat = iommu->perf_statistic;
119
119
unsigned long flags;
···
122
122
memset(str, 0, size);
123
123
124
124
for (i = 0; i < COUNTS_NUM; i++)
125
-
bytes += snprintf(str + bytes, size - bytes,
125
+
bytes += scnprintf(str + bytes, size - bytes,
126
126
"%s", latency_counter_names[i]);
127
127
128
128
spin_lock_irqsave(&latency_lock, flags);
···
130
130
if (!dmar_latency_enabled(iommu, i))
131
131
continue;
132
132
133
-
bytes += snprintf(str + bytes, size - bytes,
133
+
bytes += scnprintf(str + bytes, size - bytes,
134
134
"\n%s", latency_type_names[i]);
135
135
136
136
for (j = 0; j < COUNTS_NUM; j++) {
···
156
156
break;
157
157
}
158
158
159
-
bytes += snprintf(str + bytes, size - bytes,
159
+
bytes += scnprintf(str + bytes, size - bytes,
160
160
"%12lld", val);
161
161
}
162
162
}
163
163
spin_unlock_irqrestore(&latency_lock, flags);
164
-
165
-
return bytes;
166
164
}
+2
-3
drivers/iommu/intel/perf.h
+2
-3
drivers/iommu/intel/perf.h
···
40
40
bool dmar_latency_enabled(struct intel_iommu *iommu, enum latency_type type);
41
41
void dmar_latency_update(struct intel_iommu *iommu, enum latency_type type,
42
42
u64 latency);
43
-
int dmar_latency_snapshot(struct intel_iommu *iommu, char *str, size_t size);
43
+
void dmar_latency_snapshot(struct intel_iommu *iommu, char *str, size_t size);
44
44
#else
45
45
static inline int
46
46
dmar_latency_enable(struct intel_iommu *iommu, enum latency_type type)
···
64
64
{
65
65
}
66
66
67
-
static inline int
67
+
static inline void
68
68
dmar_latency_snapshot(struct intel_iommu *iommu, char *str, size_t size)
69
69
{
70
-
return 0;
71
70
}
72
71
#endif /* CONFIG_DMAR_PERF */
+2
-5
drivers/iommu/intel/prq.c
+2
-5
drivers/iommu/intel/prq.c
···
151
151
QI_PGRP_PASID_P(req->pasid_present) |
152
152
QI_PGRP_RESP_CODE(result) |
153
153
QI_PGRP_RESP_TYPE;
154
-
desc.qw1 = QI_PGRP_IDX(req->prg_index) |
155
-
QI_PGRP_LPIG(req->lpig);
154
+
desc.qw1 = QI_PGRP_IDX(req->prg_index);
156
155
157
156
qi_submit_sync(iommu, &desc, 1, 0);
158
157
}
···
378
379
struct iommu_fault_page_request *prm;
379
380
struct qi_desc desc;
380
381
bool pasid_present;
381
-
bool last_page;
382
382
u16 sid;
383
383
384
384
prm = &evt->fault.prm;
385
385
sid = PCI_DEVID(bus, devfn);
386
386
pasid_present = prm->flags & IOMMU_FAULT_PAGE_REQUEST_PASID_VALID;
387
-
last_page = prm->flags & IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE;
388
387
389
388
desc.qw0 = QI_PGRP_PASID(prm->pasid) | QI_PGRP_DID(sid) |
390
389
QI_PGRP_PASID_P(pasid_present) |
391
390
QI_PGRP_RESP_CODE(msg->code) |
392
391
QI_PGRP_RESP_TYPE;
393
-
desc.qw1 = QI_PGRP_IDX(prm->grpid) | QI_PGRP_LPIG(last_page);
392
+
desc.qw1 = QI_PGRP_IDX(prm->grpid);
394
393
desc.qw2 = 0;
395
394
desc.qw3 = 0;
396
395
+88
-55
drivers/iommu/io-pgtable-dart.c
+88
-55
drivers/iommu/io-pgtable-dart.c
···
27
27
28
28
#define DART1_MAX_ADDR_BITS 36
29
29
30
-
#define DART_MAX_TABLES 4
31
-
#define DART_LEVELS 2
30
+
#define DART_MAX_TABLE_BITS 2
31
+
#define DART_MAX_TABLES BIT(DART_MAX_TABLE_BITS)
32
+
#define DART_MAX_LEVELS 4 /* Includes TTBR level */
32
33
33
34
/* Struct accessors */
34
35
#define io_pgtable_to_data(x) \
···
69
68
struct dart_io_pgtable {
70
69
struct io_pgtable iop;
71
70
71
+
int levels;
72
72
int tbl_bits;
73
73
int bits_per_level;
74
74
···
158
156
return old;
159
157
}
160
158
161
-
static int dart_get_table(struct dart_io_pgtable *data, unsigned long iova)
159
+
static int dart_get_index(struct dart_io_pgtable *data, unsigned long iova, int level)
162
160
{
163
-
return (iova >> (3 * data->bits_per_level + ilog2(sizeof(dart_iopte)))) &
164
-
((1 << data->tbl_bits) - 1);
161
+
return (iova >> (level * data->bits_per_level + ilog2(sizeof(dart_iopte)))) &
162
+
((1 << data->bits_per_level) - 1);
165
163
}
166
164
167
-
static int dart_get_l1_index(struct dart_io_pgtable *data, unsigned long iova)
168
-
{
169
-
170
-
return (iova >> (2 * data->bits_per_level + ilog2(sizeof(dart_iopte)))) &
171
-
((1 << data->bits_per_level) - 1);
172
-
}
173
-
174
-
static int dart_get_l2_index(struct dart_io_pgtable *data, unsigned long iova)
165
+
static int dart_get_last_index(struct dart_io_pgtable *data, unsigned long iova)
175
166
{
176
167
177
168
return (iova >> (data->bits_per_level + ilog2(sizeof(dart_iopte)))) &
178
169
((1 << data->bits_per_level) - 1);
179
170
}
180
171
181
-
static dart_iopte *dart_get_l2(struct dart_io_pgtable *data, unsigned long iova)
172
+
static dart_iopte *dart_get_last(struct dart_io_pgtable *data, unsigned long iova)
182
173
{
183
174
dart_iopte pte, *ptep;
184
-
int tbl = dart_get_table(data, iova);
175
+
int level = data->levels;
176
+
int tbl = dart_get_index(data, iova, level);
177
+
178
+
if (tbl >= (1 << data->tbl_bits))
179
+
return NULL;
185
180
186
181
ptep = data->pgd[tbl];
187
182
if (!ptep)
188
183
return NULL;
189
184
190
-
ptep += dart_get_l1_index(data, iova);
191
-
pte = READ_ONCE(*ptep);
185
+
while (--level > 1) {
186
+
ptep += dart_get_index(data, iova, level);
187
+
pte = READ_ONCE(*ptep);
192
188
193
-
/* Valid entry? */
194
-
if (!pte)
195
-
return NULL;
189
+
/* Valid entry? */
190
+
if (!pte)
191
+
return NULL;
196
192
197
-
/* Deref to get level 2 table */
198
-
return iopte_deref(pte, data);
193
+
/* Deref to get next level table */
194
+
ptep = iopte_deref(pte, data);
195
+
}
196
+
197
+
return ptep;
199
198
}
200
199
201
200
static dart_iopte dart_prot_to_pte(struct dart_io_pgtable *data,
···
233
230
int ret = 0, tbl, num_entries, max_entries, map_idx_start;
234
231
dart_iopte pte, *cptep, *ptep;
235
232
dart_iopte prot;
233
+
int level = data->levels;
236
234
237
235
if (WARN_ON(pgsize != cfg->pgsize_bitmap))
238
236
return -EINVAL;
···
244
240
if (!(iommu_prot & (IOMMU_READ | IOMMU_WRITE)))
245
241
return -EINVAL;
246
242
247
-
tbl = dart_get_table(data, iova);
243
+
tbl = dart_get_index(data, iova, level);
244
+
245
+
if (tbl >= (1 << data->tbl_bits))
246
+
return -ENOMEM;
248
247
249
248
ptep = data->pgd[tbl];
250
-
ptep += dart_get_l1_index(data, iova);
251
-
pte = READ_ONCE(*ptep);
252
-
253
-
/* no L2 table present */
254
-
if (!pte) {
255
-
cptep = iommu_alloc_pages_sz(gfp, tblsz);
256
-
if (!cptep)
257
-
return -ENOMEM;
258
-
259
-
pte = dart_install_table(cptep, ptep, 0, data);
260
-
if (pte)
261
-
iommu_free_pages(cptep);
262
-
263
-
/* L2 table is present (now) */
249
+
while (--level > 1) {
250
+
ptep += dart_get_index(data, iova, level);
264
251
pte = READ_ONCE(*ptep);
265
-
}
266
252
267
-
ptep = iopte_deref(pte, data);
253
+
/* no table present */
254
+
if (!pte) {
255
+
cptep = iommu_alloc_pages_sz(gfp, tblsz);
256
+
if (!cptep)
257
+
return -ENOMEM;
258
+
259
+
pte = dart_install_table(cptep, ptep, 0, data);
260
+
if (pte)
261
+
iommu_free_pages(cptep);
262
+
263
+
/* L2 table is present (now) */
264
+
pte = READ_ONCE(*ptep);
265
+
}
266
+
267
+
ptep = iopte_deref(pte, data);
268
+
}
268
269
269
270
/* install a leaf entries into L2 table */
270
271
prot = dart_prot_to_pte(data, iommu_prot);
271
-
map_idx_start = dart_get_l2_index(data, iova);
272
+
map_idx_start = dart_get_last_index(data, iova);
272
273
max_entries = DART_PTES_PER_TABLE(data) - map_idx_start;
273
274
num_entries = min_t(int, pgcount, max_entries);
274
275
ptep += map_idx_start;
···
302
293
if (WARN_ON(pgsize != cfg->pgsize_bitmap || !pgcount))
303
294
return 0;
304
295
305
-
ptep = dart_get_l2(data, iova);
296
+
ptep = dart_get_last(data, iova);
306
297
307
298
/* Valid L2 IOPTE pointer? */
308
299
if (WARN_ON(!ptep))
309
300
return 0;
310
301
311
-
unmap_idx_start = dart_get_l2_index(data, iova);
302
+
unmap_idx_start = dart_get_last_index(data, iova);
312
303
ptep += unmap_idx_start;
313
304
314
305
max_entries = DART_PTES_PER_TABLE(data) - unmap_idx_start;
···
339
330
struct dart_io_pgtable *data = io_pgtable_ops_to_data(ops);
340
331
dart_iopte pte, *ptep;
341
332
342
-
ptep = dart_get_l2(data, iova);
333
+
ptep = dart_get_last(data, iova);
343
334
344
335
/* Valid L2 IOPTE pointer? */
345
336
if (!ptep)
346
337
return 0;
347
338
348
-
ptep += dart_get_l2_index(data, iova);
339
+
ptep += dart_get_last_index(data, iova);
349
340
350
341
pte = READ_ONCE(*ptep);
351
342
/* Found translation */
···
362
353
dart_alloc_pgtable(struct io_pgtable_cfg *cfg)
363
354
{
364
355
struct dart_io_pgtable *data;
365
-
int tbl_bits, bits_per_level, va_bits, pg_shift;
356
+
int levels, max_tbl_bits, tbl_bits, bits_per_level, va_bits, pg_shift;
357
+
358
+
/*
359
+
* Old 4K page DARTs can use up to 4 top-level tables.
360
+
* Newer ones only ever use a maximum of 1.
361
+
*/
362
+
if (cfg->pgsize_bitmap == SZ_4K)
363
+
max_tbl_bits = DART_MAX_TABLE_BITS;
364
+
else
365
+
max_tbl_bits = 0;
366
366
367
367
pg_shift = __ffs(cfg->pgsize_bitmap);
368
368
bits_per_level = pg_shift - ilog2(sizeof(dart_iopte));
369
369
370
370
va_bits = cfg->ias - pg_shift;
371
371
372
-
tbl_bits = max_t(int, 0, va_bits - (bits_per_level * DART_LEVELS));
373
-
if ((1 << tbl_bits) > DART_MAX_TABLES)
372
+
levels = max_t(int, 2, (va_bits - max_tbl_bits + bits_per_level - 1) / bits_per_level);
373
+
374
+
if (levels > (DART_MAX_LEVELS - 1))
375
+
return NULL;
376
+
377
+
tbl_bits = max_t(int, 0, va_bits - (bits_per_level * levels));
378
+
379
+
if (tbl_bits > max_tbl_bits)
374
380
return NULL;
375
381
376
382
data = kzalloc(sizeof(*data), GFP_KERNEL);
377
383
if (!data)
378
384
return NULL;
379
385
386
+
data->levels = levels + 1; /* Table level counts as one level */
380
387
data->tbl_bits = tbl_bits;
381
388
data->bits_per_level = bits_per_level;
382
389
···
428
403
return NULL;
429
404
430
405
cfg->apple_dart_cfg.n_ttbrs = 1 << data->tbl_bits;
406
+
cfg->apple_dart_cfg.n_levels = data->levels;
431
407
432
408
for (i = 0; i < cfg->apple_dart_cfg.n_ttbrs; ++i) {
433
409
data->pgd[i] =
···
448
422
return NULL;
449
423
}
450
424
451
-
static void apple_dart_free_pgtable(struct io_pgtable *iop)
425
+
static void apple_dart_free_pgtables(struct dart_io_pgtable *data, dart_iopte *ptep, int level)
452
426
{
453
-
struct dart_io_pgtable *data = io_pgtable_to_data(iop);
454
-
dart_iopte *ptep, *end;
455
-
int i;
427
+
dart_iopte *end;
428
+
dart_iopte *start = ptep;
456
429
457
-
for (i = 0; i < (1 << data->tbl_bits) && data->pgd[i]; ++i) {
458
-
ptep = data->pgd[i];
430
+
if (level > 1) {
459
431
end = (void *)ptep + DART_GRANULE(data);
460
432
461
433
while (ptep != end) {
462
434
dart_iopte pte = *ptep++;
463
435
464
436
if (pte)
465
-
iommu_free_pages(iopte_deref(pte, data));
437
+
apple_dart_free_pgtables(data, iopte_deref(pte, data), level - 1);
466
438
}
467
-
iommu_free_pages(data->pgd[i]);
468
439
}
440
+
iommu_free_pages(start);
441
+
}
442
+
443
+
static void apple_dart_free_pgtable(struct io_pgtable *iop)
444
+
{
445
+
struct dart_io_pgtable *data = io_pgtable_to_data(iop);
446
+
int i;
447
+
448
+
for (i = 0; i < (1 << data->tbl_bits) && data->pgd[i]; ++i)
449
+
apple_dart_free_pgtables(data, data->pgd[i], data->levels - 1);
469
450
470
451
kfree(data);
471
452
}
+1
-1
drivers/iommu/omap-iommu.c
+1
-1
drivers/iommu/omap-iommu.c
+16
-1
drivers/iommu/riscv/iommu-platform.c
+16
-1
drivers/iommu/riscv/iommu-platform.c
···
10
10
* Tomasz Jeznach <tjeznach@rivosinc.com>
11
11
*/
12
12
13
+
#include <linux/acpi.h>
14
+
#include <linux/irqchip/riscv-imsic.h>
13
15
#include <linux/kernel.h>
14
16
#include <linux/msi.h>
15
17
#include <linux/of_irq.h>
···
48
46
enum riscv_iommu_igs_settings igs;
49
47
struct device *dev = &pdev->dev;
50
48
struct riscv_iommu_device *iommu = NULL;
49
+
struct irq_domain *msi_domain;
51
50
struct resource *res = NULL;
52
51
int vec, ret;
53
52
···
79
76
switch (igs) {
80
77
case RISCV_IOMMU_CAPABILITIES_IGS_BOTH:
81
78
case RISCV_IOMMU_CAPABILITIES_IGS_MSI:
82
-
if (is_of_node(dev->fwnode))
79
+
if (is_of_node(dev_fwnode(dev))) {
83
80
of_msi_configure(dev, to_of_node(dev->fwnode));
81
+
} else {
82
+
msi_domain = irq_find_matching_fwnode(imsic_acpi_get_fwnode(dev),
83
+
DOMAIN_BUS_PLATFORM_MSI);
84
+
dev_set_msi_domain(dev, msi_domain);
85
+
}
84
86
85
87
if (!dev_get_msi_domain(dev)) {
86
88
dev_warn(dev, "failed to find an MSI domain\n");
···
158
150
{},
159
151
};
160
152
153
+
static const struct acpi_device_id riscv_iommu_acpi_match[] = {
154
+
{ "RSCV0004", 0 },
155
+
{}
156
+
};
157
+
MODULE_DEVICE_TABLE(acpi, riscv_iommu_acpi_match);
158
+
161
159
static struct platform_driver riscv_iommu_platform_driver = {
162
160
.probe = riscv_iommu_platform_probe,
163
161
.remove = riscv_iommu_platform_remove,
···
172
158
.name = "riscv,iommu",
173
159
.of_match_table = riscv_iommu_of_match,
174
160
.suppress_bind_attrs = true,
161
+
.acpi_match_table = riscv_iommu_acpi_match,
175
162
},
176
163
};
177
164
+10
drivers/iommu/riscv/iommu.c
+10
drivers/iommu/riscv/iommu.c
···
12
12
13
13
#define pr_fmt(fmt) "riscv-iommu: " fmt
14
14
15
+
#include <linux/acpi.h>
16
+
#include <linux/acpi_rimt.h>
15
17
#include <linux/compiler.h>
16
18
#include <linux/crash_dump.h>
17
19
#include <linux/init.h>
···
1650
1648
if (rc) {
1651
1649
dev_err_probe(iommu->dev, rc, "cannot register sysfs interface\n");
1652
1650
goto err_iodir_off;
1651
+
}
1652
+
1653
+
if (!acpi_disabled) {
1654
+
rc = rimt_iommu_register(iommu->dev);
1655
+
if (rc) {
1656
+
dev_err_probe(iommu->dev, rc, "cannot register iommu with RIMT\n");
1657
+
goto err_remove_sysfs;
1658
+
}
1653
1659
}
1654
1660
1655
1661
rc = iommu_device_register(&iommu->iommu, &riscv_iommu_ops, iommu->dev);
+28
include/linux/acpi_rimt.h
+28
include/linux/acpi_rimt.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (C) 2024-2025, Ventana Micro Systems Inc.
4
+
* Author: Sunil V L <sunilvl@ventanamicro.com>
5
+
*/
6
+
7
+
#ifndef _ACPI_RIMT_H
8
+
#define _ACPI_RIMT_H
9
+
10
+
#ifdef CONFIG_ACPI_RIMT
11
+
int rimt_iommu_register(struct device *dev);
12
+
#else
13
+
static inline int rimt_iommu_register(struct device *dev)
14
+
{
15
+
return -ENODEV;
16
+
}
17
+
#endif
18
+
19
+
#if defined(CONFIG_IOMMU_API) && defined(CONFIG_ACPI_RIMT)
20
+
int rimt_iommu_configure_id(struct device *dev, const u32 *id_in);
21
+
#else
22
+
static inline int rimt_iommu_configure_id(struct device *dev, const u32 *id_in)
23
+
{
24
+
return -ENODEV;
25
+
}
26
+
#endif
27
+
28
+
#endif /* _ACPI_RIMT_H */