net/mlx5e: Avoid a hundred -Wflex-array-member-not-at-end warnings

-Wflex-array-member-not-at-end was introduced in GCC-14, and we are
getting ready to enable it, globally.

So, in this particular case, we create a new `struct mlx5e_umr_wqe_hdr`
to enclose the header part of flexible structure `struct mlx5e_umr_wqe`.
This is, all the members except the flexible arrays `inline_mtts`,
`inline_klms` and `inline_ksms` in the anonymous union. We then replace
the header part with `struct mlx5e_umr_wqe_hdr hdr;` in `struct
mlx5e_umr_wqe`, and change the type of the object currently causing
trouble `umr_wqe` from `struct mlx5e_umr_wqe` to `struct
mlx5e_umr_wqe_hdr` --this last bit gets rid of the flex-array-in-the-middle
part and avoid the warnings.

Also, no new members should be added to `struct mlx5e_umr_wqe`, instead
any new members must be included in the header structure `struct
mlx5e_umr_wqe_hdr`. To enforce this, we use `static_assert()`, ensuring
that the memory layout of both the flexible structure and the newly
created header struct remain consistent.

The next step is to refactor the rest of the related code accordingly,
which means adding a bunch of `hdr.` wherever needed.

Lastly, we use `container_of()` whenever we need to retrieve a pointer
to the flexible structure `struct mlx5e_umr_wqe`.

So, with these changes, fix 125 of the following warnings:

drivers/net/ethernet/mellanox/mlx5/core/en.h:664:48: warning: structure containing a flexible array member is not at the end of another structure [-Wflex-array-member-not-at-end]

Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Reviewed-by: Saeed Mahameed <saeedm@nvidia.com>
Link: https://patch.msgid.link/Z76HzPW1dFTLOSSy@kspp
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

authored by

Gustavo A. R. Silva and committed by

Jakub Kicinski 1 year ago bf08fd32 047e059c

+27 -19

4 changed files

expand all

drivers

net

ethernet

mellanox

mlx5

core

xsk

rx.c

en.h

en_main.c

en_rx.c

+8 -2

drivers/net/ethernet/mellanox/mlx5/core/en.h

··· 230 230 DECLARE_FLEX_ARRAY(struct mlx5_wqe_data_seg, data); 231 231 }; 232 232 233 - struct mlx5e_umr_wqe { 233 + struct mlx5e_umr_wqe_hdr { 234 234 struct mlx5_wqe_ctrl_seg ctrl; 235 235 struct mlx5_wqe_umr_ctrl_seg uctrl; 236 236 struct mlx5_mkey_seg mkc; 237 + }; 238 + 239 + struct mlx5e_umr_wqe { 240 + struct mlx5e_umr_wqe_hdr hdr; 237 241 union { 238 242 DECLARE_FLEX_ARRAY(struct mlx5_mtt, inline_mtts); 239 243 DECLARE_FLEX_ARRAY(struct mlx5_klm, inline_klms); 240 244 DECLARE_FLEX_ARRAY(struct mlx5_ksm, inline_ksms); 241 245 }; 242 246 }; 247 + static_assert(offsetof(struct mlx5e_umr_wqe, inline_mtts) == sizeof(struct mlx5e_umr_wqe_hdr), 248 + "struct members should be included in struct mlx5e_umr_wqe_hdr, not in struct mlx5e_umr_wqe"); 243 249 244 250 enum mlx5e_priv_flag { 245 251 MLX5E_PFLAG_RX_CQE_BASED_MODER, ··· 663 657 } wqe; 664 658 struct { 665 659 struct mlx5_wq_ll wq; 666 - struct mlx5e_umr_wqe umr_wqe; 660 + struct mlx5e_umr_wqe_hdr umr_wqe; 667 661 struct mlx5e_mpw_info *info; 668 662 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq; 669 663 __be32 umr_mkey_be;

+3 -3

drivers/net/ethernet/mellanox/mlx5/core/en/xsk/rx.c

··· 123 123 bitmap_zero(wi->skip_release_bitmap, rq->mpwqe.pages_per_wqe); 124 124 wi->consumed_strides = 0; 125 125 126 - umr_wqe->ctrl.opmod_idx_opcode = 126 + umr_wqe->hdr.ctrl.opmod_idx_opcode = 127 127 cpu_to_be32((icosq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) | MLX5_OPCODE_UMR); 128 128 129 129 /* Optimized for speed: keep in sync with mlx5e_mpwrq_umr_entry_size. */ ··· 134 134 offset = offset * sizeof(struct mlx5_klm) * 2 / MLX5_OCTWORD; 135 135 else if (unlikely(rq->mpwqe.umr_mode == MLX5E_MPWRQ_UMR_MODE_TRIPLE)) 136 136 offset = offset * sizeof(struct mlx5_ksm) * 4 / MLX5_OCTWORD; 137 - umr_wqe->uctrl.xlt_offset = cpu_to_be16(offset); 137 + umr_wqe->hdr.uctrl.xlt_offset = cpu_to_be16(offset); 138 138 139 139 icosq->db.wqe_info[pi] = (struct mlx5e_icosq_wqe_info) { 140 140 .wqe_type = MLX5E_ICOSQ_WQE_UMR_RX, ··· 144 144 145 145 icosq->pc += rq->mpwqe.umr_wqebbs; 146 146 147 - icosq->doorbell_cseg = &umr_wqe->ctrl; 147 + icosq->doorbell_cseg = &umr_wqe->hdr.ctrl; 148 148 149 149 return 0; 150 150

+5 -3

drivers/net/ethernet/mellanox/mlx5/core/en_main.c

··· 311 311 struct mlx5e_icosq *sq, 312 312 struct mlx5e_umr_wqe *wqe) 313 313 { 314 - struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; 315 - struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl; 314 + struct mlx5_wqe_ctrl_seg *cseg = &wqe->hdr.ctrl; 315 + struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->hdr.uctrl; 316 316 u16 octowords; 317 317 u8 ds_cnt; 318 318 ··· 393 393 bitmap_fill(wi->skip_release_bitmap, rq->mpwqe.pages_per_wqe); 394 394 } 395 395 396 - mlx5e_build_umr_wqe(rq, rq->icosq, &rq->mpwqe.umr_wqe); 396 + mlx5e_build_umr_wqe(rq, rq->icosq, 397 + container_of(&rq->mpwqe.umr_wqe, 398 + struct mlx5e_umr_wqe, hdr)); 397 399 398 400 return 0; 399 401 }

+11 -11

drivers/net/ethernet/mellanox/mlx5/core/en_rx.c

··· 631 631 __be32 key, u16 offset, u16 ksm_len) 632 632 { 633 633 memset(umr_wqe, 0, offsetof(struct mlx5e_umr_wqe, inline_ksms)); 634 - umr_wqe->ctrl.opmod_idx_opcode = 634 + umr_wqe->hdr.ctrl.opmod_idx_opcode = 635 635 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) | 636 636 MLX5_OPCODE_UMR); 637 - umr_wqe->ctrl.umr_mkey = key; 638 - umr_wqe->ctrl.qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) 637 + umr_wqe->hdr.ctrl.umr_mkey = key; 638 + umr_wqe->hdr.ctrl.qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) 639 639 | MLX5E_KSM_UMR_DS_CNT(ksm_len)); 640 - umr_wqe->uctrl.flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE; 641 - umr_wqe->uctrl.xlt_offset = cpu_to_be16(offset); 642 - umr_wqe->uctrl.xlt_octowords = cpu_to_be16(ksm_len); 643 - umr_wqe->uctrl.mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 640 + umr_wqe->hdr.uctrl.flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE; 641 + umr_wqe->hdr.uctrl.xlt_offset = cpu_to_be16(offset); 642 + umr_wqe->hdr.uctrl.xlt_octowords = cpu_to_be16(ksm_len); 643 + umr_wqe->hdr.uctrl.mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 644 644 } 645 645 646 646 static struct mlx5e_frag_page *mlx5e_shampo_hd_to_frag_page(struct mlx5e_rq *rq, int header_index) ··· 704 704 705 705 shampo->pi = (shampo->pi + ksm_entries) & (shampo->hd_per_wq - 1); 706 706 sq->pc += wqe_bbs; 707 - sq->doorbell_cseg = &umr_wqe->ctrl; 707 + sq->doorbell_cseg = &umr_wqe->hdr.ctrl; 708 708 709 709 return 0; 710 710 ··· 814 814 bitmap_zero(wi->skip_release_bitmap, rq->mpwqe.pages_per_wqe); 815 815 wi->consumed_strides = 0; 816 816 817 - umr_wqe->ctrl.opmod_idx_opcode = 817 + umr_wqe->hdr.ctrl.opmod_idx_opcode = 818 818 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) | 819 819 MLX5_OPCODE_UMR); 820 820 821 821 offset = (ix * rq->mpwqe.mtts_per_wqe) * sizeof(struct mlx5_mtt) / MLX5_OCTWORD; 822 - umr_wqe->uctrl.xlt_offset = cpu_to_be16(offset); 822 + umr_wqe->hdr.uctrl.xlt_offset = cpu_to_be16(offset); 823 823 824 824 sq->db.wqe_info[pi] = (struct mlx5e_icosq_wqe_info) { 825 825 .wqe_type = MLX5E_ICOSQ_WQE_UMR_RX, ··· 829 829 830 830 sq->pc += rq->mpwqe.umr_wqebbs; 831 831 832 - sq->doorbell_cseg = &umr_wqe->ctrl; 832 + sq->doorbell_cseg = &umr_wqe->hdr.ctrl; 833 833 834 834 return 0; 835 835

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