Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
iio: adc: Add ti-ads1018 driver
Add ti-ads1018 driver for Texas Instruments ADS1018 and ADS1118 SPI
analog-to-digital converters.
This chips' MOSI pin is shared with a data-ready interrupt. Defining
this interrupt in devicetree is optional, therefore we only create an
IIO trigger if one is found.
Handling this interrupt requires some considerations. When enabling the
trigger the CS line is tied low (active), thus we need to hold
spi_bus_lock() too, to avoid state corruption. This is done inside the
set_trigger_state() callback, to let users use other triggers without
wasting a bus lock.
Reviewed-by: Andy Shevchenko <andy@kernel.org>
Signed-off-by: Kurt Borja <kuurtb@gmail.com>
Reviewed-by: David Lechner <dlechner@baylibre.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
authored by
Kurt Borja
and committed by
Jonathan Cameron
bf0bba48
43fabbb9
+754
+1
MAINTAINERS
+1
MAINTAINERS
+12
drivers/iio/adc/Kconfig
+12
drivers/iio/adc/Kconfig
···
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This driver can also be built as a module. If so, the module will be
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called ti-ads1015.
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config TI_ADS1018
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tristate "Texas Instruments ADS1018 ADC"
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depends on SPI
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select IIO_BUFFER
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select IIO_TRIGGERED_BUFFER
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help
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If you say yes here you get support for Texas Instruments ADS1018 and
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ADS1118 ADC chips.
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This driver can also be built as a module. If so, the module will be
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called ti-ads1018.
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config TI_ADS1100
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tristate "Texas Instruments ADS1100 and ADS1000 ADC"
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depends on I2C
+1
drivers/iio/adc/Makefile
+1
drivers/iio/adc/Makefile
···
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obj-$(CONFIG_TI_ADC128S052) += ti-adc128s052.o
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obj-$(CONFIG_TI_ADC161S626) += ti-adc161s626.o
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obj-$(CONFIG_TI_ADS1015) += ti-ads1015.o
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obj-$(CONFIG_TI_ADS1018) += ti-ads1018.o
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obj-$(CONFIG_TI_ADS1100) += ti-ads1100.o
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obj-$(CONFIG_TI_ADS1119) += ti-ads1119.o
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obj-$(CONFIG_TI_ADS124S08) += ti-ads124s08.o
+740
drivers/iio/adc/ti-ads1018.c
+740
drivers/iio/adc/ti-ads1018.c
···
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+
// SPDX-License-Identifier: GPL-2.0-or-later
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+
/*
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* Texas Instruments ADS1018 ADC driver
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*
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* Copyright (C) 2025 Kurt Borja <kuurtb@gmail.com>
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*/
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+
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#include <linux/array_size.h>
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#include <linux/bitfield.h>
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#include <linux/bitmap.h>
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#include <linux/dev_printk.h>
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#include <linux/gpio/consumer.h>
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#include <linux/interrupt.h>
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#include <linux/math.h>
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#include <linux/mod_devicetable.h>
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+
#include <linux/module.h>
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#include <linux/spi/spi.h>
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#include <linux/types.h>
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#include <linux/units.h>
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+
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#include <asm/byteorder.h>
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+
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#include <linux/iio/buffer.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/trigger.h>
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#include <linux/iio/trigger_consumer.h>
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#include <linux/iio/triggered_buffer.h>
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+
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#define ADS1018_CFG_OS_TRIG BIT(15)
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#define ADS1018_CFG_TS_MODE_EN BIT(4)
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#define ADS1018_CFG_PULL_UP BIT(3)
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#define ADS1018_CFG_NOP BIT(1)
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#define ADS1018_CFG_VALID (ADS1018_CFG_PULL_UP | ADS1018_CFG_NOP)
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+
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#define ADS1018_CFG_MUX_MASK GENMASK(14, 12)
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+
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#define ADS1018_CFG_PGA_MASK GENMASK(11, 9)
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#define ADS1018_PGA_DEFAULT 2
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+
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#define ADS1018_CFG_MODE_MASK BIT(8)
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#define ADS1018_MODE_CONTINUOUS 0
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#define ADS1018_MODE_ONESHOT 1
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+
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#define ADS1018_CFG_DRATE_MASK GENMASK(7, 5)
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#define ADS1018_DRATE_DEFAULT 4
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+
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#define ADS1018_NUM_PGA_MODES 6
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#define ADS1018_CHANNELS_MAX 10
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+
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struct ads1018_chan_data {
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u8 pga_mode;
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u8 data_rate_mode;
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};
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+
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struct ads1018_chip_info {
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const char *name;
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const struct iio_chan_spec *channels;
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unsigned long num_channels;
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+
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/* IIO_VAL_INT */
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const u32 *data_rate_mode_to_hz;
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unsigned long num_data_rate_mode_to_hz;
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+
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/*
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* Let `res` be the chip's resolution and `fsr` (millivolts) be the
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* full-scale range corresponding to the PGA mode given by the array
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* index. Then, the gain is calculated using the following formula:
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*
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* gain = |fsr| / 2^(res - 1)
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*
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* This value then has to be represented in IIO_VAL_INT_PLUS_NANO
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* format. For example if:
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*
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* gain = 6144 / 2^(16 - 1) = 0.1875
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*
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* ...then the formatted value is:
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*
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* { 0, 187500000 }
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*/
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const u32 pga_mode_to_gain[ADS1018_NUM_PGA_MODES][2];
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+
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/* IIO_VAL_INT_PLUS_MICRO */
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const u32 temp_scale[2];
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};
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+
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struct ads1018 {
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struct spi_device *spi;
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struct iio_trigger *indio_trig;
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+
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struct gpio_desc *drdy_gpiod;
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int drdy_irq;
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+
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struct ads1018_chan_data chan_data[ADS1018_CHANNELS_MAX];
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const struct ads1018_chip_info *chip_info;
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+
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struct spi_message msg_read;
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struct spi_transfer xfer;
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__be16 tx_buf[2] __aligned(IIO_DMA_MINALIGN);
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__be16 rx_buf[2];
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};
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+
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#define ADS1018_VOLT_DIFF_CHAN(_index, _chan, _chan2, _realbits) { \
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.type = IIO_VOLTAGE, \
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.channel = _chan, \
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.channel2 = _chan2, \
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.scan_index = _index, \
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.scan_type = { \
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.sign = 's', \
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.realbits = _realbits, \
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.storagebits = 16, \
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.shift = 16 - _realbits, \
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.endianness = IIO_BE, \
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+
}, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
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BIT(IIO_CHAN_INFO_SCALE) | \
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BIT(IIO_CHAN_INFO_SAMP_FREQ), \
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.info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \
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.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
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.indexed = true, \
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.differential = true, \
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+
}
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+
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#define ADS1018_VOLT_CHAN(_index, _chan, _realbits) { \
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.type = IIO_VOLTAGE, \
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.channel = _chan, \
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.scan_index = _index, \
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.scan_type = { \
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.sign = 's', \
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.realbits = _realbits, \
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.storagebits = 16, \
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.shift = 16 - _realbits, \
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.endianness = IIO_BE, \
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}, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
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BIT(IIO_CHAN_INFO_SCALE) | \
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BIT(IIO_CHAN_INFO_SAMP_FREQ), \
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.info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \
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.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
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.indexed = true, \
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+
}
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+
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#define ADS1018_TEMP_CHAN(_index, _realbits) { \
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.type = IIO_TEMP, \
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.scan_index = _index, \
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.scan_type = { \
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+
.sign = 's', \
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+
.realbits = _realbits, \
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.storagebits = 16, \
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+
.shift = 16 - _realbits, \
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+
.endianness = IIO_BE, \
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+
}, \
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+
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
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BIT(IIO_CHAN_INFO_SCALE) | \
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BIT(IIO_CHAN_INFO_SAMP_FREQ), \
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.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
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+
}
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+
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static const struct iio_chan_spec ads1118_iio_channels[] = {
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ADS1018_VOLT_DIFF_CHAN(0, 0, 1, 16),
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ADS1018_VOLT_DIFF_CHAN(1, 0, 3, 16),
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ADS1018_VOLT_DIFF_CHAN(2, 1, 3, 16),
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ADS1018_VOLT_DIFF_CHAN(3, 2, 3, 16),
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ADS1018_VOLT_CHAN(4, 0, 16),
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ADS1018_VOLT_CHAN(5, 1, 16),
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+
ADS1018_VOLT_CHAN(6, 2, 16),
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+
ADS1018_VOLT_CHAN(7, 3, 16),
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ADS1018_TEMP_CHAN(8, 14),
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IIO_CHAN_SOFT_TIMESTAMP(9),
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+
};
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+
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static const struct iio_chan_spec ads1018_iio_channels[] = {
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ADS1018_VOLT_DIFF_CHAN(0, 0, 1, 12),
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ADS1018_VOLT_DIFF_CHAN(1, 0, 3, 12),
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ADS1018_VOLT_DIFF_CHAN(2, 1, 3, 12),
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ADS1018_VOLT_DIFF_CHAN(3, 2, 3, 12),
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ADS1018_VOLT_CHAN(4, 0, 12),
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ADS1018_VOLT_CHAN(5, 1, 12),
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ADS1018_VOLT_CHAN(6, 2, 12),
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ADS1018_VOLT_CHAN(7, 3, 12),
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ADS1018_TEMP_CHAN(8, 12),
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IIO_CHAN_SOFT_TIMESTAMP(9),
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+
};
183
+
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+
/**
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* ads1018_calc_delay - Calculates a suitable delay for a single-shot reading
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* @hz: Sampling frequency
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*
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* Calculates an appropriate delay for a single shot reading given a sampling
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* frequency.
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*
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* Return: Delay in microseconds (Always greater than 0).
192
+
*/
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static u32 ads1018_calc_delay(unsigned int hz)
194
+
{
195
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/*
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* Calculate the worst-case sampling rate by subtracting 10% error
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* specified in the datasheet...
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+
*/
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hz -= DIV_ROUND_UP(hz, 10);
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+
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/* ...Then calculate time per sample in microseconds. */
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return DIV_ROUND_UP(HZ_PER_MHZ, hz);
203
+
}
204
+
205
+
/**
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* ads1018_spi_read_exclusive - Reads a conversion value from the device
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* @ads1018: Device data
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* @cnv: ADC Conversion value (optional)
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* @hold_cs: Keep CS line asserted after the SPI transfer
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*
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* Reads the most recent ADC conversion value, without updating the
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* device's configuration.
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*
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* Context: Expects iio_device_claim_buffer_mode() is held and SPI bus
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* *exclusive* use.
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*
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* Return: 0 on success, negative errno on error.
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*/
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static int ads1018_spi_read_exclusive(struct ads1018 *ads1018, __be16 *cnv,
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bool hold_cs)
221
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{
222
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int ret;
223
+
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ads1018->xfer.cs_change = hold_cs;
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+
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ret = spi_sync_locked(ads1018->spi, &ads1018->msg_read);
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if (ret)
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return ret;
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+
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if (cnv)
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*cnv = ads1018->rx_buf[0];
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+
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return 0;
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}
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+
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/**
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* ads1018_single_shot - Performs a one-shot reading sequence
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* @ads1018: Device data
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* @chan: Channel specification
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* @cnv: Conversion value
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*
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* Writes a new configuration, waits an appropriate delay, then reads the most
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* recent conversion.
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*
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* Context: Expects iio_device_claim_direct() is held.
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*
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* Return: 0 on success, negative errno on error.
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*/
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static int ads1018_single_shot(struct ads1018 *ads1018,
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struct iio_chan_spec const *chan, u16 *cnv)
251
+
{
252
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u8 max_drate_mode = ads1018->chip_info->num_data_rate_mode_to_hz - 1;
253
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u8 drate = ads1018->chip_info->data_rate_mode_to_hz[max_drate_mode];
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u8 pga_mode = ads1018->chan_data[chan->scan_index].pga_mode;
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struct spi_transfer xfer[2] = {
256
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{
257
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.tx_buf = ads1018->tx_buf,
258
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.len = sizeof(ads1018->tx_buf[0]),
259
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.delay = {
260
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.value = ads1018_calc_delay(drate),
261
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.unit = SPI_DELAY_UNIT_USECS,
262
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},
263
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.cs_change = 1, /* 16-bit mode requires CS de-assert */
264
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},
265
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{
266
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.rx_buf = ads1018->rx_buf,
267
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.len = sizeof(ads1018->rx_buf[0]),
268
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},
269
+
};
270
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u16 cfg;
271
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int ret;
272
+
273
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cfg = ADS1018_CFG_VALID | ADS1018_CFG_OS_TRIG;
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cfg |= FIELD_PREP(ADS1018_CFG_MUX_MASK, chan->scan_index);
275
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cfg |= FIELD_PREP(ADS1018_CFG_PGA_MASK, pga_mode);
276
+
cfg |= FIELD_PREP(ADS1018_CFG_MODE_MASK, ADS1018_MODE_ONESHOT);
277
+
cfg |= FIELD_PREP(ADS1018_CFG_DRATE_MASK, max_drate_mode);
278
+
279
+
if (chan->type == IIO_TEMP)
280
+
cfg |= ADS1018_CFG_TS_MODE_EN;
281
+
282
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ads1018->tx_buf[0] = cpu_to_be16(cfg);
283
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ret = spi_sync_transfer(ads1018->spi, xfer, ARRAY_SIZE(xfer));
284
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if (ret)
285
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return ret;
286
+
287
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*cnv = be16_to_cpu(ads1018->rx_buf[0]);
288
+
289
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return 0;
290
+
}
291
+
292
+
static int
293
+
ads1018_read_raw_direct_mode(struct iio_dev *indio_dev,
294
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struct iio_chan_spec const *chan, int *val, int *val2,
295
+
long mask)
296
+
{
297
+
struct ads1018 *ads1018 = iio_priv(indio_dev);
298
+
const struct ads1018_chip_info *chip_info = ads1018->chip_info;
299
+
u8 addr = chan->scan_index;
300
+
u8 pga_mode, drate_mode;
301
+
u16 cnv;
302
+
int ret;
303
+
304
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switch (mask) {
305
+
case IIO_CHAN_INFO_RAW:
306
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ret = ads1018_single_shot(ads1018, chan, &cnv);
307
+
if (ret)
308
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return ret;
309
+
310
+
cnv >>= chan->scan_type.shift;
311
+
*val = sign_extend32(cnv, chan->scan_type.realbits - 1);
312
+
313
+
return IIO_VAL_INT;
314
+
315
+
case IIO_CHAN_INFO_SCALE:
316
+
switch (chan->type) {
317
+
case IIO_VOLTAGE:
318
+
pga_mode = ads1018->chan_data[addr].pga_mode;
319
+
*val = chip_info->pga_mode_to_gain[pga_mode][0];
320
+
*val2 = chip_info->pga_mode_to_gain[pga_mode][1];
321
+
return IIO_VAL_INT_PLUS_NANO;
322
+
323
+
case IIO_TEMP:
324
+
*val = chip_info->temp_scale[0];
325
+
*val2 = chip_info->temp_scale[1];
326
+
return IIO_VAL_INT_PLUS_MICRO;
327
+
328
+
default:
329
+
return -EOPNOTSUPP;
330
+
}
331
+
332
+
case IIO_CHAN_INFO_SAMP_FREQ:
333
+
drate_mode = ads1018->chan_data[addr].data_rate_mode;
334
+
*val = chip_info->data_rate_mode_to_hz[drate_mode];
335
+
return IIO_VAL_INT;
336
+
337
+
default:
338
+
return -EOPNOTSUPP;
339
+
}
340
+
}
341
+
342
+
static int
343
+
ads1018_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
344
+
int *val, int *val2, long mask)
345
+
{
346
+
int ret;
347
+
348
+
if (!iio_device_claim_direct(indio_dev))
349
+
return -EBUSY;
350
+
ret = ads1018_read_raw_direct_mode(indio_dev, chan, val, val2, mask);
351
+
iio_device_release_direct(indio_dev);
352
+
353
+
return ret;
354
+
}
355
+
356
+
static int
357
+
ads1018_read_avail(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
358
+
const int **vals, int *type, int *length, long mask)
359
+
{
360
+
struct ads1018 *ads1018 = iio_priv(indio_dev);
361
+
362
+
switch (mask) {
363
+
case IIO_CHAN_INFO_SCALE:
364
+
*type = IIO_VAL_INT_PLUS_NANO;
365
+
*vals = (const int *)ads1018->chip_info->pga_mode_to_gain;
366
+
*length = ADS1018_NUM_PGA_MODES * 2;
367
+
return IIO_AVAIL_LIST;
368
+
369
+
case IIO_CHAN_INFO_SAMP_FREQ:
370
+
*type = IIO_VAL_INT;
371
+
*vals = ads1018->chip_info->data_rate_mode_to_hz;
372
+
*length = ads1018->chip_info->num_data_rate_mode_to_hz;
373
+
return IIO_AVAIL_LIST;
374
+
375
+
default:
376
+
return -EOPNOTSUPP;
377
+
}
378
+
}
379
+
380
+
static int
381
+
ads1018_write_raw_direct_mode(struct iio_dev *indio_dev,
382
+
struct iio_chan_spec const *chan, int val, int val2,
383
+
long mask)
384
+
{
385
+
struct ads1018 *ads1018 = iio_priv(indio_dev);
386
+
const struct ads1018_chip_info *info = ads1018->chip_info;
387
+
unsigned int i;
388
+
389
+
switch (mask) {
390
+
case IIO_CHAN_INFO_SCALE:
391
+
for (i = 0; i < ADS1018_NUM_PGA_MODES; i++) {
392
+
if (val == info->pga_mode_to_gain[i][0] &&
393
+
val2 == info->pga_mode_to_gain[i][1])
394
+
break;
395
+
}
396
+
if (i == ADS1018_NUM_PGA_MODES)
397
+
return -EINVAL;
398
+
399
+
ads1018->chan_data[chan->scan_index].pga_mode = i;
400
+
return 0;
401
+
402
+
case IIO_CHAN_INFO_SAMP_FREQ:
403
+
for (i = 0; i < info->num_data_rate_mode_to_hz; i++) {
404
+
if (val == info->data_rate_mode_to_hz[i])
405
+
break;
406
+
}
407
+
if (i == info->num_data_rate_mode_to_hz)
408
+
return -EINVAL;
409
+
410
+
ads1018->chan_data[chan->scan_index].data_rate_mode = i;
411
+
return 0;
412
+
413
+
default:
414
+
return -EOPNOTSUPP;
415
+
}
416
+
}
417
+
418
+
static int
419
+
ads1018_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
420
+
int val, int val2, long mask)
421
+
{
422
+
int ret;
423
+
424
+
if (!iio_device_claim_direct(indio_dev))
425
+
return -EBUSY;
426
+
ret = ads1018_write_raw_direct_mode(indio_dev, chan, val, val2, mask);
427
+
iio_device_release_direct(indio_dev);
428
+
429
+
return ret;
430
+
}
431
+
432
+
static int
433
+
ads1018_write_raw_get_fmt(struct iio_dev *indio_dev,
434
+
struct iio_chan_spec const *chan, long mask)
435
+
{
436
+
switch (mask) {
437
+
case IIO_CHAN_INFO_SCALE:
438
+
return IIO_VAL_INT_PLUS_NANO;
439
+
default:
440
+
return IIO_VAL_INT_PLUS_MICRO;
441
+
}
442
+
}
443
+
444
+
static const struct iio_info ads1018_iio_info = {
445
+
.read_raw = ads1018_read_raw,
446
+
.read_avail = ads1018_read_avail,
447
+
.write_raw = ads1018_write_raw,
448
+
.write_raw_get_fmt = ads1018_write_raw_get_fmt,
449
+
};
450
+
451
+
static void ads1018_set_trigger_enable(struct ads1018 *ads1018)
452
+
{
453
+
spi_bus_lock(ads1018->spi->controller);
454
+
ads1018_spi_read_exclusive(ads1018, NULL, true);
455
+
enable_irq(ads1018->drdy_irq);
456
+
}
457
+
458
+
static void ads1018_set_trigger_disable(struct ads1018 *ads1018)
459
+
{
460
+
disable_irq(ads1018->drdy_irq);
461
+
ads1018_spi_read_exclusive(ads1018, NULL, false);
462
+
spi_bus_unlock(ads1018->spi->controller);
463
+
}
464
+
465
+
static int ads1018_set_trigger_state(struct iio_trigger *trig, bool state)
466
+
{
467
+
struct ads1018 *ads1018 = iio_trigger_get_drvdata(trig);
468
+
469
+
/*
470
+
* We need to lock the SPI bus and tie CS low (hold_cs) to catch
471
+
* data-ready interrupts, otherwise the MISO line enters a Hi-Z state.
472
+
*/
473
+
474
+
if (state)
475
+
ads1018_set_trigger_enable(ads1018);
476
+
else
477
+
ads1018_set_trigger_disable(ads1018);
478
+
479
+
return 0;
480
+
}
481
+
482
+
static const struct iio_trigger_ops ads1018_trigger_ops = {
483
+
.set_trigger_state = ads1018_set_trigger_state,
484
+
.validate_device = iio_trigger_validate_own_device,
485
+
};
486
+
487
+
static int ads1018_buffer_preenable(struct iio_dev *indio_dev)
488
+
{
489
+
struct ads1018 *ads1018 = iio_priv(indio_dev);
490
+
const struct ads1018_chip_info *chip_info = ads1018->chip_info;
491
+
unsigned int pga, drate, addr;
492
+
u16 cfg;
493
+
494
+
addr = find_first_bit(indio_dev->active_scan_mask,
495
+
iio_get_masklength(indio_dev));
496
+
pga = ads1018->chan_data[addr].pga_mode;
497
+
drate = ads1018->chan_data[addr].data_rate_mode;
498
+
499
+
cfg = ADS1018_CFG_VALID;
500
+
cfg |= FIELD_PREP(ADS1018_CFG_MUX_MASK, addr);
501
+
cfg |= FIELD_PREP(ADS1018_CFG_PGA_MASK, pga);
502
+
cfg |= FIELD_PREP(ADS1018_CFG_MODE_MASK, ADS1018_MODE_CONTINUOUS);
503
+
cfg |= FIELD_PREP(ADS1018_CFG_DRATE_MASK, drate);
504
+
505
+
if (chip_info->channels[addr].type == IIO_TEMP)
506
+
cfg |= ADS1018_CFG_TS_MODE_EN;
507
+
508
+
ads1018->tx_buf[0] = cpu_to_be16(cfg);
509
+
ads1018->tx_buf[1] = 0;
510
+
511
+
return spi_write(ads1018->spi, ads1018->tx_buf, sizeof(ads1018->tx_buf));
512
+
}
513
+
514
+
static int ads1018_buffer_postdisable(struct iio_dev *indio_dev)
515
+
{
516
+
struct ads1018 *ads1018 = iio_priv(indio_dev);
517
+
u16 cfg;
518
+
519
+
cfg = ADS1018_CFG_VALID;
520
+
cfg |= FIELD_PREP(ADS1018_CFG_MODE_MASK, ADS1018_MODE_ONESHOT);
521
+
522
+
ads1018->tx_buf[0] = cpu_to_be16(cfg);
523
+
ads1018->tx_buf[1] = 0;
524
+
525
+
return spi_write(ads1018->spi, ads1018->tx_buf, sizeof(ads1018->tx_buf));
526
+
}
527
+
528
+
static const struct iio_buffer_setup_ops ads1018_buffer_ops = {
529
+
.preenable = ads1018_buffer_preenable,
530
+
.postdisable = ads1018_buffer_postdisable,
531
+
.validate_scan_mask = iio_validate_scan_mask_onehot,
532
+
};
533
+
534
+
static irqreturn_t ads1018_irq_handler(int irq, void *dev_id)
535
+
{
536
+
struct ads1018 *ads1018 = dev_id;
537
+
538
+
/*
539
+
* We need to check if the "drdy" pin is actually active or if it's a
540
+
* pending interrupt triggered by the SPI transfer.
541
+
*/
542
+
if (!gpiod_get_value(ads1018->drdy_gpiod))
543
+
return IRQ_HANDLED;
544
+
545
+
iio_trigger_poll(ads1018->indio_trig);
546
+
547
+
return IRQ_HANDLED;
548
+
}
549
+
550
+
static irqreturn_t ads1018_trigger_handler(int irq, void *p)
551
+
{
552
+
struct iio_poll_func *pf = p;
553
+
struct iio_dev *indio_dev = pf->indio_dev;
554
+
struct ads1018 *ads1018 = iio_priv(indio_dev);
555
+
struct {
556
+
__be16 conv;
557
+
aligned_s64 ts;
558
+
} scan = {};
559
+
int ret;
560
+
561
+
if (iio_trigger_using_own(indio_dev)) {
562
+
disable_irq(ads1018->drdy_irq);
563
+
ret = ads1018_spi_read_exclusive(ads1018, &scan.conv, true);
564
+
enable_irq(ads1018->drdy_irq);
565
+
} else {
566
+
ret = spi_read(ads1018->spi, ads1018->rx_buf, sizeof(ads1018->rx_buf));
567
+
scan.conv = ads1018->rx_buf[0];
568
+
}
569
+
570
+
if (!ret)
571
+
iio_push_to_buffers_with_ts(indio_dev, &scan, sizeof(scan),
572
+
pf->timestamp);
573
+
574
+
iio_trigger_notify_done(indio_dev->trig);
575
+
576
+
return IRQ_HANDLED;
577
+
}
578
+
579
+
static int ads1018_trigger_setup(struct iio_dev *indio_dev)
580
+
{
581
+
struct ads1018 *ads1018 = iio_priv(indio_dev);
582
+
struct spi_device *spi = ads1018->spi;
583
+
struct device *dev = &spi->dev;
584
+
const char *con_id = "drdy";
585
+
int ret;
586
+
587
+
ads1018->drdy_gpiod = devm_gpiod_get_optional(dev, con_id, GPIOD_IN);
588
+
if (IS_ERR(ads1018->drdy_gpiod))
589
+
return dev_err_probe(dev, PTR_ERR(ads1018->drdy_gpiod),
590
+
"Failed to get %s GPIO.\n", con_id);
591
+
592
+
/* First try to get IRQ from SPI core, then from GPIO */
593
+
if (spi->irq > 0)
594
+
ads1018->drdy_irq = spi->irq;
595
+
else if (ads1018->drdy_gpiod)
596
+
ads1018->drdy_irq = gpiod_to_irq(ads1018->drdy_gpiod);
597
+
if (ads1018->drdy_irq < 0)
598
+
return dev_err_probe(dev, ads1018->drdy_irq,
599
+
"Failed to get IRQ from %s GPIO.\n", con_id);
600
+
601
+
/* An IRQ line is only an optional requirement for the IIO trigger */
602
+
if (ads1018->drdy_irq == 0)
603
+
return 0;
604
+
605
+
ads1018->indio_trig = devm_iio_trigger_alloc(dev, "%s-dev%d-%s",
606
+
indio_dev->name,
607
+
iio_device_id(indio_dev),
608
+
con_id);
609
+
if (!ads1018->indio_trig)
610
+
return -ENOMEM;
611
+
612
+
iio_trigger_set_drvdata(ads1018->indio_trig, ads1018);
613
+
ads1018->indio_trig->ops = &ads1018_trigger_ops;
614
+
615
+
ret = devm_iio_trigger_register(dev, ads1018->indio_trig);
616
+
if (ret)
617
+
return ret;
618
+
619
+
/*
620
+
* The "data-ready" IRQ line is shared with the MOSI pin, thus we need
621
+
* to keep it disabled until we actually request data.
622
+
*/
623
+
return devm_request_irq(dev, ads1018->drdy_irq, ads1018_irq_handler,
624
+
IRQF_NO_AUTOEN, ads1018->chip_info->name, ads1018);
625
+
}
626
+
627
+
static int ads1018_spi_probe(struct spi_device *spi)
628
+
{
629
+
const struct ads1018_chip_info *info = spi_get_device_match_data(spi);
630
+
struct device *dev = &spi->dev;
631
+
struct iio_dev *indio_dev;
632
+
struct ads1018 *ads1018;
633
+
int ret;
634
+
635
+
indio_dev = devm_iio_device_alloc(dev, sizeof(*ads1018));
636
+
if (!indio_dev)
637
+
return -ENOMEM;
638
+
639
+
ads1018 = iio_priv(indio_dev);
640
+
ads1018->spi = spi;
641
+
ads1018->chip_info = info;
642
+
643
+
indio_dev->modes = INDIO_DIRECT_MODE;
644
+
indio_dev->name = info->name;
645
+
indio_dev->info = &ads1018_iio_info;
646
+
indio_dev->channels = info->channels;
647
+
indio_dev->num_channels = info->num_channels;
648
+
649
+
for (unsigned int i = 0; i < ADS1018_CHANNELS_MAX; i++) {
650
+
ads1018->chan_data[i].data_rate_mode = ADS1018_DRATE_DEFAULT;
651
+
ads1018->chan_data[i].pga_mode = ADS1018_PGA_DEFAULT;
652
+
}
653
+
654
+
ads1018->xfer.rx_buf = ads1018->rx_buf;
655
+
ads1018->xfer.len = sizeof(ads1018->rx_buf);
656
+
spi_message_init_with_transfers(&ads1018->msg_read, &ads1018->xfer, 1);
657
+
658
+
ret = ads1018_trigger_setup(indio_dev);
659
+
if (ret)
660
+
return ret;
661
+
662
+
ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
663
+
iio_pollfunc_store_time,
664
+
ads1018_trigger_handler,
665
+
&ads1018_buffer_ops);
666
+
if (ret)
667
+
return ret;
668
+
669
+
return devm_iio_device_register(&spi->dev, indio_dev);
670
+
}
671
+
672
+
static const unsigned int ads1018_data_rate_table[] = {
673
+
128, 250, 490, 920, 1600, 2400, 3300,
674
+
};
675
+
676
+
static const unsigned int ads1118_data_rate_table[] = {
677
+
8, 16, 32, 64, 128, 250, 475, 860,
678
+
};
679
+
680
+
static const struct ads1018_chip_info ads1018_chip_info = {
681
+
.name = "ads1018",
682
+
.channels = ads1018_iio_channels,
683
+
.num_channels = ARRAY_SIZE(ads1018_iio_channels),
684
+
.data_rate_mode_to_hz = ads1018_data_rate_table,
685
+
.num_data_rate_mode_to_hz = ARRAY_SIZE(ads1018_data_rate_table),
686
+
.pga_mode_to_gain = {
687
+
{ 3, 0 }, /* fsr = 6144 mV */
688
+
{ 2, 0 }, /* fsr = 4096 mV */
689
+
{ 1, 0 }, /* fsr = 2048 mV */
690
+
{ 0, 500000000 }, /* fsr = 1024 mV */
691
+
{ 0, 250000000 }, /* fsr = 512 mV */
692
+
{ 0, 125000000 }, /* fsr = 256 mV */
693
+
},
694
+
.temp_scale = { 125, 0 },
695
+
};
696
+
697
+
static const struct ads1018_chip_info ads1118_chip_info = {
698
+
.name = "ads1118",
699
+
.channels = ads1118_iio_channels,
700
+
.num_channels = ARRAY_SIZE(ads1118_iio_channels),
701
+
.data_rate_mode_to_hz = ads1118_data_rate_table,
702
+
.num_data_rate_mode_to_hz = ARRAY_SIZE(ads1118_data_rate_table),
703
+
.pga_mode_to_gain = {
704
+
{ 0, 187500000 }, /* fsr = 6144 mV */
705
+
{ 0, 125000000 }, /* fsr = 4096 mV */
706
+
{ 0, 62500000 }, /* fsr = 2048 mV */
707
+
{ 0, 31250000 }, /* fsr = 1024 mV */
708
+
{ 0, 15625000 }, /* fsr = 512 mV */
709
+
{ 0, 7812500 }, /* fsr = 256 mV */
710
+
},
711
+
.temp_scale = { 31, 250000 },
712
+
};
713
+
714
+
static const struct of_device_id ads1018_of_match[] = {
715
+
{ .compatible = "ti,ads1018", .data = &ads1018_chip_info },
716
+
{ .compatible = "ti,ads1118", .data = &ads1118_chip_info },
717
+
{ }
718
+
};
719
+
MODULE_DEVICE_TABLE(of, ads1018_of_match);
720
+
721
+
static const struct spi_device_id ads1018_spi_match[] = {
722
+
{ "ads1018", (kernel_ulong_t)&ads1018_chip_info },
723
+
{ "ads1118", (kernel_ulong_t)&ads1118_chip_info },
724
+
{ }
725
+
};
726
+
MODULE_DEVICE_TABLE(spi, ads1018_spi_match);
727
+
728
+
static struct spi_driver ads1018_spi_driver = {
729
+
.driver = {
730
+
.name = "ads1018",
731
+
.of_match_table = ads1018_of_match,
732
+
},
733
+
.probe = ads1018_spi_probe,
734
+
.id_table = ads1018_spi_match,
735
+
};
736
+
module_spi_driver(ads1018_spi_driver);
737
+
738
+
MODULE_DESCRIPTION("Texas Instruments ADS1018 ADC Driver");
739
+
MODULE_LICENSE("GPL");
740
+
MODULE_AUTHOR("Kurt Borja <kuurtb@gmail.com>");