Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'riscv-for-linus-6.3-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull more RISC-V updates from Palmer Dabbelt:
- Some cleanups and fixes for the Zbb-optimized string routines
- Support for custom (vendor or implementation defined) perf events
- COMMAND_LINE_SIZE has been increased to 1024
* tag 'riscv-for-linus-6.3-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: Bump COMMAND_LINE_SIZE value to 1024
drivers/perf: RISC-V: Allow programming custom firmware events
riscv, lib: Fix Zbb strncmp
RISC-V: improve string-function assembly
+29
-22
+8
arch/riscv/include/uapi/asm/setup.h
+8
arch/riscv/include/uapi/asm/setup.h
+4
-2
arch/riscv/lib/strcmp.S
+4
-2
arch/riscv/lib/strcmp.S
···
40
40
ret
41
41
42
42
/*
43
-
* Variant of strcmp using the ZBB extension if available
43
+
* Variant of strcmp using the ZBB extension if available.
44
+
* The code was published as part of the bitmanip manual
45
+
* in Appendix A.
44
46
*/
45
47
#ifdef CONFIG_RISCV_ISA_ZBB
46
48
strcmp_zbb:
···
59
57
* a1 - string2
60
58
*
61
59
* Clobbers
62
-
* t0, t1, t2, t3, t4, t5
60
+
* t0, t1, t2, t3, t4
63
61
*/
64
62
65
63
or t2, a0, a1
+5
-5
arch/riscv/lib/strlen.S
+5
-5
arch/riscv/lib/strlen.S
···
96
96
* of valid bytes in this chunk.
97
97
*/
98
98
srli a0, t1, 3
99
-
bgtu t3, a0, 3f
99
+
bgtu t3, a0, 2f
100
100
101
101
/* Prepare for the word comparison loop. */
102
102
addi t2, t0, SZREG
···
112
112
addi t0, t0, SZREG
113
113
orc.b t1, t1
114
114
beq t1, t3, 1b
115
-
2:
115
+
116
116
not t1, t1
117
117
CZ t1, t1
118
+
srli t1, t1, 3
118
119
119
-
/* Get number of processed words. */
120
+
/* Get number of processed bytes. */
120
121
sub t2, t0, t2
121
122
122
123
/* Add number of characters in the first word. */
123
124
add a0, a0, t2
124
-
srli t1, t1, 3
125
125
126
126
/* Add number of characters in the last word. */
127
127
add a0, a0, t1
128
-
3:
128
+
2:
129
129
ret
130
130
131
131
.option pop
+10
-10
arch/riscv/lib/strncmp.S
+10
-10
arch/riscv/lib/strncmp.S
···
70
70
li t5, -1
71
71
and t2, t2, SZREG-1
72
72
add t4, a0, a2
73
-
bnez t2, 4f
73
+
bnez t2, 3f
74
74
75
75
/* Adjust limit for fast-path. */
76
76
andi t6, t4, -SZREG
···
78
78
/* Main loop for aligned string. */
79
79
.p2align 3
80
80
1:
81
-
bgt a0, t6, 3f
81
+
bge a0, t6, 3f
82
82
REG_L t0, 0(a0)
83
83
REG_L t1, 0(a1)
84
84
orc.b t3, t0
85
+
bne t3, t5, 2f
86
+
orc.b t3, t1
85
87
bne t3, t5, 2f
86
88
addi a0, a0, SZREG
87
89
addi a1, a1, SZREG
···
116
114
ret
117
115
118
116
/* Simple loop for misaligned strings. */
119
-
3:
120
-
/* Restore limit for slow-path. */
121
117
.p2align 3
122
-
4:
123
-
bge a0, t4, 6f
118
+
3:
119
+
bge a0, t4, 5f
124
120
lbu t0, 0(a0)
125
121
lbu t1, 0(a1)
126
122
addi a0, a0, 1
127
123
addi a1, a1, 1
128
-
bne t0, t1, 5f
129
-
bnez t0, 4b
124
+
bne t0, t1, 4f
125
+
bnez t0, 3b
130
126
131
-
5:
127
+
4:
132
128
sub a0, t0, t1
133
129
ret
134
130
135
-
6:
131
+
5:
136
132
li a0, 0
137
133
ret
138
134
+2
-5
drivers/perf/riscv_pmu_sbi.c
+2
-5
drivers/perf/riscv_pmu_sbi.c
···
436
436
bSoftware = config >> 63;
437
437
raw_config_val = config & RISCV_PMU_RAW_EVENT_MASK;
438
438
if (bSoftware) {
439
-
if (raw_config_val < SBI_PMU_FW_MAX)
440
-
ret = (raw_config_val & 0xFFFF) |
441
-
(SBI_PMU_EVENT_TYPE_FW << 16);
442
-
else
443
-
return -EINVAL;
439
+
ret = (raw_config_val & 0xFFFF) |
440
+
(SBI_PMU_EVENT_TYPE_FW << 16);
444
441
} else {
445
442
ret = RISCV_PMU_RAW_EVENT_IDX;
446
443
*econfig = raw_config_val;