tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'mips_fixes_5.0_4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS fixes from Paul Burton:
"A few more MIPS fixes:

- Fix 16b cmpxchg() operations which could erroneously fail if bits
15:8 of the old value are non-zero. In practice I'm not aware of
any actual users of 16b cmpxchg() on MIPS, but this fixes the
support for it was was introduced in v4.13.

- Provide a struct device to dma_alloc_coherent for Lantiq XWAY
systems with a "Voice MIPS Macro Core" (VMMC) device.

- Provide DMA masks for BCM63xx ethernet devices, fixing a regression
introduced in v4.19.

- Fix memblock reservation for the kernel when the system has a
non-zero PHYS_OFFSET, correcting the memblock conversion performed
in v4.20"

* tag 'mips_fixes_5.0_4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
MIPS: fix memory setup for platforms with PHYS_OFFSET != 0
MIPS: BCM63XX: provide DMA masks for ethernet devices
MIPS: lantiq: pass struct device to DMA API functions
MIPS: fix truncation in __cmpxchg_small for short values

Linus Torvalds bf23aba1 3eb07d20

+13 -5
+8
arch/mips/bcm63xx/dev-enet.c
··· 70 70 71 71 static int shared_device_registered; 72 72 73 + static u64 enet_dmamask = DMA_BIT_MASK(32); 74 + 73 75 static struct resource enet0_res[] = { 74 76 { 75 77 .start = -1, /* filled at runtime */ ··· 101 99 .resource = enet0_res, 102 100 .dev = { 103 101 .platform_data = &enet0_pd, 102 + .dma_mask = &enet_dmamask, 103 + .coherent_dma_mask = DMA_BIT_MASK(32), 104 104 }, 105 105 }; 106 106 ··· 135 131 .resource = enet1_res, 136 132 .dev = { 137 133 .platform_data = &enet1_pd, 134 + .dma_mask = &enet_dmamask, 135 + .coherent_dma_mask = DMA_BIT_MASK(32), 138 136 }, 139 137 }; 140 138 ··· 163 157 .resource = enetsw_res, 164 158 .dev = { 165 159 .platform_data = &enetsw_pd, 160 + .dma_mask = &enet_dmamask, 161 + .coherent_dma_mask = DMA_BIT_MASK(32), 166 162 }, 167 163 }; 168 164
+1 -2
arch/mips/kernel/cmpxchg.c
··· 54 54 unsigned long __cmpxchg_small(volatile void *ptr, unsigned long old, 55 55 unsigned long new, unsigned int size) 56 56 { 57 - u32 mask, old32, new32, load32; 57 + u32 mask, old32, new32, load32, load; 58 58 volatile u32 *ptr32; 59 59 unsigned int shift; 60 - u8 load; 61 60 62 61 /* Check that ptr is naturally aligned */ 63 62 WARN_ON((unsigned long)ptr & (size - 1));
+2 -1
arch/mips/kernel/setup.c
··· 384 384 init_initrd(); 385 385 reserved_end = (unsigned long) PFN_UP(__pa_symbol(&_end)); 386 386 387 - memblock_reserve(PHYS_OFFSET, reserved_end << PAGE_SHIFT); 387 + memblock_reserve(PHYS_OFFSET, 388 + (reserved_end << PAGE_SHIFT) - PHYS_OFFSET); 388 389 389 390 /* 390 391 * max_low_pfn is not a number of pages. The number of pages
+2 -2
arch/mips/lantiq/xway/vmmc.c
··· 31 31 dma_addr_t dma; 32 32 33 33 cp1_base = 34 - (void *) CPHYSADDR(dma_alloc_coherent(NULL, CP1_SIZE, 35 - &dma, GFP_ATOMIC)); 34 + (void *) CPHYSADDR(dma_alloc_coherent(&pdev->dev, CP1_SIZE, 35 + &dma, GFP_KERNEL)); 36 36 37 37 gpio_count = of_gpio_count(pdev->dev.of_node); 38 38 while (gpio_count > 0) {