Merge tag 'devicetree-for-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

+145 -87

Documentation/devicetree/bindings/arm/cpus.yaml

··· 10 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 11 11 12 12 description: |+ 13 - The device tree allows to describe the layout of CPUs in a system through 14 - the "cpus" node, which in turn contains a number of subnodes (ie "cpu") 15 - defining properties for every cpu. 13 + The device tree allows to describe the layout of CPUs in a system through the 14 + "cpus" node, which in turn contains a number of subnodes (ie "cpu") defining 15 + properties for every cpu. 16 16 17 17 Bindings for CPU nodes follow the Devicetree Specification, available from: 18 18 ··· 41 41 properties: 42 42 reg: 43 43 maxItems: 1 44 - description: | 45 - Usage and definition depend on ARM architecture version and 46 - configuration: 44 + description: > 45 + Usage and definition depend on ARM architecture version and configuration: 47 46 48 - On uniprocessor ARM architectures previous to v7 49 - this property is required and must be set to 0. 47 + On uniprocessor ARM architectures previous to v7 this property is required 48 + and must be set to 0. 50 49 51 - On ARM 11 MPcore based systems this property is 52 - required and matches the CPUID[11:0] register bits. 50 + On ARM 11 MPcore based systems this property is required and matches the 51 + CPUID[11:0] register bits. 53 52 54 - Bits [11:0] in the reg cell must be set to 55 - bits [11:0] in CPU ID register. 53 + Bits [11:0] in the reg cell must be set to bits [11:0] in CPU ID register. 56 54 57 55 All other bits in the reg cell must be set to 0. 58 56 59 - On 32-bit ARM v7 or later systems this property is 60 - required and matches the CPU MPIDR[23:0] register 61 - bits. 57 + On 32-bit ARM v7 or later systems this property is required and matches 58 + the CPU MPIDR[23:0] register bits. 62 59 63 - Bits [23:0] in the reg cell must be set to 64 - bits [23:0] in MPIDR. 60 + Bits [23:0] in the reg cell must be set to bits [23:0] in MPIDR. 65 61 66 62 All other bits in the reg cell must be set to 0. 67 63 68 - On ARM v8 64-bit systems this property is required 69 - and matches the MPIDR_EL1 register affinity bits. 64 + On ARM v8 64-bit systems this property is required and matches the 65 + MPIDR_EL1 register affinity bits. 70 66 71 67 * If cpus node's #address-cells property is set to 2 72 68 73 - The first reg cell bits [7:0] must be set to 74 - bits [39:32] of MPIDR_EL1. 69 + The first reg cell bits [7:0] must be set to bits [39:32] of 70 + MPIDR_EL1. 75 71 76 - The second reg cell bits [23:0] must be set to 77 - bits [23:0] of MPIDR_EL1. 72 + The second reg cell bits [23:0] must be set to bits [23:0] of 73 + MPIDR_EL1. 78 74 79 75 * If cpus node's #address-cells property is set to 1 80 76 81 - The reg cell bits [23:0] must be set to bits [23:0] 82 - of MPIDR_EL1. 77 + The reg cell bits [23:0] must be set to bits [23:0] of MPIDR_EL1. 83 78 84 79 All other bits in the reg cells must be set to 0. 85 80 ··· 268 273 description: 269 274 The DT specification defines this as 64-bit always, but some 32-bit Arm 270 275 systems have used a 32-bit value which must be supported. 271 - Required for systems that have an "enable-method" 272 - property value of "spin-table". 273 276 274 277 cpu-idle-states: 275 278 $ref: /schemas/types.yaml#/definitions/phandle-array 276 279 items: 277 280 maxItems: 1 278 - description: | 279 - List of phandles to idle state nodes supported 280 - by this cpu (see ./idle-states.yaml). 281 + description: 282 + List of phandles to idle state nodes supported by this cpu (see 283 + ./idle-states.yaml). 281 284 282 285 capacity-dmips-mhz: 283 286 description: 284 287 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in 285 - DMIPS/MHz, relative to highest capacity-dmips-mhz 286 - in the system. 288 + DMIPS/MHz, relative to highest capacity-dmips-mhz in the system. 287 289 288 290 cci-control-port: true 289 291 290 292 dynamic-power-coefficient: 291 293 $ref: /schemas/types.yaml#/definitions/uint32 292 - description: 293 - A u32 value that represents the running time dynamic 294 - power coefficient in units of uW/MHz/V^2. The 295 - coefficient can either be calculated from power 294 + description: > 295 + A u32 value that represents the running time dynamic power coefficient in 296 + units of uW/MHz/V^2. The coefficient can either be calculated from power 296 297 measurements or derived by analysis. 297 298 298 - The dynamic power consumption of the CPU is 299 - proportional to the square of the Voltage (V) and 300 - the clock frequency (f). The coefficient is used to 299 + The dynamic power consumption of the CPU is proportional to the square of 300 + the Voltage (V) and the clock frequency (f). The coefficient is used to 301 301 calculate the dynamic power as below - 302 302 303 303 Pdyn = dynamic-power-coefficient * V^2 * f 304 304 305 305 where voltage is in V, frequency is in MHz. 306 306 307 + interconnects: 308 + minItems: 1 309 + maxItems: 3 310 + 311 + nvmem-cells: 312 + maxItems: 1 313 + 314 + nvmem-cell-names: 315 + const: speed_grade 316 + 307 317 performance-domains: 308 318 maxItems: 1 309 - description: 310 - List of phandles and performance domain specifiers, as defined by 311 - bindings of the performance domain provider. See also 312 - dvfs/performance-domain.yaml. 313 319 314 320 power-domains: 315 - description: 316 - List of phandles and PM domain specifiers, as defined by bindings of the 317 - PM domain provider (see also ../power_domain.txt). 321 + minItems: 1 322 + maxItems: 2 318 323 319 324 power-domain-names: 320 325 description: 321 - A list of power domain name strings sorted in the same order as the 322 - power-domains property. 323 - 324 326 For PSCI based platforms, the name corresponding to the index of the PSCI 325 327 PM domain provider, must be "psci". For SCMI based platforms, the name 326 328 corresponding to the index of an SCMI performance domain provider, must be 327 329 "perf". 330 + minItems: 1 331 + maxItems: 2 332 + items: 333 + enum: [ psci, perf, cpr ] 334 + 335 + resets: 336 + maxItems: 1 337 + 338 + arm-supply: 339 + deprecated: true 340 + description: Use 'cpu-supply' instead 341 + 342 + cpu0-supply: 343 + deprecated: true 344 + description: Use 'cpu-supply' instead 345 + 346 + mem-supply: true 347 + 348 + proc-supply: 349 + deprecated: true 350 + description: Use 'cpu-supply' instead 351 + 352 + sram-supply: 353 + deprecated: true 354 + description: Use 'mem-supply' instead 355 + 356 + mediatek,cci: 357 + $ref: /schemas/types.yaml#/definitions/phandle 358 + description: Link to Mediatek Cache Coherent Interconnect 328 359 329 360 qcom,saw: 330 361 $ref: /schemas/types.yaml#/definitions/phandle 331 - description: | 332 - Specifies the SAW* node associated with this CPU. 333 - 334 - Required for systems that have an "enable-method" property 335 - value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2" 336 - 337 - * arm/msm/qcom,saw2.txt 362 + description: 363 + Specifies the SAW node associated with this CPU. 338 364 339 365 qcom,acc: 340 366 $ref: /schemas/types.yaml#/definitions/phandle 341 - description: | 342 - Specifies the ACC* node associated with this CPU. 367 + description: 368 + Specifies the ACC node associated with this CPU. 343 369 344 - Required for systems that have an "enable-method" property 345 - value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or 346 - "qcom,msm8916-smp". 347 - 348 - * arm/msm/qcom,kpss-acc.txt 370 + qcom,freq-domain: 371 + description: Specifies the QCom CPUFREQ HW associated with the CPU. 372 + $ref: /schemas/types.yaml#/definitions/phandle-array 373 + maxItems: 1 349 374 350 375 rockchip,pmu: 351 376 $ref: /schemas/types.yaml#/definitions/phandle 352 - description: | 377 + description: > 353 378 Specifies the syscon node controlling the cpu core power domains. 354 379 355 - Optional for systems that have an "enable-method" 356 - property value of "rockchip,rk3066-smp" 357 - While optional, it is the preferred way to get access to 358 - the cpu-core power-domains. 380 + Optional for systems that have an "enable-method" property value of 381 + "rockchip,rk3066-smp". While optional, it is the preferred way to get 382 + access to the cpu-core power-domains. 359 383 360 384 secondary-boot-reg: 361 385 $ref: /schemas/types.yaml#/definitions/uint32 362 - description: | 386 + description: > 363 387 Required for systems that have an "enable-method" property value of 364 388 "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp". 365 389 366 - This includes the following SoCs: | 367 - BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550 390 + This includes the following SoCs: 391 + BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550, 368 392 BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 369 393 370 394 The secondary-boot-reg property is a u32 value that specifies the ··· 392 378 formed by encoding the target CPU id into the low bits of the 393 379 physical start address it should jump to. 394 380 395 - if: 396 - # If the enable-method property contains one of those values 397 - properties: 398 - enable-method: 399 - contains: 400 - enum: 401 - - brcm,bcm11351-cpu-method 402 - - brcm,bcm23550 403 - - brcm,bcm-nsp-smp 404 - # and if enable-method is present 405 - required: 406 - - enable-method 381 + thermal-idle: 382 + type: object 407 383 408 - then: 409 - required: 410 - - secondary-boot-reg 384 + allOf: 385 + - $ref: /schemas/cpu.yaml# 386 + - $ref: /schemas/opp/opp-v1.yaml# 387 + - if: 388 + # If the enable-method property contains one of those values 389 + properties: 390 + enable-method: 391 + contains: 392 + enum: 393 + - brcm,bcm11351-cpu-method 394 + - brcm,bcm23550 395 + - brcm,bcm-nsp-smp 396 + # and if enable-method is present 397 + required: 398 + - enable-method 399 + then: 400 + required: 401 + - secondary-boot-reg 402 + - if: 403 + properties: 404 + enable-method: 405 + enum: 406 + - spin-table 407 + - renesas,r9a06g032-smp 408 + required: 409 + - enable-method 410 + then: 411 + required: 412 + - cpu-release-addr 413 + - if: 414 + properties: 415 + enable-method: 416 + enum: 417 + - qcom,kpss-acc-v1 418 + - qcom,kpss-acc-v2 419 + - qcom,msm8226-smp 420 + - qcom,msm8916-smp 421 + required: 422 + - enable-method 423 + then: 424 + required: 425 + - qcom,acc 426 + - qcom,saw 427 + else: 428 + if: 429 + # 2 Qualcomm platforms bootloaders need qcom,acc and qcom,saw yet use 430 + # "spin-table" or "psci" enable-methods. Disallowing the properties for 431 + # all other CPUs is the best we can do as there's not any way to 432 + # distinguish these Qualcomm platforms. 433 + not: 434 + properties: 435 + compatible: 436 + const: arm,cortex-a53 437 + then: 438 + properties: 439 + qcom,acc: false 440 + qcom,saw: false 411 441 412 442 required: 413 443 - device_type ··· 461 403 dependencies: 462 404 rockchip,pmu: [enable-method] 463 405 464 - additionalProperties: true 406 + unevaluatedProperties: false 465 407 466 408 examples: 467 409 - |

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Documentation/devicetree/bindings/arm/freescale/fsl,imx51-m4if.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/arm/freescale/fsl,imx51-m4if.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Freescale Multi Master Multi Memory Interface (M4IF) and Tigerp module 8 + 9 + description: collect the imx devices, which only have compatible and reg property 10 + 11 + maintainers: 12 + - Frank Li <Frank.Li@nxp.com> 13 + 14 + properties: 15 + compatible: 16 + oneOf: 17 + - enum: 18 + - fsl,imx51-m4if 19 + - fsl,imx51-tigerp 20 + - fsl,imx51-aipstz 21 + - fsl,imx53-aipstz 22 + - fsl,imx7d-pcie-phy 23 + - items: 24 + - const: fsl,imx53-tigerp 25 + - const: fsl,imx51-tigerp 26 + 27 + reg: 28 + maxItems: 1 29 + 30 + required: 31 + - compatible 32 + - reg 33 + 34 + additionalProperties: false 35 + 36 + examples: 37 + - | 38 + m4if@83fd8000 { 39 + compatible = "fsl,imx51-m4if"; 40 + reg = <0x83fd8000 0x1000>; 41 + };

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Documentation/devicetree/bindings/arm/freescale/m4if.txt

··· 1 - * Freescale Multi Master Multi Memory Interface (M4IF) module 2 - 3 - Required properties: 4 - - compatible : Should be "fsl,imx51-m4if" 5 - - reg : Address and length of the register set for the device 6 - 7 - Example: 8 - 9 - m4if: m4if@83fd8000 { 10 - compatible = "fsl,imx51-m4if"; 11 - reg = <0x83fd8000 0x1000>; 12 - };

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Documentation/devicetree/bindings/arm/freescale/tigerp.txt

··· 1 - * Freescale Tigerp platform module 2 - 3 - Required properties: 4 - - compatible : Should be "fsl,imx51-tigerp" 5 - - reg : Address and length of the register set for the device 6 - 7 - Example: 8 - 9 - tigerp: tigerp@83fa0000 { 10 - compatible = "fsl,imx51-tigerp"; 11 - reg = <0x83fa0000 0x28>; 12 - };

+15 -15

Documentation/devicetree/bindings/arm/psci.yaml

··· 191 191 #size-cells = <0>; 192 192 #address-cells = <1>; 193 193 194 - CPU0: cpu@0 { 194 + cpu@0 { 195 195 device_type = "cpu"; 196 196 compatible = "arm,cortex-a53"; 197 197 reg = <0x0>; 198 198 enable-method = "psci"; 199 - power-domains = <&CPU_PD0>; 199 + power-domains = <&cpu_pd0>; 200 200 power-domain-names = "psci"; 201 201 }; 202 202 203 - CPU1: cpu@1 { 203 + cpu@1 { 204 204 device_type = "cpu"; 205 205 compatible = "arm,cortex-a53"; 206 206 reg = <0x100>; 207 207 enable-method = "psci"; 208 - power-domains = <&CPU_PD1>; 208 + power-domains = <&cpu_pd1>; 209 209 power-domain-names = "psci"; 210 210 }; 211 211 212 212 idle-states { 213 213 214 - CPU_PWRDN: cpu-power-down { 214 + cpu_pwrdn: cpu-power-down { 215 215 compatible = "arm,idle-state"; 216 216 arm,psci-suspend-param = <0x0000001>; 217 217 entry-latency-us = <10>; ··· 222 222 223 223 domain-idle-states { 224 224 225 - CLUSTER_RET: cluster-retention { 225 + cluster_ret: cluster-retention { 226 226 compatible = "domain-idle-state"; 227 227 arm,psci-suspend-param = <0x1000011>; 228 228 entry-latency-us = <500>; ··· 230 230 min-residency-us = <2000>; 231 231 }; 232 232 233 - CLUSTER_PWRDN: cluster-power-down { 233 + cluster_pwrdn: cluster-power-down { 234 234 compatible = "domain-idle-state"; 235 235 arm,psci-suspend-param = <0x1000031>; 236 236 entry-latency-us = <2000>; ··· 244 244 compatible = "arm,psci-1.0"; 245 245 method = "smc"; 246 246 247 - CPU_PD0: power-domain-cpu0 { 247 + cpu_pd0: power-domain-cpu0 { 248 248 #power-domain-cells = <0>; 249 - domain-idle-states = <&CPU_PWRDN>; 250 - power-domains = <&CLUSTER_PD>; 249 + domain-idle-states = <&cpu_pwrdn>; 250 + power-domains = <&cluster_pd>; 251 251 }; 252 252 253 - CPU_PD1: power-domain-cpu1 { 253 + cpu_pd1: power-domain-cpu1 { 254 254 #power-domain-cells = <0>; 255 - domain-idle-states = <&CPU_PWRDN>; 256 - power-domains = <&CLUSTER_PD>; 255 + domain-idle-states = <&cpu_pwrdn>; 256 + power-domains = <&cluster_pd>; 257 257 }; 258 258 259 - CLUSTER_PD: power-domain-cluster { 259 + cluster_pd: power-domain-cluster { 260 260 #power-domain-cells = <0>; 261 - domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; 261 + domain-idle-states = <&cluster_ret>, <&cluster_pwrdn>; 262 262 }; 263 263 }; 264 264 ...

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Documentation/devicetree/bindings/counter/fsl,ftm-quaddec.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/counter/fsl,ftm-quaddec.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: FlexTimer Quadrature decoder counter 8 + 9 + description: 10 + Exposes a simple counter for the quadrature decoder mode. 11 + 12 + maintainers: 13 + - Frank Li <Frank.li@nxp.com> 14 + 15 + properties: 16 + compatible: 17 + const: fsl,ftm-quaddec 18 + 19 + reg: 20 + maxItems: 1 21 + 22 + big-endian: true 23 + 24 + required: 25 + - compatible 26 + - reg 27 + 28 + additionalProperties: false 29 + 30 + examples: 31 + - | 32 + counter@29d0000 { 33 + compatible = "fsl,ftm-quaddec"; 34 + reg = <0x29d0000 0x10000>; 35 + big-endian; 36 + };

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Documentation/devicetree/bindings/counter/ftm-quaddec.txt

··· 1 - FlexTimer Quadrature decoder counter 2 - 3 - This driver exposes a simple counter for the quadrature decoder mode. 4 - 5 - Required properties: 6 - - compatible: Must be "fsl,ftm-quaddec". 7 - - reg: Must be set to the memory region of the flextimer. 8 - 9 - Optional property: 10 - - big-endian: Access the device registers in big-endian mode. 11 - 12 - Example: 13 - counter0: counter@29d0000 { 14 - compatible = "fsl,ftm-quaddec"; 15 - reg = <0x0 0x29d0000 0x0 0x10000>; 16 - big-endian; 17 - status = "disabled"; 18 - };

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Documentation/devicetree/bindings/cpu/cpu-topology.txt

··· 1 - =========================================== 2 - CPU topology binding description 3 - =========================================== 4 - 5 - =========================================== 6 - 1 - Introduction 7 - =========================================== 8 - 9 - In a SMP system, the hierarchy of CPUs is defined through three entities that 10 - are used to describe the layout of physical CPUs in the system: 11 - 12 - - socket 13 - - cluster 14 - - core 15 - - thread 16 - 17 - The bottom hierarchy level sits at core or thread level depending on whether 18 - symmetric multi-threading (SMT) is supported or not. 19 - 20 - For instance in a system where CPUs support SMT, "cpu" nodes represent all 21 - threads existing in the system and map to the hierarchy level "thread" above. 22 - In systems where SMT is not supported "cpu" nodes represent all cores present 23 - in the system and map to the hierarchy level "core" above. 24 - 25 - CPU topology bindings allow one to associate cpu nodes with hierarchical groups 26 - corresponding to the system hierarchy; syntactically they are defined as device 27 - tree nodes. 28 - 29 - Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be 30 - used for any other architecture as well. 31 - 32 - The cpu nodes, as per bindings defined in [4], represent the devices that 33 - correspond to physical CPUs and are to be mapped to the hierarchy levels. 34 - 35 - A topology description containing phandles to cpu nodes that are not compliant 36 - with bindings standardized in [4] is therefore considered invalid. 37 - 38 - =========================================== 39 - 2 - cpu-map node 40 - =========================================== 41 - 42 - The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct 43 - child of the cpus node and provides a container where the actual topology 44 - nodes are listed. 45 - 46 - - cpu-map node 47 - 48 - Usage: Optional - On SMP systems provide CPUs topology to the OS. 49 - Uniprocessor systems do not require a topology 50 - description and therefore should not define a 51 - cpu-map node. 52 - 53 - Description: The cpu-map node is just a container node where its 54 - subnodes describe the CPU topology. 55 - 56 - Node name must be "cpu-map". 57 - 58 - The cpu-map node's parent node must be the cpus node. 59 - 60 - The cpu-map node's child nodes can be: 61 - 62 - - one or more cluster nodes or 63 - - one or more socket nodes in a multi-socket system 64 - 65 - Any other configuration is considered invalid. 66 - 67 - The cpu-map node can only contain 4 types of child nodes: 68 - 69 - - socket node 70 - - cluster node 71 - - core node 72 - - thread node 73 - 74 - whose bindings are described in paragraph 3. 75 - 76 - The nodes describing the CPU topology (socket/cluster/core/thread) can 77 - only be defined within the cpu-map node and every core/thread in the 78 - system must be defined within the topology. Any other configuration is 79 - invalid and therefore must be ignored. 80 - 81 - =========================================== 82 - 2.1 - cpu-map child nodes naming convention 83 - =========================================== 84 - 85 - cpu-map child nodes must follow a naming convention where the node name 86 - must be "socketN", "clusterN", "coreN", "threadN" depending on the node type 87 - (ie socket/cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes 88 - which are siblings within a single common parent node must be given a unique and 89 - sequential N value, starting from 0). 90 - cpu-map child nodes which do not share a common parent node can have the same 91 - name (ie same number N as other cpu-map child nodes at different device tree 92 - levels) since name uniqueness will be guaranteed by the device tree hierarchy. 93 - 94 - =========================================== 95 - 3 - socket/cluster/core/thread node bindings 96 - =========================================== 97 - 98 - Bindings for socket/cluster/cpu/thread nodes are defined as follows: 99 - 100 - - socket node 101 - 102 - Description: must be declared within a cpu-map node, one node 103 - per physical socket in the system. A system can 104 - contain single or multiple physical socket. 105 - The association of sockets and NUMA nodes is beyond 106 - the scope of this bindings, please refer [2] for 107 - NUMA bindings. 108 - 109 - This node is optional for a single socket system. 110 - 111 - The socket node name must be "socketN" as described in 2.1 above. 112 - A socket node can not be a leaf node. 113 - 114 - A socket node's child nodes must be one or more cluster nodes. 115 - 116 - Any other configuration is considered invalid. 117 - 118 - - cluster node 119 - 120 - Description: must be declared within a cpu-map node, one node 121 - per cluster. A system can contain several layers of 122 - clustering within a single physical socket and cluster 123 - nodes can be contained in parent cluster nodes. 124 - 125 - The cluster node name must be "clusterN" as described in 2.1 above. 126 - A cluster node can not be a leaf node. 127 - 128 - A cluster node's child nodes must be: 129 - 130 - - one or more cluster nodes; or 131 - - one or more core nodes 132 - 133 - Any other configuration is considered invalid. 134 - 135 - - core node 136 - 137 - Description: must be declared in a cluster node, one node per core in 138 - the cluster. If the system does not support SMT, core 139 - nodes are leaf nodes, otherwise they become containers of 140 - thread nodes. 141 - 142 - The core node name must be "coreN" as described in 2.1 above. 143 - 144 - A core node must be a leaf node if SMT is not supported. 145 - 146 - Properties for core nodes that are leaf nodes: 147 - 148 - - cpu 149 - Usage: required 150 - Value type: <phandle> 151 - Definition: a phandle to the cpu node that corresponds to the 152 - core node. 153 - 154 - If a core node is not a leaf node (CPUs supporting SMT) a core node's 155 - child nodes can be: 156 - 157 - - one or more thread nodes 158 - 159 - Any other configuration is considered invalid. 160 - 161 - - thread node 162 - 163 - Description: must be declared in a core node, one node per thread 164 - in the core if the system supports SMT. Thread nodes are 165 - always leaf nodes in the device tree. 166 - 167 - The thread node name must be "threadN" as described in 2.1 above. 168 - 169 - A thread node must be a leaf node. 170 - 171 - A thread node must contain the following property: 172 - 173 - - cpu 174 - Usage: required 175 - Value type: <phandle> 176 - Definition: a phandle to the cpu node that corresponds to 177 - the thread node. 178 - 179 - =========================================== 180 - 4 - Example dts 181 - =========================================== 182 - 183 - Example 1 (ARM 64-bit, 16-cpu system, two clusters of clusters in a single 184 - physical socket): 185 - 186 - cpus { 187 - #size-cells = <0>; 188 - #address-cells = <2>; 189 - 190 - cpu-map { 191 - socket0 { 192 - cluster0 { 193 - cluster0 { 194 - core0 { 195 - thread0 { 196 - cpu = <&CPU0>; 197 - }; 198 - thread1 { 199 - cpu = <&CPU1>; 200 - }; 201 - }; 202 - 203 - core1 { 204 - thread0 { 205 - cpu = <&CPU2>; 206 - }; 207 - thread1 { 208 - cpu = <&CPU3>; 209 - }; 210 - }; 211 - }; 212 - 213 - cluster1 { 214 - core0 { 215 - thread0 { 216 - cpu = <&CPU4>; 217 - }; 218 - thread1 { 219 - cpu = <&CPU5>; 220 - }; 221 - }; 222 - 223 - core1 { 224 - thread0 { 225 - cpu = <&CPU6>; 226 - }; 227 - thread1 { 228 - cpu = <&CPU7>; 229 - }; 230 - }; 231 - }; 232 - }; 233 - 234 - cluster1 { 235 - cluster0 { 236 - core0 { 237 - thread0 { 238 - cpu = <&CPU8>; 239 - }; 240 - thread1 { 241 - cpu = <&CPU9>; 242 - }; 243 - }; 244 - core1 { 245 - thread0 { 246 - cpu = <&CPU10>; 247 - }; 248 - thread1 { 249 - cpu = <&CPU11>; 250 - }; 251 - }; 252 - }; 253 - 254 - cluster1 { 255 - core0 { 256 - thread0 { 257 - cpu = <&CPU12>; 258 - }; 259 - thread1 { 260 - cpu = <&CPU13>; 261 - }; 262 - }; 263 - core1 { 264 - thread0 { 265 - cpu = <&CPU14>; 266 - }; 267 - thread1 { 268 - cpu = <&CPU15>; 269 - }; 270 - }; 271 - }; 272 - }; 273 - }; 274 - }; 275 - 276 - CPU0: cpu@0 { 277 - device_type = "cpu"; 278 - compatible = "arm,cortex-a57"; 279 - reg = <0x0 0x0>; 280 - enable-method = "spin-table"; 281 - cpu-release-addr = <0 0x20000000>; 282 - }; 283 - 284 - CPU1: cpu@1 { 285 - device_type = "cpu"; 286 - compatible = "arm,cortex-a57"; 287 - reg = <0x0 0x1>; 288 - enable-method = "spin-table"; 289 - cpu-release-addr = <0 0x20000000>; 290 - }; 291 - 292 - CPU2: cpu@100 { 293 - device_type = "cpu"; 294 - compatible = "arm,cortex-a57"; 295 - reg = <0x0 0x100>; 296 - enable-method = "spin-table"; 297 - cpu-release-addr = <0 0x20000000>; 298 - }; 299 - 300 - CPU3: cpu@101 { 301 - device_type = "cpu"; 302 - compatible = "arm,cortex-a57"; 303 - reg = <0x0 0x101>; 304 - enable-method = "spin-table"; 305 - cpu-release-addr = <0 0x20000000>; 306 - }; 307 - 308 - CPU4: cpu@10000 { 309 - device_type = "cpu"; 310 - compatible = "arm,cortex-a57"; 311 - reg = <0x0 0x10000>; 312 - enable-method = "spin-table"; 313 - cpu-release-addr = <0 0x20000000>; 314 - }; 315 - 316 - CPU5: cpu@10001 { 317 - device_type = "cpu"; 318 - compatible = "arm,cortex-a57"; 319 - reg = <0x0 0x10001>; 320 - enable-method = "spin-table"; 321 - cpu-release-addr = <0 0x20000000>; 322 - }; 323 - 324 - CPU6: cpu@10100 { 325 - device_type = "cpu"; 326 - compatible = "arm,cortex-a57"; 327 - reg = <0x0 0x10100>; 328 - enable-method = "spin-table"; 329 - cpu-release-addr = <0 0x20000000>; 330 - }; 331 - 332 - CPU7: cpu@10101 { 333 - device_type = "cpu"; 334 - compatible = "arm,cortex-a57"; 335 - reg = <0x0 0x10101>; 336 - enable-method = "spin-table"; 337 - cpu-release-addr = <0 0x20000000>; 338 - }; 339 - 340 - CPU8: cpu@100000000 { 341 - device_type = "cpu"; 342 - compatible = "arm,cortex-a57"; 343 - reg = <0x1 0x0>; 344 - enable-method = "spin-table"; 345 - cpu-release-addr = <0 0x20000000>; 346 - }; 347 - 348 - CPU9: cpu@100000001 { 349 - device_type = "cpu"; 350 - compatible = "arm,cortex-a57"; 351 - reg = <0x1 0x1>; 352 - enable-method = "spin-table"; 353 - cpu-release-addr = <0 0x20000000>; 354 - }; 355 - 356 - CPU10: cpu@100000100 { 357 - device_type = "cpu"; 358 - compatible = "arm,cortex-a57"; 359 - reg = <0x1 0x100>; 360 - enable-method = "spin-table"; 361 - cpu-release-addr = <0 0x20000000>; 362 - }; 363 - 364 - CPU11: cpu@100000101 { 365 - device_type = "cpu"; 366 - compatible = "arm,cortex-a57"; 367 - reg = <0x1 0x101>; 368 - enable-method = "spin-table"; 369 - cpu-release-addr = <0 0x20000000>; 370 - }; 371 - 372 - CPU12: cpu@100010000 { 373 - device_type = "cpu"; 374 - compatible = "arm,cortex-a57"; 375 - reg = <0x1 0x10000>; 376 - enable-method = "spin-table"; 377 - cpu-release-addr = <0 0x20000000>; 378 - }; 379 - 380 - CPU13: cpu@100010001 { 381 - device_type = "cpu"; 382 - compatible = "arm,cortex-a57"; 383 - reg = <0x1 0x10001>; 384 - enable-method = "spin-table"; 385 - cpu-release-addr = <0 0x20000000>; 386 - }; 387 - 388 - CPU14: cpu@100010100 { 389 - device_type = "cpu"; 390 - compatible = "arm,cortex-a57"; 391 - reg = <0x1 0x10100>; 392 - enable-method = "spin-table"; 393 - cpu-release-addr = <0 0x20000000>; 394 - }; 395 - 396 - CPU15: cpu@100010101 { 397 - device_type = "cpu"; 398 - compatible = "arm,cortex-a57"; 399 - reg = <0x1 0x10101>; 400 - enable-method = "spin-table"; 401 - cpu-release-addr = <0 0x20000000>; 402 - }; 403 - }; 404 - 405 - Example 2 (ARM 32-bit, dual-cluster, 8-cpu system, no SMT): 406 - 407 - cpus { 408 - #size-cells = <0>; 409 - #address-cells = <1>; 410 - 411 - cpu-map { 412 - cluster0 { 413 - core0 { 414 - cpu = <&CPU0>; 415 - }; 416 - core1 { 417 - cpu = <&CPU1>; 418 - }; 419 - core2 { 420 - cpu = <&CPU2>; 421 - }; 422 - core3 { 423 - cpu = <&CPU3>; 424 - }; 425 - }; 426 - 427 - cluster1 { 428 - core0 { 429 - cpu = <&CPU4>; 430 - }; 431 - core1 { 432 - cpu = <&CPU5>; 433 - }; 434 - core2 { 435 - cpu = <&CPU6>; 436 - }; 437 - core3 { 438 - cpu = <&CPU7>; 439 - }; 440 - }; 441 - }; 442 - 443 - CPU0: cpu@0 { 444 - device_type = "cpu"; 445 - compatible = "arm,cortex-a15"; 446 - reg = <0x0>; 447 - }; 448 - 449 - CPU1: cpu@1 { 450 - device_type = "cpu"; 451 - compatible = "arm,cortex-a15"; 452 - reg = <0x1>; 453 - }; 454 - 455 - CPU2: cpu@2 { 456 - device_type = "cpu"; 457 - compatible = "arm,cortex-a15"; 458 - reg = <0x2>; 459 - }; 460 - 461 - CPU3: cpu@3 { 462 - device_type = "cpu"; 463 - compatible = "arm,cortex-a15"; 464 - reg = <0x3>; 465 - }; 466 - 467 - CPU4: cpu@100 { 468 - device_type = "cpu"; 469 - compatible = "arm,cortex-a7"; 470 - reg = <0x100>; 471 - }; 472 - 473 - CPU5: cpu@101 { 474 - device_type = "cpu"; 475 - compatible = "arm,cortex-a7"; 476 - reg = <0x101>; 477 - }; 478 - 479 - CPU6: cpu@102 { 480 - device_type = "cpu"; 481 - compatible = "arm,cortex-a7"; 482 - reg = <0x102>; 483 - }; 484 - 485 - CPU7: cpu@103 { 486 - device_type = "cpu"; 487 - compatible = "arm,cortex-a7"; 488 - reg = <0x103>; 489 - }; 490 - }; 491 - 492 - Example 3: HiFive Unleashed (RISC-V 64 bit, 4 core system) 493 - 494 - { 495 - #address-cells = <2>; 496 - #size-cells = <2>; 497 - compatible = "sifive,fu540g", "sifive,fu500"; 498 - model = "sifive,hifive-unleashed-a00"; 499 - 500 - ... 501 - cpus { 502 - #address-cells = <1>; 503 - #size-cells = <0>; 504 - cpu-map { 505 - socket0 { 506 - cluster0 { 507 - core0 { 508 - cpu = <&CPU1>; 509 - }; 510 - core1 { 511 - cpu = <&CPU2>; 512 - }; 513 - core2 { 514 - cpu0 = <&CPU2>; 515 - }; 516 - core3 { 517 - cpu0 = <&CPU3>; 518 - }; 519 - }; 520 - }; 521 - }; 522 - 523 - CPU1: cpu@1 { 524 - device_type = "cpu"; 525 - compatible = "sifive,rocket0", "riscv"; 526 - reg = <0x1>; 527 - } 528 - 529 - CPU2: cpu@2 { 530 - device_type = "cpu"; 531 - compatible = "sifive,rocket0", "riscv"; 532 - reg = <0x2>; 533 - } 534 - CPU3: cpu@3 { 535 - device_type = "cpu"; 536 - compatible = "sifive,rocket0", "riscv"; 537 - reg = <0x3>; 538 - } 539 - CPU4: cpu@4 { 540 - device_type = "cpu"; 541 - compatible = "sifive,rocket0", "riscv"; 542 - reg = <0x4>; 543 - } 544 - } 545 - }; 546 - =============================================================================== 547 - [1] ARM Linux kernel documentation 548 - Documentation/devicetree/bindings/arm/cpus.yaml 549 - [2] Devicetree NUMA binding description 550 - Documentation/devicetree/bindings/numa.txt 551 - [3] RISC-V Linux kernel documentation 552 - Documentation/devicetree/bindings/riscv/cpus.yaml 553 - [4] https://www.devicetree.org/specifications/

-250

Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt

··· 1 - Binding for MediaTek's CPUFreq driver 2 - ===================================== 3 - 4 - Required properties: 5 - - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names. 6 - - clock-names: Should contain the following: 7 - "cpu" - The multiplexer for clock input of CPU cluster. 8 - "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock 9 - source (usually MAINPLL) when the original CPU PLL is under 10 - transition and not stable yet. 11 - Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for 12 - generic clock consumer properties. 13 - - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml 14 - for detail. 15 - - proc-supply: Regulator for Vproc of CPU cluster. 16 - 17 - Optional properties: 18 - - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver 19 - needs to do "voltage tracking" to step by step scale up/down Vproc and 20 - Vsram to fit SoC specific needs. When absent, the voltage scaling 21 - flow is handled by hardware, hence no software "voltage tracking" is 22 - needed. 23 - - mediatek,cci: 24 - Used to confirm the link status between cpufreq and mediatek cci. Because 25 - cpufreq and mediatek cci could share the same regulator in some MediaTek SoCs. 26 - To prevent the issue of high frequency and low voltage, we need to use this 27 - property to make sure mediatek cci is ready. 28 - For details of mediatek cci, please refer to 29 - Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml 30 - - #cooling-cells: 31 - For details, please refer to 32 - Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml 33 - 34 - Example 1 (MT7623 SoC): 35 - 36 - cpu_opp_table: opp_table { 37 - compatible = "operating-points-v2"; 38 - opp-shared; 39 - 40 - opp-598000000 { 41 - opp-hz = /bits/ 64 <598000000>; 42 - opp-microvolt = <1050000>; 43 - }; 44 - 45 - opp-747500000 { 46 - opp-hz = /bits/ 64 <747500000>; 47 - opp-microvolt = <1050000>; 48 - }; 49 - 50 - opp-1040000000 { 51 - opp-hz = /bits/ 64 <1040000000>; 52 - opp-microvolt = <1150000>; 53 - }; 54 - 55 - opp-1196000000 { 56 - opp-hz = /bits/ 64 <1196000000>; 57 - opp-microvolt = <1200000>; 58 - }; 59 - 60 - opp-1300000000 { 61 - opp-hz = /bits/ 64 <1300000000>; 62 - opp-microvolt = <1300000>; 63 - }; 64 - }; 65 - 66 - cpu0: cpu@0 { 67 - device_type = "cpu"; 68 - compatible = "arm,cortex-a7"; 69 - reg = <0x0>; 70 - clocks = <&infracfg CLK_INFRA_CPUSEL>, 71 - <&apmixedsys CLK_APMIXED_MAINPLL>; 72 - clock-names = "cpu", "intermediate"; 73 - operating-points-v2 = <&cpu_opp_table>; 74 - #cooling-cells = <2>; 75 - }; 76 - cpu@1 { 77 - device_type = "cpu"; 78 - compatible = "arm,cortex-a7"; 79 - reg = <0x1>; 80 - operating-points-v2 = <&cpu_opp_table>; 81 - }; 82 - cpu@2 { 83 - device_type = "cpu"; 84 - compatible = "arm,cortex-a7"; 85 - reg = <0x2>; 86 - operating-points-v2 = <&cpu_opp_table>; 87 - }; 88 - cpu@3 { 89 - device_type = "cpu"; 90 - compatible = "arm,cortex-a7"; 91 - reg = <0x3>; 92 - operating-points-v2 = <&cpu_opp_table>; 93 - }; 94 - 95 - Example 2 (MT8173 SoC): 96 - cpu_opp_table_a: opp_table_a { 97 - compatible = "operating-points-v2"; 98 - opp-shared; 99 - 100 - opp-507000000 { 101 - opp-hz = /bits/ 64 <507000000>; 102 - opp-microvolt = <859000>; 103 - }; 104 - 105 - opp-702000000 { 106 - opp-hz = /bits/ 64 <702000000>; 107 - opp-microvolt = <908000>; 108 - }; 109 - 110 - opp-1001000000 { 111 - opp-hz = /bits/ 64 <1001000000>; 112 - opp-microvolt = <983000>; 113 - }; 114 - 115 - opp-1105000000 { 116 - opp-hz = /bits/ 64 <1105000000>; 117 - opp-microvolt = <1009000>; 118 - }; 119 - 120 - opp-1183000000 { 121 - opp-hz = /bits/ 64 <1183000000>; 122 - opp-microvolt = <1028000>; 123 - }; 124 - 125 - opp-1404000000 { 126 - opp-hz = /bits/ 64 <1404000000>; 127 - opp-microvolt = <1083000>; 128 - }; 129 - 130 - opp-1508000000 { 131 - opp-hz = /bits/ 64 <1508000000>; 132 - opp-microvolt = <1109000>; 133 - }; 134 - 135 - opp-1573000000 { 136 - opp-hz = /bits/ 64 <1573000000>; 137 - opp-microvolt = <1125000>; 138 - }; 139 - }; 140 - 141 - cpu_opp_table_b: opp_table_b { 142 - compatible = "operating-points-v2"; 143 - opp-shared; 144 - 145 - opp-507000000 { 146 - opp-hz = /bits/ 64 <507000000>; 147 - opp-microvolt = <828000>; 148 - }; 149 - 150 - opp-702000000 { 151 - opp-hz = /bits/ 64 <702000000>; 152 - opp-microvolt = <867000>; 153 - }; 154 - 155 - opp-1001000000 { 156 - opp-hz = /bits/ 64 <1001000000>; 157 - opp-microvolt = <927000>; 158 - }; 159 - 160 - opp-1209000000 { 161 - opp-hz = /bits/ 64 <1209000000>; 162 - opp-microvolt = <968000>; 163 - }; 164 - 165 - opp-1404000000 { 166 - opp-hz = /bits/ 64 <1007000000>; 167 - opp-microvolt = <1028000>; 168 - }; 169 - 170 - opp-1612000000 { 171 - opp-hz = /bits/ 64 <1612000000>; 172 - opp-microvolt = <1049000>; 173 - }; 174 - 175 - opp-1807000000 { 176 - opp-hz = /bits/ 64 <1807000000>; 177 - opp-microvolt = <1089000>; 178 - }; 179 - 180 - opp-1989000000 { 181 - opp-hz = /bits/ 64 <1989000000>; 182 - opp-microvolt = <1125000>; 183 - }; 184 - }; 185 - 186 - cpu0: cpu@0 { 187 - device_type = "cpu"; 188 - compatible = "arm,cortex-a53"; 189 - reg = <0x000>; 190 - enable-method = "psci"; 191 - cpu-idle-states = <&CPU_SLEEP_0>; 192 - clocks = <&infracfg CLK_INFRA_CA53SEL>, 193 - <&apmixedsys CLK_APMIXED_MAINPLL>; 194 - clock-names = "cpu", "intermediate"; 195 - operating-points-v2 = <&cpu_opp_table_a>; 196 - }; 197 - 198 - cpu1: cpu@1 { 199 - device_type = "cpu"; 200 - compatible = "arm,cortex-a53"; 201 - reg = <0x001>; 202 - enable-method = "psci"; 203 - cpu-idle-states = <&CPU_SLEEP_0>; 204 - clocks = <&infracfg CLK_INFRA_CA53SEL>, 205 - <&apmixedsys CLK_APMIXED_MAINPLL>; 206 - clock-names = "cpu", "intermediate"; 207 - operating-points-v2 = <&cpu_opp_table_a>; 208 - }; 209 - 210 - cpu2: cpu@100 { 211 - device_type = "cpu"; 212 - compatible = "arm,cortex-a72"; 213 - reg = <0x100>; 214 - enable-method = "psci"; 215 - cpu-idle-states = <&CPU_SLEEP_0>; 216 - clocks = <&infracfg CLK_INFRA_CA72SEL>, 217 - <&apmixedsys CLK_APMIXED_MAINPLL>; 218 - clock-names = "cpu", "intermediate"; 219 - operating-points-v2 = <&cpu_opp_table_b>; 220 - }; 221 - 222 - cpu3: cpu@101 { 223 - device_type = "cpu"; 224 - compatible = "arm,cortex-a72"; 225 - reg = <0x101>; 226 - enable-method = "psci"; 227 - cpu-idle-states = <&CPU_SLEEP_0>; 228 - clocks = <&infracfg CLK_INFRA_CA72SEL>, 229 - <&apmixedsys CLK_APMIXED_MAINPLL>; 230 - clock-names = "cpu", "intermediate"; 231 - operating-points-v2 = <&cpu_opp_table_b>; 232 - }; 233 - 234 - &cpu0 { 235 - proc-supply = <&mt6397_vpca15_reg>; 236 - }; 237 - 238 - &cpu1 { 239 - proc-supply = <&mt6397_vpca15_reg>; 240 - }; 241 - 242 - &cpu2 { 243 - proc-supply = <&da9211_vcpu_reg>; 244 - sram-supply = <&mt6397_vsramca7_reg>; 245 - }; 246 - 247 - &cpu3 { 248 - proc-supply = <&da9211_vcpu_reg>; 249 - sram-supply = <&mt6397_vsramca7_reg>; 250 - };

+66 -1

Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml

··· 128 128 - power-domains 129 129 - ports 130 130 131 - additionalProperties: false 131 + unevaluatedProperties: false 132 132 133 133 examples: 134 134 - | ··· 176 176 dsi0_out: endpoint { 177 177 data-lanes = <1 2 3 4>; 178 178 remote-endpoint = <&adv7535_in>; 179 + }; 180 + }; 181 + }; 182 + }; 183 + 184 + - | 185 + #include <dt-bindings/gpio/gpio.h> 186 + 187 + dsi1: dsi@10860000 { 188 + #address-cells = <1>; 189 + #size-cells = <0>; 190 + compatible = "renesas,r9a07g044-mipi-dsi", "renesas,rzg2l-mipi-dsi"; 191 + reg = <0x10860000 0x20000>; 192 + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 193 + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 194 + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 195 + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 196 + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 197 + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 198 + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 199 + interrupt-names = "seq0", "seq1", "vin1", "rcv", 200 + "ferr", "ppi", "debug"; 201 + clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>, 202 + <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>, 203 + <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>, 204 + <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>, 205 + <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>, 206 + <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>; 207 + clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk"; 208 + resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>, 209 + <&cpg R9A07G044_MIPI_DSI_ARESET_N>, 210 + <&cpg R9A07G044_MIPI_DSI_PRESET_N>; 211 + reset-names = "rst", "arst", "prst"; 212 + power-domains = <&cpg>; 213 + 214 + panel@0 { 215 + compatible = "rocktech,jh057n00900"; 216 + reg = <0>; 217 + vcc-supply = <&reg_2v8_p>; 218 + iovcc-supply = <&reg_1v8_p>; 219 + reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; 220 + 221 + port { 222 + panel_in: endpoint { 223 + remote-endpoint = <&dsi1_out>; 224 + }; 225 + }; 226 + }; 227 + 228 + ports { 229 + #address-cells = <1>; 230 + #size-cells = <0>; 231 + 232 + port@0 { 233 + reg = <0>; 234 + dsi1_in: endpoint { 235 + remote-endpoint = <&du_out_dsi1>; 236 + }; 237 + }; 238 + 239 + port@1 { 240 + reg = <1>; 241 + dsi1_out: endpoint { 242 + data-lanes = <1 2 3 4>; 243 + remote-endpoint = <&panel_in>; 179 244 }; 180 245 }; 181 246 };

-17

Documentation/devicetree/bindings/display/fsl,tcon.txt

··· 1 - Device Tree bindings for Freescale TCON Driver 2 - 3 - Required properties: 4 - - compatible: Should be one of 5 - * "fsl,vf610-tcon". 6 - 7 - - reg: Address and length of the register set for tcon. 8 - - clocks: From common clock binding: handle to tcon ipg clock. 9 - - clock-names: From common clock binding: Shall be "ipg". 10 - 11 - Examples: 12 - timing-controller@4003d000 { 13 - compatible = "fsl,vf610-tcon"; 14 - reg = <0x4003d000 0x1000>; 15 - clocks = <&clks VF610_CLK_TCON0>; 16 - clock-names = "ipg"; 17 - };

+43

Documentation/devicetree/bindings/display/fsl,vf610-tcon.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/display/fsl,vf610-tcon.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Freescale TCON 8 + 9 + maintainers: 10 + - Frank Li <Frank.Li@nxp.com> 11 + 12 + properties: 13 + compatible: 14 + const: fsl,vf610-tcon 15 + 16 + reg: 17 + maxItems: 1 18 + 19 + clocks: 20 + maxItems: 1 21 + 22 + clock-names: 23 + items: 24 + - const: ipg 25 + 26 + required: 27 + - compatible 28 + - reg 29 + - clocks 30 + - clock-names 31 + 32 + additionalProperties: false 33 + 34 + examples: 35 + - | 36 + #include <dt-bindings/clock/vf610-clock.h> 37 + 38 + timing-controller@4003d000 { 39 + compatible = "fsl,vf610-tcon"; 40 + reg = <0x4003d000 0x1000>; 41 + clocks = <&clks VF610_CLK_TCON0>; 42 + clock-names = "ipg"; 43 + };

+36

Documentation/devicetree/bindings/display/imx/fsl,imx-display-subsystem.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/display/imx/fsl,imx-display-subsystem.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Freescale i.MX DRM master device 8 + 9 + maintainers: 10 + - Frank Li <Frank.Li@nxp.com> 11 + 12 + description: 13 + The freescale i.MX DRM master device is a virtual device needed to list all 14 + IPU or other display interface nodes that comprise the graphics subsystem. 15 + 16 + properties: 17 + compatible: 18 + const: fsl,imx-display-subsystem 19 + 20 + ports: 21 + $ref: /schemas/types.yaml#/definitions/phandle-array 22 + description: 23 + Should contain a list of phandles pointing to camera 24 + sensor interface ports of IPU devices. 25 + 26 + required: 27 + - compatible 28 + 29 + additionalProperties: false 30 + 31 + examples: 32 + - | 33 + display-subsystem { 34 + compatible = "fsl,imx-display-subsystem"; 35 + ports = <&ipu_di0>; 36 + };

+74

Documentation/devicetree/bindings/display/imx/fsl,imx-parallel-display.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/display/imx/fsl,imx-parallel-display.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Parallel display support 8 + 9 + maintainers: 10 + - Frank Li <Frank.Li@nxp.com> 11 + 12 + properties: 13 + compatible: 14 + const: fsl,imx-parallel-display 15 + 16 + interface-pix-fmt: 17 + $ref: /schemas/types.yaml#/definitions/string 18 + enum: 19 + - rgb24 20 + - rgb565 21 + - bgr666 22 + - lvds666 23 + 24 + ddc: 25 + $ref: /schemas/types.yaml#/definitions/phandle 26 + description: 27 + phandle describing the i2c bus handling the display data channel 28 + 29 + '#address-cells': 30 + const: 1 31 + 32 + '#size-cells': 33 + const: 0 34 + 35 + port@0: 36 + $ref: /schemas/graph.yaml#/$defs/port-base 37 + unevaluatedProperties: false 38 + description: input port connected to the IPU display interface 39 + 40 + port@1: 41 + $ref: /schemas/graph.yaml#/$defs/port-base 42 + unevaluatedProperties: false 43 + description: output port connected to a panel 44 + 45 + required: 46 + - compatible 47 + 48 + additionalProperties: false 49 + 50 + examples: 51 + - | 52 + display { 53 + compatible = "fsl,imx-parallel-display"; 54 + #address-cells = <1>; 55 + #size-cells = <0>; 56 + interface-pix-fmt = "rgb24"; 57 + 58 + port@0 { 59 + reg = <0>; 60 + 61 + endpoint { 62 + remote-endpoint = <&ipu_di0_disp0>; 63 + }; 64 + }; 65 + 66 + port@1 { 67 + reg = <1>; 68 + 69 + endpoint { 70 + remote-endpoint = <&panel_in>; 71 + }; 72 + }; 73 + }; 74 +

+97

Documentation/devicetree/bindings/display/imx/fsl,imx6q-ipu.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/display/imx/fsl,imx6q-ipu.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Freescale i.MX IPUv3 8 + 9 + maintainers: 10 + - Frank Li <Frank.Li@nxp.com> 11 + 12 + properties: 13 + compatible: 14 + oneOf: 15 + - enum: 16 + - fsl,imx51-ipu 17 + - fsl,imx53-ipu 18 + - fsl,imx6q-ipu 19 + - items: 20 + - const: fsl,imx6qp-ipu 21 + - const: fsl,imx6q-ipu 22 + 23 + reg: 24 + maxItems: 1 25 + 26 + interrupts: 27 + minItems: 1 28 + maxItems: 2 29 + 30 + clocks: 31 + maxItems: 3 32 + 33 + clock-names: 34 + items: 35 + - const: bus 36 + - const: di0 37 + - const: di1 38 + 39 + resets: 40 + maxItems: 1 41 + 42 + '#address-cells': 43 + const: 1 44 + 45 + '#size-cells': 46 + const: 0 47 + 48 + fsl,prg: 49 + $ref: /schemas/types.yaml#/definitions/phandle 50 + description: phandle to prg node associated with this IPU instance 51 + 52 + port@0: 53 + $ref: /schemas/graph.yaml#/$defs/port-base 54 + unevaluatedProperties: false 55 + description: CSI0 56 + 57 + port@1: 58 + $ref: /schemas/graph.yaml#/$defs/port-base 59 + unevaluatedProperties: false 60 + description: CSI1 61 + 62 + port@2: 63 + $ref: /schemas/graph.yaml#/$defs/port-base 64 + unevaluatedProperties: false 65 + description: DI0 66 + 67 + port@3: 68 + $ref: /schemas/graph.yaml#/$defs/port-base 69 + unevaluatedProperties: false 70 + description: DI1 71 + 72 + required: 73 + - compatible 74 + - reg 75 + - interrupts 76 + - resets 77 + 78 + additionalProperties: false 79 + 80 + examples: 81 + - | 82 + display-controller@18000000 { 83 + compatible = "fsl,imx53-ipu"; 84 + reg = <0x18000000 0x080000000>; 85 + #address-cells = <1>; 86 + #size-cells = <0>; 87 + interrupts = <11 10>; 88 + resets = <&src 2>; 89 + 90 + port@2 { 91 + reg = <2>; 92 + 93 + endpoint { 94 + remote-endpoint = <&display_in>; 95 + }; 96 + }; 97 + };

+193

Documentation/devicetree/bindings/display/imx/fsl,imx6q-ldb.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/display/imx/fsl,imx6q-ldb.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Freescale LVDS Display Bridge (ldb) 8 + 9 + description: 10 + The LVDS Display Bridge device tree node contains up to two lvds-channel 11 + nodes describing each of the two LVDS encoder channels of the bridge. 12 + 13 + maintainers: 14 + - Frank Li <Frank.Li@nxp.com> 15 + 16 + properties: 17 + compatible: 18 + oneOf: 19 + - enum: 20 + - fsl,imx53-ldb 21 + - items: 22 + - enum: 23 + - fsl,imx6q-ldb 24 + - const: fsl,imx53-ldb 25 + 26 + reg: 27 + maxItems: 1 28 + 29 + '#address-cells': 30 + const: 1 31 + 32 + '#size-cells': 33 + const: 0 34 + 35 + gpr: 36 + $ref: /schemas/types.yaml#/definitions/phandle 37 + description: 38 + The phandle points to the iomuxc-gpr region containing the LVDS 39 + control register. 40 + 41 + clocks: 42 + minItems: 6 43 + maxItems: 8 44 + 45 + clock-names: 46 + oneOf: 47 + - items: 48 + - const: di0_pll 49 + - const: di1_pll 50 + - const: di0_sel 51 + - const: di1_sel 52 + - const: di0 53 + - const: di1 54 + - items: 55 + - const: di0_pll 56 + - const: di1_pll 57 + - const: di0_sel 58 + - const: di1_sel 59 + - const: di2_sel 60 + - const: di3_sel 61 + - const: di0 62 + - const: di1 63 + 64 + fsl,dual-channel: 65 + $ref: /schemas/types.yaml#/definitions/flag 66 + description: 67 + if it exists, only LVDS channel 0 should 68 + be configured - one input will be distributed on both outputs in dual 69 + channel mode 70 + 71 + patternProperties: 72 + '^lvds-channel@[0-1]$': 73 + type: object 74 + description: 75 + Each LVDS Channel has to contain either an of graph link to a panel device node 76 + or a display-timings node that describes the video timings for the connected 77 + LVDS display as well as the fsl,data-mapping and fsl,data-width properties. 78 + 79 + properties: 80 + reg: 81 + maxItems: 1 82 + 83 + '#address-cells': 84 + const: 1 85 + 86 + '#size-cells': 87 + const: 0 88 + 89 + display-timings: 90 + $ref: /schemas/display/panel/display-timings.yaml# 91 + 92 + fsl,data-mapping: 93 + enum: 94 + - spwg 95 + - jeida 96 + 97 + fsl,data-width: 98 + $ref: /schemas/types.yaml#/definitions/uint32 99 + description: should be <18> or <24> 100 + enum: 101 + - 18 102 + - 24 103 + 104 + fsl,panel: 105 + $ref: /schemas/types.yaml#/definitions/phandle 106 + description: phandle to lcd panel 107 + 108 + patternProperties: 109 + '^port@[0-4]$': 110 + $ref: /schemas/graph.yaml#/properties/port 111 + description: 112 + On i.MX5, the internal two-input-multiplexer is used. Due to hardware 113 + limitations, only one input port (port@[0,1]) can be used for each channel 114 + (lvds-channel@[0,1], respectively). 115 + On i.MX6, there should be four input ports (port@[0-3]) that correspond 116 + to the four LVDS multiplexer inputs. 117 + A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected 118 + to a panel input port. Optionally, the output port can be left out if 119 + display-timings are used instead. 120 + 121 + additionalProperties: false 122 + 123 + required: 124 + - compatible 125 + - gpr 126 + - clocks 127 + - clock-names 128 + 129 + additionalProperties: false 130 + 131 + examples: 132 + - | 133 + #include <dt-bindings/clock/imx5-clock.h> 134 + 135 + ldb@53fa8008 { 136 + compatible = "fsl,imx53-ldb"; 137 + reg = <0x53fa8008 0x4>; 138 + #address-cells = <1>; 139 + #size-cells = <0>; 140 + gpr = <&gpr>; 141 + clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, 142 + <&clks IMX5_CLK_LDB_DI1_SEL>, 143 + <&clks IMX5_CLK_IPU_DI0_SEL>, 144 + <&clks IMX5_CLK_IPU_DI1_SEL>, 145 + <&clks IMX5_CLK_LDB_DI0_GATE>, 146 + <&clks IMX5_CLK_LDB_DI1_GATE>; 147 + clock-names = "di0_pll", "di1_pll", 148 + "di0_sel", "di1_sel", 149 + "di0", "di1"; 150 + 151 + /* Using an of-graph endpoint link to connect the panel */ 152 + lvds-channel@0 { 153 + reg = <0>; 154 + #address-cells = <1>; 155 + #size-cells = <0>; 156 + 157 + port@0 { 158 + reg = <0>; 159 + 160 + endpoint { 161 + remote-endpoint = <&ipu_di0_lvds0>; 162 + }; 163 + }; 164 + 165 + port@2 { 166 + reg = <2>; 167 + 168 + endpoint { 169 + remote-endpoint = <&panel_in>; 170 + }; 171 + }; 172 + }; 173 + 174 + /* Using display-timings and fsl,data-mapping/width instead */ 175 + lvds-channel@1 { 176 + reg = <1>; 177 + #address-cells = <1>; 178 + #size-cells = <0>; 179 + fsl,data-mapping = "spwg"; 180 + fsl,data-width = <24>; 181 + 182 + display-timings {/* ... */ 183 + }; 184 + 185 + port@1 { 186 + reg = <1>; 187 + 188 + endpoint { 189 + remote-endpoint = <&ipu_di1_lvds1>; 190 + }; 191 + }; 192 + }; 193 + };

+55

Documentation/devicetree/bindings/display/imx/fsl,imx6qp-pre.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/display/imx/fsl,imx6qp-pre.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Freescale i.MX PRE (Prefetch Resolve Engine) 8 + 9 + maintainers: 10 + - Frank Li <Frank.Li@nxp.com> 11 + 12 + properties: 13 + compatible: 14 + const: fsl,imx6qp-pre 15 + 16 + reg: 17 + maxItems: 1 18 + 19 + interrupts: 20 + maxItems: 1 21 + 22 + clocks: 23 + maxItems: 1 24 + 25 + clock-names: 26 + items: 27 + - const: axi 28 + fsl,iram: 29 + $ref: /schemas/types.yaml#/definitions/phandle 30 + description: 31 + phandle pointing to the mmio-sram device node, that should be 32 + used for the PRE SRAM double buffer. 33 + 34 + required: 35 + - compatible 36 + - reg 37 + - interrupts 38 + - clocks 39 + - clock-names 40 + 41 + additionalProperties: false 42 + 43 + examples: 44 + - | 45 + #include <dt-bindings/clock/imx6qdl-clock.h> 46 + #include <dt-bindings/interrupt-controller/arm-gic.h> 47 + 48 + pre@21c8000 { 49 + compatible = "fsl,imx6qp-pre"; 50 + reg = <0x021c8000 0x1000>; 51 + interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; 52 + clocks = <&clks IMX6QDL_CLK_PRE0>; 53 + clock-names = "axi"; 54 + fsl,iram = <&ocram2>; 55 + };

+54

Documentation/devicetree/bindings/display/imx/fsl,imx6qp-prg.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/display/imx/fsl,imx6qp-prg.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Freescale i.MX PRG (Prefetch Resolve Gasket) 8 + 9 + maintainers: 10 + - Frank Li <Frank.Li@nxp.com> 11 + 12 + properties: 13 + compatible: 14 + const: fsl,imx6qp-prg 15 + 16 + reg: 17 + maxItems: 1 18 + 19 + clocks: 20 + maxItems: 2 21 + 22 + clock-names: 23 + items: 24 + - const: ipg 25 + - const: axi 26 + 27 + fsl,pres: 28 + $ref: /schemas/types.yaml#/definitions/phandle-array 29 + items: 30 + maxItems: 1 31 + description: 32 + phandles to the PRE units attached to this PRG, with the fixed 33 + PRE as the first entry and the muxable PREs following. 34 + 35 + required: 36 + - compatible 37 + - reg 38 + - clocks 39 + - clock-names 40 + 41 + additionalProperties: false 42 + 43 + examples: 44 + - | 45 + #include <dt-bindings/clock/imx6qdl-clock.h> 46 + 47 + prg@21cc000 { 48 + compatible = "fsl,imx6qp-prg"; 49 + reg = <0x021cc000 0x1000>; 50 + clocks = <&clks IMX6QDL_CLK_PRG0_APB>, <&clks IMX6QDL_CLK_PRG0_AXI>; 51 + clock-names = "ipg", "axi"; 52 + fsl,pres = <&pre1>, <&pre2>, <&pre3>; 53 + }; 54 +

-160

Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt

··· 1 - Freescale i.MX DRM master device 2 - ================================ 3 - 4 - The freescale i.MX DRM master device is a virtual device needed to list all 5 - IPU or other display interface nodes that comprise the graphics subsystem. 6 - 7 - Required properties: 8 - - compatible: Should be "fsl,imx-display-subsystem" 9 - - ports: Should contain a list of phandles pointing to display interface ports 10 - of IPU devices 11 - 12 - example: 13 - 14 - display-subsystem { 15 - compatible = "fsl,imx-display-subsystem"; 16 - ports = <&ipu_di0>; 17 - }; 18 - 19 - 20 - Freescale i.MX IPUv3 21 - ==================== 22 - 23 - Required properties: 24 - - compatible: Should be "fsl,<chip>-ipu" where <chip> is one of 25 - - imx51 26 - - imx53 27 - - imx6q 28 - - imx6qp 29 - - reg: should be register base and length as documented in the 30 - datasheet 31 - - interrupts: Should contain sync interrupt and error interrupt, 32 - in this order. 33 - - resets: phandle pointing to the system reset controller and 34 - reset line index, see reset/fsl,imx-src.txt for details 35 - Additional required properties for fsl,imx6qp-ipu: 36 - - fsl,prg: phandle to prg node associated with this IPU instance 37 - Optional properties: 38 - - port@[0-3]: Port nodes with endpoint definitions as defined in 39 - Documentation/devicetree/bindings/media/video-interfaces.txt. 40 - Ports 0 and 1 should correspond to CSI0 and CSI1, 41 - ports 2 and 3 should correspond to DI0 and DI1, respectively. 42 - 43 - example: 44 - 45 - ipu: ipu@18000000 { 46 - #address-cells = <1>; 47 - #size-cells = <0>; 48 - compatible = "fsl,imx53-ipu"; 49 - reg = <0x18000000 0x080000000>; 50 - interrupts = <11 10>; 51 - resets = <&src 2>; 52 - 53 - ipu_di0: port@2 { 54 - reg = <2>; 55 - 56 - ipu_di0_disp0: endpoint { 57 - remote-endpoint = <&display_in>; 58 - }; 59 - }; 60 - }; 61 - 62 - Freescale i.MX PRE (Prefetch Resolve Engine) 63 - ============================================ 64 - 65 - Required properties: 66 - - compatible: should be "fsl,imx6qp-pre" 67 - - reg: should be register base and length as documented in the 68 - datasheet 69 - - clocks : phandle to the PRE axi clock input, as described 70 - in Documentation/devicetree/bindings/clock/clock-bindings.txt and 71 - Documentation/devicetree/bindings/clock/imx6q-clock.yaml. 72 - - clock-names: should be "axi" 73 - - interrupts: should contain the PRE interrupt 74 - - fsl,iram: phandle pointing to the mmio-sram device node, that should be 75 - used for the PRE SRAM double buffer. 76 - 77 - example: 78 - 79 - pre@21c8000 { 80 - compatible = "fsl,imx6qp-pre"; 81 - reg = <0x021c8000 0x1000>; 82 - interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; 83 - clocks = <&clks IMX6QDL_CLK_PRE0>; 84 - clock-names = "axi"; 85 - fsl,iram = <&ocram2>; 86 - }; 87 - 88 - Freescale i.MX PRG (Prefetch Resolve Gasket) 89 - ============================================ 90 - 91 - Required properties: 92 - - compatible: should be "fsl,imx6qp-prg" 93 - - reg: should be register base and length as documented in the 94 - datasheet 95 - - clocks : phandles to the PRG ipg and axi clock inputs, as described 96 - in Documentation/devicetree/bindings/clock/clock-bindings.txt and 97 - Documentation/devicetree/bindings/clock/imx6q-clock.yaml. 98 - - clock-names: should be "ipg" and "axi" 99 - - fsl,pres: phandles to the PRE units attached to this PRG, with the fixed 100 - PRE as the first entry and the muxable PREs following. 101 - 102 - example: 103 - 104 - prg@21cc000 { 105 - compatible = "fsl,imx6qp-prg"; 106 - reg = <0x021cc000 0x1000>; 107 - clocks = <&clks IMX6QDL_CLK_PRG0_APB>, 108 - <&clks IMX6QDL_CLK_PRG0_AXI>; 109 - clock-names = "ipg", "axi"; 110 - fsl,pres = <&pre1>, <&pre2>, <&pre3>; 111 - }; 112 - 113 - Parallel display support 114 - ======================== 115 - 116 - Required properties: 117 - - compatible: Should be "fsl,imx-parallel-display" 118 - Optional properties: 119 - - interface-pix-fmt: How this display is connected to the 120 - display interface. Currently supported types: "rgb24", "rgb565", "bgr666" 121 - and "lvds666". 122 - - ddc: phandle describing the i2c bus handling the display data 123 - channel 124 - - port@[0-1]: Port nodes with endpoint definitions as defined in 125 - Documentation/devicetree/bindings/media/video-interfaces.txt. 126 - Port 0 is the input port connected to the IPU display interface, 127 - port 1 is the output port connected to a panel. 128 - 129 - example: 130 - 131 - disp0 { 132 - compatible = "fsl,imx-parallel-display"; 133 - interface-pix-fmt = "rgb24"; 134 - 135 - port@0 { 136 - reg = <0>; 137 - 138 - display_in: endpoint { 139 - remote-endpoint = <&ipu_di0_disp0>; 140 - }; 141 - }; 142 - 143 - port@1 { 144 - reg = <1>; 145 - 146 - display_out: endpoint { 147 - remote-endpoint = <&panel_in>; 148 - }; 149 - }; 150 - }; 151 - 152 - panel { 153 - ... 154 - 155 - port { 156 - panel_in: endpoint { 157 - remote-endpoint = <&display_out>; 158 - }; 159 - }; 160 - };

-146

Documentation/devicetree/bindings/display/imx/ldb.txt

··· 1 - Device-Tree bindings for LVDS Display Bridge (ldb) 2 - 3 - LVDS Display Bridge 4 - =================== 5 - 6 - The LVDS Display Bridge device tree node contains up to two lvds-channel 7 - nodes describing each of the two LVDS encoder channels of the bridge. 8 - 9 - Required properties: 10 - - #address-cells : should be <1> 11 - - #size-cells : should be <0> 12 - - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb". 13 - Both LDB versions are similar, but i.MX6 has an additional 14 - multiplexer in the front to select any of the four IPU display 15 - interfaces as input for each LVDS channel. 16 - - gpr : should be <&gpr> on i.MX53 and i.MX6q. 17 - The phandle points to the iomuxc-gpr region containing the LVDS 18 - control register. 19 - - clocks, clock-names : phandles to the LDB divider and selector clocks and to 20 - the display interface selector clocks, as described in 21 - Documentation/devicetree/bindings/clock/clock-bindings.txt 22 - The following clocks are expected on i.MX53: 23 - "di0_pll" - LDB LVDS channel 0 mux 24 - "di1_pll" - LDB LVDS channel 1 mux 25 - "di0" - LDB LVDS channel 0 gate 26 - "di1" - LDB LVDS channel 1 gate 27 - "di0_sel" - IPU1 DI0 mux 28 - "di1_sel" - IPU1 DI1 mux 29 - On i.MX6q the following additional clocks are needed: 30 - "di2_sel" - IPU2 DI0 mux 31 - "di3_sel" - IPU2 DI1 mux 32 - The needed clock numbers for each are documented in 33 - Documentation/devicetree/bindings/clock/imx5-clock.yaml, and in 34 - Documentation/devicetree/bindings/clock/imx6q-clock.yaml. 35 - 36 - Optional properties: 37 - - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q 38 - - pinctrl-0 : a phandle pointing to LVDS pin settings on i.MX53, 39 - not used on i.MX6q 40 - - fsl,dual-channel : boolean. if it exists, only LVDS channel 0 should 41 - be configured - one input will be distributed on both outputs in dual 42 - channel mode 43 - 44 - LVDS Channel 45 - ============ 46 - 47 - Each LVDS Channel has to contain either an of graph link to a panel device node 48 - or a display-timings node that describes the video timings for the connected 49 - LVDS display as well as the fsl,data-mapping and fsl,data-width properties. 50 - 51 - Required properties: 52 - - reg : should be <0> or <1> 53 - - port: Input and output port nodes with endpoint definitions as defined in 54 - Documentation/devicetree/bindings/graph.txt. 55 - On i.MX5, the internal two-input-multiplexer is used. Due to hardware 56 - limitations, only one input port (port@[0,1]) can be used for each channel 57 - (lvds-channel@[0,1], respectively). 58 - On i.MX6, there should be four input ports (port@[0-3]) that correspond 59 - to the four LVDS multiplexer inputs. 60 - A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected 61 - to a panel input port. Optionally, the output port can be left out if 62 - display-timings are used instead. 63 - 64 - Optional properties (required if display-timings are used): 65 - - display-timings : A node that describes the display timings as defined in 66 - Documentation/devicetree/bindings/display/panel/display-timing.txt. 67 - - fsl,data-mapping : should be "spwg" or "jeida" 68 - This describes how the color bits are laid out in the 69 - serialized LVDS signal. 70 - - fsl,data-width : should be <18> or <24> 71 - 72 - example: 73 - 74 - gpr: iomuxc-gpr@53fa8000 { 75 - /* ... */ 76 - }; 77 - 78 - ldb: ldb@53fa8008 { 79 - #address-cells = <1>; 80 - #size-cells = <0>; 81 - compatible = "fsl,imx53-ldb"; 82 - gpr = <&gpr>; 83 - clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, 84 - <&clks IMX5_CLK_LDB_DI1_SEL>, 85 - <&clks IMX5_CLK_IPU_DI0_SEL>, 86 - <&clks IMX5_CLK_IPU_DI1_SEL>, 87 - <&clks IMX5_CLK_LDB_DI0_GATE>, 88 - <&clks IMX5_CLK_LDB_DI1_GATE>; 89 - clock-names = "di0_pll", "di1_pll", 90 - "di0_sel", "di1_sel", 91 - "di0", "di1"; 92 - 93 - /* Using an of-graph endpoint link to connect the panel */ 94 - lvds-channel@0 { 95 - #address-cells = <1>; 96 - #size-cells = <0>; 97 - reg = <0>; 98 - 99 - port@0 { 100 - reg = <0>; 101 - 102 - lvds0_in: endpoint { 103 - remote-endpoint = <&ipu_di0_lvds0>; 104 - }; 105 - }; 106 - 107 - port@2 { 108 - reg = <2>; 109 - 110 - lvds0_out: endpoint { 111 - remote-endpoint = <&panel_in>; 112 - }; 113 - }; 114 - }; 115 - 116 - /* Using display-timings and fsl,data-mapping/width instead */ 117 - lvds-channel@1 { 118 - #address-cells = <1>; 119 - #size-cells = <0>; 120 - reg = <1>; 121 - fsl,data-mapping = "spwg"; 122 - fsl,data-width = <24>; 123 - 124 - display-timings { 125 - /* ... */ 126 - }; 127 - 128 - port@1 { 129 - reg = <1>; 130 - 131 - lvds1_in: endpoint { 132 - remote-endpoint = <&ipu_di1_lvds1>; 133 - }; 134 - }; 135 - }; 136 - }; 137 - 138 - panel: lvds-panel { 139 - /* ... */ 140 - 141 - port { 142 - panel_in: endpoint { 143 - remote-endpoint = <&lvds0_out>; 144 - }; 145 - }; 146 - };

-74

Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt

··· 1 - Rockchip RK3399 specific extensions to the cdn Display Port 2 - ================================ 3 - 4 - Required properties: 5 - - compatible: must be "rockchip,rk3399-cdn-dp" 6 - 7 - - reg: physical base address of the controller and length 8 - 9 - - clocks: from common clock binding: handle to dp clock. 10 - 11 - - clock-names: from common clock binding: 12 - Required elements: "core-clk" "pclk" "spdif" "grf" 13 - 14 - - resets : a list of phandle + reset specifier pairs 15 - - reset-names : string of reset names 16 - Required elements: "apb", "core", "dptx", "spdif" 17 - - power-domains : power-domain property defined with a phandle 18 - to respective power domain. 19 - - assigned-clocks: main clock, should be <&cru SCLK_DP_CORE> 20 - - assigned-clock-rates : the DP core clk frequency, shall be: 100000000 21 - 22 - - rockchip,grf: this soc should set GRF regs, so need get grf here. 23 - 24 - - ports: contain a port nodes with endpoint definitions as defined in 25 - Documentation/devicetree/bindings/media/video-interfaces.txt. 26 - contained 2 endpoints, connecting to the output of vop. 27 - 28 - - phys: from general PHY binding: the phandle for the PHY device. 29 - 30 - - extcon: extcon specifier for the Power Delivery 31 - 32 - - #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF 33 - 34 - ------------------------------------------------------------------------------- 35 - 36 - Example: 37 - cdn_dp: dp@fec00000 { 38 - compatible = "rockchip,rk3399-cdn-dp"; 39 - reg = <0x0 0xfec00000 0x0 0x100000>; 40 - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 41 - clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, 42 - <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; 43 - clock-names = "core-clk", "pclk", "spdif", "grf"; 44 - assigned-clocks = <&cru SCLK_DP_CORE>; 45 - assigned-clock-rates = <100000000>; 46 - power-domains = <&power RK3399_PD_HDCP>; 47 - phys = <&tcphy0_dp>, <&tcphy1_dp>; 48 - resets = <&cru SRST_DPTX_SPDIF_REC>; 49 - reset-names = "spdif"; 50 - extcon = <&fusb0>, <&fusb1>; 51 - rockchip,grf = <&grf>; 52 - #address-cells = <1>; 53 - #size-cells = <0>; 54 - #sound-dai-cells = <1>; 55 - 56 - ports { 57 - #address-cells = <1>; 58 - #size-cells = <0>; 59 - 60 - dp_in: port { 61 - #address-cells = <1>; 62 - #size-cells = <0>; 63 - dp_in_vopb: endpoint@0 { 64 - reg = <0>; 65 - remote-endpoint = <&vopb_out_dp>; 66 - }; 67 - 68 - dp_in_vopl: endpoint@1 { 69 - reg = <1>; 70 - remote-endpoint = <&vopl_out_dp>; 71 - }; 72 - }; 73 - }; 74 - };

+170

Documentation/devicetree/bindings/display/rockchip/rockchip,rk3399-cdn-dp.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3399-cdn-dp.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Rockchip RK3399 specific extensions to the CDN Display Port 8 + 9 + maintainers: 10 + - Andy Yan <andy.yan@rock-chip.com> 11 + - Heiko Stuebner <heiko@sntech.de> 12 + - Sandy Huang <hjc@rock-chips.com> 13 + 14 + allOf: 15 + - $ref: /schemas/sound/dai-common.yaml# 16 + 17 + properties: 18 + compatible: 19 + items: 20 + - const: rockchip,rk3399-cdn-dp 21 + 22 + reg: 23 + maxItems: 1 24 + 25 + clocks: 26 + items: 27 + - description: DP core work clock 28 + - description: APB clock 29 + - description: SPDIF interface clock 30 + - description: GRF clock 31 + 32 + clock-names: 33 + items: 34 + - const: core-clk 35 + - const: pclk 36 + - const: spdif 37 + - const: grf 38 + 39 + extcon: 40 + $ref: /schemas/types.yaml#/definitions/phandle-array 41 + minItems: 1 42 + items: 43 + - description: Extcon device providing the cable state for DP PHY device 0 44 + - description: Extcon device providing the cable state for DP PHY device 1 45 + description: 46 + List of phandle to the extcon device providing the cable state for the DP PHY. 47 + 48 + interrupts: 49 + maxItems: 1 50 + 51 + phys: 52 + minItems: 1 53 + items: 54 + - description: DP output to the DP PHY device 0 55 + - description: DP output to the DP PHY device 1 56 + description: 57 + RK3399 have two DP-USB PHY, specifying one PHY which want to use, or 58 + specify two PHYs here to let the driver determine which PHY to use. 59 + 60 + ports: 61 + $ref: /schemas/graph.yaml#/properties/ports 62 + 63 + properties: 64 + port@0: 65 + $ref: /schemas/graph.yaml#/properties/port 66 + description: Input of the CDN DP 67 + 68 + properties: 69 + endpoint@0: 70 + description: Connection to the VOPB 71 + 72 + endpoint@1: 73 + description: Connection to the VOPL 74 + 75 + port@1: 76 + $ref: /schemas/graph.yaml#/properties/port 77 + description: Output of the CDN DP 78 + 79 + required: 80 + - port@0 81 + - port@1 82 + 83 + power-domains: 84 + maxItems: 1 85 + 86 + resets: 87 + maxItems: 4 88 + 89 + reset-names: 90 + items: 91 + - const: spdif 92 + - const: dptx 93 + - const: apb 94 + - const: core 95 + 96 + rockchip,grf: 97 + $ref: /schemas/types.yaml#/definitions/phandle 98 + description: 99 + Phandle to GRF register to control HPD. 100 + 101 + "#sound-dai-cells": 102 + const: 1 103 + 104 + required: 105 + - compatible 106 + - reg 107 + - clocks 108 + - clock-names 109 + - interrupts 110 + - phys 111 + - ports 112 + - resets 113 + - reset-names 114 + - rockchip,grf 115 + - "#sound-dai-cells" 116 + 117 + unevaluatedProperties: false 118 + 119 + examples: 120 + - | 121 + #include <dt-bindings/clock/rk3399-cru.h> 122 + #include <dt-bindings/interrupt-controller/arm-gic.h> 123 + #include <dt-bindings/power/rk3399-power.h> 124 + soc { 125 + #address-cells = <2>; 126 + #size-cells = <2>; 127 + 128 + dp@fec00000 { 129 + compatible = "rockchip,rk3399-cdn-dp"; 130 + reg = <0x0 0xfec00000 0x0 0x100000>; 131 + assigned-clocks = <&cru SCLK_DP_CORE>; 132 + assigned-clock-rates = <100000000>; 133 + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 134 + clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, <&cru SCLK_SPDIF_REC_DPTX>, 135 + <&cru PCLK_VIO_GRF>; 136 + clock-names = "core-clk", "pclk", "spdif", "grf"; 137 + power-domains = <&power RK3399_PD_HDCP>; 138 + phys = <&tcphy0_dp>, <&tcphy1_dp>; 139 + resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, 140 + <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; 141 + reset-names = "spdif", "dptx", "apb", "core"; 142 + rockchip,grf = <&grf>; 143 + #sound-dai-cells = <1>; 144 + 145 + ports { 146 + #address-cells = <1>; 147 + #size-cells = <0>; 148 + 149 + dp_in: port@0 { 150 + reg = <0>; 151 + #address-cells = <1>; 152 + #size-cells = <0>; 153 + 154 + dp_in_vopb: endpoint@0 { 155 + reg = <0>; 156 + remote-endpoint = <&vopb_out_dp>; 157 + }; 158 + 159 + dp_in_vopl: endpoint@1 { 160 + reg = <1>; 161 + remote-endpoint = <&vopl_out_dp>; 162 + }; 163 + }; 164 + 165 + dp_out: port@1 { 166 + reg = <1>; 167 + }; 168 + }; 169 + }; 170 + };

+14 -1

Documentation/devicetree/bindings/example-schema.yaml

··· 178 178 description: Child nodes are just another property from a json-schema 179 179 perspective. 180 180 type: object # DT nodes are json objects 181 - # Child nodes also need additionalProperties or unevaluatedProperties 181 + # Child nodes also need additionalProperties or unevaluatedProperties, where 182 + # 'false' should be used in most cases (see 'child-node-with-own-schema' 183 + # below). 182 184 additionalProperties: false 183 185 properties: 184 186 vendor,a-child-node-property: ··· 190 188 191 189 required: 192 190 - vendor,a-child-node-property 191 + 192 + child-node-with-own-schema: 193 + description: | 194 + Child node with their own compatible and device schema which ends in 195 + 'additionalProperties: false' or 'unevaluatedProperties: false' can 196 + mention only the compatible and use here 'additionalProperties: true'. 197 + type: object 198 + additionalProperties: true 199 + properties: 200 + compatible: 201 + const: vendor,sub-device 193 202 194 203 # Describe the relationship between different properties 195 204 dependencies:

+4

Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml

··· 25 25 - realtek,rtd1619-mali 26 26 - renesas,r9a07g044-mali 27 27 - renesas,r9a07g054-mali 28 + - renesas,r9a09g047-mali 29 + - renesas,r9a09g056-mali 28 30 - renesas,r9a09g057-mali 29 31 - rockchip,px30-mali 30 32 - rockchip,rk3562-mali ··· 147 145 enum: 148 146 - renesas,r9a07g044-mali 149 147 - renesas,r9a07g054-mali 148 + - renesas,r9a09g047-mali 149 + - renesas,r9a09g056-mali 150 150 - renesas,r9a09g057-mali 151 151 then: 152 152 properties:

-37

Documentation/devicetree/bindings/interrupt-controller/abilis,tb10x-ictl.txt

··· 1 - TB10x Top Level Interrupt Controller 2 - ==================================== 3 - 4 - The Abilis TB10x SOC contains a custom interrupt controller. It performs 5 - one-to-one mapping of external interrupt sources to CPU interrupts and 6 - provides support for reconfigurable trigger modes. 7 - 8 - Required properties 9 - ------------------- 10 - 11 - - compatible: Should be "abilis,tb10x-ictl" 12 - - reg: specifies physical base address and size of register range. 13 - - interrupt-congroller: Identifies the node as an interrupt controller. 14 - - #interrupt cells: Specifies the number of cells used to encode an interrupt 15 - source connected to this controller. The value shall be 2. 16 - - interrupts: Specifies the list of interrupt lines which are handled by 17 - the interrupt controller in the parent controller's notation. Interrupts 18 - are mapped one-to-one to parent interrupts. 19 - 20 - Example 21 - ------- 22 - 23 - intc: interrupt-controller { /* Parent interrupt controller */ 24 - interrupt-controller; 25 - #interrupt-cells = <1>; /* For example below */ 26 - /* ... */ 27 - }; 28 - 29 - tb10x_ictl: pic@2000 { /* TB10x interrupt controller */ 30 - compatible = "abilis,tb10x-ictl"; 31 - reg = <0x2000 0x20>; 32 - interrupt-controller; 33 - #interrupt-cells = <2>; 34 - interrupt-parent = <&intc>; 35 - interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 36 - 20 21 22 23 24 25 26 27 28 29 30 31>; 37 - };

+54

Documentation/devicetree/bindings/interrupt-controller/abilis,tb10x-ictl.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/abilis,tb10x-ictl.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: TB10x Top Level Interrupt Controller 8 + 9 + maintainers: 10 + - Christian Ruppert <christian.ruppert@abilis.com> 11 + 12 + description: 13 + The Abilis TB10x SOC contains a custom interrupt controller. It performs 14 + one-to-one mapping of external interrupt sources to CPU interrupts and 15 + provides support for reconfigurable trigger modes. 16 + 17 + properties: 18 + compatible: 19 + const: abilis,tb10x-ictl 20 + 21 + reg: 22 + maxItems: 1 23 + 24 + interrupt-controller: true 25 + 26 + '#interrupt-cells': 27 + const: 2 28 + 29 + interrupts: 30 + description: A one-to-one mapping of external interrupt sources to parent 31 + interrupts. 32 + minItems: 1 33 + maxItems: 32 34 + 35 + required: 36 + - compatible 37 + - reg 38 + - interrupt-controller 39 + - '#interrupt-cells' 40 + - interrupts 41 + 42 + additionalProperties: false 43 + 44 + examples: 45 + - | 46 + interrupt-controller@2000 { 47 + compatible = "abilis,tb10x-ictl"; 48 + reg = <0x2000 0x20>; 49 + interrupt-controller; 50 + #interrupt-cells = <2>; 51 + interrupts = <5>, <6>, <7>, <8>, <9>, <10>, <11>, <12>, <13>, <14>, 52 + <15>, <16>, <17>, <18>, <19>, <20>, <21>, <22>, <23>, 53 + <24>, <25>, <26>, <27>, <28>, <29>, <30>, <31>; 54 + };

-25

Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt

··· 1 - Alpine MSIX controller 2 - 3 - See arm,gic-v3.txt for SPI and MSI definitions. 4 - 5 - Required properties: 6 - 7 - - compatible: should be "al,alpine-msix" 8 - - reg: physical base address and size of the registers 9 - - interrupt-controller: identifies the node as an interrupt controller 10 - - msi-controller: identifies the node as an PCI Message Signaled Interrupt 11 - controller 12 - - al,msi-base-spi: SPI base of the MSI frame 13 - - al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0 14 - 15 - Example: 16 - 17 - msix: msix { 18 - compatible = "al,alpine-msix"; 19 - reg = <0x0 0xfbe00000 0x0 0x100000>; 20 - interrupt-parent = <&gic>; 21 - interrupt-controller; 22 - msi-controller; 23 - al,msi-base-spi = <160>; 24 - al,msi-num-spis = <160>; 25 - };

+49

Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/al,alpine-msix.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Alpine MSIX controller 8 + 9 + maintainers: 10 + - Antoine Tenart <atenart@kernel.org> 11 + 12 + properties: 13 + compatible: 14 + const: al,alpine-msix 15 + 16 + reg: 17 + maxItems: 1 18 + 19 + interrupt-parent: true 20 + 21 + msi-controller: true 22 + 23 + al,msi-base-spi: 24 + description: SPI base of the MSI frame 25 + $ref: /schemas/types.yaml#/definitions/uint32 26 + 27 + al,msi-num-spis: 28 + description: number of SPIs assigned to the MSI frame, relative to SPI0 29 + $ref: /schemas/types.yaml#/definitions/uint32 30 + 31 + required: 32 + - compatible 33 + - reg 34 + - msi-controller 35 + - al,msi-base-spi 36 + - al,msi-num-spis 37 + 38 + additionalProperties: false 39 + 40 + examples: 41 + - | 42 + msi-controller@fbe00000 { 43 + compatible = "al,alpine-msix"; 44 + reg = <0xfbe00000 0x100000>; 45 + interrupt-parent = <&gic>; 46 + msi-controller; 47 + al,msi-base-spi = <160>; 48 + al,msi-num-spis = <160>; 49 + };

+65

Documentation/devicetree/bindings/interrupt-controller/altr,msi-controller.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 + # Copyright (C) 2015, 2024, Intel Corporation 3 + %YAML 1.2 4 + --- 5 + $id: http://devicetree.org/schemas/interrupt-controller/altr,msi-controller.yaml# 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 + 8 + title: Altera PCIe MSI controller 9 + 10 + maintainers: 11 + - Matthew Gerlach <matthew.gerlach@linux.intel.com> 12 + 13 + properties: 14 + compatible: 15 + enum: 16 + - altr,msi-1.0 17 + 18 + reg: 19 + items: 20 + - description: CSR registers 21 + - description: Vectors slave port region 22 + 23 + reg-names: 24 + items: 25 + - const: csr 26 + - const: vector_slave 27 + 28 + interrupts: 29 + maxItems: 1 30 + 31 + msi-controller: true 32 + 33 + num-vectors: 34 + description: number of vectors 35 + $ref: /schemas/types.yaml#/definitions/uint32 36 + minimum: 1 37 + maximum: 32 38 + 39 + required: 40 + - compatible 41 + - reg 42 + - reg-names 43 + - interrupts 44 + - msi-controller 45 + - num-vectors 46 + 47 + allOf: 48 + - $ref: /schemas/interrupt-controller/msi-controller.yaml# 49 + 50 + unevaluatedProperties: false 51 + 52 + examples: 53 + - | 54 + #include <dt-bindings/interrupt-controller/arm-gic.h> 55 + #include <dt-bindings/interrupt-controller/irq.h> 56 + msi@ff200000 { 57 + compatible = "altr,msi-1.0"; 58 + reg = <0xff200000 0x00000010>, 59 + <0xff200010 0x00000080>; 60 + reg-names = "csr", "vector_slave"; 61 + interrupt-parent = <&hps_0_arm_gic_0>; 62 + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 63 + msi-controller; 64 + num-vectors = <32>; 65 + };

-27

Documentation/devicetree/bindings/interrupt-controller/amazon,al-fic.txt

··· 1 - Amazon's Annapurna Labs Fabric Interrupt Controller 2 - 3 - Required properties: 4 - 5 - - compatible: should be "amazon,al-fic" 6 - - reg: physical base address and size of the registers 7 - - interrupt-controller: identifies the node as an interrupt controller 8 - - #interrupt-cells : must be 2. Specifies the number of cells needed to encode 9 - an interrupt source. Supported trigger types are low-to-high edge 10 - triggered and active high level-sensitive. 11 - - interrupts: describes which input line in the interrupt parent, this 12 - fic's output is connected to. This field property depends on the parent's 13 - binding 14 - 15 - Please refer to interrupts.txt in this directory for details of the common 16 - Interrupt Controllers bindings used by client devices. 17 - 18 - Example: 19 - 20 - amazon_fic: interrupt-controller@fd8a8500 { 21 - compatible = "amazon,al-fic"; 22 - interrupt-controller; 23 - #interrupt-cells = <2>; 24 - reg = <0x0 0xfd8a8500 0x0 0x1000>; 25 - interrupt-parent = <&gic>; 26 - interrupts = <GIC_SPI 0x0 IRQ_TYPE_LEVEL_HIGH>; 27 - };

+46

Documentation/devicetree/bindings/interrupt-controller/amazon,al-fic.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/amazon,al-fic.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Amazon Annapurna Labs Fabric Interrupt Controller 8 + 9 + maintainers: 10 + - Talel Shenhar <talel@amazon.com> 11 + 12 + properties: 13 + compatible: 14 + const: amazon,al-fic 15 + 16 + reg: 17 + maxItems: 1 18 + 19 + interrupt-controller: true 20 + 21 + '#interrupt-cells': 22 + const: 2 23 + 24 + interrupts: 25 + maxItems: 1 26 + 27 + required: 28 + - compatible 29 + - reg 30 + - interrupt-controller 31 + - '#interrupt-cells' 32 + - interrupts 33 + 34 + additionalProperties: false 35 + 36 + examples: 37 + - | 38 + #include <dt-bindings/interrupt-controller/arm-gic.h> 39 + 40 + interrupt-controller@fd8a8500 { 41 + compatible = "amazon,al-fic"; 42 + reg = <0xfd8a8500 0x1000>; 43 + interrupt-controller; 44 + #interrupt-cells = <2>; 45 + interrupts = <GIC_SPI 0x0 IRQ_TYPE_LEVEL_HIGH>; 46 + };

-36

Documentation/devicetree/bindings/interrupt-controller/arm,nvic.txt

··· 1 - * ARM Nested Vector Interrupt Controller (NVIC) 2 - 3 - The NVIC provides an interrupt controller that is tightly coupled to 4 - Cortex-M based processor cores. The NVIC implemented on different SoCs 5 - vary in the number of interrupts and priority bits per interrupt. 6 - 7 - Main node required properties: 8 - 9 - - compatible : should be one of: 10 - "arm,v6m-nvic" 11 - "arm,v7m-nvic" 12 - "arm,v8m-nvic" 13 - - interrupt-controller : Identifies the node as an interrupt controller 14 - - #interrupt-cells : Specifies the number of cells needed to encode an 15 - interrupt source. The type shall be a <u32> and the value shall be 2. 16 - 17 - The 1st cell contains the interrupt number for the interrupt type. 18 - 19 - The 2nd cell is the priority of the interrupt. 20 - 21 - - reg : Specifies base physical address(s) and size of the NVIC registers. 22 - This is at a fixed address (0xe000e100) and size (0xc00). 23 - 24 - - arm,num-irq-priority-bits: The number of priority bits implemented by the 25 - given SoC 26 - 27 - Example: 28 - 29 - intc: interrupt-controller@e000e100 { 30 - compatible = "arm,v7m-nvic"; 31 - #interrupt-cells = <2>; 32 - #address-cells = <1>; 33 - interrupt-controller; 34 - reg = <0xe000e100 0xc00>; 35 - arm,num-irq-priority-bits = <4>; 36 - };

+61

Documentation/devicetree/bindings/interrupt-controller/arm,nvic.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/arm,nvic.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: ARM Nested Vector Interrupt Controller (NVIC) 8 + 9 + maintainers: 10 + - Rob Herring <robh@kernel.org> 11 + 12 + description: 13 + The NVIC provides an interrupt controller that is tightly coupled to Cortex-M 14 + based processor cores. The NVIC implemented on different SoCs vary in the 15 + number of interrupts and priority bits per interrupt. 16 + 17 + properties: 18 + compatible: 19 + enum: 20 + - arm,v6m-nvic 21 + - arm,v7m-nvic 22 + - arm,v8m-nvic 23 + 24 + reg: 25 + maxItems: 1 26 + 27 + '#address-cells': 28 + const: 0 29 + 30 + interrupt-controller: true 31 + 32 + '#interrupt-cells': 33 + const: 2 34 + description: | 35 + Number of cells to encode an interrupt source: 36 + first = interrupt number, second = priority. 37 + 38 + arm,num-irq-priority-bits: 39 + description: Number of priority bits implemented by the SoC 40 + minimum: 1 41 + maximum: 8 42 + 43 + required: 44 + - compatible 45 + - reg 46 + - interrupt-controller 47 + - '#interrupt-cells' 48 + - arm,num-irq-priority-bits 49 + 50 + additionalProperties: false 51 + 52 + examples: 53 + - | 54 + interrupt-controller@e000e100 { 55 + compatible = "arm,v7m-nvic"; 56 + #interrupt-cells = <2>; 57 + #address-cells = <0>; 58 + interrupt-controller; 59 + reg = <0xe000e100 0xc00>; 60 + arm,num-irq-priority-bits = <4>; 61 + };

-38

Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt

··· 1 - * ARM Versatile FPGA interrupt controller 2 - 3 - One or more FPGA IRQ controllers can be synthesized in an ARM reference board 4 - such as the Integrator or Versatile family. The output of these different 5 - controllers are OR:ed together and fed to the CPU tile's IRQ input. Each 6 - instance can handle up to 32 interrupts. 7 - 8 - Required properties: 9 - - compatible: "arm,versatile-fpga-irq" 10 - - interrupt-controller: Identifies the node as an interrupt controller 11 - - #interrupt-cells: The number of cells to define the interrupts. Must be 1 12 - as the FPGA IRQ controller has no configuration options for interrupt 13 - sources. The cell is a u32 and defines the interrupt number. 14 - - reg: The register bank for the FPGA interrupt controller. 15 - - clear-mask: a u32 number representing the mask written to clear all IRQs 16 - on the controller at boot for example. 17 - - valid-mask: a u32 number representing a bit mask determining which of 18 - the interrupts are valid. Unconnected/unused lines are set to 0, and 19 - the system till not make it possible for devices to request these 20 - interrupts. 21 - 22 - The "oxsemi,ox810se-rps-irq" compatible is deprecated. 23 - 24 - Example: 25 - 26 - pic: pic@14000000 { 27 - compatible = "arm,versatile-fpga-irq"; 28 - #interrupt-cells = <1>; 29 - interrupt-controller; 30 - reg = <0x14000000 0x100>; 31 - clear-mask = <0xffffffff>; 32 - valid-mask = <0x003fffff>; 33 - }; 34 - 35 - Optional properties: 36 - - interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ 37 - output is simply connected to the input of another IRQ controller, 38 - then the parent IRQ shall be specified in this property.

+61

Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/arm,versatile-fpga-irq.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: ARM Versatile FPGA IRQ Controller 8 + 9 + maintainers: 10 + - Linus Walleij <linus.walleij@linaro.org> 11 + 12 + description: 13 + One or more FPGA IRQ controllers can be synthesized in an ARM reference board 14 + such as the Integrator or Versatile family. The output of these different 15 + controllers are OR:ed together and fed to the CPU tile's IRQ input. Each 16 + instance can handle up to 32 interrupts. 17 + 18 + properties: 19 + compatible: 20 + const: arm,versatile-fpga-irq 21 + 22 + interrupt-controller: true 23 + 24 + '#interrupt-cells': 25 + const: 1 26 + 27 + reg: 28 + maxItems: 1 29 + 30 + clear-mask: 31 + description: A mask written to clear all IRQs on the controller at boot. 32 + $ref: /schemas/types.yaml#/definitions/uint32 33 + 34 + valid-mask: 35 + description: 36 + A bit mask determining which interrupts are valid; unused lines are set to 0. 37 + $ref: /schemas/types.yaml#/definitions/uint32 38 + 39 + interrupts: 40 + maxItems: 1 41 + 42 + additionalProperties: false 43 + 44 + required: 45 + - compatible 46 + - interrupt-controller 47 + - '#interrupt-cells' 48 + - reg 49 + - clear-mask 50 + - valid-mask 51 + 52 + examples: 53 + - | 54 + interrupt-controller@14000000 { 55 + compatible = "arm,versatile-fpga-irq"; 56 + #interrupt-cells = <1>; 57 + interrupt-controller; 58 + reg = <0x14000000 0x100>; 59 + clear-mask = <0xffffffff>; 60 + valid-mask = <0x003fffff>; 61 + };

-25

Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-i2c-ic.txt

··· 1 - Device tree configuration for the I2C Interrupt Controller on the AST24XX and 2 - AST25XX SoCs. 3 - 4 - Required Properties: 5 - - #address-cells : should be 1 6 - - #size-cells : should be 1 7 - - #interrupt-cells : should be 1 8 - - compatible : should be "aspeed,ast2400-i2c-ic" 9 - or "aspeed,ast2500-i2c-ic" 10 - - reg : address start and range of controller 11 - - interrupts : interrupt number 12 - - interrupt-controller : denotes that the controller receives and fires 13 - new interrupts for child busses 14 - 15 - Example: 16 - 17 - i2c_ic: interrupt-controller@0 { 18 - #address-cells = <1>; 19 - #size-cells = <1>; 20 - #interrupt-cells = <1>; 21 - compatible = "aspeed,ast2400-i2c-ic"; 22 - reg = <0x0 0x40>; 23 - interrupts = <12>; 24 - interrupt-controller; 25 - };

+46

Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-i2c-ic.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2400-i2c-ic.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Aspeed I2C Interrupt Controller (AST24XX/AST25XX) 8 + 9 + maintainers: 10 + - Ryan Chen <ryan_chen@aspeedtech.com> 11 + 12 + properties: 13 + compatible: 14 + enum: 15 + - aspeed,ast2400-i2c-ic 16 + - aspeed,ast2500-i2c-ic 17 + 18 + reg: 19 + maxItems: 1 20 + 21 + interrupts: 22 + maxItems: 1 23 + 24 + interrupt-controller: true 25 + 26 + '#interrupt-cells': 27 + const: 1 28 + 29 + required: 30 + - compatible 31 + - reg 32 + - '#interrupt-cells' 33 + - interrupts 34 + - interrupt-controller 35 + 36 + additionalProperties: false 37 + 38 + examples: 39 + - | 40 + interrupt-controller@0 { 41 + compatible = "aspeed,ast2400-i2c-ic"; 42 + reg = <0x0 0x40>; 43 + #interrupt-cells = <1>; 44 + interrupts = <12>; 45 + interrupt-controller; 46 + };

+48

Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2500-scu-ic.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + # Copyright 2025 Eddie James 3 + %YAML 1.2 4 + --- 5 + $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2500-scu-ic.yaml# 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 + 8 + title: Aspeed AST25XX and AST26XX SCU Interrupt Controller 9 + 10 + maintainers: 11 + - Eddie James <eajames@linux.ibm.com> 12 + 13 + properties: 14 + compatible: 15 + enum: 16 + - aspeed,ast2500-scu-ic 17 + - aspeed,ast2600-scu-ic0 18 + - aspeed,ast2600-scu-ic1 19 + 20 + reg: 21 + maxItems: 1 22 + 23 + '#interrupt-cells': 24 + const: 1 25 + 26 + interrupts: 27 + maxItems: 1 28 + 29 + interrupt-controller: true 30 + 31 + required: 32 + - compatible 33 + - reg 34 + - '#interrupt-cells' 35 + - interrupts 36 + - interrupt-controller 37 + 38 + additionalProperties: false 39 + 40 + examples: 41 + - | 42 + interrupt-controller@18 { 43 + compatible = "aspeed,ast2500-scu-ic"; 44 + reg = <0x18 0x4>; 45 + #interrupt-cells = <1>; 46 + interrupts = <21>; 47 + interrupt-controller; 48 + };

-23

Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic.txt

··· 1 - Aspeed AST25XX and AST26XX SCU Interrupt Controller 2 - 3 - Required Properties: 4 - - #interrupt-cells : must be 1 5 - - compatible : must be "aspeed,ast2500-scu-ic", 6 - "aspeed,ast2600-scu-ic0" or 7 - "aspeed,ast2600-scu-ic1" 8 - - interrupts : interrupt from the parent controller 9 - - interrupt-controller : indicates that the controller receives and 10 - fires new interrupts for child busses 11 - 12 - Example: 13 - 14 - syscon@1e6e2000 { 15 - ranges = <0 0x1e6e2000 0x1a8>; 16 - 17 - scu_ic: interrupt-controller@18 { 18 - #interrupt-cells = <1>; 19 - compatible = "aspeed,ast2500-scu-ic"; 20 - interrupts = <21>; 21 - interrupt-controller; 22 - }; 23 - };

-131

Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt

··· 1 - BCM2835 Top-Level ("ARMCTRL") Interrupt Controller 2 - 3 - The BCM2835 contains a custom top-level interrupt controller, which supports 4 - 72 interrupt sources using a 2-level register scheme. The interrupt 5 - controller, or the HW block containing it, is referred to occasionally 6 - as "armctrl" in the SoC documentation, hence naming of this binding. 7 - 8 - The BCM2836 contains the same interrupt controller with the same 9 - interrupts, but the per-CPU interrupt controller is the root, and an 10 - interrupt there indicates that the ARMCTRL has an interrupt to handle. 11 - 12 - Required properties: 13 - 14 - - compatible : should be "brcm,bcm2835-armctrl-ic" or 15 - "brcm,bcm2836-armctrl-ic" 16 - - reg : Specifies base physical address and size of the registers. 17 - - interrupt-controller : Identifies the node as an interrupt controller 18 - - #interrupt-cells : Specifies the number of cells needed to encode an 19 - interrupt source. The value shall be 2. 20 - 21 - The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic 22 - pending" register, or 1/2 respectively for interrupts in the "IRQ pending 23 - 1/2" register. 24 - 25 - The 2nd cell contains the interrupt number within the bank. Valid values 26 - are 0..7 for bank 0, and 0..31 for bank 1. 27 - 28 - Additional required properties for brcm,bcm2836-armctrl-ic: 29 - - interrupts : Specifies the interrupt on the parent for this interrupt 30 - controller to handle. 31 - 32 - The interrupt sources are as follows: 33 - 34 - Bank 0: 35 - 0: ARM_TIMER 36 - 1: ARM_MAILBOX 37 - 2: ARM_DOORBELL_0 38 - 3: ARM_DOORBELL_1 39 - 4: VPU0_HALTED 40 - 5: VPU1_HALTED 41 - 6: ILLEGAL_TYPE0 42 - 7: ILLEGAL_TYPE1 43 - 44 - Bank 1: 45 - 0: TIMER0 46 - 1: TIMER1 47 - 2: TIMER2 48 - 3: TIMER3 49 - 4: CODEC0 50 - 5: CODEC1 51 - 6: CODEC2 52 - 7: VC_JPEG 53 - 8: ISP 54 - 9: VC_USB 55 - 10: VC_3D 56 - 11: TRANSPOSER 57 - 12: MULTICORESYNC0 58 - 13: MULTICORESYNC1 59 - 14: MULTICORESYNC2 60 - 15: MULTICORESYNC3 61 - 16: DMA0 62 - 17: DMA1 63 - 18: VC_DMA2 64 - 19: VC_DMA3 65 - 20: DMA4 66 - 21: DMA5 67 - 22: DMA6 68 - 23: DMA7 69 - 24: DMA8 70 - 25: DMA9 71 - 26: DMA10 72 - 27: DMA11-14 - shared interrupt for DMA 11 to 14 73 - 28: DMAALL - triggers on all dma interrupts (including channel 15) 74 - 29: AUX 75 - 30: ARM 76 - 31: VPUDMA 77 - 78 - Bank 2: 79 - 0: HOSTPORT 80 - 1: VIDEOSCALER 81 - 2: CCP2TX 82 - 3: SDC 83 - 4: DSI0 84 - 5: AVE 85 - 6: CAM0 86 - 7: CAM1 87 - 8: HDMI0 88 - 9: HDMI1 89 - 10: PIXELVALVE1 90 - 11: I2CSPISLV 91 - 12: DSI1 92 - 13: PWA0 93 - 14: PWA1 94 - 15: CPR 95 - 16: SMI 96 - 17: GPIO0 97 - 18: GPIO1 98 - 19: GPIO2 99 - 20: GPIO3 100 - 21: VC_I2C 101 - 22: VC_SPI 102 - 23: VC_I2SPCM 103 - 24: VC_SDIO 104 - 25: VC_UART 105 - 26: SLIMBUS 106 - 27: VEC 107 - 28: CPG 108 - 29: RNG 109 - 30: VC_ARASANSDIO 110 - 31: AVSPMON 111 - 112 - Example: 113 - 114 - /* BCM2835, first level */ 115 - intc: interrupt-controller { 116 - compatible = "brcm,bcm2835-armctrl-ic"; 117 - reg = <0x7e00b200 0x200>; 118 - interrupt-controller; 119 - #interrupt-cells = <2>; 120 - }; 121 - 122 - /* BCM2836, second level */ 123 - intc: interrupt-controller { 124 - compatible = "brcm,bcm2836-armctrl-ic"; 125 - reg = <0x7e00b200 0x200>; 126 - interrupt-controller; 127 - #interrupt-cells = <2>; 128 - 129 - interrupt-parent = <&local_intc>; 130 - interrupts = <8>; 131 - };

+162

Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.yaml

··· 1 + %YAML 1.2 2 + --- 3 + $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2835-armctrl-ic.yaml# 4 + $schema: http://devicetree.org/meta-schemas/core.yaml# 5 + 6 + title: BCM2835 ARMCTRL Interrupt Controller 7 + 8 + maintainers: 9 + - Florian Fainelli <florian.fainelli@broadcom.com> 10 + - Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com> 11 + 12 + description: > 13 + The BCM2835 contains a custom top-level interrupt controller, which supports 14 + 72 interrupt sources using a 2-level register scheme. The interrupt 15 + controller, or the HW block containing it, is referred to occasionally as 16 + "armctrl" in the SoC documentation, hence naming of this binding. 17 + 18 + The BCM2836 contains the same interrupt controller with the same interrupts, 19 + but the per-CPU interrupt controller is the root, and an interrupt there 20 + indicates that the ARMCTRL has an interrupt to handle. 21 + 22 + The interrupt sources are as follows: 23 + 24 + Bank 0: 25 + 0: ARM_TIMER 26 + 1: ARM_MAILBOX 27 + 2: ARM_DOORBELL_0 28 + 3: ARM_DOORBELL_1 29 + 4: VPU0_HALTED 30 + 5: VPU1_HALTED 31 + 6: ILLEGAL_TYPE0 32 + 7: ILLEGAL_TYPE1 33 + 34 + Bank 1: 35 + 0: TIMER0 36 + 1: TIMER1 37 + 2: TIMER2 38 + 3: TIMER3 39 + 4: CODEC0 40 + 5: CODEC1 41 + 6: CODEC2 42 + 7: VC_JPEG 43 + 8: ISP 44 + 9: VC_USB 45 + 10: VC_3D 46 + 11: TRANSPOSER 47 + 12: MULTICORESYNC0 48 + 13: MULTICORESYNC1 49 + 14: MULTICORESYNC2 50 + 15: MULTICORESYNC3 51 + 16: DMA0 52 + 17: DMA1 53 + 18: VC_DMA2 54 + 19: VC_DMA3 55 + 20: DMA4 56 + 21: DMA5 57 + 22: DMA6 58 + 23: DMA7 59 + 24: DMA8 60 + 25: DMA9 61 + 26: DMA10 62 + 27: DMA11-14 - shared interrupt for DMA 11 to 14 63 + 28: DMAALL - triggers on all dma interrupts (including channel 15) 64 + 29: AUX 65 + 30: ARM 66 + 31: VPUDMA 67 + 68 + Bank 2: 69 + 0: HOSTPORT 70 + 1: VIDEOSCALER 71 + 2: CCP2TX 72 + 3: SDC 73 + 4: DSI0 74 + 5: AVE 75 + 6: CAM0 76 + 7: CAM1 77 + 8: HDMI0 78 + 9: HDMI1 79 + 10: PIXELVALVE1 80 + 11: I2CSPISLV 81 + 12: DSI1 82 + 13: PWA0 83 + 14: PWA1 84 + 15: CPR 85 + 16: SMI 86 + 17: GPIO0 87 + 18: GPIO1 88 + 19: GPIO2 89 + 20: GPIO3 90 + 21: VC_I2C 91 + 22: VC_SPI 92 + 23: VC_I2SPCM 93 + 24: VC_SDIO 94 + 25: VC_UART 95 + 26: SLIMBUS 96 + 27: VEC 97 + 28: CPG 98 + 29: RNG 99 + 30: VC_ARASANSDIO 100 + 31: AVSPMON 101 + 102 + properties: 103 + compatible: 104 + enum: 105 + - brcm,bcm2835-armctrl-ic 106 + - brcm,bcm2836-armctrl-ic 107 + 108 + reg: 109 + maxItems: 1 110 + 111 + interrupt-controller: true 112 + 113 + '#interrupt-cells': 114 + const: 2 115 + description: > 116 + The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic 117 + pending" register, or 1/2 respectively for interrupts in the "IRQ pending 118 + 1/2" register. 119 + 120 + The 2nd cell contains the interrupt number within the bank. Valid values 121 + are 0..7 for bank 0, and 0..31 for bank 1. 122 + 123 + interrupts: 124 + maxItems: 1 125 + 126 + required: 127 + - compatible 128 + - reg 129 + - interrupt-controller 130 + - '#interrupt-cells' 131 + 132 + allOf: 133 + - if: 134 + properties: 135 + compatible: 136 + contains: 137 + const: brcm,bcm2836-armctrl-ic 138 + then: 139 + required: 140 + - interrupts 141 + else: 142 + properties: 143 + interrupts: false 144 + 145 + additionalProperties: false 146 + 147 + examples: 148 + - | 149 + interrupt-controller@7e00b200 { 150 + compatible = "brcm,bcm2835-armctrl-ic"; 151 + reg = <0x7e00b200 0x200>; 152 + interrupt-controller; 153 + #interrupt-cells = <2>; 154 + }; 155 + - | 156 + interrupt-controller@7e00b200 { 157 + compatible = "brcm,bcm2836-armctrl-ic"; 158 + reg = <0x7e00b200 0x200>; 159 + interrupt-controller; 160 + #interrupt-cells = <2>; 161 + interrupts = <8>; 162 + };

-55

Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-l1-intc.txt

··· 1 - Broadcom BCM6345-style Level 1 interrupt controller 2 - 3 - This block is a first level interrupt controller that is typically connected 4 - directly to one of the HW INT lines on each CPU. 5 - 6 - Key elements of the hardware design include: 7 - 8 - - 32, 64 or 128 incoming level IRQ lines 9 - 10 - - Most onchip peripherals are wired directly to an L1 input 11 - 12 - - A separate instance of the register set for each CPU, allowing individual 13 - peripheral IRQs to be routed to any CPU 14 - 15 - - Contains one or more enable/status word pairs per CPU 16 - 17 - - No atomic set/clear operations 18 - 19 - - No polarity/level/edge settings 20 - 21 - - No FIFO or priority encoder logic; software is expected to read all 22 - 2-4 status words to determine which IRQs are pending 23 - 24 - Required properties: 25 - 26 - - compatible: should be "brcm,bcm<soc>-l1-intc", "brcm,bcm6345-l1-intc" 27 - - reg: specifies the base physical address and size of the registers; 28 - the number of supported IRQs is inferred from the size argument 29 - - interrupt-controller: identifies the node as an interrupt controller 30 - - #interrupt-cells: specifies the number of cells needed to encode an interrupt 31 - source, should be 1. 32 - - interrupts: specifies the interrupt line(s) in the interrupt-parent controller 33 - node; valid values depend on the type of parent interrupt controller 34 - 35 - If multiple reg ranges and interrupt-parent entries are present on an SMP 36 - system, the driver will allow IRQ SMP affinity to be set up through the 37 - /proc/irq/ interface. In the simplest possible configuration, only one 38 - reg range and one interrupt-parent is needed. 39 - 40 - The driver operates in native CPU endian by default, there is no support for 41 - specifying an alternative endianness. 42 - 43 - Example: 44 - 45 - periph_intc: interrupt-controller@10000000 { 46 - compatible = "brcm,bcm63168-l1-intc", "brcm,bcm6345-l1-intc"; 47 - reg = <0x10000020 0x20>, 48 - <0x10000040 0x20>; 49 - 50 - interrupt-controller; 51 - #interrupt-cells = <1>; 52 - 53 - interrupt-parent = <&cpu_intc>; 54 - interrupts = <2>, <3>; 55 - };

+81

Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-l1-intc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm6345-l1-intc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Broadcom BCM6345-style Level 1 interrupt controller 8 + 9 + maintainers: 10 + - Simon Arlott <simon@octiron.net> 11 + 12 + description: > 13 + This block is a first level interrupt controller that is typically connected 14 + directly to one of the HW INT lines on each CPU. 15 + 16 + Key elements of the hardware design include: 17 + 18 + - 32, 64 or 128 incoming level IRQ lines 19 + 20 + - Most onchip peripherals are wired directly to an L1 input 21 + 22 + - A separate instance of the register set for each CPU, allowing individual 23 + peripheral IRQs to be routed to any CPU 24 + 25 + - Contains one or more enable/status word pairs per CPU 26 + 27 + - No atomic set/clear operations 28 + 29 + - No polarity/level/edge settings 30 + 31 + - No FIFO or priority encoder logic; software is expected to read all 32 + 2-4 status words to determine which IRQs are pending 33 + 34 + If multiple reg ranges and interrupt-parent entries are present on an SMP 35 + system, the driver will allow IRQ SMP affinity to be set up through the 36 + /proc/irq/ interface. In the simplest possible configuration, only one 37 + reg range and one interrupt-parent is needed. 38 + 39 + The driver operates in native CPU endian by default, there is no support for 40 + specifying an alternative endianness. 41 + 42 + properties: 43 + compatible: 44 + const: brcm,bcm6345-l1-intc 45 + 46 + reg: 47 + description: One entry per CPU core 48 + minItems: 1 49 + maxItems: 2 50 + 51 + interrupt-controller: true 52 + 53 + "#interrupt-cells": 54 + const: 1 55 + 56 + interrupts: 57 + description: One entry per CPU core 58 + minItems: 1 59 + maxItems: 2 60 + 61 + required: 62 + - compatible 63 + - reg 64 + - interrupt-controller 65 + - '#interrupt-cells' 66 + - interrupts 67 + 68 + additionalProperties: false 69 + 70 + examples: 71 + - | 72 + interrupt-controller@10000000 { 73 + compatible = "brcm,bcm6345-l1-intc"; 74 + reg = <0x10000020 0x20>, 75 + <0x10000040 0x20>; 76 + 77 + interrupt-controller; 78 + #interrupt-cells = <1>; 79 + 80 + interrupts = <2>, <3>; 81 + };

-18

Documentation/devicetree/bindings/interrupt-controller/cdns,xtensa-mx.txt

··· 1 - * Xtensa Interrupt Distributor and Programmable Interrupt Controller (MX) 2 - 3 - Required properties: 4 - - compatible: Should be "cdns,xtensa-mx". 5 - 6 - Remaining properties have exact same meaning as in Xtensa PIC 7 - (see cdns,xtensa-pic.txt). 8 - 9 - Examples: 10 - pic: pic { 11 - compatible = "cdns,xtensa-mx"; 12 - /* one cell: internal irq number, 13 - * two cells: second cell == 0: internal irq number 14 - * second cell == 1: external irq number 15 - */ 16 - #interrupt-cells = <2>; 17 - interrupt-controller; 18 - };

-25

Documentation/devicetree/bindings/interrupt-controller/cdns,xtensa-pic.txt

··· 1 - * Xtensa built-in Programmable Interrupt Controller (PIC) 2 - 3 - Required properties: 4 - - compatible: Should be "cdns,xtensa-pic". 5 - - interrupt-controller: Identifies the node as an interrupt controller. 6 - - #interrupt-cells: The number of cells to define the interrupts. 7 - It may be either 1 or 2. 8 - When it's 1, the first cell is the internal IRQ number. 9 - When it's 2, the first cell is the IRQ number, and the second cell 10 - specifies whether it's internal (0) or external (1). 11 - Periferals are usually connected to a fixed external IRQ, but for different 12 - core variants it may be mapped to different internal IRQ. 13 - IRQ sensitivity and priority are fixed for each core variant and may not be 14 - changed at runtime. 15 - 16 - Examples: 17 - pic: pic { 18 - compatible = "cdns,xtensa-pic"; 19 - /* one cell: internal irq number, 20 - * two cells: second cell == 0: internal irq number 21 - * second cell == 1: external irq number 22 - */ 23 - #interrupt-cells = <2>; 24 - interrupt-controller; 25 - };

+50

Documentation/devicetree/bindings/interrupt-controller/cdns,xtensa-pic.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + # Copyright 2025 Max Filippov <jcmvbkbc@gmail.com> 3 + 4 + %YAML 1.2 5 + --- 6 + $id: http://devicetree.org/schemas/interrupt-controller/cdns,xtensa-pic.yaml# 7 + $schema: http://devicetree.org/meta-schemas/core.yaml# 8 + 9 + title: Xtensa Interrupt Controllers 10 + 11 + maintainers: 12 + - Max Filippov <jcmvbkbc@gmail.com> 13 + 14 + description: 15 + Xtensa Interrupt Distributor and Programmable Interrupt Controller (MX) and 16 + Xtensa built-in Programmable Interrupt Controller (PIC) 17 + 18 + properties: 19 + compatible: 20 + enum: 21 + - cdns,xtensa-mx 22 + - cdns,xtensa-pic 23 + 24 + '#interrupt-cells': 25 + enum: [ 1, 2 ] 26 + description: 27 + Number of cells to define the interrupts. When 1, the first cell is the 28 + internal IRQ number; when 2, the second cell specifies internal (0) or 29 + external (1). 30 + 31 + interrupt-controller: true 32 + 33 + required: 34 + - compatible 35 + - '#interrupt-cells' 36 + - interrupt-controller 37 + 38 + additionalProperties: false 39 + 40 + examples: 41 + - | 42 + interrupt-controller { 43 + compatible = "cdns,xtensa-pic"; 44 + /* one cell: internal irq number, 45 + * two cells: second cell == 0: internal irq number 46 + * second cell == 1: external irq number 47 + */ 48 + #interrupt-cells = <2>; 49 + interrupt-controller; 50 + };

+63

Documentation/devicetree/bindings/interrupt-controller/chrp,open-pic.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/chrp,open-pic.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Open PIC Interrupt Controller 8 + 9 + maintainers: 10 + - Rob Herring <robh@kernel.org> 11 + 12 + description: 13 + This binding specifies what properties must be available in the device tree 14 + representation of an Open PIC compliant interrupt controller. This binding is 15 + based on the binding defined for Open PIC in [1] and is a superset of that 16 + binding. 17 + 18 + properties: 19 + compatible: 20 + oneOf: 21 + - items: 22 + - const: fsl,mpic 23 + - const: chrp,open-pic 24 + - const: chrp,open-pic 25 + 26 + device_type: 27 + const: open-pci 28 + deprecated: true 29 + 30 + reg: 31 + maxItems: 1 32 + 33 + interrupt-controller: true 34 + 35 + '#address-cells': 36 + const: 0 37 + 38 + '#interrupt-cells': 39 + const: 2 40 + 41 + pic-no-reset: 42 + description: Indicates the PIC shall not be reset during runtime initialization. 43 + type: boolean 44 + 45 + required: 46 + - compatible 47 + - reg 48 + - interrupt-controller 49 + - '#address-cells' 50 + - '#interrupt-cells' 51 + 52 + additionalProperties: false 53 + 54 + examples: 55 + - | 56 + interrupt-controller@40000 { 57 + compatible = "chrp,open-pic"; 58 + reg = <0x40000 0x40000>; 59 + interrupt-controller; 60 + #address-cells = <0>; 61 + #interrupt-cells = <2>; 62 + pic-no-reset; 63 + };

-41

Documentation/devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt

··· 1 - Cirrus Logic CLPS711X Interrupt Controller 2 - 3 - Required properties: 4 - 5 - - compatible: Should be "cirrus,ep7209-intc". 6 - - reg: Specifies base physical address of the registers set. 7 - - interrupt-controller: Identifies the node as an interrupt controller. 8 - - #interrupt-cells: Specifies the number of cells needed to encode an 9 - interrupt source. The value shall be 1. 10 - 11 - The interrupt sources are as follows: 12 - ID Name Description 13 - --------------------------- 14 - 1: BLINT Battery low (FIQ) 15 - 3: MCINT Media changed (FIQ) 16 - 4: CSINT CODEC sound 17 - 5: EINT1 External 1 18 - 6: EINT2 External 2 19 - 7: EINT3 External 3 20 - 8: TC1OI TC1 under flow 21 - 9: TC2OI TC2 under flow 22 - 10: RTCMI RTC compare match 23 - 11: TINT 64Hz tick 24 - 12: UTXINT1 UART1 transmit FIFO half empty 25 - 13: URXINT1 UART1 receive FIFO half full 26 - 14: UMSINT UART1 modem status changed 27 - 15: SSEOTI SSI1 end of transfer 28 - 16: KBDINT Keyboard 29 - 17: SS2RX SSI2 receive FIFO half or greater full 30 - 18: SS2TX SSI2 transmit FIFO less than half empty 31 - 28: UTXINT2 UART2 transmit FIFO half empty 32 - 29: URXINT2 UART2 receive FIFO half full 33 - 32: DAIINT DAI interface (FIQ) 34 - 35 - Example: 36 - intc: interrupt-controller { 37 - compatible = "cirrus,ep7312-intc", "cirrus,ep7209-intc"; 38 - reg = <0x80000000 0x4000>; 39 - interrupt-controller; 40 - #interrupt-cells = <1>; 41 - };

+71

Documentation/devicetree/bindings/interrupt-controller/cirrus,ep7209-intc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/cirrus,ep7209-intc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Cirrus Logic CLPS711X Interrupt Controller 8 + 9 + maintainers: 10 + - Alexander Shiyan <shc_work@mail.ru> 11 + 12 + description: > 13 + Cirrus Logic CLPS711X Interrupt Controller 14 + 15 + The interrupt sources are as follows: 16 + ID Name Description 17 + --------------------------- 18 + 1: BLINT Battery low (FIQ) 19 + 3: MCINT Media changed (FIQ) 20 + 4: CSINT CODEC sound 21 + 5: EINT1 External 1 22 + 6: EINT2 External 2 23 + 7: EINT3 External 3 24 + 8: TC1OI TC1 under flow 25 + 9: TC2OI TC2 under flow 26 + 10: RTCMI RTC compare match 27 + 11: TINT 64Hz tick 28 + 12: UTXINT1 UART1 transmit FIFO half empty 29 + 13: URXINT1 UART1 receive FIFO half full 30 + 14: UMSINT UART1 modem status changed 31 + 15: SSEOTI SSI1 end of transfer 32 + 16: KBDINT Keyboard 33 + 17: SS2RX SSI2 receive FIFO half or greater full 34 + 18: SS2TX SSI2 transmit FIFO less than half empty 35 + 28: UTXINT2 UART2 transmit FIFO half empty 36 + 29: URXINT2 UART2 receive FIFO half full 37 + 32: DAIINT DAI interface (FIQ) 38 + 39 + properties: 40 + compatible: 41 + oneOf: 42 + - items: 43 + - const: cirrus,ep7312-intc 44 + - const: cirrus,ep7209-intc 45 + - items: 46 + - const: cirrus,ep7209-intc 47 + 48 + reg: 49 + maxItems: 1 50 + 51 + interrupt-controller: true 52 + 53 + '#interrupt-cells': 54 + const: 1 55 + 56 + required: 57 + - compatible 58 + - reg 59 + - interrupt-controller 60 + - '#interrupt-cells' 61 + 62 + additionalProperties: false 63 + 64 + examples: 65 + - | 66 + interrupt-controller@80000000 { 67 + compatible = "cirrus,ep7312-intc", "cirrus,ep7209-intc"; 68 + reg = <0x80000000 0x4000>; 69 + interrupt-controller; 70 + #interrupt-cells = <1>; 71 + };

+47

Documentation/devicetree/bindings/interrupt-controller/cnxt,cx92755-ic.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/cnxt,cx92755-ic.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Conexant Digicolor Interrupt Controller 8 + 9 + maintainers: 10 + - Baruch Siach <baruch@tkos.co.il> 11 + 12 + description: Conexant Digicolor Interrupt Controller 13 + 14 + properties: 15 + compatible: 16 + const: cnxt,cx92755-ic 17 + 18 + reg: 19 + maxItems: 1 20 + 21 + interrupt-controller: true 22 + 23 + '#interrupt-cells': 24 + const: 1 25 + 26 + syscon: 27 + description: A phandle to the syscon node describing UC registers 28 + $ref: /schemas/types.yaml#/definitions/phandle 29 + 30 + required: 31 + - compatible 32 + - reg 33 + - interrupt-controller 34 + - '#interrupt-cells' 35 + - syscon 36 + 37 + additionalProperties: false 38 + 39 + examples: 40 + - | 41 + interrupt-controller@f0000040 { 42 + compatible = "cnxt,cx92755-ic"; 43 + interrupt-controller; 44 + #interrupt-cells = <1>; 45 + reg = <0xf0000040 0x40>; 46 + syscon = <&uc_regs>; 47 + };

-62

Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt

··· 1 - ============================== 2 - C-SKY APB Interrupt Controller 3 - ============================== 4 - 5 - C-SKY APB Interrupt Controller is a simple soc interrupt controller 6 - on the apb bus and we only use it as root irq controller. 7 - 8 - - csky,apb-intc is used in a lot of csky fpgas and socs, it support 64 irq nums. 9 - - csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported. 10 - - csky,gx6605s-intc is gx6605s soc internal irq interrupt controller, 64 irq nums. 11 - 12 - ============================= 13 - intc node bindings definition 14 - ============================= 15 - 16 - Description: Describes APB interrupt controller 17 - 18 - PROPERTIES 19 - 20 - - compatible 21 - Usage: required 22 - Value type: <string> 23 - Definition: must be "csky,apb-intc" 24 - "csky,dual-apb-intc" 25 - "csky,gx6605s-intc" 26 - - #interrupt-cells 27 - Usage: required 28 - Value type: <u32> 29 - Definition: must be <1> 30 - - reg 31 - Usage: required 32 - Value type: <u32 u32> 33 - Definition: <phyaddr size> in soc from cpu view 34 - - interrupt-controller: 35 - Usage: required 36 - - csky,support-pulse-signal: 37 - Usage: select 38 - Description: to support pulse signal flag 39 - 40 - Examples: 41 - --------- 42 - 43 - intc: interrupt-controller@500000 { 44 - compatible = "csky,apb-intc"; 45 - #interrupt-cells = <1>; 46 - reg = <0x00500000 0x400>; 47 - interrupt-controller; 48 - }; 49 - 50 - intc: interrupt-controller@500000 { 51 - compatible = "csky,dual-apb-intc"; 52 - #interrupt-cells = <1>; 53 - reg = <0x00500000 0x400>; 54 - interrupt-controller; 55 - }; 56 - 57 - intc: interrupt-controller@500000 { 58 - compatible = "csky,gx6605s-intc"; 59 - #interrupt-cells = <1>; 60 - reg = <0x00500000 0x400>; 61 - interrupt-controller; 62 - };

+54

Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/csky,apb-intc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: C-SKY APB Interrupt Controller 8 + 9 + maintainers: 10 + - Guo Ren <guoren@kernel.org> 11 + 12 + description: > 13 + C-SKY APB Interrupt Controller is a simple soc interrupt controller on the apb 14 + bus and we only use it as root irq controller. 15 + 16 + - csky,apb-intc is used in a lot of csky fpgas and socs, it support 64 irq nums. 17 + - csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported. 18 + - csky,gx6605s-intc is gx6605s soc internal irq interrupt controller, 64 irq nums. 19 + 20 + properties: 21 + compatible: 22 + enum: 23 + - csky,apb-intc 24 + - csky,dual-apb-intc 25 + - csky,gx6605s-intc 26 + 27 + reg: 28 + maxItems: 1 29 + 30 + '#interrupt-cells': 31 + const: 1 32 + 33 + interrupt-controller: true 34 + 35 + csky,support-pulse-signal: 36 + type: boolean 37 + description: Support for pulse signal flag. 38 + 39 + additionalProperties: false 40 + 41 + required: 42 + - compatible 43 + - reg 44 + - '#interrupt-cells' 45 + - interrupt-controller 46 + 47 + examples: 48 + - | 49 + intc: interrupt-controller@500000 { 50 + compatible = "csky,apb-intc"; 51 + #interrupt-cells = <1>; 52 + reg = <0x00500000 0x400>; 53 + interrupt-controller; 54 + };

-52

Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt

··· 1 - =========================================== 2 - C-SKY Multi-processors Interrupt Controller 3 - =========================================== 4 - 5 - C-SKY Multi-processors Interrupt Controller is designed for ck807/ck810/ck860 6 - SMP soc, and it also could be used in non-SMP system. 7 - 8 - Interrupt number definition: 9 - 0-15 : software irq, and we use 15 as our IPI_IRQ. 10 - 16-31 : private irq, and we use 16 as the co-processor timer. 11 - 31-1024: common irq for soc ip. 12 - 13 - Interrupt trigger mode: (Defined in dt-bindings/interrupt-controller/irq.h) 14 - IRQ_TYPE_LEVEL_HIGH (default) 15 - IRQ_TYPE_LEVEL_LOW 16 - IRQ_TYPE_EDGE_RISING 17 - IRQ_TYPE_EDGE_FALLING 18 - 19 - ============================= 20 - intc node bindings definition 21 - ============================= 22 - 23 - Description: Describes SMP interrupt controller 24 - 25 - PROPERTIES 26 - 27 - - compatible 28 - Usage: required 29 - Value type: <string> 30 - Definition: must be "csky,mpintc" 31 - - #interrupt-cells 32 - Usage: required 33 - Value type: <u32> 34 - Definition: <2> 35 - - interrupt-controller: 36 - Usage: required 37 - 38 - Examples: ("interrupts = <irq_num IRQ_TYPE_XXX>") 39 - --------- 40 - #include <dt-bindings/interrupt-controller/irq.h> 41 - 42 - intc: interrupt-controller { 43 - compatible = "csky,mpintc"; 44 - #interrupt-cells = <2>; 45 - interrupt-controller; 46 - }; 47 - 48 - device: device-example { 49 - ... 50 - interrupts = <34 IRQ_TYPE_EDGE_RISING>; 51 - interrupt-parent = <&intc>; 52 - };

+43

Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/csky,mpintc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: C-SKY Multi-processors Interrupt Controller 8 + 9 + maintainers: 10 + - Guo Ren <guoren@kernel.org> 11 + 12 + description: > 13 + C-SKY Multi-processors Interrupt Controller is designed for ck807/ck810/ck860 14 + SMP soc, and it also could be used in non-SMP system. 15 + 16 + Interrupt number definition: 17 + 0-15 : software irq, and we use 15 as our IPI_IRQ. 18 + 16-31 : private irq, and we use 16 as the co-processor timer. 19 + 31-1024: common irq for soc ip. 20 + 21 + properties: 22 + compatible: 23 + const: csky,mpintc 24 + 25 + '#interrupt-cells': 26 + const: 2 27 + 28 + interrupt-controller: true 29 + 30 + required: 31 + - compatible 32 + - "#interrupt-cells" 33 + - interrupt-controller 34 + 35 + additionalProperties: false 36 + 37 + examples: 38 + - | 39 + interrupt-controller { 40 + compatible = "csky,mpintc"; 41 + #interrupt-cells = <2>; 42 + interrupt-controller; 43 + };

-21

Documentation/devicetree/bindings/interrupt-controller/digicolor-ic.txt

··· 1 - Conexant Digicolor Interrupt Controller 2 - 3 - Required properties: 4 - 5 - - compatible : should be "cnxt,cx92755-ic" 6 - - reg : Specifies base physical address and size of the interrupt controller 7 - registers (IC) area 8 - - interrupt-controller : Identifies the node as an interrupt controller 9 - - #interrupt-cells : Specifies the number of cells needed to encode an 10 - interrupt source. The value shall be 1. 11 - - syscon: A phandle to the syscon node describing UC registers 12 - 13 - Example: 14 - 15 - intc: interrupt-controller@f0000040 { 16 - compatible = "cnxt,cx92755-ic"; 17 - interrupt-controller; 18 - #interrupt-cells = <1>; 19 - reg = <0xf0000040 0x40>; 20 - syscon = <&uc_regs>; 21 - };

-17

Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt

··· 1 - EZchip NPS Interrupt Controller 2 - 3 - Required properties: 4 - 5 - - compatible : should be "ezchip,nps400-ic" 6 - - interrupt-controller : Identifies the node as an interrupt controller 7 - - #interrupt-cells : Specifies the number of cells needed to encode an 8 - interrupt source. The value shall be 1. 9 - 10 - 11 - Example: 12 - 13 - intc: interrupt-controller { 14 - compatible = "ezchip,nps400-ic"; 15 - interrupt-controller; 16 - #interrupt-cells = <1>; 17 - };

+34

Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/ezchip,nps400-ic.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: EZchip NPS Interrupt Controller 8 + 9 + maintainers: 10 + - Noam Camus <noamc@ezchip.com> 11 + 12 + properties: 13 + compatible: 14 + const: ezchip,nps400-ic 15 + 16 + interrupt-controller: true 17 + 18 + '#interrupt-cells': 19 + const: 1 20 + 21 + required: 22 + - compatible 23 + - interrupt-controller 24 + - '#interrupt-cells' 25 + 26 + additionalProperties: false 27 + 28 + examples: 29 + - | 30 + interrupt-controller { 31 + compatible = "ezchip,nps400-ic"; 32 + interrupt-controller; 33 + #interrupt-cells = <1>; 34 + };

-25

Documentation/devicetree/bindings/interrupt-controller/faraday,ftintc010.txt

··· 1 - * Faraday Technologt FTINTC010 interrupt controller 2 - 3 - This interrupt controller is a stock IP block from Faraday Technology found 4 - in the Gemini SoCs and other designs. 5 - 6 - Required properties: 7 - - compatible: must be one of 8 - "faraday,ftintc010" 9 - "cortina,gemini-interrupt-controller" (deprecated) 10 - - reg: The register bank for the interrupt controller. 11 - - interrupt-controller: Identifies the node as an interrupt controller 12 - - #interrupt-cells: The number of cells to define the interrupts. 13 - Must be 2 as the controller can specify level or rising edge 14 - IRQs. The bindings follows the standard binding for controllers 15 - with two cells specified in 16 - interrupt-controller/interrupts.txt 17 - 18 - Example: 19 - 20 - interrupt-controller@48000000 { 21 - compatible = "faraday,ftintc010" 22 - reg = <0x48000000 0x1000>; 23 - interrupt-controller; 24 - #interrupt-cells = <2>; 25 - };

+51

Documentation/devicetree/bindings/interrupt-controller/faraday,ftintc010.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + --- 3 + $id: http://devicetree.org/schemas/interrupt-controller/faraday,ftintc010.yaml# 4 + $schema: http://devicetree.org/meta-schemas/core.yaml# 5 + 6 + title: Faraday Technology FTINTC010 interrupt controller 7 + 8 + maintainers: 9 + - Linus Walleij <linus.walleij@linaro.org> 10 + 11 + description: 12 + This interrupt controller is a stock IP block from Faraday Technology found 13 + in the Gemini SoCs and other designs. 14 + 15 + properties: 16 + compatible: 17 + oneOf: 18 + - items: 19 + - const: moxa,moxart-ic 20 + - const: faraday,ftintc010 21 + - enum: 22 + - faraday,ftintc010 23 + - cortina,gemini-interrupt-controller 24 + 25 + reg: 26 + maxItems: 1 27 + 28 + interrupt-controller: true 29 + 30 + '#interrupt-cells': 31 + const: 2 32 + 33 + resets: 34 + maxItems: 1 35 + 36 + required: 37 + - compatible 38 + - reg 39 + - interrupt-controller 40 + - '#interrupt-cells' 41 + 42 + additionalProperties: false 43 + 44 + examples: 45 + - | 46 + interrupt-controller@48000000 { 47 + compatible = "faraday,ftintc010"; 48 + reg = <0x48000000 0x1000>; 49 + interrupt-controller; 50 + #interrupt-cells = <2>; 51 + };

+48

Documentation/devicetree/bindings/interrupt-controller/fsl,tzic.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/fsl,tzic.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Freescale tzic Interrupt controller 8 + 9 + maintainers: 10 + - Frank Li <Frank.Li@nxp.com> 11 + 12 + properties: 13 + compatible: 14 + oneOf: 15 + - items: 16 + - enum: 17 + - fsl,imx51-tzic 18 + - fsl,imx53-tzic 19 + - const: fsl,tzic 20 + - items: 21 + - const: fsl,imx50-tzic 22 + - const: fsl,imx53-tzic 23 + - const: fsl,tzic 24 + 25 + reg: 26 + maxItems: 1 27 + 28 + interrupt-controller: true 29 + 30 + '#interrupt-cells': 31 + const: 1 32 + 33 + required: 34 + - compatible 35 + - reg 36 + - interrupt-controller 37 + - '#interrupt-cells' 38 + 39 + additionalProperties: false 40 + 41 + examples: 42 + - | 43 + tz-interrupt-controller@fffc000 { 44 + compatible = "fsl,imx53-tzic", "fsl,tzic"; 45 + reg = <0x0fffc000 0x4000>; 46 + interrupt-controller; 47 + #interrupt-cells = <1>; 48 + };

-30

Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.txt

··· 1 - Android Goldfish PIC 2 - 3 - Android Goldfish programmable interrupt device used by Android 4 - emulator. 5 - 6 - Required properties: 7 - 8 - - compatible : should contain "google,goldfish-pic" 9 - - reg : <registers mapping> 10 - - interrupts : <interrupt mapping> 11 - 12 - Example for mips when used in cascade mode: 13 - 14 - cpuintc { 15 - #interrupt-cells = <0x1>; 16 - #address-cells = <0>; 17 - interrupt-controller; 18 - compatible = "mti,cpu-interrupt-controller"; 19 - }; 20 - 21 - interrupt-controller@1f000000 { 22 - compatible = "google,goldfish-pic"; 23 - reg = <0x1f000000 0x1000>; 24 - 25 - interrupt-controller; 26 - #interrupt-cells = <0x1>; 27 - 28 - interrupt-parent = <&cpuintc>; 29 - interrupts = <0x2>; 30 - };

+47

Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/google,goldfish-pic.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Android Goldfish PIC 8 + 9 + maintainers: 10 + - Miodrag Dinic <miodrag.dinic@mips.com> 11 + 12 + description: 13 + Android Goldfish programmable interrupt device used by Android emulator. 14 + 15 + properties: 16 + compatible: 17 + const: google,goldfish-pic 18 + 19 + reg: 20 + maxItems: 1 21 + 22 + interrupts: 23 + maxItems: 1 24 + 25 + interrupt-controller: true 26 + 27 + '#interrupt-cells': 28 + const: 1 29 + 30 + required: 31 + - compatible 32 + - reg 33 + - interrupts 34 + - interrupt-controller 35 + - '#interrupt-cells' 36 + 37 + examples: 38 + - | 39 + interrupt-controller@1f000000 { 40 + compatible = "google,goldfish-pic"; 41 + reg = <0x1f000000 0x1000>; 42 + interrupt-controller; 43 + #interrupt-cells = <1>; 44 + interrupts = <2>; 45 + }; 46 + 47 + additionalProperties: false

-105

Documentation/devicetree/bindings/interrupt-controller/img,pdc-intc.txt

··· 1 - * ImgTec Powerdown Controller (PDC) Interrupt Controller Binding 2 - 3 - This binding specifies what properties must be available in the device tree 4 - representation of a PDC IRQ controller. This has a number of input interrupt 5 - lines which can wake the system, and are passed on through output interrupt 6 - lines. 7 - 8 - Required properties: 9 - 10 - - compatible: Specifies the compatibility list for the interrupt controller. 11 - The type shall be <string> and the value shall include "img,pdc-intc". 12 - 13 - - reg: Specifies the base PDC physical address(s) and size(s) of the 14 - addressable register space. The type shall be <prop-encoded-array>. 15 - 16 - - interrupt-controller: The presence of this property identifies the node 17 - as an interrupt controller. No property value shall be defined. 18 - 19 - - #interrupt-cells: Specifies the number of cells needed to encode an 20 - interrupt source. The type shall be a <u32> and the value shall be 2. 21 - 22 - - num-perips: Number of waking peripherals. 23 - 24 - - num-syswakes: Number of SysWake inputs. 25 - 26 - - interrupts: List of interrupt specifiers. The first specifier shall be the 27 - shared SysWake interrupt, and remaining specifies shall be PDC peripheral 28 - interrupts in order. 29 - 30 - * Interrupt Specifier Definition 31 - 32 - Interrupt specifiers consists of 2 cells encoded as follows: 33 - 34 - - <1st-cell>: The interrupt-number that identifies the interrupt source. 35 - 0-7: Peripheral interrupts 36 - 8-15: SysWake interrupts 37 - 38 - - <2nd-cell>: The level-sense information, encoded using the Linux interrupt 39 - flags as follows (only 4 valid for peripheral interrupts): 40 - 0 = none (decided by software) 41 - 1 = low-to-high edge triggered 42 - 2 = high-to-low edge triggered 43 - 3 = both edge triggered 44 - 4 = active-high level-sensitive (required for perip irqs) 45 - 8 = active-low level-sensitive 46 - 47 - * Examples 48 - 49 - Example 1: 50 - 51 - /* 52 - * TZ1090 PDC block 53 - */ 54 - pdc: pdc@02006000 { 55 - // This is an interrupt controller node. 56 - interrupt-controller; 57 - 58 - // Three cells to encode interrupt sources. 59 - #interrupt-cells = <2>; 60 - 61 - // Offset address of 0x02006000 and size of 0x1000. 62 - reg = <0x02006000 0x1000>; 63 - 64 - // Compatible with Meta hardware trigger block. 65 - compatible = "img,pdc-intc"; 66 - 67 - // Three peripherals are connected. 68 - num-perips = <3>; 69 - 70 - // Four SysWakes are connected. 71 - num-syswakes = <4>; 72 - 73 - interrupts = <18 4 /* level */>, /* Syswakes */ 74 - <30 4 /* level */>, /* Peripheral 0 (RTC) */ 75 - <29 4 /* level */>, /* Peripheral 1 (IR) */ 76 - <31 4 /* level */>; /* Peripheral 2 (WDT) */ 77 - }; 78 - 79 - Example 2: 80 - 81 - /* 82 - * An SoC peripheral that is wired through the PDC. 83 - */ 84 - rtc0 { 85 - // The interrupt controller that this device is wired to. 86 - interrupt-parent = <&pdc>; 87 - 88 - // Interrupt source Peripheral 0 89 - interrupts = <0 /* Peripheral 0 (RTC) */ 90 - 4> /* IRQ_TYPE_LEVEL_HIGH */ 91 - }; 92 - 93 - Example 3: 94 - 95 - /* 96 - * An interrupt generating device that is wired to a SysWake pin. 97 - */ 98 - touchscreen0 { 99 - // The interrupt controller that this device is wired to. 100 - interrupt-parent = <&pdc>; 101 - 102 - // Interrupt source SysWake 0 that is active-low level-sensitive 103 - interrupts = <8 /* SysWake0 */ 104 - 8 /* IRQ_TYPE_LEVEL_LOW */>; 105 - };

+79

Documentation/devicetree/bindings/interrupt-controller/img,pdc-intc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/img,pdc-intc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: ImgTec Powerdown Controller (PDC) Interrupt Controller 8 + 9 + maintainers: 10 + - James Hogan <jhogan@kernel.org> 11 + 12 + description: 13 + ImgTec Powerdown Controller (PDC) Interrupt Controller has a number of input 14 + interrupt lines which can wake the system, and are passed on through output 15 + interrupt lines. 16 + 17 + properties: 18 + compatible: 19 + const: img,pdc-intc 20 + 21 + reg: 22 + maxItems: 1 23 + 24 + interrupt-controller: true 25 + 26 + '#interrupt-cells': 27 + description: > 28 + <1st-cell>: The interrupt-number that identifies the interrupt source. 29 + 0-7: Peripheral interrupts 30 + 8-15: SysWake interrupts 31 + 32 + <2nd-cell>: The level-sense information, encoded using the Linux interrupt 33 + flags as follows (only 4 valid for peripheral interrupts): 34 + 0 = none (decided by software) 35 + 1 = low-to-high edge triggered 36 + 2 = high-to-low edge triggered 37 + 3 = both edge triggered 38 + 4 = active-high level-sensitive (required for perip irqs) 39 + 8 = active-low level-sensitive 40 + const: 2 41 + 42 + num-perips: 43 + description: Number of waking peripherals 44 + $ref: /schemas/types.yaml#/definitions/uint32 45 + maximum: 8 46 + 47 + num-syswakes: 48 + description: Number of SysWake inputs 49 + $ref: /schemas/types.yaml#/definitions/uint32 50 + maximum: 8 51 + 52 + interrupts: 53 + description: 54 + First entry is syswake IRQ. Subsequent entries are 1 per peripheral. 55 + minItems: 2 56 + maxItems: 9 57 + 58 + required: 59 + - compatible 60 + - reg 61 + - interrupt-controller 62 + - '#interrupt-cells' 63 + - num-perips 64 + - num-syswakes 65 + - interrupts 66 + 67 + additionalProperties: false 68 + 69 + examples: 70 + - | 71 + interrupt-controller@2006000 { 72 + compatible = "img,pdc-intc"; 73 + reg = <0x02006000 0x1000>; 74 + interrupts = <18 4>, <30 4>, <29 4>, <31 4>; 75 + interrupt-controller; 76 + #interrupt-cells = <2>; 77 + num-perips = <3>; 78 + num-syswakes = <4>; 79 + };

-26

Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt

··· 1 - J-Core Advanced Interrupt Controller 2 - 3 - Required properties: 4 - 5 - - compatible: Should be "jcore,aic1" for the (obsolete) first-generation aic 6 - with 8 interrupt lines with programmable priorities, or "jcore,aic2" for 7 - the "aic2" core with 64 interrupts. 8 - 9 - - reg: Memory region(s) for configuration. For SMP, there should be one 10 - region per cpu, indexed by the sequential, zero-based hardware cpu 11 - number. 12 - 13 - - interrupt-controller: Identifies the node as an interrupt controller 14 - 15 - - #interrupt-cells: Specifies the number of cells needed to encode an 16 - interrupt source. The value shall be 1. 17 - 18 - 19 - Example: 20 - 21 - aic: interrupt-controller@200 { 22 - compatible = "jcore,aic2"; 23 - reg = < 0x200 0x30 0x500 0x30 >; 24 - interrupt-controller; 25 - #interrupt-cells = <1>; 26 - };

+43

Documentation/devicetree/bindings/interrupt-controller/jcore,aic.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + # Copyright 2018 Linaro Ltd. 3 + %YAML 1.2 4 + --- 5 + $id: http://devicetree.org/schemas/interrupt-controller/jcore,aic.yaml# 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 + 8 + title: J-Core Advanced Interrupt Controller 9 + 10 + maintainers: 11 + - Rich Felker <dalias@libc.org> 12 + 13 + properties: 14 + compatible: 15 + enum: 16 + - jcore,aic1 17 + - jcore,aic2 18 + 19 + reg: 20 + description: Memory region(s) for configuration. For SMP, there should be one 21 + region per CPU, indexed by the sequential, zero-based hardware CPU number. 22 + 23 + interrupt-controller: true 24 + 25 + '#interrupt-cells': 26 + const: 1 27 + 28 + required: 29 + - compatible 30 + - reg 31 + - interrupt-controller 32 + - '#interrupt-cells' 33 + 34 + additionalProperties: false 35 + 36 + examples: 37 + - | 38 + aic: interrupt-controller@200 { 39 + compatible = "jcore,aic2"; 40 + reg = <0x200 0x30>, <0x500 0x30>; 41 + interrupt-controller; 42 + #interrupt-cells = <1>; 43 + };

-18

Documentation/devicetree/bindings/interrupt-controller/lsi,zevio-intc.txt

··· 1 - TI-NSPIRE interrupt controller 2 - 3 - Required properties: 4 - - compatible: Compatible property value should be "lsi,zevio-intc". 5 - 6 - - reg: Physical base address of the controller and length of memory mapped 7 - region. 8 - 9 - - interrupt-controller : Identifies the node as an interrupt controller 10 - 11 - Example: 12 - 13 - interrupt-controller { 14 - compatible = "lsi,zevio-intc"; 15 - interrupt-controller; 16 - reg = <0xDC000000 0x1000>; 17 - #interrupt-cells = <1>; 18 - };

+43

Documentation/devicetree/bindings/interrupt-controller/lsi,zevio-intc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + # Copyright 2025 Daniel Tang <dt.tangr@gmail.com> 3 + %YAML 1.2 4 + --- 5 + $id: http://devicetree.org/schemas/interrupt-controller/lsi,zevio-intc.yaml# 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 + 8 + title: TI-NSPIRE Interrupt Controller 9 + 10 + maintainers: 11 + - Daniel Tang <dt.tangr@gmail.com> 12 + 13 + description: | 14 + TI-NSPIRE interrupt controller 15 + 16 + properties: 17 + compatible: 18 + const: lsi,zevio-intc 19 + 20 + reg: 21 + maxItems: 1 22 + 23 + interrupt-controller: true 24 + 25 + '#interrupt-cells': 26 + const: 1 27 + 28 + required: 29 + - compatible 30 + - reg 31 + - interrupt-controller 32 + - '#interrupt-cells' 33 + 34 + additionalProperties: false 35 + 36 + examples: 37 + - | 38 + interrupt-controller@dc000000 { 39 + compatible = "lsi,zevio-intc"; 40 + interrupt-controller; 41 + reg = <0xdc000000 0x1000>; 42 + #interrupt-cells = <1>; 43 + };

+50

Documentation/devicetree/bindings/interrupt-controller/marvell,ap806-gicp.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/marvell,ap806-gicp.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Marvell GICP Controller 8 + 9 + maintainers: 10 + - Thomas Petazzoni <thomas.petazzoni@bootlin.com> 11 + 12 + description: 13 + GICP is a Marvell extension of the GIC that allows to trigger GIC SPI 14 + interrupts by doing a memory transaction. It is used by the ICU 15 + located in the Marvell CP110 to turn wired interrupts inside the CP 16 + into GIC SPI interrupts. 17 + 18 + properties: 19 + compatible: 20 + const: marvell,ap806-gicp 21 + 22 + reg: 23 + maxItems: 1 24 + 25 + marvell,spi-ranges: 26 + description: Tuples of GIC SPI interrupt ranges available for this GICP 27 + $ref: /schemas/types.yaml#/definitions/uint32-matrix 28 + items: 29 + items: 30 + - description: SPI interrupt base 31 + - description: Number of interrupts in the range 32 + 33 + msi-controller: true 34 + 35 + required: 36 + - compatible 37 + - reg 38 + - msi-controller 39 + - marvell,spi-ranges 40 + 41 + additionalProperties: false 42 + 43 + examples: 44 + - | 45 + msi-controller@3f0040 { 46 + compatible = "marvell,ap806-gicp"; 47 + reg = <0x3f0040 0x10>; 48 + marvell,spi-ranges = <64 64>, <288 64>; 49 + msi-controller; 50 + };

+58

Documentation/devicetree/bindings/interrupt-controller/marvell,ap806-sei.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/marvell,ap806-sei.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Marvell SEI (System Error Interrupt) Controller 8 + 9 + maintainers: 10 + - Miquel Raynal <miquel.raynal@bootlin.com> 11 + 12 + description: > 13 + Marvell SEI (System Error Interrupt) controller is an interrupt aggregator. It 14 + receives interrupts from several sources and aggregates them to a single 15 + interrupt line (an SPI) on the parent interrupt controller. 16 + 17 + This interrupt controller can handle up to 64 SEIs, a set comes from the AP 18 + and is wired while a second set comes from the CPs by the mean of MSIs. 19 + 20 + properties: 21 + compatible: 22 + const: marvell,ap806-sei 23 + 24 + reg: 25 + maxItems: 1 26 + 27 + interrupts: 28 + maxItems: 1 29 + 30 + '#interrupt-cells': 31 + const: 1 32 + 33 + interrupt-controller: true 34 + 35 + msi-controller: true 36 + 37 + required: 38 + - compatible 39 + - reg 40 + - interrupts 41 + - '#interrupt-cells' 42 + - interrupt-controller 43 + - msi-controller 44 + 45 + additionalProperties: false 46 + 47 + examples: 48 + - | 49 + #include <dt-bindings/interrupt-controller/arm-gic.h> 50 + 51 + interrupt-controller@3f0200 { 52 + compatible = "marvell,ap806-sei"; 53 + reg = <0x3f0200 0x40>; 54 + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 55 + #interrupt-cells = <1>; 56 + interrupt-controller; 57 + msi-controller; 58 + };

-25

Documentation/devicetree/bindings/interrupt-controller/marvell,armada-8k-pic.txt

··· 1 - Marvell Armada 7K/8K PIC Interrupt controller 2 - --------------------------------------------- 3 - 4 - This is the Device Tree binding for the PIC, a secondary interrupt 5 - controller available on the Marvell Armada 7K/8K ARM64 SoCs, and 6 - typically connected to the GIC as the primary interrupt controller. 7 - 8 - Required properties: 9 - - compatible: should be "marvell,armada-8k-pic" 10 - - interrupt-controller: identifies the node as an interrupt controller 11 - - #interrupt-cells: the number of cells to define interrupts on this 12 - controller. Should be 1 13 - - reg: the register area for the PIC interrupt controller 14 - - interrupts: the interrupt to the primary interrupt controller, 15 - typically the GIC 16 - 17 - Example: 18 - 19 - pic: interrupt-controller@3f0100 { 20 - compatible = "marvell,armada-8k-pic"; 21 - reg = <0x3f0100 0x10>; 22 - #interrupt-cells = <1>; 23 - interrupt-controller; 24 - interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 25 - };

+52

Documentation/devicetree/bindings/interrupt-controller/marvell,armada-8k-pic.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/marvell,armada-8k-pic.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Marvell Armada 7K/8K PIC Interrupt controller 8 + 9 + maintainers: 10 + - Thomas Petazzoni <thomas.petazzoni@bootlin.com> 11 + 12 + description: 13 + The Marvell Armada 7K/8K PIC is a secondary interrupt controller available on 14 + the Marvell Armada 7K/8K ARM64 SoCs, and typically connected to the GIC as the 15 + primary interrupt controller. 16 + 17 + properties: 18 + compatible: 19 + const: marvell,armada-8k-pic 20 + 21 + reg: 22 + maxItems: 1 23 + 24 + "#interrupt-cells": 25 + const: 1 26 + 27 + interrupt-controller: true 28 + 29 + interrupts: 30 + maxItems: 1 31 + description: Interrupt to the primary interrupt controller (GIC). 32 + 33 + required: 34 + - compatible 35 + - reg 36 + - "#interrupt-cells" 37 + - interrupt-controller 38 + - interrupts 39 + 40 + additionalProperties: false 41 + 42 + examples: 43 + - | 44 + #include <dt-bindings/interrupt-controller/arm-gic.h> 45 + 46 + interrupt-controller@3f0100 { 47 + compatible = "marvell,armada-8k-pic"; 48 + reg = <0x3f0100 0x10>; 49 + #interrupt-cells = <1>; 50 + interrupt-controller; 51 + interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 52 + };

+98

Documentation/devicetree/bindings/interrupt-controller/marvell,cp110-icu.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/marvell,cp110-icu.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + maintainers: 8 + - Miquel Raynal <miquel.raynal@bootlin.com> 9 + - Thomas Petazzoni <thomas.petazzoni@bootlin.com> 10 + 11 + title: Marvell ICU Interrupt Controller 12 + 13 + description: 14 + The Marvell ICU (Interrupt Consolidation Unit) controller is responsible for 15 + collecting all wired-interrupt sources in the CP and communicating them to the 16 + GIC in the AP. The unit translates interrupt requests on input wires to MSG 17 + memory mapped transactions to the GIC. These messages access different GIC 18 + memory areas depending on their type (NSR, SR, SEI, REI, etc). 19 + 20 + properties: 21 + compatible: 22 + const: marvell,cp110-icu 23 + 24 + reg: 25 + maxItems: 1 26 + 27 + '#address-cells': 28 + const: 1 29 + 30 + '#size-cells': 31 + const: 1 32 + 33 + ranges: true 34 + 35 + patternProperties: 36 + "^interrupt-controller@": 37 + type: object 38 + description: Interrupt group child nodes 39 + additionalProperties: false 40 + 41 + properties: 42 + compatible: 43 + enum: 44 + - marvell,cp110-icu-nsr 45 + - marvell,cp110-icu-sr 46 + - marvell,cp110-icu-sei 47 + - marvell,cp110-icu-rei 48 + 49 + reg: 50 + maxItems: 1 51 + 52 + '#interrupt-cells': 53 + const: 2 54 + 55 + interrupt-controller: true 56 + 57 + msi-parent: 58 + maxItems: 1 59 + description: Phandle to the GICP controller 60 + 61 + required: 62 + - compatible 63 + - reg 64 + - '#interrupt-cells' 65 + - interrupt-controller 66 + - msi-parent 67 + 68 + required: 69 + - compatible 70 + - reg 71 + 72 + additionalProperties: false 73 + 74 + examples: 75 + - | 76 + interrupt-controller@1e0000 { 77 + compatible = "marvell,cp110-icu"; 78 + reg = <0x1e0000 0x440>; 79 + #address-cells = <1>; 80 + #size-cells = <1>; 81 + ranges; 82 + 83 + interrupt-controller@10 { 84 + compatible = "marvell,cp110-icu-nsr"; 85 + reg = <0x10 0x20>; 86 + #interrupt-cells = <2>; 87 + interrupt-controller; 88 + msi-parent = <&gicp>; 89 + }; 90 + 91 + interrupt-controller@50 { 92 + compatible = "marvell,cp110-icu-sei"; 93 + reg = <0x50 0x10>; 94 + #interrupt-cells = <2>; 95 + interrupt-controller; 96 + msi-parent = <&sei>; 97 + }; 98 + };

-27

Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt

··· 1 - Marvell GICP Controller 2 - ----------------------- 3 - 4 - GICP is a Marvell extension of the GIC that allows to trigger GIC SPI 5 - interrupts by doing a memory transaction. It is used by the ICU 6 - located in the Marvell CP110 to turn wired interrupts inside the CP 7 - into GIC SPI interrupts. 8 - 9 - Required properties: 10 - 11 - - compatible: Must be "marvell,ap806-gicp" 12 - 13 - - reg: Must be the address and size of the GICP SPI registers 14 - 15 - - marvell,spi-ranges: tuples of GIC SPI interrupts ranges available 16 - for this GICP 17 - 18 - - msi-controller: indicates that this is an MSI controller 19 - 20 - Example: 21 - 22 - gicp_spi: gicp-spi@3f0040 { 23 - compatible = "marvell,ap806-gicp"; 24 - reg = <0x3f0040 0x10>; 25 - marvell,spi-ranges = <64 64>, <288 64>; 26 - msi-controller; 27 - };

-112

Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt

··· 1 - Marvell ICU Interrupt Controller 2 - -------------------------------- 3 - 4 - The Marvell ICU (Interrupt Consolidation Unit) controller is 5 - responsible for collecting all wired-interrupt sources in the CP and 6 - communicating them to the GIC in the AP, the unit translates interrupt 7 - requests on input wires to MSG memory mapped transactions to the GIC. 8 - These messages will access a different GIC memory area depending on 9 - their type (NSR, SR, SEI, REI, etc). 10 - 11 - Required properties: 12 - 13 - - compatible: Should be "marvell,cp110-icu" 14 - 15 - - reg: Should contain ICU registers location and length. 16 - 17 - Subnodes: Each group of interrupt is declared as a subnode of the ICU, 18 - with their own compatible. 19 - 20 - Required properties for the icu_nsr/icu_sei subnodes: 21 - 22 - - compatible: Should be one of: 23 - * "marvell,cp110-icu-nsr" 24 - * "marvell,cp110-icu-sr" 25 - * "marvell,cp110-icu-sei" 26 - * "marvell,cp110-icu-rei" 27 - 28 - - #interrupt-cells: Specifies the number of cells needed to encode an 29 - interrupt source. The value shall be 2. 30 - 31 - The 1st cell is the index of the interrupt in the ICU unit. 32 - 33 - The 2nd cell is the type of the interrupt. See arm,gic.txt for 34 - details. 35 - 36 - - interrupt-controller: Identifies the node as an interrupt 37 - controller. 38 - 39 - - msi-parent: Should point to the GICP controller, the GIC extension 40 - that allows to trigger interrupts using MSG memory mapped 41 - transactions. 42 - 43 - Note: each 'interrupts' property referring to any 'icu_xxx' node shall 44 - have a different number within [0:206]. 45 - 46 - Example: 47 - 48 - icu: interrupt-controller@1e0000 { 49 - compatible = "marvell,cp110-icu"; 50 - reg = <0x1e0000 0x440>; 51 - 52 - CP110_LABEL(icu_nsr): interrupt-controller@10 { 53 - compatible = "marvell,cp110-icu-nsr"; 54 - reg = <0x10 0x20>; 55 - #interrupt-cells = <2>; 56 - interrupt-controller; 57 - msi-parent = <&gicp>; 58 - }; 59 - 60 - CP110_LABEL(icu_sei): interrupt-controller@50 { 61 - compatible = "marvell,cp110-icu-sei"; 62 - reg = <0x50 0x10>; 63 - #interrupt-cells = <2>; 64 - interrupt-controller; 65 - msi-parent = <&sei>; 66 - }; 67 - }; 68 - 69 - node1 { 70 - interrupt-parent = <&icu_nsr>; 71 - interrupts = <106 IRQ_TYPE_LEVEL_HIGH>; 72 - }; 73 - 74 - node2 { 75 - interrupt-parent = <&icu_sei>; 76 - interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; 77 - }; 78 - 79 - /* Would not work with the above nodes */ 80 - node3 { 81 - interrupt-parent = <&icu_nsr>; 82 - interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; 83 - }; 84 - 85 - The legacy bindings were different in this way: 86 - 87 - - #interrupt-cells: The value was 3. 88 - The 1st cell was the group type of the ICU interrupt. Possible 89 - group types were: 90 - ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure 91 - ICU_GRP_SR (0x1) : Shared peripheral interrupt, secure 92 - ICU_GRP_SEI (0x4) : System error interrupt 93 - ICU_GRP_REI (0x5) : RAM error interrupt 94 - The 2nd cell was the index of the interrupt in the ICU unit. 95 - The 3rd cell was the type of the interrupt. See arm,gic.txt for 96 - details. 97 - 98 - Example: 99 - 100 - icu: interrupt-controller@1e0000 { 101 - compatible = "marvell,cp110-icu"; 102 - reg = <0x1e0000 0x440>; 103 - 104 - #interrupt-cells = <3>; 105 - interrupt-controller; 106 - msi-parent = <&gicp>; 107 - }; 108 - 109 - node1 { 110 - interrupt-parent = <&icu>; 111 - interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>; 112 - };

-42

Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.txt

··· 1 - 2 - * Marvell ODMI for MSI support 3 - 4 - Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller 5 - which can be used by on-board peripheral for MSI interrupts. 6 - 7 - Required properties: 8 - 9 - - compatible : The value here should contain: 10 - 11 - "marvell,ap806-odmi-controller", "marvell,odmi-controller". 12 - 13 - - interrupt,controller : Identifies the node as an interrupt controller. 14 - 15 - - msi-controller : Identifies the node as an MSI controller. 16 - 17 - - marvell,odmi-frames : Number of ODMI frames available. Each frame 18 - provides a number of events. 19 - 20 - - reg : List of register definitions, one for each 21 - ODMI frame. 22 - 23 - - marvell,spi-base : List of GIC base SPI interrupts, one for each 24 - ODMI frame. Those SPI interrupts are 0-based, 25 - i.e marvell,spi-base = <128> will use SPI #96. 26 - See Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml 27 - for details about the GIC Device Tree binding. 28 - 29 - Example: 30 - 31 - odmi: odmi@300000 { 32 - compatible = "marvell,ap806-odmi-controller", 33 - "marvell,odmi-controller"; 34 - interrupt-controller; 35 - msi-controller; 36 - marvell,odmi-frames = <4>; 37 - reg = <0x300000 0x4000>, 38 - <0x304000 0x4000>, 39 - <0x308000 0x4000>, 40 - <0x30C000 0x4000>; 41 - marvell,spi-base = <128>, <136>, <144>, <152>; 42 - };

+54

Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/marvell,odmi-controller.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Marvell ODMI controller 8 + 9 + maintainers: 10 + - Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 11 + 12 + description: 13 + Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller which can 14 + be used by on-board peripherals for MSI interrupts. 15 + 16 + properties: 17 + compatible: 18 + const: marvell,odmi-controller 19 + 20 + reg: 21 + description: List of register definitions, one for each ODMI frame. 22 + 23 + msi-controller: true 24 + 25 + marvell,odmi-frames: 26 + description: Number of ODMI frames available. Each frame provides a number of events. 27 + $ref: /schemas/types.yaml#/definitions/uint32 28 + 29 + marvell,spi-base: 30 + description: > 31 + List of GIC base SPI interrupts, one for each ODMI frame. Those SPI 32 + interrupts are 0-based, i.e. marvell,spi-base = <128> will use SPI #96. 33 + See Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml 34 + for details. 35 + $ref: /schemas/types.yaml#/definitions/uint32-array 36 + 37 + required: 38 + - compatible 39 + - reg 40 + - msi-controller 41 + - marvell,odmi-frames 42 + - marvell,spi-base 43 + 44 + additionalProperties: false 45 + 46 + examples: 47 + - | 48 + msi-controller@300000 { 49 + compatible = "marvell,odmi-controller"; 50 + msi-controller; 51 + marvell,odmi-frames = <4>; 52 + reg = <0x300000 0x4000>, <0x304000 0x4000>, <0x308000 0x4000>, <0x30C000 0x4000>; 53 + marvell,spi-base = <128>, <136>, <144>, <152>; 54 + };

+52

Documentation/devicetree/bindings/interrupt-controller/marvell,orion-bridge-intc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + --- 3 + $id: http://devicetree.org/schemas/interrupt-controller/marvell,orion-bridge-intc.yaml# 4 + $schema: http://devicetree.org/meta-schemas/core.yaml# 5 + 6 + title: Marvell Orion SoC Bridge Interrupt Controller 7 + 8 + maintainers: 9 + - Andrew Lunn <andrew@lunn.ch> 10 + - Gregory Clement <gregory.clement@bootlin.com> 11 + 12 + properties: 13 + compatible: 14 + const: marvell,orion-bridge-intc 15 + 16 + reg: 17 + minItems: 1 18 + maxItems: 2 19 + 20 + interrupt-controller: true 21 + 22 + '#interrupt-cells': 23 + const: 1 24 + 25 + interrupts: 26 + description: Bridge interrupt of the main interrupt controller 27 + 28 + marvell,#interrupts: 29 + description: Number of interrupts provided by bridge interrupt controller. 30 + $ref: /schemas/types.yaml#/definitions/uint32 31 + default: 32 32 + 33 + required: 34 + - compatible 35 + - reg 36 + - interrupt-controller 37 + - '#interrupt-cells' 38 + - interrupts 39 + 40 + additionalProperties: false 41 + 42 + examples: 43 + - | 44 + interrupt-controller@20110 { 45 + compatible = "marvell,orion-bridge-intc"; 46 + reg = <0x20110 0x8>; 47 + interrupt-controller; 48 + #interrupt-cells = <1>; 49 + interrupts = <0>; 50 + /* Dove bridge provides 5 interrupts */ 51 + marvell,#interrupts = <5>; 52 + };

-48

Documentation/devicetree/bindings/interrupt-controller/marvell,orion-intc.txt

··· 1 - Marvell Orion SoC interrupt controllers 2 - 3 - * Main interrupt controller 4 - 5 - Required properties: 6 - - compatible: shall be "marvell,orion-intc" 7 - - reg: base address(es) of interrupt registers starting with CAUSE register 8 - - interrupt-controller: identifies the node as an interrupt controller 9 - - #interrupt-cells: number of cells to encode an interrupt source, shall be 1 10 - 11 - The interrupt sources map to the corresponding bits in the interrupt 12 - registers, i.e. 13 - - 0 maps to bit 0 of first base address, 14 - - 1 maps to bit 1 of first base address, 15 - - 32 maps to bit 0 of second base address, and so on. 16 - 17 - Example: 18 - intc: interrupt-controller { 19 - compatible = "marvell,orion-intc"; 20 - interrupt-controller; 21 - #interrupt-cells = <1>; 22 - /* Dove has 64 first level interrupts */ 23 - reg = <0x20200 0x10>, <0x20210 0x10>; 24 - }; 25 - 26 - * Bridge interrupt controller 27 - 28 - Required properties: 29 - - compatible: shall be "marvell,orion-bridge-intc" 30 - - reg: base address of bridge interrupt registers starting with CAUSE register 31 - - interrupts: bridge interrupt of the main interrupt controller 32 - - interrupt-controller: identifies the node as an interrupt controller 33 - - #interrupt-cells: number of cells to encode an interrupt source, shall be 1 34 - 35 - Optional properties: 36 - - marvell,#interrupts: number of interrupts provided by bridge interrupt 37 - controller, defaults to 32 if not set 38 - 39 - Example: 40 - bridge_intc: interrupt-controller { 41 - compatible = "marvell,orion-bridge-intc"; 42 - interrupt-controller; 43 - #interrupt-cells = <1>; 44 - reg = <0x20110 0x8>; 45 - interrupts = <0>; 46 - /* Dove bridge provides 5 interrupts */ 47 - marvell,#interrupts = <5>; 48 - };

-36

Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt

··· 1 - Marvell SEI (System Error Interrupt) Controller 2 - ----------------------------------------------- 3 - 4 - Marvell SEI (System Error Interrupt) controller is an interrupt 5 - aggregator. It receives interrupts from several sources and aggregates 6 - them to a single interrupt line (an SPI) on the parent interrupt 7 - controller. 8 - 9 - This interrupt controller can handle up to 64 SEIs, a set comes from the 10 - AP and is wired while a second set comes from the CPs by the mean of 11 - MSIs. 12 - 13 - Required properties: 14 - 15 - - compatible: should be one of: 16 - * "marvell,ap806-sei" 17 - - reg: SEI registers location and length. 18 - - interrupts: identifies the parent IRQ that will be triggered. 19 - - #interrupt-cells: number of cells to define an SEI wired interrupt 20 - coming from the AP, should be 1. The cell is the IRQ 21 - number. 22 - - interrupt-controller: identifies the node as an interrupt controller 23 - for AP interrupts. 24 - - msi-controller: identifies the node as an MSI controller for the CPs 25 - interrupts. 26 - 27 - Example: 28 - 29 - sei: interrupt-controller@3f0200 { 30 - compatible = "marvell,ap806-sei"; 31 - reg = <0x3f0200 0x40>; 32 - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 33 - #interrupt-cells = <1>; 34 - interrupt-controller; 35 - msi-controller; 36 - };

-67

Documentation/devicetree/bindings/interrupt-controller/microchip,pic32-evic.txt

··· 1 - Microchip PIC32 Interrupt Controller 2 - ==================================== 3 - 4 - The Microchip PIC32 contains an Enhanced Vectored Interrupt Controller (EVIC). 5 - It handles all internal and external interrupts. This controller exists outside 6 - of the CPU and is the arbitrator of all interrupts (including interrupts from 7 - the CPU itself) before they are presented to the CPU. 8 - 9 - External interrupts have a software configurable edge polarity. Non external 10 - interrupts have a type and polarity that is determined by the source of the 11 - interrupt. 12 - 13 - Required properties 14 - ------------------- 15 - 16 - - compatible: Should be "microchip,pic32mzda-evic" 17 - - reg: Specifies physical base address and size of register range. 18 - - interrupt-controller: Identifies the node as an interrupt controller. 19 - - #interrupt cells: Specifies the number of cells used to encode an interrupt 20 - source connected to this controller. The value shall be 2 and interrupt 21 - descriptor shall have the following format: 22 - 23 - <hw_irq irq_type> 24 - 25 - hw_irq - represents the hardware interrupt number as in the data sheet. 26 - irq_type - is used to describe the type and polarity of an interrupt. For 27 - internal interrupts use IRQ_TYPE_EDGE_RISING for non persistent interrupts and 28 - IRQ_TYPE_LEVEL_HIGH for persistent interrupts. For external interrupts use 29 - IRQ_TYPE_EDGE_RISING or IRQ_TYPE_EDGE_FALLING to select the desired polarity. 30 - 31 - Optional properties 32 - ------------------- 33 - - microchip,external-irqs: u32 array of external interrupts with software 34 - polarity configuration. This array corresponds to the bits in the INTCON 35 - SFR. 36 - 37 - Example 38 - ------- 39 - 40 - evic: interrupt-controller@1f810000 { 41 - compatible = "microchip,pic32mzda-evic"; 42 - interrupt-controller; 43 - #interrupt-cells = <2>; 44 - reg = <0x1f810000 0x1000>; 45 - microchip,external-irqs = <3 8 13 18 23>; 46 - }; 47 - 48 - Each device/peripheral must request its interrupt line with the associated type 49 - and polarity. 50 - 51 - Internal interrupt DTS snippet 52 - ------------------------------ 53 - 54 - device@1f800000 { 55 - ... 56 - interrupts = <113 IRQ_TYPE_LEVEL_HIGH>; 57 - ... 58 - }; 59 - 60 - External interrupt DTS snippet 61 - ------------------------------ 62 - 63 - device@1f800000 { 64 - ... 65 - interrupts = <3 IRQ_TYPE_EDGE_RISING>; 66 - ... 67 - };

+60

Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mzda-evic.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/microchip,pic32mzda-evic.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Microchip PIC32 EVIC Interrupt Controller 8 + 9 + maintainers: 10 + - Cristian Birsan <cristian.birsan@microchip.com> 11 + 12 + description: > 13 + The Microchip PIC32 contains an Enhanced Vectored Interrupt Controller (EVIC). 14 + It handles all internal and external interrupts. This controller exists 15 + outside of the CPU and is the arbitrator of all interrupts (including 16 + interrupts from the CPU itself) before they are presented to the CPU. 17 + 18 + External interrupts have a software configurable edge polarity. Non external 19 + interrupts have a type and polarity that is determined by the source of the 20 + interrupt. 21 + 22 + properties: 23 + compatible: 24 + items: 25 + - const: microchip,pic32mzda-evic 26 + 27 + reg: 28 + maxItems: 1 29 + 30 + interrupt-controller: true 31 + 32 + '#interrupt-cells': 33 + const: 2 34 + 35 + interrupts: 36 + maxItems: 1 37 + 38 + microchip,external-irqs: 39 + description: 40 + External interrupts with software polarity configuration corresponding to 41 + the INTCON SFR bits. 42 + $ref: /schemas/types.yaml#/definitions/uint32-array 43 + 44 + required: 45 + - compatible 46 + - reg 47 + - interrupt-controller 48 + - '#interrupt-cells' 49 + 50 + additionalProperties: false 51 + 52 + examples: 53 + - | 54 + interrupt-controller@1f810000 { 55 + compatible = "microchip,pic32mzda-evic"; 56 + reg = <0x1f810000 0x1000>; 57 + interrupt-controller; 58 + #interrupt-cells = <2>; 59 + microchip,external-irqs = <3 8 13 18 23>; 60 + };

-97

Documentation/devicetree/bindings/interrupt-controller/open-pic.txt

··· 1 - * Open PIC Binding 2 - 3 - This binding specifies what properties must be available in the device tree 4 - representation of an Open PIC compliant interrupt controller. This binding is 5 - based on the binding defined for Open PIC in [1] and is a superset of that 6 - binding. 7 - 8 - Required properties: 9 - 10 - NOTE: Many of these descriptions were paraphrased here from [1] to aid 11 - readability. 12 - 13 - - compatible: Specifies the compatibility list for the PIC. The type 14 - shall be <string> and the value shall include "open-pic". 15 - 16 - - reg: Specifies the base physical address(s) and size(s) of this 17 - PIC's addressable register space. The type shall be <prop-encoded-array>. 18 - 19 - - interrupt-controller: The presence of this property identifies the node 20 - as an Open PIC. No property value shall be defined. 21 - 22 - - #interrupt-cells: Specifies the number of cells needed to encode an 23 - interrupt source. The type shall be a <u32> and the value shall be 2. 24 - 25 - - #address-cells: Specifies the number of cells needed to encode an 26 - address. The type shall be <u32> and the value shall be 0. As such, 27 - 'interrupt-map' nodes do not have to specify a parent unit address. 28 - 29 - Optional properties: 30 - 31 - - pic-no-reset: The presence of this property indicates that the PIC 32 - shall not be reset during runtime initialization. No property value shall 33 - be defined. The presence of this property also mandates that any 34 - initialization related to interrupt sources shall be limited to sources 35 - explicitly referenced in the device tree. 36 - 37 - * Interrupt Specifier Definition 38 - 39 - Interrupt specifiers consists of 2 cells encoded as 40 - follows: 41 - 42 - - <1st-cell>: The interrupt-number that identifies the interrupt source. 43 - 44 - - <2nd-cell>: The level-sense information, encoded as follows: 45 - 0 = low-to-high edge triggered 46 - 1 = active low level-sensitive 47 - 2 = active high level-sensitive 48 - 3 = high-to-low edge triggered 49 - 50 - * Examples 51 - 52 - Example 1: 53 - 54 - /* 55 - * An Open PIC interrupt controller 56 - */ 57 - mpic: pic@40000 { 58 - // This is an interrupt controller node. 59 - interrupt-controller; 60 - 61 - // No address cells so that 'interrupt-map' nodes which reference 62 - // this Open PIC node do not need a parent address specifier. 63 - #address-cells = <0>; 64 - 65 - // Two cells to encode interrupt sources. 66 - #interrupt-cells = <2>; 67 - 68 - // Offset address of 0x40000 and size of 0x40000. 69 - reg = <0x40000 0x40000>; 70 - 71 - // Compatible with Open PIC. 72 - compatible = "open-pic"; 73 - 74 - // The PIC shall not be reset. 75 - pic-no-reset; 76 - }; 77 - 78 - Example 2: 79 - 80 - /* 81 - * An interrupt generating device that is wired to an Open PIC. 82 - */ 83 - serial0: serial@4500 { 84 - // Interrupt source '42' that is active high level-sensitive. 85 - // Note that there are only two cells as specified in the interrupt 86 - // parent's '#interrupt-cells' property. 87 - interrupts = <42 2>; 88 - 89 - // The interrupt controller that this device is wired to. 90 - interrupt-parent = <&mpic>; 91 - }; 92 - 93 - * References 94 - 95 - [1] Devicetree Specification 96 - (https://www.devicetree.org/specifications/) 97 -

+61

Documentation/devicetree/bindings/interrupt-controller/qca,ar7100-cpu-intc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/qca,ar7100-cpu-intc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Qualcomm Atheros ath79 CPU interrupt controller 8 + 9 + maintainers: 10 + - Alban Bedel <albeu@free.fr> 11 + 12 + description: 13 + On most SoC the IRQ controller need to flush the DDR FIFO before running the 14 + interrupt handler of some devices. This is configured using the 15 + qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties. 16 + 17 + properties: 18 + compatible: 19 + oneOf: 20 + - items: 21 + - const: qca,ar9132-cpu-intc 22 + - const: qca,ar7100-cpu-intc 23 + - items: 24 + - const: qca,ar7100-cpu-intc 25 + 26 + interrupt-controller: true 27 + 28 + '#interrupt-cells': 29 + const: 1 30 + 31 + qca,ddr-wb-channel-interrupts: 32 + description: List of interrupts needing a write buffer flush 33 + $ref: /schemas/types.yaml#/definitions/uint32-array 34 + 35 + qca,ddr-wb-channels: 36 + description: List of write buffer channel phandles for each interrupt 37 + $ref: /schemas/types.yaml#/definitions/phandle-array 38 + 39 + required: 40 + - compatible 41 + - interrupt-controller 42 + - '#interrupt-cells' 43 + 44 + additionalProperties: false 45 + 46 + examples: 47 + - | 48 + interrupt-controller { 49 + compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc"; 50 + 51 + interrupt-controller; 52 + #interrupt-cells = <1>; 53 + 54 + qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>; 55 + qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>, 56 + <&ddr_ctrl 0>, <&ddr_ctrl 1>; 57 + }; 58 + 59 + ddr_ctrl: memory-controller { 60 + #qca,ddr-wb-channel-cells = <1>; 61 + };

+52

Documentation/devicetree/bindings/interrupt-controller/qca,ar7100-misc-intc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/qca,ar7100-misc-intc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller 8 + 9 + maintainers: 10 + - Alban Bedel <albeu@free.fr> 11 + - Alexander Couzens <lynxis@fe80.eu> 12 + 13 + description: 14 + The Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller is a secondary 15 + controller for lower priority interrupts. 16 + 17 + properties: 18 + compatible: 19 + oneOf: 20 + - items: 21 + - const: qca,ar9132-misc-intc 22 + - const: qca,ar7100-misc-intc 23 + - const: qca,ar7240-misc-intc 24 + reg: 25 + maxItems: 1 26 + 27 + interrupts: 28 + maxItems: 1 29 + 30 + interrupt-controller: true 31 + 32 + '#interrupt-cells': 33 + const: 1 34 + 35 + additionalProperties: false 36 + 37 + required: 38 + - compatible 39 + - reg 40 + - interrupts 41 + - interrupt-controller 42 + - "#interrupt-cells" 43 + 44 + examples: 45 + - | 46 + interrupt-controller@18060010 { 47 + compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc"; 48 + reg = <0x18060010 0x4>; 49 + interrupts = <6>; 50 + interrupt-controller; 51 + #interrupt-cells = <1>; 52 + };

-44

Documentation/devicetree/bindings/interrupt-controller/qca,ath79-cpu-intc.txt

··· 1 - Binding for Qualcomm Atheros AR7xxx/AR9XXX CPU interrupt controller 2 - 3 - On most SoC the IRQ controller need to flush the DDR FIFO before running 4 - the interrupt handler of some devices. This is configured using the 5 - qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties. 6 - 7 - Required Properties: 8 - 9 - - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-cpu-intc" 10 - as fallback 11 - - interrupt-controller : Identifies the node as an interrupt controller 12 - - #interrupt-cells : Specifies the number of cells needed to encode interrupt 13 - source, should be 1 for intc 14 - 15 - Please refer to interrupts.txt in this directory for details of the common 16 - Interrupt Controllers bindings used by client devices. 17 - 18 - Optional Properties: 19 - 20 - - qca,ddr-wb-channel-interrupts: List of the interrupts needing a write 21 - buffer flush 22 - - qca,ddr-wb-channels: List of phandles to the write buffer channels for 23 - each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt 24 - default to the entry's index. 25 - 26 - Example: 27 - 28 - interrupt-controller { 29 - compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc"; 30 - 31 - interrupt-controller; 32 - #interrupt-cells = <1>; 33 - 34 - qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>; 35 - qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>, 36 - <&ddr_ctrl 0>, <&ddr_ctrl 1>; 37 - }; 38 - 39 - ... 40 - 41 - ddr_ctrl: memory-controller@18000000 { 42 - ... 43 - #qca,ddr-wb-channel-cells = <1>; 44 - };

-45

Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt

··· 1 - Binding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller 2 - 3 - The MISC interrupt controller is a secondary controller for lower priority 4 - interrupt. 5 - 6 - Required Properties: 7 - - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or 8 - "qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc" 9 - - reg: Base address and size of the controllers memory area 10 - - interrupts: Interrupt specifier for the controllers interrupt. 11 - - interrupt-controller : Identifies the node as an interrupt controller 12 - - #interrupt-cells : Specifies the number of cells needed to encode interrupt 13 - source, should be 1 14 - 15 - Compatible fallback depends on the SoC. Use ar7100 for ar71xx and ar913x, 16 - use ar7240 for all other SoCs. 17 - 18 - Please refer to interrupts.txt in this directory for details of the common 19 - Interrupt Controllers bindings used by client devices. 20 - 21 - Example: 22 - 23 - interrupt-controller@18060010 { 24 - compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc"; 25 - reg = <0x18060010 0x4>; 26 - 27 - interrupt-parent = <&cpuintc>; 28 - interrupts = <6>; 29 - 30 - interrupt-controller; 31 - #interrupt-cells = <1>; 32 - }; 33 - 34 - Another example: 35 - 36 - interrupt-controller@18060010 { 37 - compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc"; 38 - reg = <0x18060010 0x4>; 39 - 40 - interrupt-parent = <&cpuintc>; 41 - interrupts = <6>; 42 - 43 - interrupt-controller; 44 - #interrupt-cells = <1>; 45 - };

-24

Documentation/devicetree/bindings/interrupt-controller/snps,arc700-intc.txt

··· 1 - * ARC700 incore Interrupt Controller 2 - 3 - The core interrupt controller provides 32 prioritised interrupts (2 levels) 4 - to ARC700 core. 5 - 6 - Properties: 7 - 8 - - compatible: "snps,arc700-intc" 9 - - interrupt-controller: This is an interrupt controller. 10 - - #interrupt-cells: Must be <1>. 11 - 12 - Single Cell "interrupts" property of a device specifies the IRQ number 13 - between 0 to 31 14 - 15 - intc accessed via the special ARC AUX register interface, hence "reg" property 16 - is not specified. 17 - 18 - Example: 19 - 20 - intc: interrupt-controller { 21 - compatible = "snps,arc700-intc"; 22 - interrupt-controller; 23 - #interrupt-cells = <1>; 24 - };

+42

Documentation/devicetree/bindings/interrupt-controller/snps,arc700-intc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/snps,arc700-intc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: ARC700 incore Interrupt Controller 8 + 9 + maintainers: 10 + - Vineet Gupta <vgupta@kernel.org> 11 + 12 + description: > 13 + The core interrupt controller provides 32 prioritized interrupts (2 levels) 14 + to ARC700 core. 15 + 16 + intc accessed via the special ARC AUX register interface, hence "reg" property 17 + is not specified. 18 + 19 + properties: 20 + compatible: 21 + const: snps,arc700-intc 22 + 23 + interrupt-controller: true 24 + 25 + '#interrupt-cells': 26 + description: An interrupt number 0-31 27 + const: 1 28 + 29 + required: 30 + - compatible 31 + - interrupt-controller 32 + - '#interrupt-cells' 33 + 34 + additionalProperties: false 35 + 36 + examples: 37 + - | 38 + interrupt-controller { 39 + compatible = "snps,arc700-intc"; 40 + interrupt-controller; 41 + #interrupt-cells = <1>; 42 + };

-46

Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt

··· 1 - * ARC-HS Interrupt Distribution Unit 2 - 3 - This optional 2nd level interrupt controller can be used in SMP configurations 4 - for dynamic IRQ routing, load balancing of common/external IRQs towards core 5 - intc. 6 - 7 - Properties: 8 - 9 - - compatible: "snps,archs-idu-intc" 10 - - interrupt-controller: This is an interrupt controller. 11 - - #interrupt-cells: Must be <1> or <2>. 12 - 13 - Value of the first cell specifies the "common" IRQ from peripheral to IDU. 14 - Number N of the particular interrupt line of IDU corresponds to the line N+24 15 - of the core interrupt controller. 16 - 17 - The (optional) second cell specifies any of the following flags: 18 - - bits[3:0] trigger type and level flags 19 - 1 = low-to-high edge triggered 20 - 2 = NOT SUPPORTED (high-to-low edge triggered) 21 - 4 = active high level-sensitive <<< DEFAULT 22 - 8 = NOT SUPPORTED (active low level-sensitive) 23 - When no second cell is specified, the interrupt is assumed to be level 24 - sensitive. 25 - 26 - The interrupt controller is accessed via the special ARC AUX register 27 - interface, hence "reg" property is not specified. 28 - 29 - Example: 30 - core_intc: core-interrupt-controller { 31 - compatible = "snps,archs-intc"; 32 - interrupt-controller; 33 - #interrupt-cells = <1>; 34 - }; 35 - 36 - idu_intc: idu-interrupt-controller { 37 - compatible = "snps,archs-idu-intc"; 38 - interrupt-controller; 39 - interrupt-parent = <&core_intc>; 40 - #interrupt-cells = <1>; 41 - }; 42 - 43 - some_device: serial@c0fc1000 { 44 - interrupt-parent = <&idu_intc>; 45 - interrupts = <0>; /* upstream idu IRQ #24 */ 46 - };

+48

Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/snps,archs-idu-intc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: ARC-HS Interrupt Distribution Unit 8 + 9 + maintainers: 10 + - Vineet Gupta <vgupta@kernel.org> 11 + 12 + description: > 13 + ARC-HS Interrupt Distribution Unit is an optional 2nd level interrupt 14 + controller which can be used in SMP configurations for dynamic IRQ routing, 15 + load balancing of common/external IRQs towards core intc. 16 + 17 + The interrupt controller is accessed via the special ARC AUX register 18 + interface, hence "reg" property is not specified. 19 + 20 + properties: 21 + compatible: 22 + const: snps,archs-idu-intc 23 + 24 + interrupt-controller: true 25 + 26 + '#interrupt-cells': 27 + description: | 28 + Number of interrupt specifier cells: 29 + - 1: only a common IRQ is specified. 30 + - 2: a second cell encodes trigger type and level flags: 31 + 1 = low-to-high edge triggered 32 + 4 = active high level-sensitive (default) 33 + enum: [1, 2] 34 + 35 + required: 36 + - compatible 37 + - interrupt-controller 38 + - '#interrupt-cells' 39 + 40 + additionalProperties: false 41 + 42 + examples: 43 + - | 44 + interrupt-controller { 45 + compatible = "snps,archs-idu-intc"; 46 + interrupt-controller; 47 + #interrupt-cells = <1>; 48 + };

-22

Documentation/devicetree/bindings/interrupt-controller/snps,archs-intc.txt

··· 1 - * ARC-HS incore Interrupt Controller (Provided by cores implementing ARCv2 ISA) 2 - 3 - Properties: 4 - 5 - - compatible: "snps,archs-intc" 6 - - interrupt-controller: This is an interrupt controller. 7 - - #interrupt-cells: Must be <1>. 8 - 9 - Single Cell "interrupts" property of a device specifies the IRQ number 10 - between 16 to 256 11 - 12 - intc accessed via the special ARC AUX register interface, hence "reg" property 13 - is not specified. 14 - 15 - Example: 16 - 17 - intc: interrupt-controller { 18 - compatible = "snps,archs-intc"; 19 - interrupt-controller; 20 - #interrupt-cells = <1>; 21 - interrupts = <16 17 18 19 20 21 22 23 24 25>; 22 - };

+48

Documentation/devicetree/bindings/interrupt-controller/snps,archs-intc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/snps,archs-intc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: ARC-HS incore Interrupt Controller 8 + 9 + maintainers: 10 + - Vineet Gupta <vgupta@kernel.org> 11 + 12 + description: 13 + ARC-HS incore Interrupt Controller provided by cores implementing ARCv2 ISA. 14 + intc accessed via the special ARC AUX register interface, hence "reg" property 15 + is not specified. 16 + 17 + properties: 18 + compatible: 19 + const: snps,archs-intc 20 + 21 + interrupt-controller: true 22 + 23 + '#interrupt-cells': 24 + const: 1 25 + 26 + interrupts: 27 + description: List of IRQ numbers between 16 and 256 28 + items: 29 + items: 30 + - minimum: 16 31 + maximum: 256 32 + 33 + required: 34 + - compatible 35 + - interrupt-controller 36 + - '#interrupt-cells' 37 + - interrupts 38 + 39 + additionalProperties: false 40 + 41 + examples: 42 + - | 43 + interrupt-controller { 44 + compatible = "snps,archs-intc"; 45 + interrupt-controller; 46 + #interrupt-cells = <1>; 47 + interrupts = <16>, <17>, <18>, <19>, <20>, <21>, <22>, <23>, <24>, <25>; 48 + };

-43

Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt

··· 1 - Synopsys DesignWare APB interrupt controller (dw_apb_ictl) 2 - 3 - Synopsys DesignWare provides interrupt controller IP for APB known as 4 - dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with 5 - APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt 6 - controller in some SoCs, e.g. Hisilicon SD5203. 7 - 8 - Required properties: 9 - - compatible: shall be "snps,dw-apb-ictl" 10 - - reg: physical base address of the controller and length of memory mapped 11 - region starting with ENABLE_LOW register 12 - - interrupt-controller: identifies the node as an interrupt controller 13 - - #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1 14 - 15 - Additional required property when it's used as secondary interrupt controller: 16 - - interrupts: interrupt reference to primary interrupt controller 17 - 18 - The interrupt sources map to the corresponding bits in the interrupt 19 - registers, i.e. 20 - - 0 maps to bit 0 of low interrupts, 21 - - 1 maps to bit 1 of low interrupts, 22 - - 32 maps to bit 0 of high interrupts, 23 - - 33 maps to bit 1 of high interrupts, 24 - - (optional) fast interrupts start at 64. 25 - 26 - Example: 27 - /* dw_apb_ictl is used as secondary interrupt controller */ 28 - aic: interrupt-controller@3000 { 29 - compatible = "snps,dw-apb-ictl"; 30 - reg = <0x3000 0xc00>; 31 - interrupt-controller; 32 - #interrupt-cells = <1>; 33 - interrupt-parent = <&gic>; 34 - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 35 - }; 36 - 37 - /* dw_apb_ictl is used as primary interrupt controller */ 38 - vic: interrupt-controller@10130000 { 39 - compatible = "snps,dw-apb-ictl"; 40 - reg = <0x10130000 0x1000>; 41 - interrupt-controller; 42 - #interrupt-cells = <1>; 43 - };

+64

Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/snps,dw-apb-ictl.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Synopsys DesignWare APB interrupt controller 8 + 9 + maintainers: 10 + - Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 11 + - Zhen Lei <thunder.leizhen@huawei.com> 12 + 13 + description: 14 + Synopsys DesignWare provides interrupt controller IP for APB known as 15 + dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs 16 + with APB bus, e.g. Marvell Armada 1500. It can also be used as primary 17 + interrupt controller in some SoCs, e.g. Hisilicon SD5203. 18 + 19 + properties: 20 + compatible: 21 + const: snps,dw-apb-ictl 22 + 23 + reg: 24 + maxItems: 1 25 + 26 + interrupt-controller: true 27 + 28 + '#interrupt-cells': 29 + const: 1 30 + 31 + interrupts: 32 + maxItems: 1 33 + description: > 34 + Interrupt input connected to the primary interrupt controller when used 35 + as a secondary controller. The interrupt specifier maps to bits in the 36 + low and high interrupt registers (0⇒bit 0 low, 1⇒bit 1 low, 32⇒bit 0 high, 37 + 33⇒bit 1 high, fast interrupts start at 64). 38 + 39 + required: 40 + - compatible 41 + - reg 42 + - interrupt-controller 43 + - '#interrupt-cells' 44 + 45 + additionalProperties: false 46 + 47 + examples: 48 + - | 49 + #include <dt-bindings/interrupt-controller/arm-gic.h> 50 + 51 + interrupt-controller@3000 { 52 + compatible = "snps,dw-apb-ictl"; 53 + reg = <0x3000 0xc00>; 54 + interrupt-controller; 55 + #interrupt-cells = <1>; 56 + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 57 + }; 58 + - | 59 + interrupt-controller@10130000 { 60 + compatible = "snps,dw-apb-ictl"; 61 + reg = <0x10130000 0x1000>; 62 + interrupt-controller; 63 + #interrupt-cells = <1>; 64 + };

+67

Documentation/devicetree/bindings/interrupt-controller/st,spear300-shirq.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/st,spear300-shirq.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: SPEAr3xx Shared IRQ controller 8 + 9 + maintainers: 10 + - Viresh Kumar <vireshk@kernel.org> 11 + - Shiraz Hashim <shiraz.linux.kernel@gmail.com> 12 + 13 + description: | 14 + SPEAr3xx architecture includes shared/multiplexed irqs for certain set of 15 + devices. The multiplexor provides a single interrupt to parent interrupt 16 + controller (VIC) on behalf of a group of devices. 17 + 18 + There can be multiple groups available on SPEAr3xx variants but not exceeding 19 + 4. The number of devices in a group can differ, further they may share same 20 + set of status/mask registers spanning across different bit masks. Also in some 21 + cases the group may not have enable or other registers. This makes software 22 + little complex. 23 + 24 + A single node in the device tree is used to describe the shared interrupt 25 + multiplexer (one node for all groups). A group in the interrupt controller 26 + shares config/control registers with other groups. For example, a 32-bit 27 + interrupt enable/disable config register can accommodate up to 4 interrupt 28 + groups. 29 + 30 + properties: 31 + compatible: 32 + enum: 33 + - st,spear300-shirq 34 + - st,spear310-shirq 35 + - st,spear320-shirq 36 + 37 + reg: 38 + maxItems: 1 39 + 40 + '#interrupt-cells': 41 + const: 1 42 + 43 + interrupt-controller: true 44 + 45 + interrupts: 46 + description: Interrupt specifier array for SHIRQ groups 47 + minItems: 1 48 + maxItems: 4 49 + 50 + required: 51 + - compatible 52 + - reg 53 + - '#interrupt-cells' 54 + - interrupt-controller 55 + - interrupts 56 + 57 + additionalProperties: false 58 + 59 + examples: 60 + - | 61 + interrupt-controller@b3000000 { 62 + compatible = "st,spear320-shirq"; 63 + reg = <0xb3000000 0x1000>; 64 + interrupts = <28 29 30 1>; 65 + #interrupt-cells = <1>; 66 + interrupt-controller; 67 + };

-44

Documentation/devicetree/bindings/interrupt-controller/st,spear3xx-shirq.txt

··· 1 - * SPEAr Shared IRQ layer (shirq) 2 - 3 - SPEAr3xx architecture includes shared/multiplexed irqs for certain set 4 - of devices. The multiplexor provides a single interrupt to parent 5 - interrupt controller (VIC) on behalf of a group of devices. 6 - 7 - There can be multiple groups available on SPEAr3xx variants but not 8 - exceeding 4. The number of devices in a group can differ, further they 9 - may share same set of status/mask registers spanning across different 10 - bit masks. Also in some cases the group may not have enable or other 11 - registers. This makes software little complex. 12 - 13 - A single node in the device tree is used to describe the shared 14 - interrupt multiplexor (one node for all groups). A group in the 15 - interrupt controller shares config/control registers with other groups. 16 - For example, a 32-bit interrupt enable/disable config register can 17 - accommodate up to 4 interrupt groups. 18 - 19 - Required properties: 20 - - compatible: should be, either of 21 - - "st,spear300-shirq" 22 - - "st,spear310-shirq" 23 - - "st,spear320-shirq" 24 - - interrupt-controller: Identifies the node as an interrupt controller. 25 - - #interrupt-cells: should be <1> which basically contains the offset 26 - (starting from 0) of interrupts for all the groups. 27 - - reg: Base address and size of shirq registers. 28 - - interrupts: The list of interrupts generated by the groups which are 29 - then connected to a parent interrupt controller. Each group is 30 - associated with one of the interrupts, hence number of interrupts (to 31 - parent) is equal to number of groups. The format of the interrupt 32 - specifier depends in the interrupt parent controller. 33 - 34 - Example: 35 - 36 - The following is an example from the SPEAr320 SoC dtsi file. 37 - 38 - shirq: interrupt-controller@b3000000 { 39 - compatible = "st,spear320-shirq"; 40 - reg = <0xb3000000 0x1000>; 41 - interrupts = <28 29 30 1>; 42 - #interrupt-cells = <1>; 43 - interrupt-controller; 44 - };

+49

Documentation/devicetree/bindings/interrupt-controller/technologic,ts4800-irqc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/technologic,ts4800-irqc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: TS-4800 FPGA Interrupt Controller 8 + 9 + maintainers: 10 + - Damien Riegel <damien.riegel@savoirfairelinux.com> 11 + 12 + description: 13 + TS-4800 FPGA has an internal interrupt controller. When one of the interrupts 14 + is triggered, the SoC is notified, usually using a GPIO as parent interrupt 15 + source. 16 + 17 + properties: 18 + compatible: 19 + const: technologic,ts4800-irqc 20 + 21 + reg: 22 + maxItems: 1 23 + 24 + '#interrupt-cells': 25 + const: 1 26 + 27 + interrupt-controller: true 28 + 29 + interrupts: 30 + maxItems: 1 31 + 32 + required: 33 + - compatible 34 + - reg 35 + - interrupt-controller 36 + - '#interrupt-cells' 37 + - interrupts 38 + 39 + additionalProperties: false 40 + 41 + examples: 42 + - | 43 + interrupt-controller@1000 { 44 + compatible = "technologic,ts4800-irqc"; 45 + reg = <0x1000 0x80>; 46 + interrupt-controller; 47 + #interrupt-cells = <1>; 48 + interrupts = <10>; 49 + };

-14

Documentation/devicetree/bindings/interrupt-controller/technologic,ts4800.txt

··· 1 - TS-4800 FPGA interrupt controller 2 - 3 - TS-4800 FPGA has an internal interrupt controller. When one of the 4 - interrupts is triggered, the SoC is notified, usually using a GPIO as 5 - parent interrupt source. 6 - 7 - Required properties: 8 - - compatible: should be "technologic,ts4800-irqc" 9 - - interrupt-controller: identifies the node as an interrupt controller 10 - - reg: physical base address of the controller and length of memory mapped 11 - region 12 - - #interrupt-cells: specifies the number of cells needed to encode an interrupt 13 - source, should be 1. 14 - - interrupts: specifies the interrupt line in the interrupt-parent controller

-27

Documentation/devicetree/bindings/interrupt-controller/ti,cp-intc.txt

··· 1 - * TI Common Platform Interrupt Controller 2 - 3 - Common Platform Interrupt Controller (cp_intc) is used on 4 - OMAP-L1x SoCs and can support several configurable number 5 - of interrupts. 6 - 7 - Main node required properties: 8 - 9 - - compatible : should be: 10 - "ti,cp-intc" 11 - - interrupt-controller : Identifies the node as an interrupt controller 12 - - #interrupt-cells : Specifies the number of cells needed to encode an 13 - interrupt source. The type shall be a <u32> and the value shall be 1. 14 - 15 - The cell contains the interrupt number in the range [0-128]. 16 - - ti,intc-size: Number of interrupts handled by the interrupt controller. 17 - - reg: physical base address and size of the intc registers map. 18 - 19 - Example: 20 - 21 - intc: interrupt-controller@1 { 22 - compatible = "ti,cp-intc"; 23 - interrupt-controller; 24 - #interrupt-cells = <1>; 25 - ti,intc-size = <101>; 26 - reg = <0xfffee000 0x2000>; 27 - };

+50

Documentation/devicetree/bindings/interrupt-controller/ti,cp-intc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/ti,cp-intc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: TI Common Platform Interrupt Controller 8 + 9 + maintainers: 10 + - Bartosz Golaszewski <brgl@bgdev.pl> 11 + 12 + description: 13 + Common Platform Interrupt Controller (cp_intc) is used on OMAP-L1x SoCs and 14 + can support several configurable number of interrupts. 15 + 16 + properties: 17 + compatible: 18 + const: ti,cp-intc 19 + 20 + reg: 21 + maxItems: 1 22 + 23 + interrupt-controller: true 24 + 25 + '#interrupt-cells': 26 + const: 1 27 + description: Encodes an interrupt number in the range 0–128. 28 + 29 + ti,intc-size: 30 + description: Number of interrupts handled by the interrupt controller. 31 + $ref: /schemas/types.yaml#/definitions/uint32 32 + 33 + required: 34 + - compatible 35 + - reg 36 + - interrupt-controller 37 + - '#interrupt-cells' 38 + - ti,intc-size 39 + 40 + additionalProperties: false 41 + 42 + examples: 43 + - | 44 + interrupt-controller@fffee000 { 45 + compatible = "ti,cp-intc"; 46 + reg = <0xfffee000 0x2000>; 47 + interrupt-controller; 48 + #interrupt-cells = <1>; 49 + ti,intc-size = <101>; 50 + };

-36

Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.txt

··· 1 - Keystone 2 IRQ controller IP 2 - 3 - On Keystone SOCs, DSP cores can send interrupts to ARM 4 - host using the IRQ controller IP. It provides 28 IRQ signals to ARM. 5 - The IRQ handler running on HOST OS can identify DSP signal source by 6 - analyzing SRCCx bits in IPCARx registers. This is one of the component 7 - used by the IPC mechanism used on Keystone SOCs. 8 - 9 - Required Properties: 10 - - compatible: should be "ti,keystone-irq" 11 - - ti,syscon-dev : phandle and offset pair. The phandle to syscon used to 12 - access device control registers and the offset inside 13 - device control registers range. 14 - - interrupt-controller : Identifies the node as an interrupt controller 15 - - #interrupt-cells : Specifies the number of cells needed to encode interrupt 16 - source should be 1. 17 - - interrupts: interrupt reference to primary interrupt controller 18 - 19 - Please refer to interrupts.txt in this directory for details of the common 20 - Interrupt Controllers bindings used by client devices. 21 - 22 - Example: 23 - kirq0: keystone_irq0@26202a0 { 24 - compatible = "ti,keystone-irq"; 25 - ti,syscon-dev = <&devctrl 0x2a0>; 26 - interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; 27 - interrupt-controller; 28 - #interrupt-cells = <1>; 29 - }; 30 - 31 - dsp0: dsp0 { 32 - compatible = "linux,rproc-user"; 33 - ... 34 - interrupt-parent = <&kirq0>; 35 - interrupts = <10 2>; 36 - };

+63

Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/ti,keystone-irq.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Keystone 2 IRQ controller IP 8 + 9 + maintainers: 10 + - Grygorii Strashko <grygorii.strashko@ti.com> 11 + 12 + description: 13 + On Keystone SOCs, DSP cores can send interrupts to ARM host using the IRQ 14 + controller IP. It provides 28 IRQ signals to ARM. The IRQ handler running on 15 + HOST OS can identify DSP signal source by analyzing SRCCx bits in IPCARx 16 + registers. This is one of the component used by the IPC mechanism used on 17 + Keystone SOCs. 18 + 19 + properties: 20 + compatible: 21 + const: ti,keystone-irq 22 + 23 + reg: 24 + maxItems: 1 25 + 26 + interrupt-controller: true 27 + 28 + '#interrupt-cells': 29 + const: 1 30 + 31 + interrupts: 32 + maxItems: 1 33 + 34 + ti,syscon-dev: 35 + description: Phandle and offset to syscon device 36 + $ref: /schemas/types.yaml#/definitions/phandle-array 37 + items: 38 + - items: 39 + - description: Phandle to syscon device control registers 40 + - description: Offset to control register 41 + 42 + required: 43 + - compatible 44 + - reg 45 + - interrupt-controller 46 + - '#interrupt-cells' 47 + - interrupts 48 + - ti,syscon-dev 49 + 50 + additionalProperties: false 51 + 52 + examples: 53 + - | 54 + #include <dt-bindings/interrupt-controller/arm-gic.h> 55 + 56 + interrupt-controller@2a0 { 57 + compatible = "ti,keystone-irq"; 58 + reg = <0x2a0 0x4>; 59 + ti,syscon-dev = <&devctrl 0x2a0>; 60 + interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; 61 + interrupt-controller; 62 + #interrupt-cells = <1>; 63 + };

-28

Documentation/devicetree/bindings/interrupt-controller/ti,omap-intc-irq.txt

··· 1 - Omap2/3 intc controller 2 - 3 - On TI omap2 and 3 the intc interrupt controller can provide 4 - 96 or 128 IRQ signals to the ARM host depending on the SoC. 5 - 6 - Required Properties: 7 - - compatible: should be one of 8 - "ti,omap2-intc" 9 - "ti,omap3-intc" 10 - "ti,dm814-intc" 11 - "ti,dm816-intc" 12 - "ti,am33xx-intc" 13 - 14 - - interrupt-controller : Identifies the node as an interrupt controller 15 - - #interrupt-cells : Specifies the number of cells needed to encode interrupt 16 - source, should be 1 for intc 17 - - interrupts: interrupt reference to primary interrupt controller 18 - 19 - Please refer to interrupts.txt in this directory for details of the common 20 - Interrupt Controllers bindings used by client devices. 21 - 22 - Example: 23 - intc: interrupt-controller@48200000 { 24 - compatible = "ti,omap3-intc"; 25 - interrupt-controller; 26 - #interrupt-cells = <1>; 27 - reg = <0x48200000 0x1000>; 28 - };

+52

Documentation/devicetree/bindings/interrupt-controller/ti,omap-intc-irq.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/ti,omap-intc-irq.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: TI OMAP Interrupt Controller 8 + 9 + maintainers: 10 + - Tony Lindgren <tony@atomide.com> 11 + 12 + description: 13 + On TI omap2 and 3 the intc interrupt controller can provide 96 or 128 IRQ 14 + signals to the ARM host depending on the SoC. 15 + 16 + properties: 17 + compatible: 18 + enum: 19 + - ti,omap2-intc 20 + - ti,omap3-intc 21 + - ti,dm814-intc 22 + - ti,dm816-intc 23 + - ti,am33xx-intc 24 + 25 + reg: 26 + maxItems: 1 27 + 28 + interrupts: 29 + maxItems: 1 30 + 31 + interrupt-controller: true 32 + 33 + '#interrupt-cells': 34 + const: 1 35 + 36 + required: 37 + - compatible 38 + - reg 39 + - interrupt-controller 40 + - '#interrupt-cells' 41 + 42 + additionalProperties: false 43 + 44 + examples: 45 + - | 46 + interrupt-controller@48200000 { 47 + compatible = "ti,omap3-intc"; 48 + reg = <0x48200000 0x1000>; 49 + interrupts = <32>; 50 + interrupt-controller; 51 + #interrupt-cells = <1>; 52 + };

-27

Documentation/devicetree/bindings/interrupt-controller/ti,omap2-intc.txt

··· 1 - * OMAP Interrupt Controller 2 - 3 - OMAP2/3 are using a TI interrupt controller that can support several 4 - configurable number of interrupts. 5 - 6 - Main node required properties: 7 - 8 - - compatible : should be: 9 - "ti,omap2-intc" 10 - - interrupt-controller : Identifies the node as an interrupt controller 11 - - #interrupt-cells : Specifies the number of cells needed to encode an 12 - interrupt source. The type shall be a <u32> and the value shall be 1. 13 - 14 - The cell contains the interrupt number in the range [0-128]. 15 - - ti,intc-size: Number of interrupts handled by the interrupt controller. 16 - - reg: physical base address and size of the intc registers map. 17 - 18 - Example: 19 - 20 - intc: interrupt-controller@1 { 21 - compatible = "ti,omap2-intc"; 22 - interrupt-controller; 23 - #interrupt-cells = <1>; 24 - ti,intc-size = <96>; 25 - reg = <0x48200000 0x1000>; 26 - }; 27 -

-31

Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu.txt

··· 1 - TI OMAP4 Wake-up Generator 2 - 3 - All TI OMAP4/5 (and their derivatives) an interrupt controller that 4 - routes interrupts to the GIC, and also serves as a wakeup source. It 5 - is also referred to as "WUGEN-MPU", hence the name of the binding. 6 - 7 - Required properties: 8 - 9 - - compatible : should contain at least "ti,omap4-wugen-mpu" or 10 - "ti,omap5-wugen-mpu" 11 - - reg : Specifies base physical address and size of the registers. 12 - - interrupt-controller : Identifies the node as an interrupt controller. 13 - - #interrupt-cells : Specifies the number of cells needed to encode an 14 - interrupt source. The value must be 3. 15 - 16 - Notes: 17 - 18 - - Because this HW ultimately routes interrupts to the GIC, the 19 - interrupt specifier must be that of the GIC. 20 - - Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs 21 - are explicitly forbidden. 22 - 23 - Example: 24 - 25 - wakeupgen: interrupt-controller@48281000 { 26 - compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; 27 - interrupt-controller; 28 - #interrupt-cells = <3>; 29 - reg = <0x48281000 0x1000>; 30 - interrupt-parent = <&gic>; 31 - };

+55

Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/ti,omap4-wugen-mpu.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: TI OMAP4 Wake-up Generator 8 + 9 + maintainers: 10 + - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 11 + 12 + description: > 13 + All TI OMAP4/5 (and their derivatives) are interrupt controllers that route 14 + interrupts to the GIC, and also serve as wakeup sources. They are also 15 + referred to as "WUGEN-MPU", hence the name of the binding. 16 + 17 + Notes: 18 + 19 + - Because this HW ultimately routes interrupts to the GIC, the interrupt 20 + specifier must be that of the GIC. 21 + - Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs are 22 + explicitly forbidden. 23 + 24 + properties: 25 + compatible: 26 + oneOf: 27 + - items: 28 + - const: ti,omap5-wugen-mpu 29 + - const: ti,omap4-wugen-mpu 30 + - const: ti,omap4-wugen-mpu 31 + 32 + reg: 33 + maxItems: 1 34 + 35 + interrupt-controller: true 36 + 37 + '#interrupt-cells': 38 + const: 3 39 + 40 + required: 41 + - compatible 42 + - reg 43 + - interrupt-controller 44 + - '#interrupt-cells' 45 + 46 + additionalProperties: false 47 + 48 + examples: 49 + - | 50 + interrupt-controller@48281000 { 51 + compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; 52 + reg = <0x48281000 0x1000>; 53 + interrupt-controller; 54 + #interrupt-cells = <3>; 55 + };

-16

Documentation/devicetree/bindings/interrupt-controller/via,vt8500-intc.txt

··· 1 - VIA/Wondermedia VT8500 Interrupt Controller 2 - ----------------------------------------------------- 3 - 4 - Required properties: 5 - - compatible : "via,vt8500-intc" 6 - - reg : Should contain 1 register ranges(address and length) 7 - - #interrupt-cells : should be <1> 8 - 9 - Example: 10 - 11 - intc: interrupt-controller@d8140000 { 12 - compatible = "via,vt8500-intc"; 13 - interrupt-controller; 14 - reg = <0xd8140000 0x10000>; 15 - #interrupt-cells = <1>; 16 - };

+76

Documentation/devicetree/bindings/interrupt-controller/via,vt8500-intc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/interrupt-controller/via,vt8500-intc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: VIA and WonderMedia SoCs Interrupt Controller 8 + 9 + description: 10 + This is the interrupt controller used in single-core ARM SoCs made by 11 + VIA and WonderMedia (up to and including WM8950). Each block handles 12 + up to 64 interrupt sources (level or edge triggered) and can generate 13 + up to 8 interrupts to its parent when used in a chained configuration. 14 + 15 + maintainers: 16 + - Alexey Charkov <alchark@gmail.com> 17 + 18 + allOf: 19 + - $ref: /schemas/interrupt-controller.yaml# 20 + 21 + properties: 22 + compatible: 23 + const: via,vt8500-intc 24 + 25 + reg: 26 + maxItems: 1 27 + 28 + interrupts: 29 + items: 30 + - description: 31 + Interrupt number raised by the IRQ0 output of this controller 32 + Only used if this controller is chained 33 + - description: 34 + Interrupt number raised by the IRQ1 output of this controller 35 + Only used if this controller is chained 36 + - description: 37 + Interrupt number raised by the IRQ2 output of this controller 38 + Only used if this controller is chained 39 + - description: 40 + Interrupt number raised by the IRQ3 output of this controller 41 + Only used if this controller is chained 42 + - description: 43 + Interrupt number raised by the IRQ4 output of this controller 44 + Only used if this controller is chained 45 + - description: 46 + Interrupt number raised by the IRQ5 output of this controller 47 + Only used if this controller is chained 48 + - description: 49 + Interrupt number raised by the IRQ6 output of this controller 50 + Only used if this controller is chained 51 + - description: 52 + Interrupt number raised by the IRQ7 output of this controller 53 + Only used if this controller is chained 54 + 55 + interrupt-controller: true 56 + 57 + '#interrupt-cells': 58 + const: 1 59 + 60 + required: 61 + - compatible 62 + - reg 63 + - interrupt-controller 64 + - '#interrupt-cells' 65 + 66 + additionalProperties: false 67 + 68 + examples: 69 + - | 70 + interrupt-controller@d8140000 { 71 + compatible = "via,vt8500-intc"; 72 + interrupt-controller; 73 + reg = <0xd8140000 0x10000>; 74 + #interrupt-cells = <1>; 75 + }; 76 + ...

+80

Documentation/devicetree/bindings/leds/backlight/ti,lp8864.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/leds/backlight/ti,lp8864.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Texas Instruments - LP8864/LP8866 4/6-Channel LED Driver family 8 + 9 + maintainers: 10 + - Andrew Davis <afd@ti.com> 11 + - Alexander Sverdlin <alexander.sverdlin@siemens.com> 12 + 13 + description: | 14 + LP8866-Q1, LP8866S-Q1, LP8864-Q1, LP8864S-Q1 are display LED-backlight drivers 15 + with 4/6 channels. LED brightness can be controlled globally through the I2C 16 + interface or PWM input. 17 + 18 + For more product information please see the links below: 19 + https://www.ti.com/product/LP8864-Q1 20 + https://www.ti.com/product/LP8864S-Q1 21 + https://www.ti.com/product/LP8866-Q1 22 + https://www.ti.com/product/LP8866S-Q1 23 + 24 + properties: 25 + compatible: 26 + const: ti,lp8864 27 + 28 + reg: 29 + maxItems: 1 30 + description: I2C slave address 31 + 32 + enable-gpios: 33 + maxItems: 1 34 + description: GPIO pin to enable (active high) / disable the device 35 + 36 + vled-supply: 37 + description: LED supply 38 + 39 + led: 40 + type: object 41 + $ref: common.yaml# 42 + properties: 43 + function: true 44 + color: true 45 + label: true 46 + linux,default-trigger: true 47 + 48 + additionalProperties: false 49 + 50 + required: 51 + - compatible 52 + - reg 53 + - led 54 + 55 + additionalProperties: false 56 + 57 + examples: 58 + - | 59 + #include <dt-bindings/gpio/gpio.h> 60 + #include <dt-bindings/leds/common.h> 61 + 62 + i2c { 63 + #address-cells = <1>; 64 + #size-cells = <0>; 65 + 66 + led-controller@3a { 67 + compatible = "ti,lp8864"; 68 + reg = <0x3a>; 69 + enable-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; 70 + vled-supply = <&vbatt>; 71 + 72 + led { 73 + function = LED_FUNCTION_BACKLIGHT; 74 + color = <LED_COLOR_ID_WHITE>; 75 + linux,default-trigger = "backlight"; 76 + }; 77 + }; 78 + }; 79 + 80 + ...

+4 -1

Documentation/devicetree/bindings/media/i2c/sony,imx219.yaml

··· 16 16 Image data is sent through MIPI CSI-2, which is configured as either 2 or 17 17 4 data lanes. 18 18 19 + allOf: 20 + - $ref: /schemas/media/video-interface-devices.yaml# 21 + 19 22 properties: 20 23 compatible: 21 24 const: sony,imx219 ··· 82 79 - VDDL-supply 83 80 - port 84 81 85 - additionalProperties: false 82 + unevaluatedProperties: false 86 83 87 84 examples: 88 85 - |

+12 -11

Documentation/devicetree/bindings/media/renesas,fcp.yaml

··· 36 36 reg: 37 37 maxItems: 1 38 38 39 - clocks: true 39 + clocks: 40 + minItems: 1 41 + items: 42 + - description: Main clock 43 + - description: Register access clock 44 + - description: Video clock 40 45 41 - clock-names: true 46 + clock-names: 47 + items: 48 + - const: aclk 49 + - const: pclk 50 + - const: vclk 42 51 43 52 iommus: 44 53 maxItems: 1 ··· 80 71 then: 81 72 properties: 82 73 clocks: 83 - items: 84 - - description: Main clock 85 - - description: Register access clock 86 - - description: Video clock 87 - clock-names: 88 - items: 89 - - const: aclk 90 - - const: pclk 91 - - const: vclk 74 + minItems: 3 92 75 required: 93 76 - clock-names 94 77 else:

+13 -11

Documentation/devicetree/bindings/media/renesas,vsp1.yaml

··· 34 34 interrupts: 35 35 maxItems: 1 36 36 37 - clocks: true 38 - clock-names: true 37 + clocks: 38 + minItems: 1 39 + items: 40 + - description: Main clock 41 + - description: Register access clock 42 + - description: Video clock 43 + 44 + clock-names: 45 + items: 46 + - const: aclk 47 + - const: pclk 48 + - const: vclk 39 49 40 50 power-domains: 41 51 maxItems: 1 ··· 89 79 then: 90 80 properties: 91 81 clocks: 92 - items: 93 - - description: Main clock 94 - - description: Register access clock 95 - - description: Video clock 96 - clock-names: 97 - items: 98 - - const: aclk 99 - - const: pclk 100 - - const: vclk 82 + minItems: 3 101 83 required: 102 84 - clock-names 103 85 else:

+8 -1

Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml

··· 66 66 - compatible 67 67 68 68 '^interrupt-controller@[0-9a-f]+$': 69 - description: See Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic.txt 70 69 type: object 70 + additionalProperties: true 71 + properties: 72 + compatible: 73 + contains: 74 + enum: 75 + - aspeed,ast2500-scu-ic 76 + - aspeed,ast2600-scu-ic0 77 + - aspeed,ast2600-scu-ic1 71 78 72 79 '^silicon-id@[0-9a-f]+$': 73 80 description: Unique hardware silicon identifiers within the SoC

+2 -1

Documentation/devicetree/bindings/mips/cpus.yaml

··· 50 50 device_type: true 51 51 52 52 allOf: 53 + - $ref: /schemas/opp/opp-v1.yaml# 53 54 - if: 54 55 properties: 55 56 compatible: ··· 69 68 - compatible 70 69 - reg 71 70 72 - additionalProperties: false 71 + unevaluatedProperties: false 73 72 74 73 examples: 75 74 - |

+1 -3

Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml

··· 16 16 - nxp,sja1000 17 17 - technologic,sja1000 18 18 - items: 19 - - enum: 20 - - renesas,r9a06g032-sja1000 # RZ/N1D 21 - - renesas,r9a06g033-sja1000 # RZ/N1S 19 + - const: renesas,r9a06g032-sja1000 # RZ/N1D 22 20 - const: renesas,rzn1-sja1000 # RZ/N1 23 21 24 22 reg:

-319

Documentation/devicetree/bindings/numa.txt

··· 1 - ============================================================================== 2 - NUMA binding description. 3 - ============================================================================== 4 - 5 - ============================================================================== 6 - 1 - Introduction 7 - ============================================================================== 8 - 9 - Systems employing a Non Uniform Memory Access (NUMA) architecture contain 10 - collections of hardware resources including processors, memory, and I/O buses, 11 - that comprise what is commonly known as a NUMA node. 12 - Processor accesses to memory within the local NUMA node is generally faster 13 - than processor accesses to memory outside of the local NUMA node. 14 - DT defines interfaces that allow the platform to convey NUMA node 15 - topology information to OS. 16 - 17 - ============================================================================== 18 - 2 - numa-node-id 19 - ============================================================================== 20 - 21 - For the purpose of identification, each NUMA node is associated with a unique 22 - token known as a node id. For the purpose of this binding 23 - a node id is a 32-bit integer. 24 - 25 - A device node is associated with a NUMA node by the presence of a 26 - numa-node-id property which contains the node id of the device. 27 - 28 - Example: 29 - /* numa node 0 */ 30 - numa-node-id = <0>; 31 - 32 - /* numa node 1 */ 33 - numa-node-id = <1>; 34 - 35 - ============================================================================== 36 - 3 - distance-map 37 - ============================================================================== 38 - 39 - The optional device tree node distance-map describes the relative 40 - distance (memory latency) between all numa nodes. 41 - 42 - - compatible : Should at least contain "numa-distance-map-v1". 43 - 44 - - distance-matrix 45 - This property defines a matrix to describe the relative distances 46 - between all numa nodes. 47 - It is represented as a list of node pairs and their relative distance. 48 - 49 - Note: 50 - 1. Each entry represents distance from first node to second node. 51 - The distances are equal in either direction. 52 - 2. The distance from a node to self (local distance) is represented 53 - with value 10 and all internode distance should be represented with 54 - a value greater than 10. 55 - 3. distance-matrix should have entries in lexicographical ascending 56 - order of nodes. 57 - 4. There must be only one device node distance-map which must 58 - reside in the root node. 59 - 5. If the distance-map node is not present, a default 60 - distance-matrix is used. 61 - 62 - Example: 63 - 4 nodes connected in mesh/ring topology as below, 64 - 65 - 0_______20______1 66 - | | 67 - | | 68 - 20 20 69 - | | 70 - | | 71 - |_______________| 72 - 3 20 2 73 - 74 - if relative distance for each hop is 20, 75 - then internode distance would be, 76 - 0 -> 1 = 20 77 - 1 -> 2 = 20 78 - 2 -> 3 = 20 79 - 3 -> 0 = 20 80 - 0 -> 2 = 40 81 - 1 -> 3 = 40 82 - 83 - and dt presentation for this distance matrix is, 84 - 85 - distance-map { 86 - compatible = "numa-distance-map-v1"; 87 - distance-matrix = <0 0 10>, 88 - <0 1 20>, 89 - <0 2 40>, 90 - <0 3 20>, 91 - <1 0 20>, 92 - <1 1 10>, 93 - <1 2 20>, 94 - <1 3 40>, 95 - <2 0 40>, 96 - <2 1 20>, 97 - <2 2 10>, 98 - <2 3 20>, 99 - <3 0 20>, 100 - <3 1 40>, 101 - <3 2 20>, 102 - <3 3 10>; 103 - }; 104 - 105 - ============================================================================== 106 - 4 - Empty memory nodes 107 - ============================================================================== 108 - 109 - Empty memory nodes, which no memory resides in, are allowed. There are no 110 - device nodes for these empty memory nodes. However, the NUMA node IDs and 111 - distance maps are still valid and memory may be added into them through 112 - hotplug afterwards. 113 - 114 - Example: 115 - 116 - memory@0 { 117 - device_type = "memory"; 118 - reg = <0x0 0x0 0x0 0x80000000>; 119 - numa-node-id = <0>; 120 - }; 121 - 122 - memory@80000000 { 123 - device_type = "memory"; 124 - reg = <0x0 0x80000000 0x0 0x80000000>; 125 - numa-node-id = <1>; 126 - }; 127 - 128 - /* Empty memory node 2 and 3 */ 129 - distance-map { 130 - compatible = "numa-distance-map-v1"; 131 - distance-matrix = <0 0 10>, 132 - <0 1 20>, 133 - <0 2 40>, 134 - <0 3 20>, 135 - <1 0 20>, 136 - <1 1 10>, 137 - <1 2 20>, 138 - <1 3 40>, 139 - <2 0 40>, 140 - <2 1 20>, 141 - <2 2 10>, 142 - <2 3 20>, 143 - <3 0 20>, 144 - <3 1 40>, 145 - <3 2 20>, 146 - <3 3 10>; 147 - }; 148 - 149 - ============================================================================== 150 - 5 - Example dts 151 - ============================================================================== 152 - 153 - Dual socket system consists of 2 boards connected through ccn bus and 154 - each board having one socket/soc of 8 cpus, memory and pci bus. 155 - 156 - memory@c00000 { 157 - device_type = "memory"; 158 - reg = <0x0 0xc00000 0x0 0x80000000>; 159 - /* node 0 */ 160 - numa-node-id = <0>; 161 - }; 162 - 163 - memory@10000000000 { 164 - device_type = "memory"; 165 - reg = <0x100 0x0 0x0 0x80000000>; 166 - /* node 1 */ 167 - numa-node-id = <1>; 168 - }; 169 - 170 - cpus { 171 - #address-cells = <2>; 172 - #size-cells = <0>; 173 - 174 - cpu@0 { 175 - device_type = "cpu"; 176 - compatible = "arm,armv8"; 177 - reg = <0x0 0x0>; 178 - enable-method = "psci"; 179 - /* node 0 */ 180 - numa-node-id = <0>; 181 - }; 182 - cpu@1 { 183 - device_type = "cpu"; 184 - compatible = "arm,armv8"; 185 - reg = <0x0 0x1>; 186 - enable-method = "psci"; 187 - numa-node-id = <0>; 188 - }; 189 - cpu@2 { 190 - device_type = "cpu"; 191 - compatible = "arm,armv8"; 192 - reg = <0x0 0x2>; 193 - enable-method = "psci"; 194 - numa-node-id = <0>; 195 - }; 196 - cpu@3 { 197 - device_type = "cpu"; 198 - compatible = "arm,armv8"; 199 - reg = <0x0 0x3>; 200 - enable-method = "psci"; 201 - numa-node-id = <0>; 202 - }; 203 - cpu@4 { 204 - device_type = "cpu"; 205 - compatible = "arm,armv8"; 206 - reg = <0x0 0x4>; 207 - enable-method = "psci"; 208 - numa-node-id = <0>; 209 - }; 210 - cpu@5 { 211 - device_type = "cpu"; 212 - compatible = "arm,armv8"; 213 - reg = <0x0 0x5>; 214 - enable-method = "psci"; 215 - numa-node-id = <0>; 216 - }; 217 - cpu@6 { 218 - device_type = "cpu"; 219 - compatible = "arm,armv8"; 220 - reg = <0x0 0x6>; 221 - enable-method = "psci"; 222 - numa-node-id = <0>; 223 - }; 224 - cpu@7 { 225 - device_type = "cpu"; 226 - compatible = "arm,armv8"; 227 - reg = <0x0 0x7>; 228 - enable-method = "psci"; 229 - numa-node-id = <0>; 230 - }; 231 - cpu@8 { 232 - device_type = "cpu"; 233 - compatible = "arm,armv8"; 234 - reg = <0x0 0x8>; 235 - enable-method = "psci"; 236 - /* node 1 */ 237 - numa-node-id = <1>; 238 - }; 239 - cpu@9 { 240 - device_type = "cpu"; 241 - compatible = "arm,armv8"; 242 - reg = <0x0 0x9>; 243 - enable-method = "psci"; 244 - numa-node-id = <1>; 245 - }; 246 - cpu@a { 247 - device_type = "cpu"; 248 - compatible = "arm,armv8"; 249 - reg = <0x0 0xa>; 250 - enable-method = "psci"; 251 - numa-node-id = <1>; 252 - }; 253 - cpu@b { 254 - device_type = "cpu"; 255 - compatible = "arm,armv8"; 256 - reg = <0x0 0xb>; 257 - enable-method = "psci"; 258 - numa-node-id = <1>; 259 - }; 260 - cpu@c { 261 - device_type = "cpu"; 262 - compatible = "arm,armv8"; 263 - reg = <0x0 0xc>; 264 - enable-method = "psci"; 265 - numa-node-id = <1>; 266 - }; 267 - cpu@d { 268 - device_type = "cpu"; 269 - compatible = "arm,armv8"; 270 - reg = <0x0 0xd>; 271 - enable-method = "psci"; 272 - numa-node-id = <1>; 273 - }; 274 - cpu@e { 275 - device_type = "cpu"; 276 - compatible = "arm,armv8"; 277 - reg = <0x0 0xe>; 278 - enable-method = "psci"; 279 - numa-node-id = <1>; 280 - }; 281 - cpu@f { 282 - device_type = "cpu"; 283 - compatible = "arm,armv8"; 284 - reg = <0x0 0xf>; 285 - enable-method = "psci"; 286 - numa-node-id = <1>; 287 - }; 288 - }; 289 - 290 - pcie0: pcie0@848000000000 { 291 - compatible = "arm,armv8"; 292 - device_type = "pci"; 293 - bus-range = <0 255>; 294 - #size-cells = <2>; 295 - #address-cells = <3>; 296 - reg = <0x8480 0x00000000 0 0x10000000>; /* Configuration space */ 297 - ranges = <0x03000000 0x8010 0x00000000 0x8010 0x00000000 0x70 0x00000000>; 298 - /* node 0 */ 299 - numa-node-id = <0>; 300 - }; 301 - 302 - pcie1: pcie1@948000000000 { 303 - compatible = "arm,armv8"; 304 - device_type = "pci"; 305 - bus-range = <0 255>; 306 - #size-cells = <2>; 307 - #address-cells = <3>; 308 - reg = <0x9480 0x00000000 0 0x10000000>; /* Configuration space */ 309 - ranges = <0x03000000 0x9010 0x00000000 0x9010 0x00000000 0x70 0x00000000>; 310 - /* node 1 */ 311 - numa-node-id = <1>; 312 - }; 313 - 314 - distance-map { 315 - compatible = "numa-distance-map-v1"; 316 - distance-matrix = <0 0 10>, 317 - <0 1 20>, 318 - <1 1 10>; 319 - };

+17 -1

Documentation/devicetree/bindings/opp/opp-v1.yaml

··· 18 18 19 19 This binding only supports voltage-frequency pairs. 20 20 21 - select: true 21 + deprecated: true 22 22 23 23 properties: 24 + clock-latency: 25 + $ref: /schemas/types.yaml#/definitions/uint32 26 + description: 27 + The latency in nanoseconds for clock changes. Use OPP tables for new 28 + designs instead. 29 + 30 + voltage-tolerance: 31 + $ref: /schemas/types.yaml#/definitions/uint32 32 + maximum: 10 33 + description: 34 + The voltage tolerance in percent. Use OPP tables for new designs instead. 35 + 24 36 operating-points: 25 37 $ref: /schemas/types.yaml#/definitions/uint32-matrix 26 38 items: ··· 40 28 - description: Frequency in kHz 41 29 - description: Voltage for OPP in uV 42 30 31 + dependencies: 32 + clock-latency: [ operating-points ] 33 + voltage-tolerance: [ operating-points ] 43 34 44 35 additionalProperties: true 36 + 45 37 examples: 46 38 - | 47 39 cpus {

-65

Documentation/devicetree/bindings/pci/altr,msi-controller.yaml

··· 1 - # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 - # Copyright (C) 2015, 2024, Intel Corporation 3 - %YAML 1.2 4 - --- 5 - $id: http://devicetree.org/schemas/altr,msi-controller.yaml# 6 - $schema: http://devicetree.org/meta-schemas/core.yaml# 7 - 8 - title: Altera PCIe MSI controller 9 - 10 - maintainers: 11 - - Matthew Gerlach <matthew.gerlach@linux.intel.com> 12 - 13 - properties: 14 - compatible: 15 - enum: 16 - - altr,msi-1.0 17 - 18 - reg: 19 - items: 20 - - description: CSR registers 21 - - description: Vectors slave port region 22 - 23 - reg-names: 24 - items: 25 - - const: csr 26 - - const: vector_slave 27 - 28 - interrupts: 29 - maxItems: 1 30 - 31 - msi-controller: true 32 - 33 - num-vectors: 34 - description: number of vectors 35 - $ref: /schemas/types.yaml#/definitions/uint32 36 - minimum: 1 37 - maximum: 32 38 - 39 - required: 40 - - compatible 41 - - reg 42 - - reg-names 43 - - interrupts 44 - - msi-controller 45 - - num-vectors 46 - 47 - allOf: 48 - - $ref: /schemas/interrupt-controller/msi-controller.yaml# 49 - 50 - unevaluatedProperties: false 51 - 52 - examples: 53 - - | 54 - #include <dt-bindings/interrupt-controller/arm-gic.h> 55 - #include <dt-bindings/interrupt-controller/irq.h> 56 - msi@ff200000 { 57 - compatible = "altr,msi-1.0"; 58 - reg = <0xff200000 0x00000010>, 59 - <0xff200010 0x00000080>; 60 - reg-names = "csr", "vector_slave"; 61 - interrupt-parent = <&hps_0_arm_gic_0>; 62 - interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 63 - msi-controller; 64 - num-vectors = <32>; 65 - };

+1

Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml

··· 65 65 patternProperties: 66 66 "^group-[0-9a-z-]+$": 67 67 type: object 68 + unevaluatedProperties: false 68 69 allOf: 69 70 - $ref: /schemas/pinctrl/pincfg-node.yaml 70 71 - $ref: /schemas/pinctrl/pinmux-node.yaml

+1 -3

Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml

··· 13 13 properties: 14 14 compatible: 15 15 items: 16 - - enum: 17 - - renesas,r9a06g032-pinctrl # RZ/N1D 18 - - renesas,r9a06g033-pinctrl # RZ/N1S 16 + - const: renesas,r9a06g032-pinctrl # RZ/N1D 19 17 - const: renesas,rzn1-pinctrl # Generic RZ/N1 20 18 21 19 reg:

-63

Documentation/devicetree/bindings/powerpc/fsl/pmc.txt

··· 1 - * Power Management Controller 2 - 3 - Properties: 4 - - compatible: "fsl,<chip>-pmc". 5 - 6 - "fsl,mpc8349-pmc" should be listed for any chip whose PMC is 7 - compatible. "fsl,mpc8313-pmc" should also be listed for any chip 8 - whose PMC is compatible, and implies deep-sleep capability. 9 - 10 - "fsl,mpc8548-pmc" should be listed for any chip whose PMC is 11 - compatible. "fsl,mpc8536-pmc" should also be listed for any chip 12 - whose PMC is compatible, and implies deep-sleep capability. 13 - 14 - "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is 15 - compatible; all statements below that apply to "fsl,mpc8548-pmc" also 16 - apply to "fsl,mpc8641d-pmc". 17 - 18 - Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these 19 - bit assignments are indicated via the sleep specifier in each device's 20 - sleep property. 21 - 22 - - reg: For devices compatible with "fsl,mpc8349-pmc", the first resource 23 - is the PMC block, and the second resource is the Clock Configuration 24 - block. 25 - 26 - For devices compatible with "fsl,mpc8548-pmc", the first resource 27 - is a 32-byte block beginning with DEVDISR. 28 - 29 - - interrupts: For "fsl,mpc8349-pmc"-compatible devices, the first 30 - resource is the PMC block interrupt. 31 - 32 - - fsl,mpc8313-wakeup-timer: For "fsl,mpc8313-pmc"-compatible devices, 33 - this is a phandle to an "fsl,gtm" node on which timer 4 can be used as 34 - a wakeup source from deep sleep. 35 - 36 - Sleep specifiers: 37 - 38 - fsl,mpc8349-pmc: Sleep specifiers consist of one cell. For each bit 39 - that is set in the cell, the corresponding bit in SCCR will be saved 40 - and cleared on suspend, and restored on resume. This sleep controller 41 - supports disabling and resuming devices at any time. 42 - 43 - fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of 44 - which will be ORed into PMCDR upon suspend, and cleared from PMCDR 45 - upon resume. The first two cells are as described for fsl,mpc8578-pmc. 46 - This sleep controller only supports disabling devices during system 47 - sleep, or permanently. 48 - 49 - fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the 50 - first of which will be ORed into DEVDISR (and the second into 51 - DEVDISR2, if present -- this cell should be zero or absent if the 52 - hardware does not have DEVDISR2) upon a request for permanent device 53 - disabling. This sleep controller does not support configuring devices 54 - to disable during system sleep (unless supported by another compatible 55 - match), or dynamically. 56 - 57 - Example: 58 - 59 - power@b00 { 60 - compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc"; 61 - reg = <0xb00 0x100 0xa00 0x100>; 62 - interrupts = <80 8>; 63 - };

+152

Documentation/devicetree/bindings/powerpc/fsl/pmc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/powerpc/fsl/pmc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Power Management Controller 8 + 9 + maintainers: 10 + - J. Neuschäfer <j.ne@posteo.net> 11 + 12 + description: | 13 + The Power Management Controller in several MPC8xxx SoCs helps save power by 14 + controlling chip-wide low-power states as well as peripheral clock gating. 15 + 16 + Sleep of peripheral devices is configured by the `sleep` property, for 17 + example `sleep = <&pmc 0x00000030>`. Any cells after the &pmc phandle are 18 + called a sleep specifier. 19 + 20 + For "fsl,mpc8349-pmc", sleep specifiers consist of one cell. For each bit that 21 + is set in the cell, the corresponding bit in SCCR will be saved and cleared 22 + on suspend, and restored on resume. This sleep controller supports disabling 23 + and resuming devices at any time. 24 + 25 + For "fsl,mpc8536-pmc", sleep specifiers consist of three cells, the third of 26 + which will be ORed into PMCDR upon suspend, and cleared from PMCDR upon 27 + resume. The first two cells are as described for fsl,mpc8548-pmc. This 28 + sleep controller only supports disabling devices during system sleep, or 29 + permanently. 30 + 31 + For "fsl,mpc8548-pmc" or "fsl,mpc8641d-pmc", Sleep specifiers consist of one 32 + or two cells, the first of which will be ORed into DEVDISR (and the second 33 + into DEVDISR2, if present -- this cell should be zero or absent if the 34 + hardware does not have DEVDISR2) upon a request for permanent device 35 + disabling. This sleep controller does not support configuring devices to 36 + disable during system sleep (unless supported by another compatible match), 37 + or dynamically. 38 + 39 + properties: 40 + compatible: 41 + oneOf: 42 + - items: 43 + - const: fsl,mpc8315-pmc 44 + - const: fsl,mpc8313-pmc 45 + - const: fsl,mpc8349-pmc 46 + 47 + - items: 48 + - enum: 49 + - fsl,mpc8313-pmc 50 + - fsl,mpc8323-pmc 51 + - fsl,mpc8360-pmc 52 + - fsl,mpc8377-pmc 53 + - fsl,mpc8378-pmc 54 + - fsl,mpc8379-pmc 55 + - const: fsl,mpc8349-pmc 56 + 57 + - items: 58 + - const: fsl,p1022-pmc 59 + - const: fsl,mpc8536-pmc 60 + - const: fsl,mpc8548-pmc 61 + 62 + - items: 63 + - enum: 64 + - fsl,mpc8536-pmc 65 + - fsl,mpc8568-pmc 66 + - fsl,mpc8569-pmc 67 + - const: fsl,mpc8548-pmc 68 + 69 + - enum: 70 + - fsl,mpc8548-pmc 71 + - fsl,mpc8641d-pmc 72 + 73 + description: | 74 + "fsl,mpc8349-pmc" should be listed for any chip whose PMC is 75 + compatible. "fsl,mpc8313-pmc" should also be listed for any chip 76 + whose PMC is compatible, and implies deep-sleep capability. 77 + 78 + "fsl,mpc8548-pmc" should be listed for any chip whose PMC is 79 + compatible. "fsl,mpc8536-pmc" should also be listed for any chip 80 + whose PMC is compatible, and implies deep-sleep capability. 81 + 82 + "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is 83 + compatible; all statements below that apply to "fsl,mpc8548-pmc" also 84 + apply to "fsl,mpc8641d-pmc". 85 + 86 + Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these 87 + bit assignments are indicated via the sleep specifier in each device's 88 + sleep property. 89 + 90 + reg: 91 + minItems: 1 92 + maxItems: 2 93 + 94 + interrupts: 95 + maxItems: 1 96 + 97 + fsl,mpc8313-wakeup-timer: 98 + $ref: /schemas/types.yaml#/definitions/phandle 99 + description: 100 + For "fsl,mpc8313-pmc"-compatible devices, this is a phandle to an 101 + "fsl,gtm" node on which timer 4 can be used as a wakeup source from deep 102 + sleep. 103 + 104 + allOf: 105 + - if: 106 + properties: 107 + compatible: 108 + contains: 109 + const: fsl,mpc8349-pmc 110 + then: 111 + properties: 112 + reg: 113 + items: 114 + - description: PMC block 115 + - description: Clock Configuration block 116 + 117 + - if: 118 + properties: 119 + compatible: 120 + contains: 121 + enum: 122 + - fsl,mpc8548-pmc 123 + - fsl,mpc8641d-pmc 124 + then: 125 + properties: 126 + reg: 127 + items: 128 + - description: 32-byte block beginning with DEVDISR 129 + 130 + required: 131 + - compatible 132 + - reg 133 + 134 + additionalProperties: false 135 + 136 + examples: 137 + - | 138 + #include <dt-bindings/interrupt-controller/irq.h> 139 + 140 + pmc: power@b00 { 141 + compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc"; 142 + reg = <0xb00 0x100>, <0xa00 0x100>; 143 + interrupts = <80 IRQ_TYPE_LEVEL_LOW>; 144 + }; 145 + 146 + - | 147 + power@e0070 { 148 + compatible = "fsl,mpc8548-pmc"; 149 + reg = <0xe0070 0x20>; 150 + }; 151 + 152 + ...

+3 -9

Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml

··· 17 17 properties: 18 18 compatible: 19 19 items: 20 - - enum: 21 - - renesas,r9a06g032-uart 22 - - renesas,r9a06g033-uart 20 + - const: renesas,r9a06g032-uart 23 21 - const: renesas,rzn1-uart 24 22 - const: snps,dw-apb-uart 25 23 then: ··· 43 45 compatible: 44 46 oneOf: 45 47 - items: 46 - - enum: 47 - - renesas,r9a06g032-uart 48 - - renesas,r9a06g033-uart 48 + - const: renesas,r9a06g032-uart 49 49 - const: renesas,rzn1-uart 50 50 - const: snps,dw-apb-uart 51 51 - items: 52 - - enum: 53 - - renesas,r9a06g032-uart 54 - - renesas,r9a06g033-uart 52 + - const: renesas,r9a06g032-uart 55 53 - const: renesas,rzn1-uart 56 54 - items: 57 55 - enum:

+2 -2

Documentation/devicetree/bindings/soc/fsl/fsl,qman-fqd.yaml

··· 50 50 - compatible 51 51 52 52 allOf: 53 - - $ref: reserved-memory.yaml 53 + - $ref: /schemas/reserved-memory/reserved-memory.yaml 54 54 55 55 unevaluatedProperties: false 56 56 ··· 61 61 #size-cells = <2>; 62 62 63 63 qman-fqd { 64 - compatible = "shared-dma-pool"; 64 + compatible = "fsl,qman-fqd"; 65 65 size = <0 0x400000>; 66 66 alignment = <0 0x400000>; 67 67 no-map;

+2 -1

Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml

··· 73 73 #size-cells = <0>; 74 74 75 75 cpu@0 { 76 - compatible = "qcom,kryo"; 76 + compatible = "arm,cortex-a53"; 77 77 device_type = "cpu"; 78 78 enable-method = "qcom,kpss-acc-v2"; 79 + qcom,acc = <&acc0>; 79 80 qcom,saw = <&saw0>; 80 81 reg = <0x0>; 81 82 operating-points-v2 = <&cpu_opp_table>;

+1

Documentation/devicetree/bindings/sound/qcom,sm8250.yaml

··· 28 28 - qcom,sm8750-sndcard 29 29 - const: qcom,sm8450-sndcard 30 30 - enum: 31 + - fairphone,fp5-sndcard 31 32 - qcom,apq8096-sndcard 32 33 - qcom,qcm6490-idp-sndcard 33 34 - qcom,qcs6490-rb3gen2-sndcard

+12 -7

Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml

··· 15 15 16 16 properties: 17 17 compatible: 18 - enum: 19 - - qcom,soundwire-v1.3.0 20 - - qcom,soundwire-v1.5.0 21 - - qcom,soundwire-v1.5.1 22 - - qcom,soundwire-v1.6.0 23 - - qcom,soundwire-v1.7.0 24 - - qcom,soundwire-v2.0.0 18 + oneOf: 19 + - enum: 20 + - qcom,soundwire-v1.3.0 21 + - qcom,soundwire-v1.5.0 22 + - qcom,soundwire-v1.5.1 23 + - qcom,soundwire-v1.6.0 24 + - qcom,soundwire-v1.7.0 25 + - qcom,soundwire-v2.0.0 26 + - items: 27 + - enum: 28 + - qcom,soundwire-v2.1.0 29 + - const: qcom,soundwire-v2.0.0 25 30 26 31 reg: 27 32 maxItems: 1

+1 -3

Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml

··· 83 83 const: canaan,k210-spi 84 84 - description: Renesas RZ/N1 SPI Controller 85 85 items: 86 - - enum: 87 - - renesas,r9a06g032-spi # RZ/N1D 88 - - renesas,r9a06g033-spi # RZ/N1S 86 + - const: renesas,r9a06g032-spi # RZ/N1D 89 87 - const: renesas,rzn1-spi # RZ/N1 90 88 91 89 reg:

+54

Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/timer/fsl,vf610-pit.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Freescale Periodic Interrupt Timer (PIT) 8 + 9 + maintainers: 10 + - Frank Li <Frank.Li@nxp.com> 11 + 12 + description: 13 + The PIT module is an array of timers that can be used to raise interrupts 14 + and trigger DMA channels. 15 + 16 + properties: 17 + compatible: 18 + enum: 19 + - fsl,vf610-pit 20 + 21 + reg: 22 + maxItems: 1 23 + 24 + interrupts: 25 + maxItems: 1 26 + 27 + clocks: 28 + maxItems: 1 29 + 30 + clock-names: 31 + items: 32 + - const: pit 33 + 34 + required: 35 + - compatible 36 + - reg 37 + - interrupts 38 + - clocks 39 + - clock-names 40 + 41 + additionalProperties: false 42 + 43 + examples: 44 + - | 45 + #include <dt-bindings/clock/vf610-clock.h> 46 + #include <dt-bindings/interrupt-controller/irq.h> 47 + 48 + timer@40037000 { 49 + compatible = "fsl,vf610-pit"; 50 + reg = <0x40037000 0x1000>; 51 + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; 52 + clocks = <&clks VF610_CLK_PIT>; 53 + clock-names = "pit"; 54 + };

+4

Documentation/devicetree/bindings/trivial-devices.yaml

··· 173 173 - maxim,ds3502 174 174 # Temperature Sensor, I2C interface 175 175 - maxim,max1619 176 + # Digital temperature sensor with 0.1°C accuracy 177 + - maxim,max30208 176 178 # 3-Channel Remote Temperature Sensor 177 179 - maxim,max31730 178 180 # 10-bit 10 kOhm linear programmable voltage divider ··· 345 343 - sensortek,stk8ba50 346 344 # SGX Sensortech VZ89X Sensors 347 345 - sgx,vz89x 346 + # SGX Sensortech VZ89TE Sensors 347 + - sgx,vz89te 348 348 # Silicon Labs EM3581 Zigbee SoC with SPI interface 349 349 - silabs,em3581 350 350 # Silicon Labs SI3210 Programmable CMOS SLIC/CODEC with SPI interface

+2

Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml

··· 26 26 27 27 ranges: true 28 28 29 + dma-coherent: true 30 + 29 31 power-domains: 30 32 description: specifies a phandle to PM domain provider node 31 33 maxItems: 1

+2

Documentation/devicetree/bindings/vendor-prefixes.yaml

··· 434 434 description: EBV Elektronik 435 435 "^eckelmann,.*": 436 436 description: Eckelmann AG 437 + "^econet,.*": 438 + description: EcoNet (HK) Limited 437 439 "^edgeble,.*": 438 440 description: Edgeble AI Technologies Pvt. Ltd. 439 441 "^edimax,.*":

+4 -6

Documentation/devicetree/bindings/virtio/pci-iommu.yaml

··· 20 20 virtio-iommu node doesn't have an "iommus" property, and is omitted from 21 21 the iommu-map property of the root complex. 22 22 23 + allOf: 24 + - $ref: /schemas/pci/pci-device.yaml# 25 + 23 26 properties: 24 27 # If compatible is present, it should contain the vendor and device ID 25 28 # according to the PCI Bus Binding specification. Since PCI provides ··· 36 33 - const: pci1af4,1057 37 34 38 35 reg: 39 - description: | 40 - PCI address of the IOMMU. As defined in the PCI Bus Binding 41 - reference, the reg property is a five-cell address encoded as (phys.hi 42 - phys.mid phys.lo size.hi size.lo). phys.hi should contain the device's 43 - BDF as 0b00000000 bbbbbbbb dddddfff 00000000. The other cells should be 44 - zero. See Documentation/devicetree/bindings/pci/pci.txt 36 + maxItems: 1 45 37 46 38 '#iommu-cells': 47 39 const: 1

+2

Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml

··· 35 35 - fsl,imx8mp-wdt 36 36 - fsl,imx8mq-wdt 37 37 - fsl,ls1012a-wdt 38 + - fsl,ls1021a-wdt 38 39 - fsl,ls1043a-wdt 39 40 - fsl,vf610-wdt 40 41 - const: fsl,imx21-wdt ··· 103 102 contains: 104 103 enum: 105 104 - fsl,ls1012a-wdt 105 + - fsl,ls1021a-wdt 106 106 - fsl,ls1043a-wdt 107 107 then: 108 108 properties:

+8 -3

Documentation/devicetree/bindings/writing-schema.rst

··· 117 117 should be allowed. 118 118 119 119 * additionalProperties: true 120 - Rare case, used for schemas implementing common set of properties. Such 121 - schemas are supposed to be referenced by other schemas, which then use 122 - 'unevaluatedProperties: false'. Typically bus or common-part schemas. 120 + - Top-level part: 121 + Rare case, used for schemas implementing common set of properties. Such 122 + schemas are supposed to be referenced by other schemas, which then use 123 + 'unevaluatedProperties: false'. Typically bus or common-part schemas. 124 + - Nested node: 125 + When listing only the expected compatible of the nested node and there 126 + is an another schema matching that compatible which ends with one of 127 + two above cases ('false'). 123 128 124 129 examples 125 130 Optional. A list of one or more DTS hunks implementing this binding only.

+6 -6

Documentation/devicetree/overlay-notes.rst

··· 38 38 }; 39 39 ---- foo.dts --------------------------------------------------------------- 40 40 41 - The overlay bar.dts, 41 + The overlay bar.dtso, 42 42 :: 43 43 44 - ---- bar.dts - overlay target location by label ---------------------------- 44 + ---- bar.dtso - overlay target location by label --------------------------- 45 45 /dts-v1/; 46 46 /plugin/; 47 47 &ocp { ··· 51 51 ... /* various properties and child nodes */ 52 52 }; 53 53 }; 54 - ---- bar.dts --------------------------------------------------------------- 54 + ---- bar.dtso -------------------------------------------------------------- 55 55 56 56 when loaded (and resolved as described in [1]) should result in foo+bar.dts:: 57 57 ··· 88 88 location by label syntax is preferred because the overlay can be applied to 89 89 any base DT containing the label, no matter where the label occurs in the DT. 90 90 91 - The above bar.dts example modified to use target path syntax is:: 91 + The above bar.dtso example modified to use target path syntax is:: 92 92 93 - ---- bar.dts - overlay target location by explicit path -------------------- 93 + ---- bar.dtso - overlay target location by explicit path ------------------- 94 94 /dts-v1/; 95 95 /plugin/; 96 96 &{/ocp} { ··· 100 100 ... /* various properties and child nodes */ 101 101 } 102 102 }; 103 - ---- bar.dts --------------------------------------------------------------- 103 + ---- bar.dtso -------------------------------------------------------------- 104 104 105 105 106 106 Overlay in-kernel API

+6 -6

Documentation/translations/zh_CN/devicetree/overlay-notes.rst

··· 43 43 }; 44 44 ---- foo.dts --------------------------------------------------------------- 45 45 46 - 覆盖bar.dts, 46 + 覆盖bar.dtso, 47 47 :: 48 48 49 - ---- bar.dts - 按标签覆盖目标位置 ---------------------------- 49 + ---- bar.dtso - 按标签覆盖目标位置 --------------------------- 50 50 /dts-v1/; 51 51 /插件/; 52 52 &ocp { ··· 56 56 ... /* 各种属性和子节点 */ 57 57 }; 58 58 }; 59 - ---- bar.dts --------------------------------------------------------------- 59 + ---- bar.dtso -------------------------------------------------------------- 60 60 61 61 当加载（并按照[1]中描述的方式解决）时，应该产生foo+bar.dts:: 62 62 ··· 90 90 DT中的适当位置。在这种情况下，可以提供目标路径。通过标签的目标位置的语法是比 91 91 较好的，因为不管标签在DT中出现在哪里，覆盖都可以被应用到任何包含标签的基础DT上。 92 92 93 - 上面的bar.dts例子被修改为使用目标路径语法，即为:: 93 + 上面的bar.dtso例子被修改为使用目标路径语法，即为:: 94 94 95 - ---- bar.dts - 通过明确的路径覆盖目标位置 -------------------- 95 + ---- bar.dtso - 通过明确的路径覆盖目标位置 ------------------- 96 96 /dts-v1/; 97 97 /插件/; 98 98 &{/ocp} { ··· 102 102 ... /* 各种外围设备和子节点 */ 103 103 } 104 104 }; 105 - ---- bar.dts --------------------------------------------------------------- 105 + ---- bar.dtso -------------------------------------------------------------- 106 106 107 107 108 108 内核中关于覆盖的API

+10 -8

MAINTAINERS

··· 948 948 AMAZON ANNAPURNA LABS FIC DRIVER 949 949 M: Talel Shenhar <talel@amazon.com> 950 950 S: Maintained 951 - F: Documentation/devicetree/bindings/interrupt-controller/amazon,al-fic.txt 951 + F: Documentation/devicetree/bindings/interrupt-controller/amazon,al-fic.yaml 952 952 F: drivers/irqchip/irq-al-fic.c 953 953 954 954 AMAZON ANNAPURNA LABS MEMORY CONTROLLER EDAC ··· 1736 1736 ANDROID GOLDFISH PIC DRIVER 1737 1737 M: Miodrag Dinic <miodrag.dinic@mips.com> 1738 1738 S: Supported 1739 - F: Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.txt 1739 + F: Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.yaml 1740 1740 F: drivers/irqchip/irq-goldfish-pic.c 1741 1741 1742 1742 ANDROID GOLDFISH RTC DRIVER ··· 1960 1960 F: Documentation/devicetree/bindings/auxdisplay/arm,versatile-lcd.yaml 1961 1961 F: Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml 1962 1962 F: Documentation/devicetree/bindings/i2c/arm,i2c-versatile.yaml 1963 - F: Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt 1963 + F: Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.yaml 1964 1964 F: Documentation/devicetree/bindings/mtd/mtd-physmap.yaml 1965 1965 F: arch/arm/boot/dts/arm/arm-realview-* 1966 1966 F: arch/arm/boot/dts/arm/integrator* ··· 2371 2371 L: openbmc@lists.ozlabs.org (moderated for non-subscribers) 2372 2372 S: Maintained 2373 2373 F: Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml 2374 - F: Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-i2c-ic.txt 2374 + F: Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-i2c-ic.yaml 2375 2375 F: drivers/i2c/busses/i2c-aspeed.c 2376 2376 F: drivers/irqchip/irq-aspeed-i2c-ic.c 2377 2377 ··· 3478 3478 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 3479 3479 S: Odd Fixes 3480 3480 F: Documentation/devicetree/bindings/i2c/i2c-wmt.txt 3481 + F: Documentation/devicetree/bindings/interrupt-controller/via,vt8500-intc.yaml 3481 3482 F: Documentation/devicetree/bindings/pwm/via,vt8500-pwm.yaml 3482 3483 F: arch/arm/boot/dts/vt8500/ 3483 3484 F: arch/arm/mach-vt8500/ ··· 3629 3628 M: Eddie James <eajames@linux.ibm.com> 3630 3629 L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers) 3631 3630 S: Maintained 3632 - F: Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic.txt 3631 + F: Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2500-scu-ic.yaml 3633 3632 F: drivers/irqchip/irq-aspeed-scu-ic.c 3634 3633 F: include/dt-bindings/interrupt-controller/aspeed-scu-ic.h 3635 3634 ··· 7987 7986 S: Supported 7988 7987 T: git https://gitlab.freedesktop.org/drm/misc/kernel.git 7989 7988 F: Documentation/devicetree/bindings/display/fsl,dcu.txt 7990 - F: Documentation/devicetree/bindings/display/fsl,tcon.txt 7989 + F: Documentation/devicetree/bindings/display/fsl,vf610-tcon.yaml 7991 7990 F: drivers/gpu/drm/fsl-dcu/ 7992 7991 7993 7992 DRM DRIVERS FOR FREESCALE IMX 5/6 ··· 9297 9296 M: Patrick Havelange <patrick.havelange@essensium.com> 9298 9297 L: linux-iio@vger.kernel.org 9299 9298 S: Maintained 9300 - F: Documentation/devicetree/bindings/counter/ftm-quaddec.txt 9299 + F: Documentation/devicetree/bindings/counter/fsl,ftm-quaddec.yaml 9301 9300 F: drivers/counter/ftm-quaddec.c 9302 9301 9303 9302 FLOPPY DRIVER ··· 18968 18967 M: Joyce Ooi <joyce.ooi@intel.com> 18969 18968 L: linux-pci@vger.kernel.org 18970 18969 S: Supported 18971 - F: Documentation/devicetree/bindings/pci/altr,msi-controller.yaml 18970 + F: Documentation/devicetree/bindings/interrupt-controller/altr,msi-controller.yaml 18972 18971 F: drivers/pci/controller/pcie-altera-msi.c 18973 18972 18974 18973 PCI MSI DRIVER FOR APPLIEDMICRO XGENE ··· 19609 19608 M: Lorenzo Pieralisi <lpieralisi@kernel.org> 19610 19609 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 19611 19610 S: Maintained 19611 + F: Documentation/devicetree/bindings/arm/psci.yaml 19612 19612 F: drivers/firmware/psci/ 19613 19613 F: include/linux/psci.h 19614 19614 F: include/uapi/linux/psci.h

+11 -20

drivers/of/device.c

··· 35 35 static void 36 36 of_dma_set_restricted_buffer(struct device *dev, struct device_node *np) 37 37 { 38 - struct device_node *node, *of_node = dev->of_node; 39 - int count, i; 38 + struct device_node *of_node = dev->of_node; 39 + struct of_phandle_iterator it; 40 + int rc, i = 0; 40 41 41 42 if (!IS_ENABLED(CONFIG_DMA_RESTRICTED_POOL)) 42 43 return; 43 44 44 - count = of_property_count_elems_of_size(of_node, "memory-region", 45 - sizeof(u32)); 46 45 /* 47 46 * If dev->of_node doesn't exist or doesn't contain memory-region, try 48 47 * the OF node having DMA configuration. 49 48 */ 50 - if (count <= 0) { 49 + if (!of_property_present(of_node, "memory-region")) 51 50 of_node = np; 52 - count = of_property_count_elems_of_size( 53 - of_node, "memory-region", sizeof(u32)); 54 - } 55 51 56 - for (i = 0; i < count; i++) { 57 - node = of_parse_phandle(of_node, "memory-region", i); 52 + of_for_each_phandle(&it, rc, of_node, "memory-region", NULL, 0) { 58 53 /* 59 54 * There might be multiple memory regions, but only one 60 55 * restricted-dma-pool region is allowed. 61 56 */ 62 - if (of_device_is_compatible(node, "restricted-dma-pool") && 63 - of_device_is_available(node)) { 64 - of_node_put(node); 57 + if (of_device_is_compatible(it.node, "restricted-dma-pool") && 58 + of_device_is_available(it.node)) { 59 + if (of_reserved_mem_device_init_by_idx(dev, of_node, i)) 60 + dev_warn(dev, "failed to initialise \"restricted-dma-pool\" memory node\n"); 61 + of_node_put(it.node); 65 62 break; 66 63 } 67 - of_node_put(node); 64 + i++; 68 65 } 69 66 70 - /* 71 - * Attempt to initialize a restricted-dma-pool region if one was found. 72 - * Note that count can hold a negative error code. 73 - */ 74 - if (i < count && of_reserved_mem_device_init_by_idx(dev, of_node, i)) 75 - dev_warn(dev, "failed to initialise \"restricted-dma-pool\" memory node\n"); 76 67 } 77 68 78 69 /**

+80

drivers/of/of_reserved_mem.c

··· 12 12 #define pr_fmt(fmt) "OF: reserved mem: " fmt 13 13 14 14 #include <linux/err.h> 15 + #include <linux/ioport.h> 15 16 #include <linux/libfdt.h> 16 17 #include <linux/of.h> 17 18 #include <linux/of_fdt.h> ··· 741 740 return NULL; 742 741 } 743 742 EXPORT_SYMBOL_GPL(of_reserved_mem_lookup); 743 + 744 + /** 745 + * of_reserved_mem_region_to_resource() - Get a reserved memory region as a resource 746 + * @np: node containing 'memory-region' property 747 + * @idx: index of 'memory-region' property to lookup 748 + * @res: Pointer to a struct resource to fill in with reserved region 749 + * 750 + * This function allows drivers to lookup a node's 'memory-region' property 751 + * entries by index and return a struct resource for the entry. 752 + * 753 + * Returns 0 on success with @res filled in. Returns -ENODEV if 'memory-region' 754 + * is missing or unavailable, -EINVAL for any other error. 755 + */ 756 + int of_reserved_mem_region_to_resource(const struct device_node *np, 757 + unsigned int idx, struct resource *res) 758 + { 759 + struct reserved_mem *rmem; 760 + 761 + if (!np) 762 + return -EINVAL; 763 + 764 + struct device_node __free(device_node) *target = of_parse_phandle(np, "memory-region", idx); 765 + if (!target || !of_device_is_available(target)) 766 + return -ENODEV; 767 + 768 + rmem = of_reserved_mem_lookup(target); 769 + if (!rmem) 770 + return -EINVAL; 771 + 772 + resource_set_range(res, rmem->base, rmem->size); 773 + res->name = rmem->name; 774 + return 0; 775 + } 776 + EXPORT_SYMBOL_GPL(of_reserved_mem_region_to_resource); 777 + 778 + /** 779 + * of_reserved_mem_region_to_resource_byname() - Get a reserved memory region as a resource 780 + * @np: node containing 'memory-region' property 781 + * @name: name of 'memory-region' property entry to lookup 782 + * @res: Pointer to a struct resource to fill in with reserved region 783 + * 784 + * This function allows drivers to lookup a node's 'memory-region' property 785 + * entries by name and return a struct resource for the entry. 786 + * 787 + * Returns 0 on success with @res filled in, or a negative error-code on 788 + * failure. 789 + */ 790 + int of_reserved_mem_region_to_resource_byname(const struct device_node *np, 791 + const char *name, 792 + struct resource *res) 793 + { 794 + int idx; 795 + 796 + if (!name) 797 + return -EINVAL; 798 + 799 + idx = of_property_match_string(np, "memory-region-names", name); 800 + if (idx < 0) 801 + return idx; 802 + 803 + return of_reserved_mem_region_to_resource(np, idx, res); 804 + } 805 + EXPORT_SYMBOL_GPL(of_reserved_mem_region_to_resource_byname); 806 + 807 + /** 808 + * of_reserved_mem_region_count() - Return the number of 'memory-region' entries 809 + * @np: node containing 'memory-region' property 810 + * 811 + * This function allows drivers to retrieve the number of entries for a node's 812 + * 'memory-region' property. 813 + * 814 + * Returns the number of entries on success, or negative error code on a 815 + * malformed property. 816 + */ 817 + int of_reserved_mem_region_count(const struct device_node *np) 818 + { 819 + return of_count_phandle_with_args(np, "memory-region", NULL); 820 + } 821 + EXPORT_SYMBOL_GPL(of_reserved_mem_region_count);

+6 -4

drivers/of/unittest.c

··· 2029 2029 rc = of_resolve_phandles(unittest_data_node); 2030 2030 if (rc) { 2031 2031 pr_err("%s: Failed to resolve phandles (rc=%i)\n", __func__, rc); 2032 - of_overlay_mutex_unlock(); 2033 - return -EINVAL; 2032 + rc = -EINVAL; 2033 + goto unlock; 2034 2034 } 2035 2035 2036 2036 /* attach the sub-tree to live tree */ 2037 2037 if (!of_root) { 2038 2038 pr_warn("%s: no live tree to attach sub-tree\n", __func__); 2039 2039 kfree(unittest_data); 2040 - return -ENODEV; 2040 + rc = -ENODEV; 2041 + goto unlock; 2041 2042 } 2042 2043 2043 2044 EXPECT_BEGIN(KERN_INFO, ··· 2057 2056 EXPECT_END(KERN_INFO, 2058 2057 "Duplicate name in testcase-data, renamed to \"duplicate-name#1\""); 2059 2058 2059 + unlock: 2060 2060 of_overlay_mutex_unlock(); 2061 2061 2062 - return 0; 2062 + return rc; 2063 2063 } 2064 2064 2065 2065 #ifdef CONFIG_OF_OVERLAY

+26

include/linux/of_reserved_mem.h

··· 7 7 8 8 struct of_phandle_args; 9 9 struct reserved_mem_ops; 10 + struct resource; 10 11 11 12 struct reserved_mem { 12 13 const char *name; ··· 40 39 void of_reserved_mem_device_release(struct device *dev); 41 40 42 41 struct reserved_mem *of_reserved_mem_lookup(struct device_node *np); 42 + int of_reserved_mem_region_to_resource(const struct device_node *np, 43 + unsigned int idx, struct resource *res); 44 + int of_reserved_mem_region_to_resource_byname(const struct device_node *np, 45 + const char *name, struct resource *res); 46 + int of_reserved_mem_region_count(const struct device_node *np); 47 + 43 48 #else 44 49 45 50 #define RESERVEDMEM_OF_DECLARE(name, compat, init) \ ··· 69 62 static inline struct reserved_mem *of_reserved_mem_lookup(struct device_node *np) 70 63 { 71 64 return NULL; 65 + } 66 + 67 + static inline int of_reserved_mem_region_to_resource(const struct device_node *np, 68 + unsigned int idx, 69 + struct resource *res) 70 + { 71 + return -ENOSYS; 72 + } 73 + 74 + static inline int of_reserved_mem_region_to_resource_byname(const struct device_node *np, 75 + const char *name, 76 + struct resource *res) 77 + { 78 + return -ENOSYS; 79 + } 80 + 81 + static inline int of_reserved_mem_region_count(const struct device_node *np) 82 + { 83 + return 0; 72 84 } 73 85 #endif 74 86

+1

lib/devres.c

··· 206 206 { 207 207 return __devm_ioremap_resource(dev, res, DEVM_IOREMAP_WC); 208 208 } 209 + EXPORT_SYMBOL(devm_ioremap_resource_wc); 209 210 210 211 /* 211 212 * devm_of_iomap - Requests a resource and maps the memory mapped IO

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