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Merge branch 'net-dsa-ks8995-fix-up-bindings'
Linus Walleij says:
====================
net: dsa: ks8995: Fix up bindings
After looking at the datasheets for KS8995 I realized this is
a DSA switch and need to have DT bindings as such and be implemented
as such.
This series just fixes up the bindings and the offending device tree.
The existing kernel driver which is in drivers/net/phy/spi_ks8995.c
does not implement DSA. It can be forgiven for this because it was
merged in 2011 and the DSA framework was not widely established
back then. It continues to probe fine but needs to be rewritten
to use the special DSA tag and moved to drivers/net/dsa as time
permits. (I hope I can do this.)
It's fine for the networking tree to merge both patches, I maintain
ixp4xx as well. But I can also carry the second patch through the
SoC tree if so desired.
v1: https://lore.kernel.org/20250624-ks8995-dsa-bindings-v1-0-71a8b4f63315@linaro.org
====================
Link: https://patch.msgid.link/20250625-ks8995-dsa-bindings-v2-0-ce71dce9be0b@linaro.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+213
-34
+135
Documentation/devicetree/bindings/net/dsa/micrel,ks8995.yaml
+135
Documentation/devicetree/bindings/net/dsa/micrel,ks8995.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+
%YAML 1.2
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---
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+
$id: http://devicetree.org/schemas/net/dsa/micrel,ks8995.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Micrel KS8995 Family DSA Switches
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+
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maintainers:
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- Linus Walleij <linus.walleij@linaro.org>
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+
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description:
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The Micrel KS8995 DSA Switches are 100 Mbit switches that were produced in
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the early-to-mid 2000s. The chip features a CPU port and four outgoing ports,
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each with an internal PHY. The chip itself is managed over SPI, but all the
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PHYs need to be accessed from an external MDIO channel.
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+
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Further, a fifth PHY is available and can be used separately from the switch
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fabric, connected to an external MII interface name MII-P5. This is
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unrelated from the CPU-facing port 5 which is used for DSA MII traffic.
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+
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properties:
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compatible:
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enum:
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- micrel,ks8995
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- micrel,ksz8795
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+
- micrel,ksz8864
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+
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reg:
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maxItems: 1
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+
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reset-gpios:
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description: GPIO to be used to reset the whole device
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+
maxItems: 1
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+
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allOf:
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- $ref: dsa.yaml#/$defs/ethernet-ports
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- $ref: /schemas/spi/spi-peripheral-props.yaml#
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+
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required:
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- compatible
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- reg
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+
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unevaluatedProperties: false
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+
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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+
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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+
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ethernet-switch@0 {
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compatible = "micrel,ks8995";
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reg = <0>;
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+
spi-max-frequency = <25000000>;
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+
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+
ethernet-ports {
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+
#address-cells = <1>;
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+
#size-cells = <0>;
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+
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+
ethernet-port@0 {
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+
reg = <0>;
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+
label = "lan1";
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};
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ethernet-port@1 {
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reg = <1>;
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label = "lan2";
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};
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ethernet-port@2 {
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reg = <2>;
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label = "lan3";
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};
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+
ethernet-port@3 {
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reg = <3>;
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label = "lan4";
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+
};
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+
ethernet-port@4 {
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reg = <4>;
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ethernet = <&mac2>;
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phy-mode = "mii";
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fixed-link {
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speed = <100>;
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full-duplex;
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+
};
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+
};
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};
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};
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+
};
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+
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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+
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/* The WAN port connected on MII-P5 */
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ethernet-port@1000 {
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reg = <0x00001000 0x1000>;
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label = "wan";
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+
phy-mode = "mii";
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+
phy-handle = <&phy5>;
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};
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+
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mac2: ethernet-port@2000 {
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reg = <0x00002000 0x1000>;
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+
phy-mode = "mii";
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+
fixed-link {
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speed = <100>;
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full-duplex;
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+
};
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+
};
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+
};
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+
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+
mdio {
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+
#address-cells = <1>;
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+
#size-cells = <0>;
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+
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/* LAN PHYs 1-4 accessible over external MDIO */
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+
phy1: ethernet-phy@1 {
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+
reg = <1>;
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+
};
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+
phy2: ethernet-phy@2 {
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+
reg = <2>;
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+
};
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+
phy3: ethernet-phy@3 {
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+
reg = <3>;
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+
};
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+
phy4: ethernet-phy@4 {
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+
reg = <4>;
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+
};
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+
/* WAN PHY accessible over external MDIO */
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+
phy5: ethernet-phy@5 {
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+
reg = <5>;
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+
};
135
+
};
-20
Documentation/devicetree/bindings/net/micrel-ks8995.txt
-20
Documentation/devicetree/bindings/net/micrel-ks8995.txt
···
1
-
Micrel KS8995 SPI controlled Ethernet Switch families
2
-
3
-
Required properties (according to spi-bus.txt):
4
-
- compatible: either "micrel,ks8995", "micrel,ksz8864" or "micrel,ksz8795"
5
-
6
-
Optional properties:
7
-
- reset-gpios : phandle of gpio that will be used to reset chip during probe
8
-
9
-
Example:
10
-
11
-
spi-master {
12
-
...
13
-
switch@0 {
14
-
compatible = "micrel,ksz8795";
15
-
16
-
reg = <0>;
17
-
spi-max-frequency = <50000000>;
18
-
reset-gpios = <&gpio0 46 GPIO_ACTIVE_LOW>;
19
-
};
20
-
};
+78
-14
arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts
+78
-14
arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts
···
72
72
cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
73
73
num-chipselects = <1>;
74
74
75
-
switch@0 {
75
+
ethernet-switch@0 {
76
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compatible = "micrel,ks8995";
77
77
reg = <0>;
78
78
spi-max-frequency = <50000000>;
79
+
80
+
/*
81
+
* The PHYs are accessed over the external MDIO
82
+
* bus and not internally through the switch control
83
+
* registers.
84
+
*/
85
+
ethernet-ports {
86
+
#address-cells = <1>;
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+
#size-cells = <0>;
88
+
89
+
ethernet-port@0 {
90
+
reg = <0>;
91
+
label = "1";
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+
phy-mode = "mii";
93
+
phy-handle = <&phy1>;
94
+
};
95
+
ethernet-port@1 {
96
+
reg = <1>;
97
+
label = "2";
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+
phy-mode = "mii";
99
+
phy-handle = <&phy2>;
100
+
};
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+
ethernet-port@2 {
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+
reg = <2>;
103
+
label = "3";
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+
phy-mode = "mii";
105
+
phy-handle = <&phy3>;
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+
};
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+
ethernet-port@3 {
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+
reg = <3>;
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+
label = "4";
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+
phy-mode = "mii";
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+
phy-handle = <&phy4>;
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+
};
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+
ethernet-port@4 {
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+
reg = <4>;
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+
ethernet = <ðb>;
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+
phy-mode = "mii";
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+
fixed-link {
118
+
speed = <100>;
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+
full-duplex;
120
+
};
121
+
};
122
+
123
+
};
79
124
};
80
125
};
81
126
···
180
135
};
181
136
182
137
/*
183
-
* EthB - connected to the KS8995 switch ports 1-4
184
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* FIXME: the boardfile defines .phy_mask = 0x1e for this port to enable output to
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* all four switch ports, also using an out of tree multiphy patch.
186
-
* Do we need a new binding and property for this?
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+
* EthB connects to the KS8995 CPU port and faces ports 1-4
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+
* through the switch fabric.
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+
*
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+
* To complicate things, the MDIO channel is also only
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+
* accessible through EthB, but used independently for PHY
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+
* control.
187
144
*/
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-
ethernet@c8009000 {
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+
ethb: ethernet@c8009000 {
189
146
status = "okay";
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147
queue-rx = <&qmgr 3>;
191
148
queue-txready = <&qmgr 20>;
192
-
phy-mode = "rgmii";
193
-
phy-handle = <&phy4>;
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+
phy-mode = "mii";
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+
fixed-link {
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+
speed = <100>;
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+
full-duplex;
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+
};
194
154
195
155
mdio {
196
156
#address-cells = <1>;
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157
#size-cells = <0>;
198
158
199
-
/* Should be ports 1-4 on the KS8995 switch */
159
+
/*
160
+
* LAN ports 1-4 on the KS8995 switch
161
+
* and PHY5 for WAN need to be accessed
162
+
* through this external MDIO channel.
163
+
*/
164
+
phy1: ethernet-phy@1 {
165
+
reg = <1>;
166
+
};
167
+
phy2: ethernet-phy@2 {
168
+
reg = <2>;
169
+
};
170
+
phy3: ethernet-phy@3 {
171
+
reg = <3>;
172
+
};
200
173
phy4: ethernet-phy@4 {
201
174
reg = <4>;
202
175
};
203
-
204
-
/* Should be port 5 on the KS8995 switch */
205
176
phy5: ethernet-phy@5 {
206
177
reg = <5>;
207
178
};
208
179
};
209
180
};
210
181
211
-
/* EthC - connected to KS8995 switch port 5 */
212
-
ethernet@c800a000 {
182
+
/*
183
+
* EthC connects to MII-P5 on the KS8995 bypassing
184
+
* all of the switch logic and facing PHY5
185
+
*/
186
+
ethc: ethernet@c800a000 {
213
187
status = "okay";
214
188
queue-rx = <&qmgr 4>;
215
189
queue-txready = <&qmgr 21>;
216
-
phy-mode = "rgmii";
190
+
phy-mode = "mii";
217
191
phy-handle = <&phy5>;
218
192
};
219
193
};