Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'mtd/fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
Pull mtd fixes from Miquel Raynal.
* 'mtd/fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux:
mtd: rawnand: stm32_fmc2: fix broken ECC
mtd: spi-nor: Fix address width on flash chips > 16MB
mtd: spi-nor: Don't copy self-pointing struct around
mtd: rawnand: ifc: Move the ECC engine initialization to the right place
mtd: rawnand: mxc: Move the ECC engine initialization to the right place
+44
-44
+24
-19
drivers/mtd/nand/raw/fsl_ifc_nand.c
+24
-19
drivers/mtd/nand/raw/fsl_ifc_nand.c
···
707
707
{
708
708
struct mtd_info *mtd = nand_to_mtd(chip);
709
709
struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
710
+
struct fsl_ifc_ctrl *ctrl = priv->ctrl;
711
+
struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
712
+
u32 csor;
713
+
714
+
csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor);
715
+
716
+
/* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
717
+
if (csor & CSOR_NAND_ECC_DEC_EN) {
718
+
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
719
+
mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops);
720
+
721
+
/* Hardware generates ECC per 512 Bytes */
722
+
chip->ecc.size = 512;
723
+
if ((csor & CSOR_NAND_ECC_MODE_MASK) == CSOR_NAND_ECC_MODE_4) {
724
+
chip->ecc.bytes = 8;
725
+
chip->ecc.strength = 4;
726
+
} else {
727
+
chip->ecc.bytes = 16;
728
+
chip->ecc.strength = 8;
729
+
}
730
+
} else {
731
+
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
732
+
chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
733
+
}
710
734
711
735
dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
712
736
nanddev_ntargets(&chip->base));
···
932
908
default:
933
909
dev_err(priv->dev, "bad csor %#x: bad page size\n", csor);
934
910
return -ENODEV;
935
-
}
936
-
937
-
/* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
938
-
if (csor & CSOR_NAND_ECC_DEC_EN) {
939
-
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
940
-
mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops);
941
-
942
-
/* Hardware generates ECC per 512 Bytes */
943
-
chip->ecc.size = 512;
944
-
if ((csor & CSOR_NAND_ECC_MODE_MASK) == CSOR_NAND_ECC_MODE_4) {
945
-
chip->ecc.bytes = 8;
946
-
chip->ecc.strength = 4;
947
-
} else {
948
-
chip->ecc.bytes = 16;
949
-
chip->ecc.strength = 8;
950
-
}
951
-
} else {
952
-
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
953
-
chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
954
911
}
955
912
956
913
ret = fsl_ifc_sram_init(priv);
+5
-12
drivers/mtd/nand/raw/mxc_nand.c
+5
-12
drivers/mtd/nand/raw/mxc_nand.c
···
1681
1681
struct mxc_nand_host *host = nand_get_controller_data(chip);
1682
1682
struct device *dev = mtd->dev.parent;
1683
1683
1684
+
chip->ecc.bytes = host->devtype_data->eccbytes;
1685
+
host->eccsize = host->devtype_data->eccsize;
1686
+
chip->ecc.size = 512;
1687
+
mtd_set_ooblayout(mtd, host->devtype_data->ooblayout);
1688
+
1684
1689
switch (chip->ecc.engine_type) {
1685
1690
case NAND_ECC_ENGINE_TYPE_ON_HOST:
1686
1691
chip->ecc.read_page = mxc_nand_read_page;
···
1841
1836
if (host->devtype_data->axi_offset)
1842
1837
host->regs_axi = host->base + host->devtype_data->axi_offset;
1843
1838
1844
-
this->ecc.bytes = host->devtype_data->eccbytes;
1845
-
host->eccsize = host->devtype_data->eccsize;
1846
-
1847
1839
this->legacy.select_chip = host->devtype_data->select_chip;
1848
-
this->ecc.size = 512;
1849
-
mtd_set_ooblayout(mtd, host->devtype_data->ooblayout);
1850
-
1851
-
if (host->pdata.hw_ecc) {
1852
-
this->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
1853
-
} else {
1854
-
this->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
1855
-
this->ecc.algo = NAND_ECC_ALGO_HAMMING;
1856
-
}
1857
1840
1858
1841
/* NAND bus width determines access functions used by upper layer */
1859
1842
if (host->pdata.width == 2)
+8
-7
drivers/mtd/nand/raw/stm32_fmc2_nand.c
+8
-7
drivers/mtd/nand/raw/stm32_fmc2_nand.c
···
1708
1708
return -EINVAL;
1709
1709
}
1710
1710
1711
+
/* Default ECC settings in case they are not set in the device tree */
1712
+
if (!chip->ecc.size)
1713
+
chip->ecc.size = FMC2_ECC_STEP_SIZE;
1714
+
1715
+
if (!chip->ecc.strength)
1716
+
chip->ecc.strength = FMC2_ECC_BCH8;
1717
+
1711
1718
ret = nand_ecc_choose_conf(chip, &stm32_fmc2_nfc_ecc_caps,
1712
1719
mtd->oobsize - FMC2_BBM_LEN);
1713
1720
if (ret) {
···
1734
1727
1735
1728
mtd_set_ooblayout(mtd, &stm32_fmc2_nfc_ooblayout_ops);
1736
1729
1737
-
if (chip->options & NAND_BUSWIDTH_16)
1738
-
stm32_fmc2_nfc_set_buswidth_16(nfc, true);
1730
+
stm32_fmc2_nfc_setup(chip);
1739
1731
1740
1732
return 0;
1741
1733
}
···
1957
1951
chip->controller = &nfc->base;
1958
1952
chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |
1959
1953
NAND_USES_DMA;
1960
-
1961
-
/* Default ECC settings */
1962
-
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
1963
-
chip->ecc.size = FMC2_ECC_STEP_SIZE;
1964
-
chip->ecc.strength = FMC2_ECC_BCH8;
1965
1954
1966
1955
/* Scan to find existence of the device */
1967
1956
ret = nand_scan(chip, nand->ncs);
+7
-6
drivers/mtd/spi-nor/core.c
+7
-6
drivers/mtd/spi-nor/core.c
···
2701
2701
2702
2702
memcpy(&sfdp_params, nor->params, sizeof(sfdp_params));
2703
2703
2704
-
if (spi_nor_parse_sfdp(nor, &sfdp_params)) {
2704
+
if (spi_nor_parse_sfdp(nor, nor->params)) {
2705
+
memcpy(nor->params, &sfdp_params, sizeof(*nor->params));
2705
2706
nor->addr_width = 0;
2706
2707
nor->flags &= ~SNOR_F_4B_OPCODES;
2707
-
} else {
2708
-
memcpy(nor->params, &sfdp_params, sizeof(*nor->params));
2709
2708
}
2710
2709
}
2711
2710
···
3008
3009
/* already configured from SFDP */
3009
3010
} else if (nor->info->addr_width) {
3010
3011
nor->addr_width = nor->info->addr_width;
3011
-
} else if (nor->mtd.size > 0x1000000) {
3012
-
/* enable 4-byte addressing if the device exceeds 16MiB */
3013
-
nor->addr_width = 4;
3014
3012
} else {
3015
3013
nor->addr_width = 3;
3014
+
}
3015
+
3016
+
if (nor->addr_width == 3 && nor->mtd.size > 0x1000000) {
3017
+
/* enable 4-byte addressing if the device exceeds 16MiB */
3018
+
nor->addr_width = 4;
3016
3019
}
3017
3020
3018
3021
if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {