Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-intel-next-2024-11-04' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next
drm/i915 feature pull #2 for v6.13:
Features and functionality:
- Pantherlake (PTL) Xe3 LPD display enabling for xe driver (Clint, Suraj,
Dnyaneshwar, Matt, Gustavo, Radhakrishna, Chaitanya, Haridhar, Juha-Pekka, Ravi)
- Enable dbuf overlap detection on Lunarlake and later (Stanislav, Vinod)
- Allow fastset for HDR infoframe changes (Chaitanya)
- Write DP source OUI also for non-eDP sinks (Imre)
Refactoring and cleanups:
- Independent platform identification for display (Jani)
- Display tracepoint fixes and cleanups (Gustavo)
- Share PCI ID headers between i915 and xe drivers (Jani)
- Use x100 version for full version and release checks (Jani)
- Conversions to struct intel_display (Jani, Ville)
- Reuse DP DPCD and AUX macros in gvt instead of duplication (Jani)
- Use string choice helpers (R Sundar, Sai Teja)
- Remove unused underrun detection irq code (Sai Teja)
- Color management debug improvements and other cleanups (Ville)
- Refactor panel fitter code to a separate file (Ville)
- Use try_cmpxchg() instead of open-coding (Uros Bizjak)
Fixes:
- PSR and Panel Replay fixes and workarounds (Jouni)
- Fix panel power during connector detection (Imre)
- Fix connector detection and modeset races (Imre)
- Fix C20 PHY TX MISC configuration (Gustavo)
- Improve panel fitter validity checks (Ville)
- Fix eDP short HPD interrupt handling while runtime suspended (Imre)
- Propagate DP MST DSC BW overhead/slice calculation errors (Imre)
- Stop hotplug polling for eDP connectors (Imre)
- Workaround panels reporting bad link status after PSR enable (Jouni)
- Panel Replay VRR VSC SDP related workaround and refactor (Animesh, Mitul)
- Fix memory leak on eDP init error path (Shuicheng)
- Fix GVT KVMGT Kconfig dependencies (Arnd Bergmann)
- Fix irq function documentation build warning (Rodrigo)
- Add platform check to power management fuse bit read (Clint)
- Revert kstrdup_const() and kfree_const() usage for clarity (Christophe JAILLET)
- Workaround horizontal odd panning issues in display versions 20 and 30 (Nemesa)
- Fix xe drive HDCP GSC firmware check (Suraj)
Merges:
- Backmerge drm-next to get some KVM changes (Rodrigo)
- Fix a build failure originating from previous backmerge (Jani)
Signed-off-by: Dave Airlie <airlied@redhat.com>
# Conflicts:
# drivers/gpu/drm/i915/display/intel_dp_mst.c
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87h68ni0wd.fsf@intel.com
+3690
-2975
+2
-2
Documentation/gpu/i915.rst
+2
-2
Documentation/gpu/i915.rst
···
35
35
:functions: intel_irq_init intel_irq_init_hw intel_hpd_init
36
36
37
37
.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
38
-
:functions: intel_runtime_pm_disable_interrupts
38
+
:functions: intel_irq_suspend
39
39
40
40
.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
41
-
:functions: intel_runtime_pm_enable_interrupts
41
+
:functions: intel_irq_resume
42
42
43
43
Intel GVT-g Guest Support(vGPU)
44
44
-------------------------------
+1
-1
arch/x86/kernel/early-quirks.c
+1
-1
arch/x86/kernel/early-quirks.c
+1
drivers/gpu/drm/i915/Makefile
+1
drivers/gpu/drm/i915/Makefile
+9
-10
drivers/gpu/drm/i915/display/g4x_dp.c
+9
-10
drivers/gpu/drm/i915/display/g4x_dp.c
···
170
170
{
171
171
struct intel_display *display = to_intel_display(intel_dp);
172
172
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
173
-
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
174
173
bool cur_state = intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN;
175
174
176
-
I915_STATE_WARN(dev_priv, cur_state != state,
177
-
"[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
178
-
dig_port->base.base.base.id, dig_port->base.base.name,
179
-
str_on_off(state), str_on_off(cur_state));
175
+
INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
176
+
"[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
177
+
dig_port->base.base.base.id, dig_port->base.base.name,
178
+
str_on_off(state), str_on_off(cur_state));
180
179
}
181
180
#define assert_dp_port_disabled(d) assert_dp_port((d), false)
182
181
···
184
185
struct intel_display *display = &dev_priv->display;
185
186
bool cur_state = intel_de_read(display, DP_A) & DP_PLL_ENABLE;
186
187
187
-
I915_STATE_WARN(dev_priv, cur_state != state,
188
-
"eDP PLL state assertion failure (expected %s, current %s)\n",
189
-
str_on_off(state), str_on_off(cur_state));
188
+
INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
189
+
"eDP PLL state assertion failure (expected %s, current %s)\n",
190
+
str_on_off(state), str_on_off(cur_state));
190
191
}
191
192
#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
192
193
#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
···
705
706
if (IS_CHERRYVIEW(dev_priv))
706
707
lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
707
708
708
-
vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
709
-
lane_mask);
709
+
vlv_wait_port_ready(display, dp_to_dig_port(intel_dp), lane_mask);
710
710
}
711
711
712
712
intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
···
1249
1251
intel_dp->DP = intel_de_read(display, intel_dp->output_reg);
1250
1252
1251
1253
intel_dp->reset_link_params = true;
1254
+
intel_dp_invalidate_source_oui(intel_dp);
1252
1255
1253
1256
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1254
1257
vlv_pps_pipe_reset(intel_dp);
+4
-5
drivers/gpu/drm/i915/display/g4x_hdmi.c
+4
-5
drivers/gpu/drm/i915/display/g4x_hdmi.c
···
480
480
const struct intel_crtc_state *pipe_config,
481
481
const struct drm_connector_state *conn_state)
482
482
{
483
+
struct intel_display *display = to_intel_display(encoder);
483
484
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
484
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
485
485
486
486
vlv_phy_pre_encoder_enable(encoder, pipe_config);
487
487
···
496
496
497
497
g4x_hdmi_enable_port(encoder, pipe_config);
498
498
499
-
vlv_wait_port_ready(dev_priv, dig_port, 0x0);
499
+
vlv_wait_port_ready(display, dig_port, 0x0);
500
500
}
501
501
502
502
static void vlv_hdmi_pre_pll_enable(struct intel_atomic_state *state,
···
557
557
const struct intel_crtc_state *pipe_config,
558
558
const struct drm_connector_state *conn_state)
559
559
{
560
+
struct intel_display *display = to_intel_display(encoder);
560
561
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
561
-
struct drm_device *dev = encoder->base.dev;
562
-
struct drm_i915_private *dev_priv = to_i915(dev);
563
562
564
563
chv_phy_pre_encoder_enable(encoder, pipe_config);
565
564
···
572
573
573
574
g4x_hdmi_enable_port(encoder, pipe_config);
574
575
575
-
vlv_wait_port_ready(dev_priv, dig_port, 0x0);
576
+
vlv_wait_port_ready(display, dig_port, 0x0);
576
577
577
578
/* Second common lane will stay alive on its own now */
578
579
chv_phy_release_cl2_override(encoder);
+26
-21
drivers/gpu/drm/i915/display/hsw_ips.c
+26
-21
drivers/gpu/drm/i915/display/hsw_ips.c
···
15
15
16
16
static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
17
17
{
18
+
struct intel_display *display = to_intel_display(crtc_state);
18
19
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
19
20
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
20
21
u32 val;
···
28
27
* This function is called from post_plane_update, which is run after
29
28
* a vblank wait.
30
29
*/
31
-
drm_WARN_ON(&i915->drm,
30
+
drm_WARN_ON(display->drm,
32
31
!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
33
32
34
33
val = IPS_ENABLE;
35
34
36
-
if (i915->display.ips.false_color)
35
+
if (display->ips.false_color)
37
36
val |= IPS_FALSE_COLOR;
38
37
39
38
if (IS_BROADWELL(i915)) {
40
-
drm_WARN_ON(&i915->drm,
39
+
drm_WARN_ON(display->drm,
41
40
snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL,
42
41
val | IPS_PCODE_CONTROL));
43
42
/*
···
47
46
* so we need to just enable it and continue on.
48
47
*/
49
48
} else {
50
-
intel_de_write(i915, IPS_CTL, val);
49
+
intel_de_write(display, IPS_CTL, val);
51
50
/*
52
51
* The bit only becomes 1 in the next vblank, so this wait here
53
52
* is essentially intel_wait_for_vblank. If we don't have this
···
55
54
* the HW state readout code will complain that the expected
56
55
* IPS_CTL value is not the one we read.
57
56
*/
58
-
if (intel_de_wait_for_set(i915, IPS_CTL, IPS_ENABLE, 50))
59
-
drm_err(&i915->drm,
57
+
if (intel_de_wait_for_set(display, IPS_CTL, IPS_ENABLE, 50))
58
+
drm_err(display->drm,
60
59
"Timed out waiting for IPS enable\n");
61
60
}
62
61
}
63
62
64
63
bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)
65
64
{
65
+
struct intel_display *display = to_intel_display(crtc_state);
66
66
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
67
67
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
68
68
bool need_vblank_wait = false;
···
72
70
return need_vblank_wait;
73
71
74
72
if (IS_BROADWELL(i915)) {
75
-
drm_WARN_ON(&i915->drm,
73
+
drm_WARN_ON(display->drm,
76
74
snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL, 0));
77
75
/*
78
76
* Wait for PCODE to finish disabling IPS. The BSpec specified
79
77
* 42ms timeout value leads to occasional timeouts so use 100ms
80
78
* instead.
81
79
*/
82
-
if (intel_de_wait_for_clear(i915, IPS_CTL, IPS_ENABLE, 100))
83
-
drm_err(&i915->drm,
80
+
if (intel_de_wait_for_clear(display, IPS_CTL, IPS_ENABLE, 100))
81
+
drm_err(display->drm,
84
82
"Timed out waiting for IPS disable\n");
85
83
} else {
86
-
intel_de_write(i915, IPS_CTL, 0);
87
-
intel_de_posting_read(i915, IPS_CTL);
84
+
intel_de_write(display, IPS_CTL, 0);
85
+
intel_de_posting_read(display, IPS_CTL);
88
86
}
89
87
90
88
/* We need to wait for a vblank before we can disable the plane. */
···
190
188
191
189
bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
192
190
{
191
+
struct intel_display *display = to_intel_display(crtc_state);
193
192
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
194
193
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
195
194
···
198
195
if (!hsw_crtc_supports_ips(crtc))
199
196
return false;
200
197
201
-
if (!i915->display.params.enable_ips)
198
+
if (!display->params.enable_ips)
202
199
return false;
203
200
204
201
if (crtc_state->pipe_bpp > 24)
···
212
209
* Should measure whether using a lower cdclk w/o IPS
213
210
*/
214
211
if (IS_BROADWELL(i915) &&
215
-
crtc_state->pixel_rate > i915->display.cdclk.max_cdclk_freq * 95 / 100)
212
+
crtc_state->pixel_rate > display->cdclk.max_cdclk_freq * 95 / 100)
216
213
return false;
217
214
218
215
return true;
···
262
259
263
260
void hsw_ips_get_config(struct intel_crtc_state *crtc_state)
264
261
{
262
+
struct intel_display *display = to_intel_display(crtc_state);
265
263
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
266
264
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
267
265
···
270
266
return;
271
267
272
268
if (IS_HASWELL(i915)) {
273
-
crtc_state->ips_enabled = intel_de_read(i915, IPS_CTL) & IPS_ENABLE;
269
+
crtc_state->ips_enabled = intel_de_read(display, IPS_CTL) & IPS_ENABLE;
274
270
} else {
275
271
/*
276
272
* We cannot readout IPS state on broadwell, set to
···
284
280
static int hsw_ips_debugfs_false_color_get(void *data, u64 *val)
285
281
{
286
282
struct intel_crtc *crtc = data;
287
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
283
+
struct intel_display *display = to_intel_display(crtc);
288
284
289
-
*val = i915->display.ips.false_color;
285
+
*val = display->ips.false_color;
290
286
291
287
return 0;
292
288
}
···
294
290
static int hsw_ips_debugfs_false_color_set(void *data, u64 val)
295
291
{
296
292
struct intel_crtc *crtc = data;
297
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
293
+
struct intel_display *display = to_intel_display(crtc);
298
294
struct intel_crtc_state *crtc_state;
299
295
int ret;
300
296
···
302
298
if (ret)
303
299
return ret;
304
300
305
-
i915->display.ips.false_color = val;
301
+
display->ips.false_color = val;
306
302
307
303
crtc_state = to_intel_crtc_state(crtc->base.state);
308
304
···
329
325
static int hsw_ips_debugfs_status_show(struct seq_file *m, void *unused)
330
326
{
331
327
struct intel_crtc *crtc = m->private;
328
+
struct intel_display *display = to_intel_display(crtc);
332
329
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
333
330
intel_wakeref_t wakeref;
334
331
335
332
wakeref = intel_runtime_pm_get(&i915->runtime_pm);
336
333
337
334
seq_printf(m, "Enabled by kernel parameter: %s\n",
338
-
str_yes_no(i915->display.params.enable_ips));
335
+
str_yes_no(display->params.enable_ips));
339
336
340
-
if (DISPLAY_VER(i915) >= 8) {
337
+
if (DISPLAY_VER(display) >= 8) {
341
338
seq_puts(m, "Currently: unknown\n");
342
339
} else {
343
-
if (intel_de_read(i915, IPS_CTL) & IPS_ENABLE)
340
+
if (intel_de_read(display, IPS_CTL) & IPS_ENABLE)
344
341
seq_puts(m, "Currently: enabled\n");
345
342
else
346
343
seq_puts(m, "Currently: disabled\n");
+225
-220
drivers/gpu/drm/i915/display/icl_dsi.c
+225
-220
drivers/gpu/drm/i915/display/icl_dsi.c
···
46
46
#include "intel_dsi.h"
47
47
#include "intel_dsi_vbt.h"
48
48
#include "intel_panel.h"
49
+
#include "intel_pfit.h"
49
50
#include "intel_vdsc.h"
50
51
#include "intel_vdsc_regs.h"
51
52
#include "skl_scaler.h"
52
53
#include "skl_universal_plane.h"
53
54
54
-
static int header_credits_available(struct drm_i915_private *dev_priv,
55
+
static int header_credits_available(struct intel_display *display,
55
56
enum transcoder dsi_trans)
56
57
{
57
-
return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
58
+
return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
58
59
>> FREE_HEADER_CREDIT_SHIFT;
59
60
}
60
61
61
-
static int payload_credits_available(struct drm_i915_private *dev_priv,
62
+
static int payload_credits_available(struct intel_display *display,
62
63
enum transcoder dsi_trans)
63
64
{
64
-
return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
65
+
return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
65
66
>> FREE_PLOAD_CREDIT_SHIFT;
66
67
}
67
68
68
-
static bool wait_for_header_credits(struct drm_i915_private *dev_priv,
69
+
static bool wait_for_header_credits(struct intel_display *display,
69
70
enum transcoder dsi_trans, int hdr_credit)
70
71
{
71
-
if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >=
72
+
if (wait_for_us(header_credits_available(display, dsi_trans) >=
72
73
hdr_credit, 100)) {
73
-
drm_err(&dev_priv->drm, "DSI header credits not released\n");
74
+
drm_err(display->drm, "DSI header credits not released\n");
74
75
return false;
75
76
}
76
77
77
78
return true;
78
79
}
79
80
80
-
static bool wait_for_payload_credits(struct drm_i915_private *dev_priv,
81
+
static bool wait_for_payload_credits(struct intel_display *display,
81
82
enum transcoder dsi_trans, int payld_credit)
82
83
{
83
-
if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >=
84
+
if (wait_for_us(payload_credits_available(display, dsi_trans) >=
84
85
payld_credit, 100)) {
85
-
drm_err(&dev_priv->drm, "DSI payload credits not released\n");
86
+
drm_err(display->drm, "DSI payload credits not released\n");
86
87
return false;
87
88
}
88
89
···
100
99
101
100
static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
102
101
{
103
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
102
+
struct intel_display *display = to_intel_display(encoder);
104
103
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
105
104
struct mipi_dsi_device *dsi;
106
105
enum port port;
···
110
109
/* wait for header/payload credits to be released */
111
110
for_each_dsi_port(port, intel_dsi->ports) {
112
111
dsi_trans = dsi_port_to_transcoder(port);
113
-
wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT);
114
-
wait_for_payload_credits(dev_priv, dsi_trans, MAX_PLOAD_CREDIT);
112
+
wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT);
113
+
wait_for_payload_credits(display, dsi_trans, MAX_PLOAD_CREDIT);
115
114
}
116
115
117
116
/* send nop DCS command */
···
121
120
dsi->channel = 0;
122
121
ret = mipi_dsi_dcs_nop(dsi);
123
122
if (ret < 0)
124
-
drm_err(&dev_priv->drm,
123
+
drm_err(display->drm,
125
124
"error sending DCS NOP command\n");
126
125
}
127
126
128
127
/* wait for header credits to be released */
129
128
for_each_dsi_port(port, intel_dsi->ports) {
130
129
dsi_trans = dsi_port_to_transcoder(port);
131
-
wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT);
130
+
wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT);
132
131
}
133
132
134
133
/* wait for LP TX in progress bit to be cleared */
135
134
for_each_dsi_port(port, intel_dsi->ports) {
136
135
dsi_trans = dsi_port_to_transcoder(port);
137
-
if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) &
136
+
if (wait_for_us(!(intel_de_read(display, DSI_LP_MSG(dsi_trans)) &
138
137
LPTX_IN_PROGRESS), 20))
139
-
drm_err(&dev_priv->drm, "LPTX bit not cleared\n");
138
+
drm_err(display->drm, "LPTX bit not cleared\n");
140
139
}
141
140
}
142
141
···
144
143
const struct mipi_dsi_packet *packet)
145
144
{
146
145
struct intel_dsi *intel_dsi = host->intel_dsi;
147
-
struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
146
+
struct intel_display *display = to_intel_display(&intel_dsi->base);
148
147
enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
149
148
const u8 *data = packet->payload;
150
149
u32 len = packet->payload_length;
···
152
151
153
152
/* payload queue can accept *256 bytes*, check limit */
154
153
if (len > MAX_PLOAD_CREDIT * 4) {
155
-
drm_err(&i915->drm, "payload size exceeds max queue limit\n");
154
+
drm_err(display->drm, "payload size exceeds max queue limit\n");
156
155
return -EINVAL;
157
156
}
158
157
159
158
for (i = 0; i < len; i += 4) {
160
159
u32 tmp = 0;
161
160
162
-
if (!wait_for_payload_credits(i915, dsi_trans, 1))
161
+
if (!wait_for_payload_credits(display, dsi_trans, 1))
163
162
return -EBUSY;
164
163
165
164
for (j = 0; j < min_t(u32, len - i, 4); j++)
166
165
tmp |= *data++ << 8 * j;
167
166
168
-
intel_de_write(i915, DSI_CMD_TXPYLD(dsi_trans), tmp);
167
+
intel_de_write(display, DSI_CMD_TXPYLD(dsi_trans), tmp);
169
168
}
170
169
171
170
return 0;
···
176
175
bool enable_lpdt)
177
176
{
178
177
struct intel_dsi *intel_dsi = host->intel_dsi;
179
-
struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
178
+
struct intel_display *display = to_intel_display(&intel_dsi->base);
180
179
enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
181
180
u32 tmp;
182
181
183
-
if (!wait_for_header_credits(dev_priv, dsi_trans, 1))
182
+
if (!wait_for_header_credits(display, dsi_trans, 1))
184
183
return -EBUSY;
185
184
186
-
tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans));
185
+
tmp = intel_de_read(display, DSI_CMD_TXHDR(dsi_trans));
187
186
188
187
if (packet->payload)
189
188
tmp |= PAYLOAD_PRESENT;
···
202
201
tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT);
203
202
tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT);
204
203
tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT);
205
-
intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp);
204
+
intel_de_write(display, DSI_CMD_TXHDR(dsi_trans), tmp);
206
205
207
206
return 0;
208
207
}
209
208
210
209
void icl_dsi_frame_update(struct intel_crtc_state *crtc_state)
211
210
{
212
-
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
213
-
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
211
+
struct intel_display *display = to_intel_display(crtc_state);
214
212
u32 mode_flags;
215
213
enum port port;
216
214
···
227
227
else
228
228
return;
229
229
230
-
intel_de_rmw(dev_priv, DSI_CMD_FRMCTL(port), 0, DSI_FRAME_UPDATE_REQUEST);
230
+
intel_de_rmw(display, DSI_CMD_FRMCTL(port), 0,
231
+
DSI_FRAME_UPDATE_REQUEST);
231
232
}
232
233
233
234
static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
234
235
{
235
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
236
+
struct intel_display *display = to_intel_display(encoder);
236
237
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
237
238
enum phy phy;
238
239
u32 tmp, mask, val;
···
247
246
mask = SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK;
248
247
val = SCALING_MODE_SEL(0x2) | TAP2_DISABLE | TAP3_DISABLE |
249
248
RTERM_SELECT(0x6);
250
-
tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
249
+
tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
251
250
tmp &= ~mask;
252
251
tmp |= val;
253
-
intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
254
-
intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), mask, val);
252
+
intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);
253
+
intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), mask, val);
255
254
256
255
mask = SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
257
256
RCOMP_SCALAR_MASK;
258
257
val = SWING_SEL_UPPER(0x2) | SWING_SEL_LOWER(0x2) |
259
258
RCOMP_SCALAR(0x98);
260
-
tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
259
+
tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));
261
260
tmp &= ~mask;
262
261
tmp |= val;
263
-
intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
264
-
intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_AUX(phy), mask, val);
262
+
intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp);
263
+
intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy), mask, val);
265
264
266
265
mask = POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
267
266
CURSOR_COEFF_MASK;
268
267
val = POST_CURSOR_1(0x0) | POST_CURSOR_2(0x0) |
269
268
CURSOR_COEFF(0x3f);
270
-
intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_AUX(phy), mask, val);
269
+
intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy), mask, val);
271
270
272
271
/* Bspec: must not use GRP register for write */
273
272
for (lane = 0; lane <= 3; lane++)
274
-
intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(lane, phy),
273
+
intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy),
275
274
mask, val);
276
275
}
277
276
}
···
279
278
static void configure_dual_link_mode(struct intel_encoder *encoder,
280
279
const struct intel_crtc_state *pipe_config)
281
280
{
282
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
281
+
struct intel_display *display = to_intel_display(encoder);
283
282
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
284
283
i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
285
284
u32 dss_ctl1;
286
285
287
286
/* FIXME: Move all DSS handling to intel_vdsc.c */
288
-
if (DISPLAY_VER(dev_priv) >= 12) {
287
+
if (DISPLAY_VER(display) >= 12) {
289
288
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
290
289
291
290
dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe);
···
295
294
dss_ctl2_reg = DSS_CTL2;
296
295
}
297
296
298
-
dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg);
297
+
dss_ctl1 = intel_de_read(display, dss_ctl1_reg);
299
298
dss_ctl1 |= SPLITTER_ENABLE;
300
299
dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
301
300
dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
···
310
309
dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap;
311
310
312
311
if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
313
-
drm_err(&dev_priv->drm,
312
+
drm_err(display->drm,
314
313
"DL buffer depth exceed max value\n");
315
314
316
315
dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
317
316
dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
318
-
intel_de_rmw(dev_priv, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK,
317
+
intel_de_rmw(display, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK,
319
318
RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth));
320
319
} else {
321
320
/* Interleave */
322
321
dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
323
322
}
324
323
325
-
intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1);
324
+
intel_de_write(display, dss_ctl1_reg, dss_ctl1);
326
325
}
327
326
328
327
/* aka DSI 8X clock */
···
343
342
static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
344
343
const struct intel_crtc_state *crtc_state)
345
344
{
345
+
struct intel_display *display = to_intel_display(encoder);
346
346
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
347
347
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
348
348
enum port port;
···
363
361
}
364
362
365
363
for_each_dsi_port(port, intel_dsi->ports) {
366
-
intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port),
364
+
intel_de_write(display, ICL_DSI_ESC_CLK_DIV(port),
367
365
esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
368
-
intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port));
366
+
intel_de_posting_read(display, ICL_DSI_ESC_CLK_DIV(port));
369
367
}
370
368
371
369
for_each_dsi_port(port, intel_dsi->ports) {
372
-
intel_de_write(dev_priv, ICL_DPHY_ESC_CLK_DIV(port),
370
+
intel_de_write(display, ICL_DPHY_ESC_CLK_DIV(port),
373
371
esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
374
-
intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port));
372
+
intel_de_posting_read(display, ICL_DPHY_ESC_CLK_DIV(port));
375
373
}
376
374
377
375
if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) {
378
376
for_each_dsi_port(port, intel_dsi->ports) {
379
-
intel_de_write(dev_priv, ADL_MIPIO_DW(port, 8),
377
+
intel_de_write(display, ADL_MIPIO_DW(port, 8),
380
378
esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY);
381
-
intel_de_posting_read(dev_priv, ADL_MIPIO_DW(port, 8));
379
+
intel_de_posting_read(display, ADL_MIPIO_DW(port, 8));
382
380
}
383
381
}
384
382
}
385
383
386
-
static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv,
387
-
struct intel_dsi *intel_dsi)
384
+
static void get_dsi_io_power_domains(struct intel_dsi *intel_dsi)
388
385
{
386
+
struct intel_display *display = to_intel_display(&intel_dsi->base);
387
+
struct drm_i915_private *dev_priv = to_i915(display->drm);
389
388
enum port port;
390
389
391
390
for_each_dsi_port(port, intel_dsi->ports) {
392
-
drm_WARN_ON(&dev_priv->drm, intel_dsi->io_wakeref[port]);
391
+
drm_WARN_ON(display->drm, intel_dsi->io_wakeref[port]);
393
392
intel_dsi->io_wakeref[port] =
394
393
intel_display_power_get(dev_priv,
395
394
port == PORT_A ?
···
401
398
402
399
static void gen11_dsi_enable_io_power(struct intel_encoder *encoder)
403
400
{
404
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
401
+
struct intel_display *display = to_intel_display(encoder);
405
402
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
406
403
enum port port;
407
404
408
405
for_each_dsi_port(port, intel_dsi->ports)
409
-
intel_de_rmw(dev_priv, ICL_DSI_IO_MODECTL(port),
406
+
intel_de_rmw(display, ICL_DSI_IO_MODECTL(port),
410
407
0, COMBO_PHY_MODE_DSI);
411
408
412
-
get_dsi_io_power_domains(dev_priv, intel_dsi);
409
+
get_dsi_io_power_domains(intel_dsi);
413
410
}
414
411
415
412
static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
···
425
422
426
423
static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
427
424
{
425
+
struct intel_display *display = to_intel_display(encoder);
428
426
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
429
427
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
430
428
enum phy phy;
···
434
430
435
431
/* Step 4b(i) set loadgen select for transmit and aux lanes */
436
432
for_each_dsi_phy(phy, intel_dsi->phys) {
437
-
intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_AUX(phy), LOADGEN_SELECT, 0);
433
+
intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy),
434
+
LOADGEN_SELECT, 0);
438
435
for (lane = 0; lane <= 3; lane++)
439
-
intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(lane, phy),
436
+
intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy),
440
437
LOADGEN_SELECT, lane != 2 ? LOADGEN_SELECT : 0);
441
438
}
442
439
443
440
/* Step 4b(ii) set latency optimization for transmit and aux lanes */
444
441
for_each_dsi_phy(phy, intel_dsi->phys) {
445
-
intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_AUX(phy),
442
+
intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy),
446
443
FRC_LATENCY_OPTIM_MASK, FRC_LATENCY_OPTIM_VAL(0x5));
447
-
tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
444
+
tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));
448
445
tmp &= ~FRC_LATENCY_OPTIM_MASK;
449
446
tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
450
-
intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
447
+
intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp);
451
448
452
449
/* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
453
450
if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv) ||
454
-
(DISPLAY_VER(dev_priv) >= 12)) {
455
-
intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy),
451
+
(DISPLAY_VER(display) >= 12)) {
452
+
intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy),
456
453
LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0));
457
454
458
-
tmp = intel_de_read(dev_priv,
455
+
tmp = intel_de_read(display,
459
456
ICL_PORT_PCS_DW1_LN(0, phy));
460
457
tmp &= ~LATENCY_OPTIM_MASK;
461
458
tmp |= LATENCY_OPTIM_VAL(0x1);
462
-
intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy),
459
+
intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy),
463
460
tmp);
464
461
}
465
462
}
···
469
464
470
465
static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
471
466
{
472
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
467
+
struct intel_display *display = to_intel_display(encoder);
473
468
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
474
469
u32 tmp;
475
470
enum phy phy;
476
471
477
472
/* clear common keeper enable bit */
478
473
for_each_dsi_phy(phy, intel_dsi->phys) {
479
-
tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
474
+
tmp = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));
480
475
tmp &= ~COMMON_KEEPER_EN;
481
-
intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp);
482
-
intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), COMMON_KEEPER_EN, 0);
476
+
intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), tmp);
477
+
intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy), COMMON_KEEPER_EN, 0);
483
478
}
484
479
485
480
/*
···
488
483
* as part of lane phy sequence configuration
489
484
*/
490
485
for_each_dsi_phy(phy, intel_dsi->phys)
491
-
intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 0, SUS_CLOCK_CONFIG);
486
+
intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 0,
487
+
SUS_CLOCK_CONFIG);
492
488
493
489
/* Clear training enable to change swing values */
494
490
for_each_dsi_phy(phy, intel_dsi->phys) {
495
-
tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
491
+
tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
496
492
tmp &= ~TX_TRAINING_EN;
497
-
intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
498
-
intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), TX_TRAINING_EN, 0);
493
+
intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);
494
+
intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), TX_TRAINING_EN, 0);
499
495
}
500
496
501
497
/* Program swing and de-emphasis */
···
504
498
505
499
/* Set training enable to trigger update */
506
500
for_each_dsi_phy(phy, intel_dsi->phys) {
507
-
tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
501
+
tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
508
502
tmp |= TX_TRAINING_EN;
509
-
intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
510
-
intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), 0, TX_TRAINING_EN);
503
+
intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);
504
+
intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), 0, TX_TRAINING_EN);
511
505
}
512
506
}
513
507
514
508
static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
515
509
{
516
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
510
+
struct intel_display *display = to_intel_display(encoder);
517
511
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
518
512
enum port port;
519
513
520
514
for_each_dsi_port(port, intel_dsi->ports) {
521
-
intel_de_rmw(dev_priv, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE);
515
+
intel_de_rmw(display, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE);
522
516
523
-
if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
517
+
if (wait_for_us(!(intel_de_read(display, DDI_BUF_CTL(port)) &
524
518
DDI_BUF_IS_IDLE),
525
519
500))
526
-
drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n",
520
+
drm_err(display->drm, "DDI port:%c buffer idle\n",
527
521
port_name(port));
528
522
}
529
523
}
···
532
526
gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
533
527
const struct intel_crtc_state *crtc_state)
534
528
{
529
+
struct intel_display *display = to_intel_display(encoder);
535
530
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
536
531
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
537
532
enum port port;
···
540
533
541
534
/* Program DPHY clock lanes timings */
542
535
for_each_dsi_port(port, intel_dsi->ports)
543
-
intel_de_write(dev_priv, DPHY_CLK_TIMING_PARAM(port),
536
+
intel_de_write(display, DPHY_CLK_TIMING_PARAM(port),
544
537
intel_dsi->dphy_reg);
545
538
546
539
/* Program DPHY data lanes timings */
547
540
for_each_dsi_port(port, intel_dsi->ports)
548
-
intel_de_write(dev_priv, DPHY_DATA_TIMING_PARAM(port),
541
+
intel_de_write(display, DPHY_DATA_TIMING_PARAM(port),
549
542
intel_dsi->dphy_data_lane_reg);
550
543
551
544
/*
···
554
547
* a value '0' inside TA_PARAM_REGISTERS otherwise
555
548
* leave all fields at HW default values.
556
549
*/
557
-
if (DISPLAY_VER(dev_priv) == 11) {
550
+
if (DISPLAY_VER(display) == 11) {
558
551
if (afe_clk(encoder, crtc_state) <= 800000) {
559
552
for_each_dsi_port(port, intel_dsi->ports)
560
-
intel_de_rmw(dev_priv, DPHY_TA_TIMING_PARAM(port),
553
+
intel_de_rmw(display, DPHY_TA_TIMING_PARAM(port),
561
554
TA_SURE_MASK,
562
555
TA_SURE_OVERRIDE | TA_SURE(0));
563
556
}
···
565
558
566
559
if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
567
560
for_each_dsi_phy(phy, intel_dsi->phys)
568
-
intel_de_rmw(dev_priv, ICL_DPHY_CHKN(phy),
561
+
intel_de_rmw(display, ICL_DPHY_CHKN(phy),
569
562
0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP);
570
563
}
571
564
}
···
574
567
gen11_dsi_setup_timings(struct intel_encoder *encoder,
575
568
const struct intel_crtc_state *crtc_state)
576
569
{
577
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
570
+
struct intel_display *display = to_intel_display(encoder);
578
571
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
579
572
enum port port;
580
573
581
574
/* Program T-INIT master registers */
582
575
for_each_dsi_port(port, intel_dsi->ports)
583
-
intel_de_rmw(dev_priv, ICL_DSI_T_INIT_MASTER(port),
576
+
intel_de_rmw(display, ICL_DSI_T_INIT_MASTER(port),
584
577
DSI_T_INIT_MASTER_MASK, intel_dsi->init_count);
585
578
586
579
/* shadow register inside display core */
587
580
for_each_dsi_port(port, intel_dsi->ports)
588
-
intel_de_write(dev_priv, DSI_CLK_TIMING_PARAM(port),
581
+
intel_de_write(display, DSI_CLK_TIMING_PARAM(port),
589
582
intel_dsi->dphy_reg);
590
583
591
584
/* shadow register inside display core */
592
585
for_each_dsi_port(port, intel_dsi->ports)
593
-
intel_de_write(dev_priv, DSI_DATA_TIMING_PARAM(port),
586
+
intel_de_write(display, DSI_DATA_TIMING_PARAM(port),
594
587
intel_dsi->dphy_data_lane_reg);
595
588
596
589
/* shadow register inside display core */
597
-
if (DISPLAY_VER(dev_priv) == 11) {
590
+
if (DISPLAY_VER(display) == 11) {
598
591
if (afe_clk(encoder, crtc_state) <= 800000) {
599
592
for_each_dsi_port(port, intel_dsi->ports) {
600
-
intel_de_rmw(dev_priv, DSI_TA_TIMING_PARAM(port),
593
+
intel_de_rmw(display, DSI_TA_TIMING_PARAM(port),
601
594
TA_SURE_MASK,
602
595
TA_SURE_OVERRIDE | TA_SURE(0));
603
596
}
···
607
600
608
601
static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
609
602
{
610
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
603
+
struct intel_display *display = to_intel_display(encoder);
611
604
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
612
605
u32 tmp;
613
606
enum phy phy;
614
607
615
-
mutex_lock(&dev_priv->display.dpll.lock);
616
-
tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
608
+
mutex_lock(&display->dpll.lock);
609
+
tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
617
610
for_each_dsi_phy(phy, intel_dsi->phys)
618
611
tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
619
612
620
-
intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
621
-
mutex_unlock(&dev_priv->display.dpll.lock);
613
+
intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp);
614
+
mutex_unlock(&display->dpll.lock);
622
615
}
623
616
624
617
static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
625
618
{
626
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
619
+
struct intel_display *display = to_intel_display(encoder);
627
620
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
628
621
u32 tmp;
629
622
enum phy phy;
630
623
631
-
mutex_lock(&dev_priv->display.dpll.lock);
632
-
tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
624
+
mutex_lock(&display->dpll.lock);
625
+
tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
633
626
for_each_dsi_phy(phy, intel_dsi->phys)
634
627
tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
635
628
636
-
intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
637
-
mutex_unlock(&dev_priv->display.dpll.lock);
629
+
intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp);
630
+
mutex_unlock(&display->dpll.lock);
638
631
}
639
632
640
633
static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder)
641
634
{
642
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
635
+
struct intel_display *display = to_intel_display(encoder);
643
636
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
644
637
bool clock_enabled = false;
645
638
enum phy phy;
646
639
u32 tmp;
647
640
648
-
tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
641
+
tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
649
642
650
643
for_each_dsi_phy(phy, intel_dsi->phys) {
651
644
if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)))
···
658
651
static void gen11_dsi_map_pll(struct intel_encoder *encoder,
659
652
const struct intel_crtc_state *crtc_state)
660
653
{
661
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
654
+
struct intel_display *display = to_intel_display(encoder);
662
655
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
663
656
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
664
657
enum phy phy;
665
658
u32 val;
666
659
667
-
mutex_lock(&dev_priv->display.dpll.lock);
660
+
mutex_lock(&display->dpll.lock);
668
661
669
-
val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
662
+
val = intel_de_read(display, ICL_DPCLKA_CFGCR0);
670
663
for_each_dsi_phy(phy, intel_dsi->phys) {
671
664
val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
672
665
val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
673
666
}
674
-
intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
667
+
intel_de_write(display, ICL_DPCLKA_CFGCR0, val);
675
668
676
669
for_each_dsi_phy(phy, intel_dsi->phys) {
677
670
val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
678
671
}
679
-
intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
672
+
intel_de_write(display, ICL_DPCLKA_CFGCR0, val);
680
673
681
-
intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
674
+
intel_de_posting_read(display, ICL_DPCLKA_CFGCR0);
682
675
683
-
mutex_unlock(&dev_priv->display.dpll.lock);
676
+
mutex_unlock(&display->dpll.lock);
684
677
}
685
678
686
679
static void
687
680
gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
688
681
const struct intel_crtc_state *pipe_config)
689
682
{
690
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
683
+
struct intel_display *display = to_intel_display(encoder);
691
684
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
692
685
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
693
686
enum pipe pipe = crtc->pipe;
···
697
690
698
691
for_each_dsi_port(port, intel_dsi->ports) {
699
692
dsi_trans = dsi_port_to_transcoder(port);
700
-
tmp = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans));
693
+
tmp = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));
701
694
702
695
if (intel_dsi->eotp_pkt)
703
696
tmp &= ~EOTP_DISABLED;
···
753
746
}
754
747
}
755
748
756
-
if (DISPLAY_VER(dev_priv) >= 12) {
749
+
if (DISPLAY_VER(display) >= 12) {
757
750
if (is_vid_mode(intel_dsi))
758
751
tmp |= BLANKING_PACKET_ENABLE;
759
752
}
···
786
779
tmp |= TE_SOURCE_GPIO;
787
780
}
788
781
789
-
intel_de_write(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
782
+
intel_de_write(display, DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
790
783
}
791
784
792
785
/* enable port sync mode if dual link */
793
786
if (intel_dsi->dual_link) {
794
787
for_each_dsi_port(port, intel_dsi->ports) {
795
788
dsi_trans = dsi_port_to_transcoder(port);
796
-
intel_de_rmw(dev_priv,
797
-
TRANS_DDI_FUNC_CTL2(dev_priv, dsi_trans),
789
+
intel_de_rmw(display,
790
+
TRANS_DDI_FUNC_CTL2(display, dsi_trans),
798
791
0, PORT_SYNC_MODE_ENABLE);
799
792
}
800
793
···
806
799
dsi_trans = dsi_port_to_transcoder(port);
807
800
808
801
/* select data lane width */
809
-
tmp = intel_de_read(dev_priv,
810
-
TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans));
802
+
tmp = intel_de_read(display,
803
+
TRANS_DDI_FUNC_CTL(display, dsi_trans));
811
804
tmp &= ~DDI_PORT_WIDTH_MASK;
812
805
tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
813
806
···
833
826
834
827
/* enable DDI buffer */
835
828
tmp |= TRANS_DDI_FUNC_ENABLE;
836
-
intel_de_write(dev_priv,
837
-
TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans), tmp);
829
+
intel_de_write(display,
830
+
TRANS_DDI_FUNC_CTL(display, dsi_trans), tmp);
838
831
}
839
832
840
833
/* wait for link ready */
841
834
for_each_dsi_port(port, intel_dsi->ports) {
842
835
dsi_trans = dsi_port_to_transcoder(port);
843
-
if (wait_for_us((intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)) &
836
+
if (wait_for_us((intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans)) &
844
837
LINK_READY), 2500))
845
-
drm_err(&dev_priv->drm, "DSI link not ready\n");
838
+
drm_err(display->drm, "DSI link not ready\n");
846
839
}
847
840
}
848
841
···
850
843
gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
851
844
const struct intel_crtc_state *crtc_state)
852
845
{
853
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
846
+
struct intel_display *display = to_intel_display(encoder);
854
847
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
855
848
const struct drm_display_mode *adjusted_mode =
856
849
&crtc_state->hw.adjusted_mode;
···
917
910
918
911
/* minimum hactive as per bspec: 256 pixels */
919
912
if (adjusted_mode->crtc_hdisplay < 256)
920
-
drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n");
913
+
drm_err(display->drm, "hactive is less then 256 pixels\n");
921
914
922
915
/* if RGB666 format, then hactive must be multiple of 4 pixels */
923
916
if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0)
924
-
drm_err(&dev_priv->drm,
917
+
drm_err(display->drm,
925
918
"hactive pixels are not multiple of 4\n");
926
919
927
920
/* program TRANS_HTOTAL register */
928
921
for_each_dsi_port(port, intel_dsi->ports) {
929
922
dsi_trans = dsi_port_to_transcoder(port);
930
-
intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, dsi_trans),
923
+
intel_de_write(display, TRANS_HTOTAL(display, dsi_trans),
931
924
HACTIVE(hactive - 1) | HTOTAL(htotal - 1));
932
925
}
933
926
···
936
929
if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) {
937
930
/* BSPEC: hsync size should be atleast 16 pixels */
938
931
if (hsync_size < 16)
939
-
drm_err(&dev_priv->drm,
932
+
drm_err(display->drm,
940
933
"hsync size < 16 pixels\n");
941
934
}
942
935
943
936
if (hback_porch < 16)
944
-
drm_err(&dev_priv->drm, "hback porch < 16 pixels\n");
937
+
drm_err(display->drm, "hback porch < 16 pixels\n");
945
938
946
939
if (intel_dsi->dual_link) {
947
940
hsync_start /= 2;
···
950
943
951
944
for_each_dsi_port(port, intel_dsi->ports) {
952
945
dsi_trans = dsi_port_to_transcoder(port);
953
-
intel_de_write(dev_priv,
954
-
TRANS_HSYNC(dev_priv, dsi_trans),
946
+
intel_de_write(display,
947
+
TRANS_HSYNC(display, dsi_trans),
955
948
HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1));
956
949
}
957
950
}
···
965
958
* struct drm_display_mode.
966
959
* For interlace mode: program required pixel minus 2
967
960
*/
968
-
intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, dsi_trans),
961
+
intel_de_write(display, TRANS_VTOTAL(display, dsi_trans),
969
962
VACTIVE(vactive - 1) | VTOTAL(vtotal - 1));
970
963
}
971
964
972
965
if (vsync_end < vsync_start || vsync_end > vtotal)
973
-
drm_err(&dev_priv->drm, "Invalid vsync_end value\n");
966
+
drm_err(display->drm, "Invalid vsync_end value\n");
974
967
975
968
if (vsync_start < vactive)
976
-
drm_err(&dev_priv->drm, "vsync_start less than vactive\n");
969
+
drm_err(display->drm, "vsync_start less than vactive\n");
977
970
978
971
/* program TRANS_VSYNC register for video mode only */
979
972
if (is_vid_mode(intel_dsi)) {
980
973
for_each_dsi_port(port, intel_dsi->ports) {
981
974
dsi_trans = dsi_port_to_transcoder(port);
982
-
intel_de_write(dev_priv,
983
-
TRANS_VSYNC(dev_priv, dsi_trans),
975
+
intel_de_write(display,
976
+
TRANS_VSYNC(display, dsi_trans),
984
977
VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1));
985
978
}
986
979
}
···
994
987
if (is_vid_mode(intel_dsi)) {
995
988
for_each_dsi_port(port, intel_dsi->ports) {
996
989
dsi_trans = dsi_port_to_transcoder(port);
997
-
intel_de_write(dev_priv,
998
-
TRANS_VSYNCSHIFT(dev_priv, dsi_trans),
990
+
intel_de_write(display,
991
+
TRANS_VSYNCSHIFT(display, dsi_trans),
999
992
vsync_shift);
1000
993
}
1001
994
}
···
1006
999
* FIXME get rid of these local hacks and do it right,
1007
1000
* this will not handle eg. delayed vblank correctly.
1008
1001
*/
1009
-
if (DISPLAY_VER(dev_priv) >= 12) {
1002
+
if (DISPLAY_VER(display) >= 12) {
1010
1003
for_each_dsi_port(port, intel_dsi->ports) {
1011
1004
dsi_trans = dsi_port_to_transcoder(port);
1012
-
intel_de_write(dev_priv,
1013
-
TRANS_VBLANK(dev_priv, dsi_trans),
1005
+
intel_de_write(display,
1006
+
TRANS_VBLANK(display, dsi_trans),
1014
1007
VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1));
1015
1008
}
1016
1009
}
···
1018
1011
1019
1012
static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
1020
1013
{
1021
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1014
+
struct intel_display *display = to_intel_display(encoder);
1022
1015
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1023
1016
enum port port;
1024
1017
enum transcoder dsi_trans;
1025
1018
1026
1019
for_each_dsi_port(port, intel_dsi->ports) {
1027
1020
dsi_trans = dsi_port_to_transcoder(port);
1028
-
intel_de_rmw(dev_priv, TRANSCONF(dev_priv, dsi_trans), 0,
1021
+
intel_de_rmw(display, TRANSCONF(display, dsi_trans), 0,
1029
1022
TRANSCONF_ENABLE);
1030
1023
1031
1024
/* wait for transcoder to be enabled */
1032
-
if (intel_de_wait_for_set(dev_priv, TRANSCONF(dev_priv, dsi_trans),
1025
+
if (intel_de_wait_for_set(display, TRANSCONF(display, dsi_trans),
1033
1026
TRANSCONF_STATE_ENABLE, 10))
1034
-
drm_err(&dev_priv->drm,
1027
+
drm_err(display->drm,
1035
1028
"DSI transcoder not enabled\n");
1036
1029
}
1037
1030
}
···
1039
1032
static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder,
1040
1033
const struct intel_crtc_state *crtc_state)
1041
1034
{
1042
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1035
+
struct intel_display *display = to_intel_display(encoder);
1043
1036
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1044
1037
enum port port;
1045
1038
enum transcoder dsi_trans;
···
1063
1056
dsi_trans = dsi_port_to_transcoder(port);
1064
1057
1065
1058
/* program hst_tx_timeout */
1066
-
intel_de_rmw(dev_priv, DSI_HSTX_TO(dsi_trans),
1059
+
intel_de_rmw(display, DSI_HSTX_TO(dsi_trans),
1067
1060
HSTX_TIMEOUT_VALUE_MASK,
1068
1061
HSTX_TIMEOUT_VALUE(hs_tx_timeout));
1069
1062
1070
1063
/* FIXME: DSI_CALIB_TO */
1071
1064
1072
1065
/* program lp_rx_host timeout */
1073
-
intel_de_rmw(dev_priv, DSI_LPRX_HOST_TO(dsi_trans),
1066
+
intel_de_rmw(display, DSI_LPRX_HOST_TO(dsi_trans),
1074
1067
LPRX_TIMEOUT_VALUE_MASK,
1075
1068
LPRX_TIMEOUT_VALUE(lp_rx_timeout));
1076
1069
1077
1070
/* FIXME: DSI_PWAIT_TO */
1078
1071
1079
1072
/* program turn around timeout */
1080
-
intel_de_rmw(dev_priv, DSI_TA_TO(dsi_trans),
1073
+
intel_de_rmw(display, DSI_TA_TO(dsi_trans),
1081
1074
TA_TIMEOUT_VALUE_MASK,
1082
1075
TA_TIMEOUT_VALUE(ta_timeout));
1083
1076
}
···
1086
1079
static void gen11_dsi_config_util_pin(struct intel_encoder *encoder,
1087
1080
bool enable)
1088
1081
{
1089
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1082
+
struct intel_display *display = to_intel_display(encoder);
1090
1083
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1091
1084
u32 tmp;
1092
1085
···
1098
1091
if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B)))
1099
1092
return;
1100
1093
1101
-
tmp = intel_de_read(dev_priv, UTIL_PIN_CTL);
1094
+
tmp = intel_de_read(display, UTIL_PIN_CTL);
1102
1095
1103
1096
if (enable) {
1104
1097
tmp |= UTIL_PIN_DIRECTION_INPUT;
···
1106
1099
} else {
1107
1100
tmp &= ~UTIL_PIN_ENABLE;
1108
1101
}
1109
-
intel_de_write(dev_priv, UTIL_PIN_CTL, tmp);
1102
+
intel_de_write(display, UTIL_PIN_CTL, tmp);
1110
1103
}
1111
1104
1112
1105
static void
···
1144
1137
1145
1138
static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
1146
1139
{
1147
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1140
+
struct intel_display *display = to_intel_display(encoder);
1148
1141
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1149
1142
struct mipi_dsi_device *dsi;
1150
1143
enum port port;
···
1160
1153
* FIXME: This uses the number of DW's currently in the payload
1161
1154
* receive queue. This is probably not what we want here.
1162
1155
*/
1163
-
tmp = intel_de_read(dev_priv, DSI_CMD_RXCTL(dsi_trans));
1156
+
tmp = intel_de_read(display, DSI_CMD_RXCTL(dsi_trans));
1164
1157
tmp &= NUMBER_RX_PLOAD_DW_MASK;
1165
1158
/* multiply "Number Rx Payload DW" by 4 to get max value */
1166
1159
tmp = tmp * 4;
1167
1160
dsi = intel_dsi->dsi_hosts[port]->device;
1168
1161
ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp);
1169
1162
if (ret < 0)
1170
-
drm_err(&dev_priv->drm,
1163
+
drm_err(display->drm,
1171
1164
"error setting max return pkt size%d\n", tmp);
1172
1165
}
1173
1166
···
1227
1220
static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder,
1228
1221
enum pipe pipe, bool enable)
1229
1222
{
1230
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1223
+
struct intel_display *display = to_intel_display(encoder);
1231
1224
1232
-
if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B)
1233
-
intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
1225
+
if (DISPLAY_VER(display) == 11 && pipe == PIPE_B)
1226
+
intel_de_rmw(display, CHICKEN_PAR1_1,
1234
1227
IGNORE_KVMR_PIPE_A,
1235
1228
enable ? IGNORE_KVMR_PIPE_A : 0);
1236
1229
}
···
1243
1236
*/
1244
1237
static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder)
1245
1238
{
1246
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1239
+
struct intel_display *display = to_intel_display(encoder);
1247
1240
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1248
1241
enum port port;
1249
1242
1250
-
if (DISPLAY_VER(i915) == 13) {
1243
+
if (DISPLAY_VER(display) == 13) {
1251
1244
for_each_dsi_port(port, intel_dsi->ports)
1252
-
intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
1245
+
intel_de_rmw(display, TGL_DSI_CHKN_REG(port),
1253
1246
TGL_DSI_CHKN_LSHS_GB_MASK,
1254
1247
TGL_DSI_CHKN_LSHS_GB(4));
1255
1248
}
···
1283
1276
1284
1277
static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
1285
1278
{
1286
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1279
+
struct intel_display *display = to_intel_display(encoder);
1287
1280
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1288
1281
enum port port;
1289
1282
enum transcoder dsi_trans;
···
1292
1285
dsi_trans = dsi_port_to_transcoder(port);
1293
1286
1294
1287
/* disable transcoder */
1295
-
intel_de_rmw(dev_priv, TRANSCONF(dev_priv, dsi_trans),
1288
+
intel_de_rmw(display, TRANSCONF(display, dsi_trans),
1296
1289
TRANSCONF_ENABLE, 0);
1297
1290
1298
1291
/* wait for transcoder to be disabled */
1299
-
if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dev_priv, dsi_trans),
1292
+
if (intel_de_wait_for_clear(display, TRANSCONF(display, dsi_trans),
1300
1293
TRANSCONF_STATE_ENABLE, 50))
1301
-
drm_err(&dev_priv->drm,
1294
+
drm_err(display->drm,
1302
1295
"DSI trancoder not disabled\n");
1303
1296
}
1304
1297
}
···
1315
1308
1316
1309
static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
1317
1310
{
1318
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1311
+
struct intel_display *display = to_intel_display(encoder);
1319
1312
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1320
1313
enum port port;
1321
1314
enum transcoder dsi_trans;
···
1324
1317
/* disable periodic update mode */
1325
1318
if (is_cmd_mode(intel_dsi)) {
1326
1319
for_each_dsi_port(port, intel_dsi->ports)
1327
-
intel_de_rmw(dev_priv, DSI_CMD_FRMCTL(port),
1320
+
intel_de_rmw(display, DSI_CMD_FRMCTL(port),
1328
1321
DSI_PERIODIC_FRAME_UPDATE_ENABLE, 0);
1329
1322
}
1330
1323
1331
1324
/* put dsi link in ULPS */
1332
1325
for_each_dsi_port(port, intel_dsi->ports) {
1333
1326
dsi_trans = dsi_port_to_transcoder(port);
1334
-
tmp = intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans));
1327
+
tmp = intel_de_read(display, DSI_LP_MSG(dsi_trans));
1335
1328
tmp |= LINK_ENTER_ULPS;
1336
1329
tmp &= ~LINK_ULPS_TYPE_LP11;
1337
-
intel_de_write(dev_priv, DSI_LP_MSG(dsi_trans), tmp);
1330
+
intel_de_write(display, DSI_LP_MSG(dsi_trans), tmp);
1338
1331
1339
-
if (wait_for_us((intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) &
1332
+
if (wait_for_us((intel_de_read(display, DSI_LP_MSG(dsi_trans)) &
1340
1333
LINK_IN_ULPS),
1341
1334
10))
1342
-
drm_err(&dev_priv->drm, "DSI link not in ULPS\n");
1335
+
drm_err(display->drm, "DSI link not in ULPS\n");
1343
1336
}
1344
1337
1345
1338
/* disable ddi function */
1346
1339
for_each_dsi_port(port, intel_dsi->ports) {
1347
1340
dsi_trans = dsi_port_to_transcoder(port);
1348
-
intel_de_rmw(dev_priv,
1349
-
TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans),
1341
+
intel_de_rmw(display,
1342
+
TRANS_DDI_FUNC_CTL(display, dsi_trans),
1350
1343
TRANS_DDI_FUNC_ENABLE, 0);
1351
1344
}
1352
1345
···
1354
1347
if (intel_dsi->dual_link) {
1355
1348
for_each_dsi_port(port, intel_dsi->ports) {
1356
1349
dsi_trans = dsi_port_to_transcoder(port);
1357
-
intel_de_rmw(dev_priv,
1358
-
TRANS_DDI_FUNC_CTL2(dev_priv, dsi_trans),
1350
+
intel_de_rmw(display,
1351
+
TRANS_DDI_FUNC_CTL2(display, dsi_trans),
1359
1352
PORT_SYNC_MODE_ENABLE, 0);
1360
1353
}
1361
1354
}
···
1363
1356
1364
1357
static void gen11_dsi_disable_port(struct intel_encoder *encoder)
1365
1358
{
1366
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1359
+
struct intel_display *display = to_intel_display(encoder);
1367
1360
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1368
1361
enum port port;
1369
1362
1370
1363
gen11_dsi_ungate_clocks(encoder);
1371
1364
for_each_dsi_port(port, intel_dsi->ports) {
1372
-
intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);
1365
+
intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);
1373
1366
1374
-
if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
1367
+
if (wait_for_us((intel_de_read(display, DDI_BUF_CTL(port)) &
1375
1368
DDI_BUF_IS_IDLE),
1376
1369
8))
1377
-
drm_err(&dev_priv->drm,
1370
+
drm_err(display->drm,
1378
1371
"DDI port:%c buffer not idle\n",
1379
1372
port_name(port));
1380
1373
}
···
1383
1376
1384
1377
static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
1385
1378
{
1379
+
struct intel_display *display = to_intel_display(encoder);
1386
1380
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1387
1381
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1388
1382
enum port port;
···
1401
1393
1402
1394
/* set mode to DDI */
1403
1395
for_each_dsi_port(port, intel_dsi->ports)
1404
-
intel_de_rmw(dev_priv, ICL_DSI_IO_MODECTL(port),
1396
+
intel_de_rmw(display, ICL_DSI_IO_MODECTL(port),
1405
1397
COMBO_PHY_MODE_DSI, 0);
1406
1398
}
1407
1399
···
1513
1505
1514
1506
static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi)
1515
1507
{
1516
-
struct drm_device *dev = intel_dsi->base.base.dev;
1517
-
struct drm_i915_private *dev_priv = to_i915(dev);
1508
+
struct intel_display *display = to_intel_display(&intel_dsi->base);
1518
1509
enum transcoder dsi_trans;
1519
1510
u32 val;
1520
1511
···
1522
1515
else
1523
1516
dsi_trans = TRANSCODER_DSI_0;
1524
1517
1525
-
val = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans));
1518
+
val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));
1526
1519
return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE);
1527
1520
}
1528
1521
···
1565
1558
static void gen11_dsi_sync_state(struct intel_encoder *encoder,
1566
1559
const struct intel_crtc_state *crtc_state)
1567
1560
{
1568
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1561
+
struct intel_display *display = to_intel_display(encoder);
1569
1562
struct intel_crtc *intel_crtc;
1570
1563
enum pipe pipe;
1571
1564
···
1576
1569
pipe = intel_crtc->pipe;
1577
1570
1578
1571
/* wa verify 1409054076:icl,jsl,ehl */
1579
-
if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B &&
1580
-
!(intel_de_read(dev_priv, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A))
1581
-
drm_dbg_kms(&dev_priv->drm,
1572
+
if (DISPLAY_VER(display) == 11 && pipe == PIPE_B &&
1573
+
!(intel_de_read(display, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A))
1574
+
drm_dbg_kms(display->drm,
1582
1575
"[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n",
1583
1576
encoder->base.base.id,
1584
1577
encoder->base.name);
···
1587
1580
static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
1588
1581
struct intel_crtc_state *crtc_state)
1589
1582
{
1590
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1583
+
struct intel_display *display = to_intel_display(encoder);
1591
1584
struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1592
-
int dsc_max_bpc = DISPLAY_VER(dev_priv) >= 12 ? 12 : 10;
1585
+
int dsc_max_bpc = DISPLAY_VER(display) >= 12 ? 12 : 10;
1593
1586
bool use_dsc;
1594
1587
int ret;
1595
1588
···
1614
1607
return ret;
1615
1608
1616
1609
/* DSI specific sanity checks on the common code */
1617
-
drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable);
1618
-
drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422);
1619
-
drm_WARN_ON(&dev_priv->drm,
1610
+
drm_WARN_ON(display->drm, vdsc_cfg->vbr_enable);
1611
+
drm_WARN_ON(display->drm, vdsc_cfg->simple_422);
1612
+
drm_WARN_ON(display->drm,
1620
1613
vdsc_cfg->pic_width % vdsc_cfg->slice_width);
1621
-
drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8);
1622
-
drm_WARN_ON(&dev_priv->drm,
1614
+
drm_WARN_ON(display->drm, vdsc_cfg->slice_height < 8);
1615
+
drm_WARN_ON(display->drm,
1623
1616
vdsc_cfg->pic_height % vdsc_cfg->slice_height);
1624
1617
1625
1618
ret = drm_dsc_compute_rc_parameters(vdsc_cfg);
···
1635
1628
struct intel_crtc_state *pipe_config,
1636
1629
struct drm_connector_state *conn_state)
1637
1630
{
1638
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1631
+
struct intel_display *display = to_intel_display(encoder);
1639
1632
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1640
1633
struct intel_connector *intel_connector = intel_dsi->attached_connector;
1641
1634
struct drm_display_mode *adjusted_mode =
···
1669
1662
pipe_config->clock_set = true;
1670
1663
1671
1664
if (gen11_dsi_dsc_compute_config(encoder, pipe_config))
1672
-
drm_dbg_kms(&i915->drm, "Attempting to use DSC failed\n");
1665
+
drm_dbg_kms(display->drm, "Attempting to use DSC failed\n");
1673
1666
1674
1667
pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
1675
1668
···
1687
1680
static void gen11_dsi_get_power_domains(struct intel_encoder *encoder,
1688
1681
struct intel_crtc_state *crtc_state)
1689
1682
{
1690
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1691
-
1692
-
get_dsi_io_power_domains(i915,
1693
-
enc_to_intel_dsi(encoder));
1683
+
get_dsi_io_power_domains(enc_to_intel_dsi(encoder));
1694
1684
}
1695
1685
1696
1686
static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
1697
1687
enum pipe *pipe)
1698
1688
{
1689
+
struct intel_display *display = to_intel_display(encoder);
1699
1690
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1700
1691
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1701
1692
enum transcoder dsi_trans;
···
1709
1704
1710
1705
for_each_dsi_port(port, intel_dsi->ports) {
1711
1706
dsi_trans = dsi_port_to_transcoder(port);
1712
-
tmp = intel_de_read(dev_priv,
1713
-
TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans));
1707
+
tmp = intel_de_read(display,
1708
+
TRANS_DDI_FUNC_CTL(display, dsi_trans));
1714
1709
switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1715
1710
case TRANS_DDI_EDP_INPUT_A_ON:
1716
1711
*pipe = PIPE_A;
···
1725
1720
*pipe = PIPE_D;
1726
1721
break;
1727
1722
default:
1728
-
drm_err(&dev_priv->drm, "Invalid PIPE input\n");
1723
+
drm_err(display->drm, "Invalid PIPE input\n");
1729
1724
goto out;
1730
1725
}
1731
1726
1732
-
tmp = intel_de_read(dev_priv, TRANSCONF(dev_priv, dsi_trans));
1727
+
tmp = intel_de_read(display, TRANSCONF(display, dsi_trans));
1733
1728
ret = tmp & TRANSCONF_ENABLE;
1734
1729
}
1735
1730
out:
···
1839
1834
1840
1835
static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
1841
1836
{
1842
-
struct drm_device *dev = intel_dsi->base.base.dev;
1843
-
struct drm_i915_private *dev_priv = to_i915(dev);
1837
+
struct intel_display *display = to_intel_display(&intel_dsi->base);
1844
1838
struct intel_connector *connector = intel_dsi->attached_connector;
1845
1839
struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
1846
1840
u32 tlpx_ns;
···
1863
1859
*/
1864
1860
prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
1865
1861
if (prepare_cnt > ICL_PREPARE_CNT_MAX) {
1866
-
drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n",
1862
+
drm_dbg_kms(display->drm, "prepare_cnt out of range (%d)\n",
1867
1863
prepare_cnt);
1868
1864
prepare_cnt = ICL_PREPARE_CNT_MAX;
1869
1865
}
···
1872
1868
clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
1873
1869
ths_prepare_ns, tlpx_ns);
1874
1870
if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) {
1875
-
drm_dbg_kms(&dev_priv->drm,
1871
+
drm_dbg_kms(display->drm,
1876
1872
"clk_zero_cnt out of range (%d)\n", clk_zero_cnt);
1877
1873
clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX;
1878
1874
}
···
1880
1876
/* trail cnt in escape clocks*/
1881
1877
trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
1882
1878
if (trail_cnt > ICL_TRAIL_CNT_MAX) {
1883
-
drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n",
1879
+
drm_dbg_kms(display->drm, "trail_cnt out of range (%d)\n",
1884
1880
trail_cnt);
1885
1881
trail_cnt = ICL_TRAIL_CNT_MAX;
1886
1882
}
···
1888
1884
/* tclk pre count in escape clocks */
1889
1885
tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
1890
1886
if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) {
1891
-
drm_dbg_kms(&dev_priv->drm,
1887
+
drm_dbg_kms(display->drm,
1892
1888
"tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt);
1893
1889
tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
1894
1890
}
···
1897
1893
hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
1898
1894
ths_prepare_ns, tlpx_ns);
1899
1895
if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) {
1900
-
drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n",
1896
+
drm_dbg_kms(display->drm, "hs_zero_cnt out of range (%d)\n",
1901
1897
hs_zero_cnt);
1902
1898
hs_zero_cnt = ICL_HS_ZERO_CNT_MAX;
1903
1899
}
···
1905
1901
/* hs exit zero cnt in escape clocks */
1906
1902
exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
1907
1903
if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) {
1908
-
drm_dbg_kms(&dev_priv->drm,
1904
+
drm_dbg_kms(display->drm,
1909
1905
"exit_zero_cnt out of range (%d)\n",
1910
1906
exit_zero_cnt);
1911
1907
exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX;
···
1947
1943
fixed_mode->vdisplay);
1948
1944
}
1949
1945
1950
-
void icl_dsi_init(struct drm_i915_private *dev_priv,
1946
+
void icl_dsi_init(struct intel_display *display,
1951
1947
const struct intel_bios_encoder_data *devdata)
1952
1948
{
1953
-
struct intel_display *display = &dev_priv->display;
1954
1949
struct intel_dsi *intel_dsi;
1955
1950
struct intel_encoder *encoder;
1956
1951
struct intel_connector *intel_connector;
···
1977
1974
encoder->devdata = devdata;
1978
1975
1979
1976
/* register DSI encoder with DRM subsystem */
1980
-
drm_encoder_init(&dev_priv->drm, &encoder->base, &gen11_dsi_encoder_funcs,
1977
+
drm_encoder_init(display->drm, &encoder->base,
1978
+
&gen11_dsi_encoder_funcs,
1981
1979
DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));
1982
1980
1983
1981
encoder->pre_pll_enable = gen11_dsi_pre_pll_enable;
···
2003
1999
encoder->shutdown = intel_dsi_shutdown;
2004
2000
2005
2001
/* register DSI connector with DRM subsystem */
2006
-
drm_connector_init(&dev_priv->drm, connector, &gen11_dsi_connector_funcs,
2002
+
drm_connector_init(display->drm, connector,
2003
+
&gen11_dsi_connector_funcs,
2007
2004
DRM_MODE_CONNECTOR_DSI);
2008
2005
drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs);
2009
2006
connector->display_info.subpixel_order = SubPixelHorizontalRGB;
···
2017
2012
2018
2013
intel_bios_init_panel_late(display, &intel_connector->panel, encoder->devdata, NULL);
2019
2014
2020
-
mutex_lock(&dev_priv->drm.mode_config.mutex);
2015
+
mutex_lock(&display->drm->mode_config.mutex);
2021
2016
intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
2022
-
mutex_unlock(&dev_priv->drm.mode_config.mutex);
2017
+
mutex_unlock(&display->drm->mode_config.mutex);
2023
2018
2024
2019
if (!intel_panel_preferred_fixed_mode(intel_connector)) {
2025
-
drm_err(&dev_priv->drm, "DSI fixed mode info missing\n");
2020
+
drm_err(display->drm, "DSI fixed mode info missing\n");
2026
2021
goto err;
2027
2022
}
2028
2023
···
2035
2030
else
2036
2031
intel_dsi->ports = BIT(port);
2037
2032
2038
-
if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))
2033
+
if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))
2039
2034
intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports;
2040
2035
2041
-
if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
2036
+
if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
2042
2037
intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports;
2043
2038
2044
2039
for_each_dsi_port(port, intel_dsi->ports) {
···
2052
2047
}
2053
2048
2054
2049
if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
2055
-
drm_dbg_kms(&dev_priv->drm, "no device found\n");
2050
+
drm_dbg_kms(display->drm, "no device found\n");
2056
2051
goto err;
2057
2052
}
2058
2053
+2
-2
drivers/gpu/drm/i915/display/icl_dsi.h
+2
-2
drivers/gpu/drm/i915/display/icl_dsi.h
···
6
6
#ifndef __ICL_DSI_H__
7
7
#define __ICL_DSI_H__
8
8
9
-
struct drm_i915_private;
10
9
struct intel_bios_encoder_data;
11
10
struct intel_crtc_state;
11
+
struct intel_display;
12
12
13
-
void icl_dsi_init(struct drm_i915_private *dev_priv,
13
+
void icl_dsi_init(struct intel_display *display,
14
14
const struct intel_bios_encoder_data *devdata);
15
15
void icl_dsi_frame_update(struct intel_crtc_state *crtc_state);
16
16
+6
drivers/gpu/drm/i915/display/intel_atomic_plane.c
+6
drivers/gpu/drm/i915/display/intel_atomic_plane.c
···
1024
1024
*/
1025
1025
hsub = 1;
1026
1026
vsub = 1;
1027
+
1028
+
/* Wa_16023981245 */
1029
+
if ((DISPLAY_VERx100(i915) == 2000 ||
1030
+
DISPLAY_VERx100(i915) == 3000) &&
1031
+
src_x % 2 != 0)
1032
+
hsub = 2;
1027
1033
} else {
1028
1034
hsub = fb->format->hsub;
1029
1035
vsub = fb->format->vsub;
+3
-3
drivers/gpu/drm/i915/display/intel_backlight.c
+3
-3
drivers/gpu/drm/i915/display/intel_backlight.c
···
949
949
else
950
950
props.power = BACKLIGHT_POWER_OFF;
951
951
952
-
name = kstrdup_const("intel_backlight", GFP_KERNEL);
952
+
name = kstrdup("intel_backlight", GFP_KERNEL);
953
953
if (!name)
954
954
return -ENOMEM;
955
955
···
963
963
* compatibility. Use unique names for subsequent backlight devices as a
964
964
* fallback when the default name already exists.
965
965
*/
966
-
kfree_const(name);
966
+
kfree(name);
967
967
name = kasprintf(GFP_KERNEL, "card%d-%s-backlight",
968
968
i915->drm.primary->index, connector->base.name);
969
969
if (!name)
···
987
987
connector->base.base.id, connector->base.name, name);
988
988
989
989
out:
990
-
kfree_const(name);
990
+
kfree(name);
991
991
992
992
return ret;
993
993
}
+17
-29
drivers/gpu/drm/i915/display/intel_bios.c
+17
-29
drivers/gpu/drm/i915/display/intel_bios.c
···
1169
1169
static void
1170
1170
parse_general_features(struct intel_display *display)
1171
1171
{
1172
-
struct drm_i915_private *i915 = to_i915(display->drm);
1173
1172
const struct bdb_general_features *general;
1174
1173
1175
1174
general = bdb_find_section(display, BDB_GENERAL_FEATURES);
···
1178
1179
display->vbt.int_tv_support = general->int_tv_support;
1179
1180
/* int_crt_support can't be trusted on earlier platforms */
1180
1181
if (display->vbt.version >= 155 &&
1181
-
(HAS_DDI(display) || IS_VALLEYVIEW(i915)))
1182
+
(HAS_DDI(display) || display->platform.valleyview))
1182
1183
display->vbt.int_crt_support = general->int_crt_support;
1183
1184
display->vbt.lvds_use_ssc = general->enable_ssc;
1184
1185
display->vbt.lvds_ssc_freq =
···
1541
1542
parse_psr(struct intel_display *display,
1542
1543
struct intel_panel *panel)
1543
1544
{
1544
-
struct drm_i915_private *i915 = to_i915(display->drm);
1545
1545
const struct bdb_psr *psr;
1546
1546
const struct psr_table *psr_table;
1547
1547
int panel_type = panel->vbt.panel_type;
···
1565
1567
* Old decimal value is wake up time in multiples of 100 us.
1566
1568
*/
1567
1569
if (display->vbt.version >= 205 &&
1568
-
(DISPLAY_VER(display) >= 9 && !IS_BROXTON(i915))) {
1570
+
(DISPLAY_VER(display) >= 9 && !display->platform.broxton)) {
1569
1571
switch (psr_table->tp1_wakeup_time) {
1570
1572
case 0:
1571
1573
panel->vbt.psr.tp1_wakeup_time_us = 500;
···
2027
2029
static void fixup_mipi_sequences(struct intel_display *display,
2028
2030
struct intel_panel *panel)
2029
2031
{
2030
-
struct drm_i915_private *i915 = to_i915(display->drm);
2031
-
2032
2032
if (DISPLAY_VER(display) >= 11)
2033
2033
icl_fixup_mipi_sequences(display, panel);
2034
-
else if (IS_VALLEYVIEW(i915))
2034
+
else if (display->platform.valleyview)
2035
2035
vlv_fixup_mipi_sequences(display, panel);
2036
2036
}
2037
2037
···
2239
2243
const u8 *ddc_pin_map;
2240
2244
int i, n_entries;
2241
2245
2242
-
if (INTEL_PCH_TYPE(i915) >= PCH_MTL || IS_ALDERLAKE_P(i915)) {
2246
+
if (INTEL_PCH_TYPE(i915) >= PCH_MTL || display->platform.alderlake_p) {
2243
2247
ddc_pin_map = adlp_ddc_pin_map;
2244
2248
n_entries = ARRAY_SIZE(adlp_ddc_pin_map);
2245
-
} else if (IS_ALDERLAKE_S(i915)) {
2249
+
} else if (display->platform.alderlake_s) {
2246
2250
ddc_pin_map = adls_ddc_pin_map;
2247
2251
n_entries = ARRAY_SIZE(adls_ddc_pin_map);
2248
2252
} else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
2249
2253
return vbt_pin;
2250
-
} else if (IS_ROCKETLAKE(i915) && INTEL_PCH_TYPE(i915) == PCH_TGP) {
2254
+
} else if (display->platform.rocketlake && INTEL_PCH_TYPE(i915) == PCH_TGP) {
2251
2255
ddc_pin_map = rkl_pch_tgp_ddc_pin_map;
2252
2256
n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map);
2253
2257
} else if (HAS_PCH_TGP(i915) && DISPLAY_VER(display) == 9) {
···
2330
2334
static enum port dvo_port_to_port(struct intel_display *display,
2331
2335
u8 dvo_port)
2332
2336
{
2333
-
struct drm_i915_private *i915 = to_i915(display->drm);
2334
2337
/*
2335
2338
* Each DDI port can have more than one value on the "DVO Port" field,
2336
2339
* so look for all the possible values for each port.
···
2386
2391
ARRAY_SIZE(xelpd_port_mapping[0]),
2387
2392
xelpd_port_mapping,
2388
2393
dvo_port);
2389
-
else if (IS_ALDERLAKE_S(i915))
2394
+
else if (display->platform.alderlake_s)
2390
2395
return __dvo_port_to_port(ARRAY_SIZE(adls_port_mapping),
2391
2396
ARRAY_SIZE(adls_port_mapping[0]),
2392
2397
adls_port_mapping,
2393
2398
dvo_port);
2394
-
else if (IS_DG1(i915) || IS_ROCKETLAKE(i915))
2399
+
else if (display->platform.dg1 || display->platform.rocketlake)
2395
2400
return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping),
2396
2401
ARRAY_SIZE(rkl_port_mapping[0]),
2397
2402
rkl_port_mapping,
···
2514
2519
enum port port)
2515
2520
{
2516
2521
struct intel_display *display = devdata->display;
2517
-
struct drm_i915_private *i915 = to_i915(display->drm);
2518
2522
2519
2523
if (!intel_bios_encoder_supports_dvi(devdata))
2520
2524
return;
···
2523
2529
* with a HSW VBT where the level shifter value goes
2524
2530
* up to 11, whereas the BDW max is 9.
2525
2531
*/
2526
-
if (IS_BROADWELL(i915) && devdata->child.hdmi_level_shifter_value > 9) {
2532
+
if (display->platform.broadwell && devdata->child.hdmi_level_shifter_value > 9) {
2527
2533
drm_dbg_kms(display->drm,
2528
2534
"Bogus port %c VBT HDMI level shift %d, adjusting to %d\n",
2529
2535
port_name(port), devdata->child.hdmi_level_shifter_value, 9);
···
2612
2618
2613
2619
static bool is_port_valid(struct intel_display *display, enum port port)
2614
2620
{
2615
-
struct drm_i915_private *i915 = to_i915(display->drm);
2616
2621
/*
2617
2622
* On some ICL SKUs port F is not present, but broken VBTs mark
2618
2623
* the port as present. Only try to initialize port F for the
2619
2624
* SKUs that may actually have it.
2620
2625
*/
2621
-
if (port == PORT_F && IS_ICELAKE(i915))
2622
-
return IS_ICL_WITH_PORT_F(i915);
2626
+
if (port == PORT_F && display->platform.icelake)
2627
+
return display->platform.icelake_port_f;
2623
2628
2624
2629
return true;
2625
2630
}
···
2716
2723
2717
2724
static bool has_ddi_port_info(struct intel_display *display)
2718
2725
{
2719
-
struct drm_i915_private *i915 = to_i915(display->drm);
2720
-
2721
-
return DISPLAY_VER(display) >= 5 || IS_G4X(i915);
2726
+
return DISPLAY_VER(display) >= 5 || display->platform.g4x;
2722
2727
}
2723
2728
2724
2729
static void parse_ddi_ports(struct intel_display *display)
···
2787
2796
static void
2788
2797
parse_general_definitions(struct intel_display *display)
2789
2798
{
2790
-
struct drm_i915_private *i915 = to_i915(display->drm);
2791
2799
const struct bdb_general_definitions *defs;
2792
2800
struct intel_bios_encoder_data *devdata;
2793
2801
const struct child_device_config *child;
···
2811
2821
2812
2822
bus_pin = defs->crt_ddc_gmbus_pin;
2813
2823
drm_dbg_kms(display->drm, "crt_ddc_bus_pin: %d\n", bus_pin);
2814
-
if (intel_gmbus_is_valid_pin(i915, bus_pin))
2824
+
if (intel_gmbus_is_valid_pin(display, bus_pin))
2815
2825
display->vbt.crt_ddc_pin = bus_pin;
2816
2826
2817
2827
if (!child_device_size_valid(display, defs->child_dev_size))
···
2897
2907
unsigned int ports = DISPLAY_RUNTIME_INFO(display)->port_mask;
2898
2908
enum port port;
2899
2909
2900
-
if (!HAS_DDI(display) && !IS_CHERRYVIEW(i915))
2910
+
if (!HAS_DDI(display) && !display->platform.cherryview)
2901
2911
return;
2902
2912
2903
2913
for_each_port_masked(port, ports) {
···
3328
3338
*/
3329
3339
bool intel_bios_is_lvds_present(struct intel_display *display, u8 *i2c_pin)
3330
3340
{
3331
-
struct drm_i915_private *i915 = to_i915(display->drm);
3332
3341
const struct intel_bios_encoder_data *devdata;
3333
3342
3334
3343
if (list_empty(&display->vbt.display_devices))
···
3344
3355
child->device_type != DEVICE_TYPE_LFP)
3345
3356
continue;
3346
3357
3347
-
if (intel_gmbus_is_valid_pin(i915, child->i2c_pin))
3358
+
if (intel_gmbus_is_valid_pin(display, child->i2c_pin))
3348
3359
*i2c_pin = child->i2c_pin;
3349
3360
3350
3361
/* However, we cannot trust the BIOS writers to populate
···
3592
3603
3593
3604
static enum aux_ch map_aux_ch(struct intel_display *display, u8 aux_channel)
3594
3605
{
3595
-
struct drm_i915_private *i915 = to_i915(display->drm);
3596
3606
const u8 *aux_ch_map;
3597
3607
int i, n_entries;
3598
3608
3599
3609
if (DISPLAY_VER(display) >= 13) {
3600
3610
aux_ch_map = adlp_aux_ch_map;
3601
3611
n_entries = ARRAY_SIZE(adlp_aux_ch_map);
3602
-
} else if (IS_ALDERLAKE_S(i915)) {
3612
+
} else if (display->platform.alderlake_s) {
3603
3613
aux_ch_map = adls_aux_ch_map;
3604
3614
n_entries = ARRAY_SIZE(adls_aux_ch_map);
3605
-
} else if (IS_DG1(i915) || IS_ROCKETLAKE(i915)) {
3615
+
} else if (display->platform.dg1 || display->platform.rocketlake) {
3606
3616
aux_ch_map = rkl_aux_ch_map;
3607
3617
n_entries = ARRAY_SIZE(rkl_aux_ch_map);
3608
3618
} else {
+1
-1
drivers/gpu/drm/i915/display/intel_bw.c
+1
-1
drivers/gpu/drm/i915/display/intel_bw.c
···
743
743
if (!HAS_DISPLAY(dev_priv))
744
744
return;
745
745
746
-
if (DISPLAY_VER_FULL(dev_priv) >= IP_VER(14, 1) && IS_DGFX(dev_priv))
746
+
if (DISPLAY_VERx100(dev_priv) >= 1401 && IS_DGFX(dev_priv))
747
747
xe2_hpd_get_bw_info(dev_priv, &xe2_hpd_sa_info);
748
748
else if (DISPLAY_VER(dev_priv) >= 14)
749
749
tgl_get_bw_info(dev_priv, &mtl_sa_info);
+60
-5
drivers/gpu/drm/i915/display/intel_cdclk.c
+60
-5
drivers/gpu/drm/i915/display/intel_cdclk.c
···
1468
1468
{}
1469
1469
};
1470
1470
1471
+
static const struct intel_cdclk_vals xe3lpd_cdclk_table[] = {
1472
+
{ .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
1473
+
{ .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1474
+
{ .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1475
+
{ .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
1476
+
{ .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
1477
+
{ .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
1478
+
{ .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
1479
+
{ .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
1480
+
{ .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
1481
+
{ .refclk = 38400, .cdclk = 326400, .ratio = 17, .waveform = 0xffff },
1482
+
{ .refclk = 38400, .cdclk = 345600, .ratio = 18, .waveform = 0xffff },
1483
+
{ .refclk = 38400, .cdclk = 364800, .ratio = 19, .waveform = 0xffff },
1484
+
{ .refclk = 38400, .cdclk = 384000, .ratio = 20, .waveform = 0xffff },
1485
+
{ .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff },
1486
+
{ .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff },
1487
+
{ .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff },
1488
+
{ .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff },
1489
+
{ .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
1490
+
{ .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff },
1491
+
{ .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff },
1492
+
{ .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff },
1493
+
{ .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
1494
+
{ .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff },
1495
+
{ .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff },
1496
+
{ .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff },
1497
+
{ .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff },
1498
+
{ .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1499
+
{ .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff },
1500
+
{ .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff },
1501
+
{}
1502
+
};
1503
+
1471
1504
static const int cdclk_squash_len = 16;
1472
1505
1473
1506
static int cdclk_squash_divider(u16 waveform)
···
1625
1592
return calc_voltage_level(cdclk,
1626
1593
ARRAY_SIZE(rplu_voltage_level_max_cdclk),
1627
1594
rplu_voltage_level_max_cdclk);
1595
+
}
1596
+
1597
+
static u8 xe3lpd_calc_voltage_level(int cdclk)
1598
+
{
1599
+
/*
1600
+
* Starting with xe3lpd power controller does not need the voltage
1601
+
* index when doing the modeset update. This function is best left
1602
+
* defined but returning 0 to the mask.
1603
+
*/
1604
+
return 0;
1628
1605
}
1629
1606
1630
1607
static void icl_readout_refclk(struct intel_display *display,
···
2058
2015
{
2059
2016
struct drm_i915_private *dev_priv = to_i915(display->drm);
2060
2017
2061
-
return (DISPLAY_VER_FULL(display) == IP_VER(20, 0) ||
2062
-
DISPLAY_VER_FULL(display) == IP_VER(14, 0) ||
2018
+
return (DISPLAY_VERx100(display) == 2000 ||
2019
+
DISPLAY_VERx100(display) == 1400 ||
2063
2020
IS_DG2(dev_priv)) &&
2064
2021
display->cdclk.hw.vco > 0;
2065
2022
}
···
3480
3437
{
3481
3438
struct drm_i915_private *dev_priv = to_i915(display->drm);
3482
3439
3483
-
if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
3440
+
if (DISPLAY_VER(display) >= 30) {
3441
+
display->cdclk.max_cdclk_freq = 691200;
3442
+
} else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
3484
3443
if (display->cdclk.hw.ref == 24000)
3485
3444
display->cdclk.max_cdclk_freq = 552000;
3486
3445
else
···
3695
3650
display, &i915_cdclk_info_fops);
3696
3651
}
3697
3652
3653
+
static const struct intel_cdclk_funcs xe3lpd_cdclk_funcs = {
3654
+
.get_cdclk = bxt_get_cdclk,
3655
+
.set_cdclk = bxt_set_cdclk,
3656
+
.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3657
+
.calc_voltage_level = xe3lpd_calc_voltage_level,
3658
+
};
3659
+
3698
3660
static const struct intel_cdclk_funcs rplu_cdclk_funcs = {
3699
3661
.get_cdclk = bxt_get_cdclk,
3700
3662
.set_cdclk = bxt_set_cdclk,
···
3846
3794
{
3847
3795
struct drm_i915_private *dev_priv = to_i915(display->drm);
3848
3796
3849
-
if (DISPLAY_VER(display) >= 20) {
3797
+
if (DISPLAY_VER(display) >= 30) {
3798
+
display->funcs.cdclk = &xe3lpd_cdclk_funcs;
3799
+
display->cdclk.table = xe3lpd_cdclk_table;
3800
+
} else if (DISPLAY_VER(display) >= 20) {
3850
3801
display->funcs.cdclk = &rplu_cdclk_funcs;
3851
3802
display->cdclk.table = xe2lpd_cdclk_table;
3852
-
} else if (DISPLAY_VER_FULL(display) >= IP_VER(14, 1)) {
3803
+
} else if (DISPLAY_VERx100(display) >= 1401) {
3853
3804
display->funcs.cdclk = &rplu_cdclk_funcs;
3854
3805
display->cdclk.table = xe2hpd_cdclk_table;
3855
3806
} else if (DISPLAY_VER(display) >= 14) {
+344
-329
drivers/gpu/drm/i915/display/intel_color.c
+344
-329
drivers/gpu/drm/i915/display/intel_color.c
···
250
250
static void ilk_read_pipe_csc(struct intel_crtc *crtc,
251
251
struct intel_csc_matrix *csc)
252
252
{
253
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
253
+
struct intel_display *display = to_intel_display(crtc);
254
254
enum pipe pipe = crtc->pipe;
255
255
u32 tmp;
256
256
257
-
csc->preoff[0] = intel_de_read_fw(i915, PIPE_CSC_PREOFF_HI(pipe));
258
-
csc->preoff[1] = intel_de_read_fw(i915, PIPE_CSC_PREOFF_ME(pipe));
259
-
csc->preoff[2] = intel_de_read_fw(i915, PIPE_CSC_PREOFF_LO(pipe));
257
+
csc->preoff[0] = intel_de_read_fw(display, PIPE_CSC_PREOFF_HI(pipe));
258
+
csc->preoff[1] = intel_de_read_fw(display, PIPE_CSC_PREOFF_ME(pipe));
259
+
csc->preoff[2] = intel_de_read_fw(display, PIPE_CSC_PREOFF_LO(pipe));
260
260
261
-
tmp = intel_de_read_fw(i915, PIPE_CSC_COEFF_RY_GY(pipe));
261
+
tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_RY_GY(pipe));
262
262
csc->coeff[0] = tmp >> 16;
263
263
csc->coeff[1] = tmp & 0xffff;
264
-
tmp = intel_de_read_fw(i915, PIPE_CSC_COEFF_BY(pipe));
264
+
tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_BY(pipe));
265
265
csc->coeff[2] = tmp >> 16;
266
266
267
-
tmp = intel_de_read_fw(i915, PIPE_CSC_COEFF_RU_GU(pipe));
267
+
tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_RU_GU(pipe));
268
268
csc->coeff[3] = tmp >> 16;
269
269
csc->coeff[4] = tmp & 0xffff;
270
-
tmp = intel_de_read_fw(i915, PIPE_CSC_COEFF_BU(pipe));
270
+
tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_BU(pipe));
271
271
csc->coeff[5] = tmp >> 16;
272
272
273
-
tmp = intel_de_read_fw(i915, PIPE_CSC_COEFF_RV_GV(pipe));
273
+
tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_RV_GV(pipe));
274
274
csc->coeff[6] = tmp >> 16;
275
275
csc->coeff[7] = tmp & 0xffff;
276
-
tmp = intel_de_read_fw(i915, PIPE_CSC_COEFF_BV(pipe));
276
+
tmp = intel_de_read_fw(display, PIPE_CSC_COEFF_BV(pipe));
277
277
csc->coeff[8] = tmp >> 16;
278
278
279
-
if (DISPLAY_VER(i915) < 7)
279
+
if (DISPLAY_VER(display) < 7)
280
280
return;
281
281
282
-
csc->postoff[0] = intel_de_read_fw(i915, PIPE_CSC_POSTOFF_HI(pipe));
283
-
csc->postoff[1] = intel_de_read_fw(i915, PIPE_CSC_POSTOFF_ME(pipe));
284
-
csc->postoff[2] = intel_de_read_fw(i915, PIPE_CSC_POSTOFF_LO(pipe));
282
+
csc->postoff[0] = intel_de_read_fw(display, PIPE_CSC_POSTOFF_HI(pipe));
283
+
csc->postoff[1] = intel_de_read_fw(display, PIPE_CSC_POSTOFF_ME(pipe));
284
+
csc->postoff[2] = intel_de_read_fw(display, PIPE_CSC_POSTOFF_LO(pipe));
285
285
}
286
286
287
287
static void ilk_read_csc(struct intel_crtc_state *crtc_state)
···
353
353
static void icl_read_output_csc(struct intel_crtc *crtc,
354
354
struct intel_csc_matrix *csc)
355
355
{
356
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
356
+
struct intel_display *display = to_intel_display(crtc);
357
357
enum pipe pipe = crtc->pipe;
358
358
u32 tmp;
359
359
360
-
csc->preoff[0] = intel_de_read_fw(i915, PIPE_CSC_OUTPUT_PREOFF_HI(pipe));
361
-
csc->preoff[1] = intel_de_read_fw(i915, PIPE_CSC_OUTPUT_PREOFF_ME(pipe));
362
-
csc->preoff[2] = intel_de_read_fw(i915, PIPE_CSC_OUTPUT_PREOFF_LO(pipe));
360
+
csc->preoff[0] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_PREOFF_HI(pipe));
361
+
csc->preoff[1] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_PREOFF_ME(pipe));
362
+
csc->preoff[2] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_PREOFF_LO(pipe));
363
363
364
-
tmp = intel_de_read_fw(i915, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe));
364
+
tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe));
365
365
csc->coeff[0] = tmp >> 16;
366
366
csc->coeff[1] = tmp & 0xffff;
367
-
tmp = intel_de_read_fw(i915, PIPE_CSC_OUTPUT_COEFF_BY(pipe));
367
+
tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_BY(pipe));
368
368
csc->coeff[2] = tmp >> 16;
369
369
370
-
tmp = intel_de_read_fw(i915, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe));
370
+
tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe));
371
371
csc->coeff[3] = tmp >> 16;
372
372
csc->coeff[4] = tmp & 0xffff;
373
-
tmp = intel_de_read_fw(i915, PIPE_CSC_OUTPUT_COEFF_BU(pipe));
373
+
tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_BU(pipe));
374
374
csc->coeff[5] = tmp >> 16;
375
375
376
-
tmp = intel_de_read_fw(i915, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe));
376
+
tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe));
377
377
csc->coeff[6] = tmp >> 16;
378
378
csc->coeff[7] = tmp & 0xffff;
379
-
tmp = intel_de_read_fw(i915, PIPE_CSC_OUTPUT_COEFF_BV(pipe));
379
+
tmp = intel_de_read_fw(display, PIPE_CSC_OUTPUT_COEFF_BV(pipe));
380
380
csc->coeff[8] = tmp >> 16;
381
381
382
-
csc->postoff[0] = intel_de_read_fw(i915, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe));
383
-
csc->postoff[1] = intel_de_read_fw(i915, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe));
384
-
csc->postoff[2] = intel_de_read_fw(i915, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe));
382
+
csc->postoff[0] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe));
383
+
csc->postoff[1] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe));
384
+
csc->postoff[2] = intel_de_read_fw(display, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe));
385
385
}
386
386
387
387
static void icl_read_csc(struct intel_crtc_state *crtc_state)
···
402
402
403
403
static bool ilk_limited_range(const struct intel_crtc_state *crtc_state)
404
404
{
405
-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
405
+
struct intel_display *display = to_intel_display(crtc_state);
406
+
struct drm_i915_private *i915 = to_i915(display->drm);
406
407
407
408
/* icl+ have dedicated output CSC */
408
-
if (DISPLAY_VER(i915) >= 11)
409
+
if (DISPLAY_VER(display) >= 11)
409
410
return false;
410
411
411
412
/* pre-hsw have TRANSCONF_COLOR_RANGE_SELECT */
412
-
if (DISPLAY_VER(i915) < 7 || IS_IVYBRIDGE(i915))
413
+
if (DISPLAY_VER(display) < 7 || IS_IVYBRIDGE(i915))
413
414
return false;
414
415
415
416
return crtc_state->limited_color_range;
···
418
417
419
418
static bool ilk_lut_limited_range(const struct intel_crtc_state *crtc_state)
420
419
{
421
-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
420
+
struct intel_display *display = to_intel_display(crtc_state);
422
421
423
422
if (!ilk_limited_range(crtc_state))
424
423
return false;
···
426
425
if (crtc_state->c8_planes)
427
426
return false;
428
427
429
-
if (DISPLAY_VER(i915) == 10)
428
+
if (DISPLAY_VER(display) == 10)
430
429
return crtc_state->hw.gamma_lut;
431
430
else
432
431
return crtc_state->hw.gamma_lut &&
···
441
440
return !ilk_lut_limited_range(crtc_state);
442
441
}
443
442
444
-
static void ilk_csc_copy(struct drm_i915_private *i915,
443
+
static void ilk_csc_copy(struct intel_display *display,
445
444
struct intel_csc_matrix *dst,
446
445
const struct intel_csc_matrix *src)
447
446
{
448
447
*dst = *src;
449
448
450
-
if (DISPLAY_VER(i915) < 7)
449
+
if (DISPLAY_VER(display) < 7)
451
450
memset(dst->postoff, 0, sizeof(dst->postoff));
452
451
}
453
452
···
455
454
struct intel_csc_matrix *csc,
456
455
bool limited_color_range)
457
456
{
458
-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
457
+
struct intel_display *display = to_intel_display(crtc_state);
459
458
const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
460
459
const u64 *input;
461
460
u64 temp[9];
···
463
462
464
463
/* for preoff/postoff */
465
464
if (limited_color_range)
466
-
ilk_csc_copy(i915, csc, &ilk_csc_matrix_limited_range);
465
+
ilk_csc_copy(display, csc, &ilk_csc_matrix_limited_range);
467
466
else
468
-
ilk_csc_copy(i915, csc, &ilk_csc_matrix_identity);
467
+
ilk_csc_copy(display, csc, &ilk_csc_matrix_identity);
469
468
470
469
if (limited_color_range)
471
470
input = ctm_mult_by_limited(temp, ctm->matrix);
···
513
512
514
513
static void ilk_assign_csc(struct intel_crtc_state *crtc_state)
515
514
{
516
-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
515
+
struct intel_display *display = to_intel_display(crtc_state);
516
+
struct drm_i915_private *i915 = to_i915(display->drm);
517
517
bool limited_color_range = ilk_csc_limited_range(crtc_state);
518
518
519
519
if (crtc_state->hw.ctm) {
520
-
drm_WARN_ON(&i915->drm, !crtc_state->csc_enable);
520
+
drm_WARN_ON(display->drm, !crtc_state->csc_enable);
521
521
522
522
ilk_csc_convert_ctm(crtc_state, &crtc_state->csc, limited_color_range);
523
523
} else if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {
524
-
drm_WARN_ON(&i915->drm, !crtc_state->csc_enable);
524
+
drm_WARN_ON(display->drm, !crtc_state->csc_enable);
525
525
526
-
ilk_csc_copy(i915, &crtc_state->csc, &ilk_csc_matrix_rgb_to_ycbcr);
526
+
ilk_csc_copy(display, &crtc_state->csc, &ilk_csc_matrix_rgb_to_ycbcr);
527
527
} else if (limited_color_range) {
528
-
drm_WARN_ON(&i915->drm, !crtc_state->csc_enable);
528
+
drm_WARN_ON(display->drm, !crtc_state->csc_enable);
529
529
530
-
ilk_csc_copy(i915, &crtc_state->csc, &ilk_csc_matrix_limited_range);
530
+
ilk_csc_copy(display, &crtc_state->csc, &ilk_csc_matrix_limited_range);
531
531
} else if (crtc_state->csc_enable) {
532
532
/*
533
533
* On GLK both pipe CSC and degamma LUT are controlled
···
536
534
* LUT is needed but CSC is not we need to load an
537
535
* identity matrix.
538
536
*/
539
-
drm_WARN_ON(&i915->drm, !IS_GEMINILAKE(i915));
537
+
drm_WARN_ON(display->drm, !IS_GEMINILAKE(i915));
540
538
541
-
ilk_csc_copy(i915, &crtc_state->csc, &ilk_csc_matrix_identity);
539
+
ilk_csc_copy(display, &crtc_state->csc, &ilk_csc_matrix_identity);
542
540
} else {
543
541
intel_csc_clear(&crtc_state->csc);
544
542
}
···
555
553
556
554
static void icl_assign_csc(struct intel_crtc_state *crtc_state)
557
555
{
558
-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
556
+
struct intel_display *display = to_intel_display(crtc_state);
559
557
560
558
if (crtc_state->hw.ctm) {
561
-
drm_WARN_ON(&i915->drm, (crtc_state->csc_mode & ICL_CSC_ENABLE) == 0);
559
+
drm_WARN_ON(display->drm, (crtc_state->csc_mode & ICL_CSC_ENABLE) == 0);
562
560
563
561
ilk_csc_convert_ctm(crtc_state, &crtc_state->csc, false);
564
562
} else {
565
-
drm_WARN_ON(&i915->drm, (crtc_state->csc_mode & ICL_CSC_ENABLE) != 0);
563
+
drm_WARN_ON(display->drm, (crtc_state->csc_mode & ICL_CSC_ENABLE) != 0);
566
564
567
565
intel_csc_clear(&crtc_state->csc);
568
566
}
569
567
570
568
if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {
571
-
drm_WARN_ON(&i915->drm, (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE) == 0);
569
+
drm_WARN_ON(display->drm, (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE) == 0);
572
570
573
-
ilk_csc_copy(i915, &crtc_state->output_csc, &ilk_csc_matrix_rgb_to_ycbcr);
571
+
ilk_csc_copy(display, &crtc_state->output_csc, &ilk_csc_matrix_rgb_to_ycbcr);
574
572
} else if (crtc_state->limited_color_range) {
575
-
drm_WARN_ON(&i915->drm, (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE) == 0);
573
+
drm_WARN_ON(display->drm, (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE) == 0);
576
574
577
-
ilk_csc_copy(i915, &crtc_state->output_csc, &ilk_csc_matrix_limited_range);
575
+
ilk_csc_copy(display, &crtc_state->output_csc, &ilk_csc_matrix_limited_range);
578
576
} else {
579
-
drm_WARN_ON(&i915->drm, (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE) != 0);
577
+
drm_WARN_ON(display->drm, (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE) != 0);
580
578
581
579
intel_csc_clear(&crtc_state->output_csc);
582
580
}
···
634
632
static void vlv_load_wgc_csc(struct intel_crtc *crtc,
635
633
const struct intel_csc_matrix *csc)
636
634
{
637
-
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
635
+
struct intel_display *display = to_intel_display(crtc);
638
636
enum pipe pipe = crtc->pipe;
639
637
640
-
intel_de_write_fw(dev_priv, PIPE_WGC_C01_C00(dev_priv, pipe),
638
+
intel_de_write_fw(display, PIPE_WGC_C01_C00(display, pipe),
641
639
csc->coeff[1] << 16 | csc->coeff[0]);
642
-
intel_de_write_fw(dev_priv, PIPE_WGC_C02(dev_priv, pipe),
640
+
intel_de_write_fw(display, PIPE_WGC_C02(display, pipe),
643
641
csc->coeff[2]);
644
642
645
-
intel_de_write_fw(dev_priv, PIPE_WGC_C11_C10(dev_priv, pipe),
643
+
intel_de_write_fw(display, PIPE_WGC_C11_C10(display, pipe),
646
644
csc->coeff[4] << 16 | csc->coeff[3]);
647
-
intel_de_write_fw(dev_priv, PIPE_WGC_C12(dev_priv, pipe),
645
+
intel_de_write_fw(display, PIPE_WGC_C12(display, pipe),
648
646
csc->coeff[5]);
649
647
650
-
intel_de_write_fw(dev_priv, PIPE_WGC_C21_C20(dev_priv, pipe),
648
+
intel_de_write_fw(display, PIPE_WGC_C21_C20(display, pipe),
651
649
csc->coeff[7] << 16 | csc->coeff[6]);
652
-
intel_de_write_fw(dev_priv, PIPE_WGC_C22(dev_priv, pipe),
650
+
intel_de_write_fw(display, PIPE_WGC_C22(display, pipe),
653
651
csc->coeff[8]);
654
652
}
655
653
656
654
static void vlv_read_wgc_csc(struct intel_crtc *crtc,
657
655
struct intel_csc_matrix *csc)
658
656
{
659
-
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
657
+
struct intel_display *display = to_intel_display(crtc);
660
658
enum pipe pipe = crtc->pipe;
661
659
u32 tmp;
662
660
663
-
tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C01_C00(dev_priv, pipe));
661
+
tmp = intel_de_read_fw(display, PIPE_WGC_C01_C00(display, pipe));
664
662
csc->coeff[0] = tmp & 0xffff;
665
663
csc->coeff[1] = tmp >> 16;
666
664
667
-
tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C02(dev_priv, pipe));
665
+
tmp = intel_de_read_fw(display, PIPE_WGC_C02(display, pipe));
668
666
csc->coeff[2] = tmp & 0xffff;
669
667
670
-
tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C11_C10(dev_priv, pipe));
668
+
tmp = intel_de_read_fw(display, PIPE_WGC_C11_C10(display, pipe));
671
669
csc->coeff[3] = tmp & 0xffff;
672
670
csc->coeff[4] = tmp >> 16;
673
671
674
-
tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C12(dev_priv, pipe));
672
+
tmp = intel_de_read_fw(display, PIPE_WGC_C12(display, pipe));
675
673
csc->coeff[5] = tmp & 0xffff;
676
674
677
-
tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C21_C20(dev_priv, pipe));
675
+
tmp = intel_de_read_fw(display, PIPE_WGC_C21_C20(display, pipe));
678
676
csc->coeff[6] = tmp & 0xffff;
679
677
csc->coeff[7] = tmp >> 16;
680
678
681
-
tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C22(dev_priv, pipe));
679
+
tmp = intel_de_read_fw(display, PIPE_WGC_C22(display, pipe));
682
680
csc->coeff[8] = tmp & 0xffff;
683
681
}
684
682
···
692
690
693
691
static void vlv_assign_csc(struct intel_crtc_state *crtc_state)
694
692
{
695
-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
693
+
struct intel_display *display = to_intel_display(crtc_state);
696
694
697
695
if (crtc_state->hw.ctm) {
698
-
drm_WARN_ON(&i915->drm, !crtc_state->wgc_enable);
696
+
drm_WARN_ON(display->drm, !crtc_state->wgc_enable);
699
697
700
698
vlv_wgc_csc_convert_ctm(crtc_state, &crtc_state->csc);
701
699
} else {
702
-
drm_WARN_ON(&i915->drm, crtc_state->wgc_enable);
700
+
drm_WARN_ON(display->drm, crtc_state->wgc_enable);
703
701
704
702
intel_csc_clear(&crtc_state->csc);
705
703
}
···
736
734
static void chv_load_cgm_csc(struct intel_crtc *crtc,
737
735
const struct intel_csc_matrix *csc)
738
736
{
739
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
737
+
struct intel_display *display = to_intel_display(crtc);
740
738
enum pipe pipe = crtc->pipe;
741
739
742
-
intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF01(pipe),
740
+
intel_de_write_fw(display, CGM_PIPE_CSC_COEFF01(pipe),
743
741
csc->coeff[1] << 16 | csc->coeff[0]);
744
-
intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF23(pipe),
742
+
intel_de_write_fw(display, CGM_PIPE_CSC_COEFF23(pipe),
745
743
csc->coeff[3] << 16 | csc->coeff[2]);
746
-
intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF45(pipe),
744
+
intel_de_write_fw(display, CGM_PIPE_CSC_COEFF45(pipe),
747
745
csc->coeff[5] << 16 | csc->coeff[4]);
748
-
intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF67(pipe),
746
+
intel_de_write_fw(display, CGM_PIPE_CSC_COEFF67(pipe),
749
747
csc->coeff[7] << 16 | csc->coeff[6]);
750
-
intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF8(pipe),
748
+
intel_de_write_fw(display, CGM_PIPE_CSC_COEFF8(pipe),
751
749
csc->coeff[8]);
752
750
}
753
751
754
752
static void chv_read_cgm_csc(struct intel_crtc *crtc,
755
753
struct intel_csc_matrix *csc)
756
754
{
757
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
755
+
struct intel_display *display = to_intel_display(crtc);
758
756
enum pipe pipe = crtc->pipe;
759
757
u32 tmp;
760
758
761
-
tmp = intel_de_read_fw(i915, CGM_PIPE_CSC_COEFF01(pipe));
759
+
tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF01(pipe));
762
760
csc->coeff[0] = tmp & 0xffff;
763
761
csc->coeff[1] = tmp >> 16;
764
762
765
-
tmp = intel_de_read_fw(i915, CGM_PIPE_CSC_COEFF23(pipe));
763
+
tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF23(pipe));
766
764
csc->coeff[2] = tmp & 0xffff;
767
765
csc->coeff[3] = tmp >> 16;
768
766
769
-
tmp = intel_de_read_fw(i915, CGM_PIPE_CSC_COEFF45(pipe));
767
+
tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF45(pipe));
770
768
csc->coeff[4] = tmp & 0xffff;
771
769
csc->coeff[5] = tmp >> 16;
772
770
773
-
tmp = intel_de_read_fw(i915, CGM_PIPE_CSC_COEFF67(pipe));
771
+
tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF67(pipe));
774
772
csc->coeff[6] = tmp & 0xffff;
775
773
csc->coeff[7] = tmp >> 16;
776
774
777
-
tmp = intel_de_read_fw(i915, CGM_PIPE_CSC_COEFF8(pipe));
775
+
tmp = intel_de_read_fw(display, CGM_PIPE_CSC_COEFF8(pipe));
778
776
csc->coeff[8] = tmp & 0xffff;
779
777
}
780
778
···
788
786
789
787
static void chv_assign_csc(struct intel_crtc_state *crtc_state)
790
788
{
791
-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
789
+
struct intel_display *display = to_intel_display(crtc_state);
792
790
793
-
drm_WARN_ON(&i915->drm, crtc_state->wgc_enable);
791
+
drm_WARN_ON(display->drm, crtc_state->wgc_enable);
794
792
795
793
if (crtc_state->hw.ctm) {
796
-
drm_WARN_ON(&i915->drm, (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) == 0);
794
+
drm_WARN_ON(display->drm, (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) == 0);
797
795
798
796
chv_cgm_csc_convert_ctm(crtc_state, &crtc_state->csc);
799
797
} else {
800
-
drm_WARN_ON(&i915->drm, (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) == 0);
798
+
drm_WARN_ON(display->drm, (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) == 0);
801
799
802
800
crtc_state->csc = chv_cgm_csc_matrix_identity;
803
801
}
···
1021
1019
const struct intel_crtc_state *crtc_state)
1022
1020
{
1023
1021
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1024
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1022
+
struct intel_display *display = to_intel_display(crtc);
1025
1023
1026
1024
/* update TRANSCONF GAMMA_MODE */
1027
1025
ilk_set_pipeconf(crtc_state);
1028
1026
1029
-
intel_de_write_fw(i915, PIPE_CSC_MODE(crtc->pipe),
1027
+
intel_de_write_fw(display, PIPE_CSC_MODE(crtc->pipe),
1030
1028
crtc_state->csc_mode);
1031
1029
}
1032
1030
···
1034
1032
const struct intel_crtc_state *crtc_state)
1035
1033
{
1036
1034
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1037
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1035
+
struct intel_display *display = to_intel_display(crtc);
1038
1036
1039
-
intel_de_write(i915, GAMMA_MODE(crtc->pipe),
1037
+
intel_de_write(display, GAMMA_MODE(crtc->pipe),
1040
1038
crtc_state->gamma_mode);
1041
1039
1042
-
intel_de_write_fw(i915, PIPE_CSC_MODE(crtc->pipe),
1040
+
intel_de_write_fw(display, PIPE_CSC_MODE(crtc->pipe),
1043
1041
crtc_state->csc_mode);
1044
1042
}
1045
1043
1046
1044
static u32 hsw_read_gamma_mode(struct intel_crtc *crtc)
1047
1045
{
1048
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1046
+
struct intel_display *display = to_intel_display(crtc);
1049
1047
1050
-
return intel_de_read(i915, GAMMA_MODE(crtc->pipe));
1048
+
return intel_de_read(display, GAMMA_MODE(crtc->pipe));
1051
1049
}
1052
1050
1053
1051
static u32 ilk_read_csc_mode(struct intel_crtc *crtc)
1054
1052
{
1055
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1053
+
struct intel_display *display = to_intel_display(crtc);
1056
1054
1057
-
return intel_de_read(i915, PIPE_CSC_MODE(crtc->pipe));
1055
+
return intel_de_read(display, PIPE_CSC_MODE(crtc->pipe));
1058
1056
}
1059
1057
1060
1058
static void i9xx_get_config(struct intel_crtc_state *crtc_state)
1061
1059
{
1060
+
struct intel_display *display = to_intel_display(crtc_state);
1062
1061
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1063
1062
struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1064
-
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1065
1063
enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
1066
1064
u32 tmp;
1067
1065
1068
-
tmp = intel_de_read(dev_priv, DSPCNTR(dev_priv, i9xx_plane));
1066
+
tmp = intel_de_read(display, DSPCNTR(display, i9xx_plane));
1069
1067
1070
1068
if (tmp & DISP_PIPE_GAMMA_ENABLE)
1071
1069
crtc_state->gamma_enable = true;
1072
1070
1073
-
if (!HAS_GMCH(dev_priv) && tmp & DISP_PIPE_CSC_ENABLE)
1071
+
if (!HAS_GMCH(display) && tmp & DISP_PIPE_CSC_ENABLE)
1074
1072
crtc_state->csc_enable = true;
1075
1073
}
1076
1074
···
1086
1084
1087
1085
static void skl_get_config(struct intel_crtc_state *crtc_state)
1088
1086
{
1087
+
struct intel_display *display = to_intel_display(crtc_state);
1089
1088
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1090
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1091
1089
u32 tmp;
1092
1090
1093
1091
crtc_state->gamma_mode = hsw_read_gamma_mode(crtc);
1094
1092
crtc_state->csc_mode = ilk_read_csc_mode(crtc);
1095
1093
1096
-
tmp = intel_de_read(i915, SKL_BOTTOM_COLOR(crtc->pipe));
1094
+
tmp = intel_de_read(display, SKL_BOTTOM_COLOR(crtc->pipe));
1097
1095
1098
1096
if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
1099
1097
crtc_state->gamma_enable = true;
···
1105
1103
static void skl_color_commit_arm(struct intel_dsb *dsb,
1106
1104
const struct intel_crtc_state *crtc_state)
1107
1105
{
1106
+
struct intel_display *display = to_intel_display(crtc_state);
1108
1107
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1109
-
struct intel_display *display = to_intel_display(crtc->base.dev);
1110
1108
enum pipe pipe = crtc->pipe;
1111
1109
u32 val = 0;
1112
1110
···
1132
1130
static void icl_color_commit_arm(struct intel_dsb *dsb,
1133
1131
const struct intel_crtc_state *crtc_state)
1134
1132
{
1133
+
struct intel_display *display = to_intel_display(crtc_state);
1135
1134
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1136
-
struct intel_display *display = to_intel_display(crtc->base.dev);
1137
1135
enum pipe pipe = crtc->pipe;
1138
1136
1139
1137
/*
···
1149
1147
1150
1148
static void icl_color_post_update(const struct intel_crtc_state *crtc_state)
1151
1149
{
1150
+
struct intel_display *display = to_intel_display(crtc_state);
1152
1151
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1153
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1154
1152
1155
1153
/*
1156
1154
* Despite Wa_1406463849, ICL CSC is no longer disarmed by
···
1166
1164
*
1167
1165
* TGL+ no longer need this workaround.
1168
1166
*/
1169
-
intel_de_read_fw(i915, PIPE_CSC_PREOFF_HI(crtc->pipe));
1167
+
intel_de_read_fw(display, PIPE_CSC_PREOFF_HI(crtc->pipe));
1170
1168
}
1171
1169
1172
1170
static struct drm_property_blob *
1173
-
create_linear_lut(struct drm_i915_private *i915, int lut_size)
1171
+
create_linear_lut(struct intel_display *display, int lut_size)
1174
1172
{
1175
1173
struct drm_property_blob *blob;
1176
1174
struct drm_color_lut *lut;
1177
1175
int i;
1178
1176
1179
-
blob = drm_property_create_blob(&i915->drm,
1177
+
blob = drm_property_create_blob(display->drm,
1180
1178
sizeof(lut[0]) * lut_size,
1181
1179
NULL);
1182
1180
if (IS_ERR(blob))
···
1204
1202
}
1205
1203
1206
1204
static struct drm_property_blob *
1207
-
create_resized_lut(struct drm_i915_private *i915,
1205
+
create_resized_lut(struct intel_display *display,
1208
1206
const struct drm_property_blob *blob_in, int lut_out_size,
1209
1207
bool limited_color_range)
1210
1208
{
···
1213
1211
const struct drm_color_lut *lut_in;
1214
1212
struct drm_color_lut *lut_out;
1215
1213
1216
-
blob_out = drm_property_create_blob(&i915->drm,
1214
+
blob_out = drm_property_create_blob(display->drm,
1217
1215
sizeof(lut_out[0]) * lut_out_size,
1218
1216
NULL);
1219
1217
if (IS_ERR(blob_out))
···
1241
1239
static void i9xx_load_lut_8(struct intel_crtc *crtc,
1242
1240
const struct drm_property_blob *blob)
1243
1241
{
1244
-
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1242
+
struct intel_display *display = to_intel_display(crtc);
1245
1243
const struct drm_color_lut *lut;
1246
1244
enum pipe pipe = crtc->pipe;
1247
1245
int i;
···
1252
1250
lut = blob->data;
1253
1251
1254
1252
for (i = 0; i < 256; i++)
1255
-
intel_de_write_fw(dev_priv, PALETTE(dev_priv, pipe, i),
1253
+
intel_de_write_fw(display, PALETTE(display, pipe, i),
1256
1254
i9xx_lut_8(&lut[i]));
1257
1255
}
1258
1256
1259
1257
static void i9xx_load_lut_10(struct intel_crtc *crtc,
1260
1258
const struct drm_property_blob *blob)
1261
1259
{
1262
-
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1260
+
struct intel_display *display = to_intel_display(crtc);
1263
1261
const struct drm_color_lut *lut = blob->data;
1264
1262
int i, lut_size = drm_color_lut_size(blob);
1265
1263
enum pipe pipe = crtc->pipe;
1266
1264
1267
1265
for (i = 0; i < lut_size - 1; i++) {
1268
-
intel_de_write_fw(dev_priv,
1269
-
PALETTE(dev_priv, pipe, 2 * i + 0),
1266
+
intel_de_write_fw(display,
1267
+
PALETTE(display, pipe, 2 * i + 0),
1270
1268
i9xx_lut_10_ldw(&lut[i]));
1271
-
intel_de_write_fw(dev_priv,
1272
-
PALETTE(dev_priv, pipe, 2 * i + 1),
1269
+
intel_de_write_fw(display,
1270
+
PALETTE(display, pipe, 2 * i + 1),
1273
1271
i9xx_lut_10_udw(&lut[i]));
1274
1272
}
1275
1273
}
···
1295
1293
static void i965_load_lut_10p6(struct intel_crtc *crtc,
1296
1294
const struct drm_property_blob *blob)
1297
1295
{
1298
-
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1296
+
struct intel_display *display = to_intel_display(crtc);
1299
1297
const struct drm_color_lut *lut = blob->data;
1300
1298
int i, lut_size = drm_color_lut_size(blob);
1301
1299
enum pipe pipe = crtc->pipe;
1302
1300
1303
1301
for (i = 0; i < lut_size - 1; i++) {
1304
-
intel_de_write_fw(dev_priv,
1305
-
PALETTE(dev_priv, pipe, 2 * i + 0),
1302
+
intel_de_write_fw(display,
1303
+
PALETTE(display, pipe, 2 * i + 0),
1306
1304
i965_lut_10p6_ldw(&lut[i]));
1307
-
intel_de_write_fw(dev_priv,
1308
-
PALETTE(dev_priv, pipe, 2 * i + 1),
1305
+
intel_de_write_fw(display,
1306
+
PALETTE(display, pipe, 2 * i + 1),
1309
1307
i965_lut_10p6_udw(&lut[i]));
1310
1308
}
1311
1309
1312
-
intel_de_write_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 0), lut[i].red);
1313
-
intel_de_write_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 1), lut[i].green);
1314
-
intel_de_write_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 2), lut[i].blue);
1310
+
intel_de_write_fw(display, PIPEGCMAX(display, pipe, 0), lut[i].red);
1311
+
intel_de_write_fw(display, PIPEGCMAX(display, pipe, 1), lut[i].green);
1312
+
intel_de_write_fw(display, PIPEGCMAX(display, pipe, 2), lut[i].blue);
1315
1313
}
1316
1314
1317
1315
static void i965_load_luts(const struct intel_crtc_state *crtc_state)
···
1335
1333
static void ilk_lut_write(const struct intel_crtc_state *crtc_state,
1336
1334
i915_reg_t reg, u32 val)
1337
1335
{
1338
-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1336
+
struct intel_display *display = to_intel_display(crtc_state);
1339
1337
1340
1338
if (crtc_state->dsb_color_vblank)
1341
1339
intel_dsb_reg_write(crtc_state->dsb_color_vblank, reg, val);
1342
1340
else
1343
-
intel_de_write_fw(i915, reg, val);
1341
+
intel_de_write_fw(display, reg, val);
1344
1342
}
1345
1343
1346
1344
static void ilk_load_lut_8(const struct intel_crtc_state *crtc_state,
···
1547
1545
}
1548
1546
}
1549
1547
1550
-
static int glk_degamma_lut_size(struct drm_i915_private *i915)
1548
+
static int glk_degamma_lut_size(struct intel_display *display)
1551
1549
{
1552
-
if (DISPLAY_VER(i915) >= 13)
1550
+
if (DISPLAY_VER(display) >= 13)
1553
1551
return 131;
1554
1552
else
1555
1553
return 35;
···
1581
1579
static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state,
1582
1580
const struct drm_property_blob *blob)
1583
1581
{
1582
+
struct intel_display *display = to_intel_display(crtc_state);
1584
1583
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1585
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1586
1584
const struct drm_color_lut *lut = blob->data;
1587
1585
int i, lut_size = drm_color_lut_size(blob);
1588
1586
enum pipe pipe = crtc->pipe;
···
1613
1611
* as compared to just 16 to achieve this.
1614
1612
*/
1615
1613
ilk_lut_write(crtc_state, PRE_CSC_GAMC_DATA(pipe),
1616
-
DISPLAY_VER(i915) >= 14 ?
1614
+
DISPLAY_VER(display) >= 14 ?
1617
1615
mtl_degamma_lut(&lut[i]) : glk_degamma_lut(&lut[i]));
1618
1616
}
1619
1617
1620
1618
/* Clamp values > 1.0. */
1621
-
while (i++ < glk_degamma_lut_size(i915))
1619
+
while (i++ < glk_degamma_lut_size(display))
1622
1620
ilk_lut_write(crtc_state, PRE_CSC_GAMC_DATA(pipe),
1623
-
DISPLAY_VER(i915) >= 14 ?
1621
+
DISPLAY_VER(display) >= 14 ?
1624
1622
1 << 24 : 1 << 16);
1625
1623
1626
1624
ilk_lut_write(crtc_state, PRE_CSC_GAMC_INDEX(pipe), 0);
···
1821
1819
static void chv_load_cgm_degamma(struct intel_crtc *crtc,
1822
1820
const struct drm_property_blob *blob)
1823
1821
{
1824
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1822
+
struct intel_display *display = to_intel_display(crtc);
1825
1823
const struct drm_color_lut *lut = blob->data;
1826
1824
int i, lut_size = drm_color_lut_size(blob);
1827
1825
enum pipe pipe = crtc->pipe;
1828
1826
1829
1827
for (i = 0; i < lut_size; i++) {
1830
-
intel_de_write_fw(i915, CGM_PIPE_DEGAMMA(pipe, i, 0),
1828
+
intel_de_write_fw(display, CGM_PIPE_DEGAMMA(pipe, i, 0),
1831
1829
chv_cgm_degamma_ldw(&lut[i]));
1832
-
intel_de_write_fw(i915, CGM_PIPE_DEGAMMA(pipe, i, 1),
1830
+
intel_de_write_fw(display, CGM_PIPE_DEGAMMA(pipe, i, 1),
1833
1831
chv_cgm_degamma_udw(&lut[i]));
1834
1832
}
1835
1833
}
···
1855
1853
static void chv_load_cgm_gamma(struct intel_crtc *crtc,
1856
1854
const struct drm_property_blob *blob)
1857
1855
{
1858
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1856
+
struct intel_display *display = to_intel_display(crtc);
1859
1857
const struct drm_color_lut *lut = blob->data;
1860
1858
int i, lut_size = drm_color_lut_size(blob);
1861
1859
enum pipe pipe = crtc->pipe;
1862
1860
1863
1861
for (i = 0; i < lut_size; i++) {
1864
-
intel_de_write_fw(i915, CGM_PIPE_GAMMA(pipe, i, 0),
1862
+
intel_de_write_fw(display, CGM_PIPE_GAMMA(pipe, i, 0),
1865
1863
chv_cgm_gamma_ldw(&lut[i]));
1866
-
intel_de_write_fw(i915, CGM_PIPE_GAMMA(pipe, i, 1),
1864
+
intel_de_write_fw(display, CGM_PIPE_GAMMA(pipe, i, 1),
1867
1865
chv_cgm_gamma_udw(&lut[i]));
1868
1866
}
1869
1867
}
1870
1868
1871
1869
static void chv_load_luts(const struct intel_crtc_state *crtc_state)
1872
1870
{
1871
+
struct intel_display *display = to_intel_display(crtc_state);
1873
1872
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1874
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1875
1873
const struct drm_property_blob *pre_csc_lut = crtc_state->pre_csc_lut;
1876
1874
const struct drm_property_blob *post_csc_lut = crtc_state->post_csc_lut;
1877
1875
···
1886
1884
else
1887
1885
i965_load_luts(crtc_state);
1888
1886
1889
-
intel_de_write_fw(i915, CGM_PIPE_MODE(crtc->pipe),
1887
+
intel_de_write_fw(display, CGM_PIPE_MODE(crtc->pipe),
1890
1888
crtc_state->cgm_mode);
1891
1889
}
1892
1890
1893
1891
void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
1894
1892
{
1895
-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1893
+
struct intel_display *display = to_intel_display(crtc_state);
1896
1894
1897
1895
if (crtc_state->dsb_color_vblank)
1898
1896
return;
1899
1897
1900
-
i915->display.funcs.color->load_luts(crtc_state);
1898
+
display->funcs.color->load_luts(crtc_state);
1901
1899
}
1902
1900
1903
1901
void intel_color_commit_noarm(struct intel_dsb *dsb,
1904
1902
const struct intel_crtc_state *crtc_state)
1905
1903
{
1906
-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1904
+
struct intel_display *display = to_intel_display(crtc_state);
1907
1905
1908
-
if (i915->display.funcs.color->color_commit_noarm)
1909
-
i915->display.funcs.color->color_commit_noarm(dsb, crtc_state);
1906
+
if (display->funcs.color->color_commit_noarm)
1907
+
display->funcs.color->color_commit_noarm(dsb, crtc_state);
1910
1908
}
1911
1909
1912
1910
void intel_color_commit_arm(struct intel_dsb *dsb,
1913
1911
const struct intel_crtc_state *crtc_state)
1914
1912
{
1915
-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1913
+
struct intel_display *display = to_intel_display(crtc_state);
1916
1914
1917
-
i915->display.funcs.color->color_commit_arm(dsb, crtc_state);
1915
+
display->funcs.color->color_commit_arm(dsb, crtc_state);
1918
1916
}
1919
1917
1920
1918
void intel_color_post_update(const struct intel_crtc_state *crtc_state)
1921
1919
{
1922
-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1920
+
struct intel_display *display = to_intel_display(crtc_state);
1923
1921
1924
-
if (i915->display.funcs.color->color_post_update)
1925
-
i915->display.funcs.color->color_post_update(crtc_state);
1922
+
if (display->funcs.color->color_post_update)
1923
+
display->funcs.color->color_post_update(crtc_state);
1926
1924
}
1927
1925
1928
1926
void intel_color_modeset(const struct intel_crtc_state *crtc_state)
···
1945
1943
void intel_color_prepare_commit(struct intel_atomic_state *state,
1946
1944
struct intel_crtc *crtc)
1947
1945
{
1948
-
struct drm_i915_private *i915 = to_i915(state->base.dev);
1946
+
struct intel_display *display = to_intel_display(state);
1949
1947
struct intel_crtc_state *crtc_state =
1950
1948
intel_atomic_get_new_crtc_state(state, crtc);
1951
1949
···
1963
1961
if (!crtc_state->dsb_color_vblank)
1964
1962
return;
1965
1963
1966
-
i915->display.funcs.color->load_luts(crtc_state);
1964
+
display->funcs.color->load_luts(crtc_state);
1967
1965
1968
1966
intel_dsb_wait_vblank_delay(state, crtc_state->dsb_color_vblank);
1969
1967
intel_dsb_interrupt(crtc_state->dsb_color_vblank);
···
2032
2030
int intel_color_check(struct intel_atomic_state *state,
2033
2031
struct intel_crtc *crtc)
2034
2032
{
2035
-
struct drm_i915_private *i915 = to_i915(state->base.dev);
2033
+
struct intel_display *display = to_intel_display(state);
2036
2034
const struct intel_crtc_state *old_crtc_state =
2037
2035
intel_atomic_get_old_crtc_state(state, crtc);
2038
2036
struct intel_crtc_state *new_crtc_state =
···
2048
2046
if (!intel_crtc_needs_color_update(new_crtc_state))
2049
2047
return 0;
2050
2048
2051
-
return i915->display.funcs.color->color_check(state, crtc);
2049
+
return display->funcs.color->color_check(state, crtc);
2052
2050
}
2053
2051
2054
2052
void intel_color_get_config(struct intel_crtc_state *crtc_state)
2055
2053
{
2056
-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2054
+
struct intel_display *display = to_intel_display(crtc_state);
2057
2055
2058
-
if (i915->display.funcs.color->get_config)
2059
-
i915->display.funcs.color->get_config(crtc_state);
2056
+
display->funcs.color->get_config(crtc_state);
2060
2057
2061
-
i915->display.funcs.color->read_luts(crtc_state);
2058
+
display->funcs.color->read_luts(crtc_state);
2062
2059
2063
-
if (i915->display.funcs.color->read_csc)
2064
-
i915->display.funcs.color->read_csc(crtc_state);
2060
+
if (display->funcs.color->read_csc)
2061
+
display->funcs.color->read_csc(crtc_state);
2065
2062
}
2066
2063
2067
2064
bool intel_color_lut_equal(const struct intel_crtc_state *crtc_state,
···
2068
2067
const struct drm_property_blob *blob2,
2069
2068
bool is_pre_csc_lut)
2070
2069
{
2071
-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2070
+
struct intel_display *display = to_intel_display(crtc_state);
2072
2071
2073
2072
/*
2074
2073
* FIXME c8_planes readout missing thus
···
2077
2076
if (!is_pre_csc_lut && crtc_state->c8_planes)
2078
2077
return true;
2079
2078
2080
-
return i915->display.funcs.color->lut_equal(crtc_state, blob1, blob2,
2081
-
is_pre_csc_lut);
2079
+
return display->funcs.color->lut_equal(crtc_state, blob1, blob2,
2080
+
is_pre_csc_lut);
2082
2081
}
2083
2082
2084
2083
static bool need_plane_update(struct intel_plane *plane,
2085
2084
const struct intel_crtc_state *crtc_state)
2086
2085
{
2087
-
struct drm_i915_private *i915 = to_i915(plane->base.dev);
2086
+
struct intel_display *display = to_intel_display(plane);
2088
2087
2089
2088
/*
2090
2089
* On pre-SKL the pipe gamma enable and pipe csc enable for
···
2092
2091
* We have to reconfigure that even if the plane is inactive.
2093
2092
*/
2094
2093
return crtc_state->active_planes & BIT(plane->id) ||
2095
-
(DISPLAY_VER(i915) < 9 &&
2096
-
plane->id == PLANE_PRIMARY);
2094
+
(DISPLAY_VER(display) < 9 && plane->id == PLANE_PRIMARY);
2097
2095
}
2098
2096
2099
2097
static int
2100
2098
intel_color_add_affected_planes(struct intel_atomic_state *state,
2101
2099
struct intel_crtc *crtc)
2102
2100
{
2103
-
struct drm_i915_private *i915 = to_i915(state->base.dev);
2101
+
struct intel_display *display = to_intel_display(state);
2104
2102
const struct intel_crtc_state *old_crtc_state =
2105
2103
intel_atomic_get_old_crtc_state(state, crtc);
2106
2104
struct intel_crtc_state *new_crtc_state =
···
2114
2114
new_crtc_state->csc_enable == old_crtc_state->csc_enable)
2115
2115
return 0;
2116
2116
2117
-
for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
2117
+
for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
2118
2118
struct intel_plane_state *plane_state;
2119
2119
2120
2120
if (!need_plane_update(plane, new_crtc_state))
···
2129
2129
new_crtc_state->do_async_flip = false;
2130
2130
2131
2131
/* plane control register changes blocked by CxSR */
2132
-
if (HAS_GMCH(i915))
2132
+
if (HAS_GMCH(display))
2133
2133
new_crtc_state->disable_cxsr = true;
2134
2134
}
2135
2135
···
2138
2138
2139
2139
static u32 intel_gamma_lut_tests(const struct intel_crtc_state *crtc_state)
2140
2140
{
2141
-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2141
+
struct intel_display *display = to_intel_display(crtc_state);
2142
2142
const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
2143
2143
2144
2144
if (lut_is_legacy(gamma_lut))
2145
2145
return 0;
2146
2146
2147
-
return DISPLAY_INFO(i915)->color.gamma_lut_tests;
2147
+
return DISPLAY_INFO(display)->color.gamma_lut_tests;
2148
2148
}
2149
2149
2150
2150
static u32 intel_degamma_lut_tests(const struct intel_crtc_state *crtc_state)
2151
2151
{
2152
-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2152
+
struct intel_display *display = to_intel_display(crtc_state);
2153
2153
2154
-
return DISPLAY_INFO(i915)->color.degamma_lut_tests;
2154
+
return DISPLAY_INFO(display)->color.degamma_lut_tests;
2155
2155
}
2156
2156
2157
2157
static int intel_gamma_lut_size(const struct intel_crtc_state *crtc_state)
2158
2158
{
2159
-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2159
+
struct intel_display *display = to_intel_display(crtc_state);
2160
2160
const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
2161
2161
2162
2162
if (lut_is_legacy(gamma_lut))
2163
2163
return LEGACY_LUT_LENGTH;
2164
2164
2165
-
return DISPLAY_INFO(i915)->color.gamma_lut_size;
2165
+
return DISPLAY_INFO(display)->color.gamma_lut_size;
2166
2166
}
2167
2167
2168
2168
static u32 intel_degamma_lut_size(const struct intel_crtc_state *crtc_state)
2169
2169
{
2170
-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2170
+
struct intel_display *display = to_intel_display(crtc_state);
2171
2171
2172
-
return DISPLAY_INFO(i915)->color.degamma_lut_size;
2172
+
return DISPLAY_INFO(display)->color.degamma_lut_size;
2173
2173
}
2174
2174
2175
-
static int check_lut_size(struct drm_i915_private *i915,
2175
+
static int check_lut_size(struct intel_crtc *crtc, const char *lut_name,
2176
2176
const struct drm_property_blob *lut, int expected)
2177
2177
{
2178
+
struct intel_display *display = to_intel_display(crtc);
2178
2179
int len;
2179
2180
2180
2181
if (!lut)
···
2183
2182
2184
2183
len = drm_color_lut_size(lut);
2185
2184
if (len != expected) {
2186
-
drm_dbg_kms(&i915->drm, "Invalid LUT size; got %d, expected %d\n",
2187
-
len, expected);
2185
+
drm_dbg_kms(display->drm,
2186
+
"[CRTC:%d:%s] Invalid %s LUT size; got %d, expected %d\n",
2187
+
crtc->base.base.id, crtc->base.name, lut_name, len, expected);
2188
2188
return -EINVAL;
2189
2189
}
2190
2190
···
2195
2193
static int _check_luts(const struct intel_crtc_state *crtc_state,
2196
2194
u32 degamma_tests, u32 gamma_tests)
2197
2195
{
2198
-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2196
+
struct intel_display *display = to_intel_display(crtc_state);
2197
+
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2199
2198
const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
2200
2199
const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
2201
2200
int gamma_length, degamma_length;
2202
2201
2203
2202
/* C8 relies on its palette being stored in the legacy LUT */
2204
2203
if (crtc_state->c8_planes && !lut_is_legacy(crtc_state->hw.gamma_lut)) {
2205
-
drm_dbg_kms(&i915->drm,
2206
-
"C8 pixelformat requires the legacy LUT\n");
2204
+
drm_dbg_kms(display->drm,
2205
+
"[CRTC:%d:%s] C8 pixelformat requires the legacy LUT\n",
2206
+
crtc->base.base.id, crtc->base.name);
2207
2207
return -EINVAL;
2208
2208
}
2209
2209
2210
2210
degamma_length = intel_degamma_lut_size(crtc_state);
2211
2211
gamma_length = intel_gamma_lut_size(crtc_state);
2212
2212
2213
-
if (check_lut_size(i915, degamma_lut, degamma_length) ||
2214
-
check_lut_size(i915, gamma_lut, gamma_length))
2213
+
if (check_lut_size(crtc, "degamma", degamma_lut, degamma_length) ||
2214
+
check_lut_size(crtc, "gamma", gamma_lut, gamma_length))
2215
2215
return -EINVAL;
2216
2216
2217
2217
if (drm_color_lut_check(degamma_lut, degamma_tests) ||
···
2245
2241
drm_color_lut_extract(b, 10);
2246
2242
}
2247
2243
2248
-
static int i9xx_check_lut_10(struct drm_i915_private *dev_priv,
2244
+
static int i9xx_check_lut_10(struct intel_crtc *crtc,
2249
2245
const struct drm_property_blob *blob)
2250
2246
{
2247
+
struct intel_display *display = to_intel_display(crtc);
2251
2248
const struct drm_color_lut *lut = blob->data;
2252
2249
int lut_size = drm_color_lut_size(blob);
2253
2250
const struct drm_color_lut *a = &lut[lut_size - 2];
···
2257
2252
if (i9xx_lut_10_diff(b->red, a->red) > 0x7f ||
2258
2253
i9xx_lut_10_diff(b->green, a->green) > 0x7f ||
2259
2254
i9xx_lut_10_diff(b->blue, a->blue) > 0x7f) {
2260
-
drm_dbg_kms(&dev_priv->drm, "Last gamma LUT entry exceeds max slope\n");
2255
+
drm_dbg_kms(display->drm,
2256
+
"[CRTC:%d:%s] Last gamma LUT entry exceeds max slope\n",
2257
+
crtc->base.base.id, crtc->base.name);
2261
2258
return -EINVAL;
2262
2259
}
2263
2260
···
2268
2261
2269
2262
void intel_color_assert_luts(const struct intel_crtc_state *crtc_state)
2270
2263
{
2271
-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2264
+
struct intel_display *display = to_intel_display(crtc_state);
2272
2265
2273
2266
/* make sure {pre,post}_csc_lut were correctly assigned */
2274
-
if (DISPLAY_VER(i915) >= 11 || HAS_GMCH(i915)) {
2275
-
drm_WARN_ON(&i915->drm,
2267
+
if (DISPLAY_VER(display) >= 11 || HAS_GMCH(display)) {
2268
+
drm_WARN_ON(display->drm,
2276
2269
crtc_state->pre_csc_lut != crtc_state->hw.degamma_lut);
2277
-
drm_WARN_ON(&i915->drm,
2270
+
drm_WARN_ON(display->drm,
2278
2271
crtc_state->post_csc_lut != crtc_state->hw.gamma_lut);
2279
-
} else if (DISPLAY_VER(i915) == 10) {
2280
-
drm_WARN_ON(&i915->drm,
2272
+
} else if (DISPLAY_VER(display) == 10) {
2273
+
drm_WARN_ON(display->drm,
2281
2274
crtc_state->post_csc_lut == crtc_state->hw.gamma_lut &&
2282
2275
crtc_state->pre_csc_lut != crtc_state->hw.degamma_lut &&
2283
-
crtc_state->pre_csc_lut != i915->display.color.glk_linear_degamma_lut);
2284
-
drm_WARN_ON(&i915->drm,
2276
+
crtc_state->pre_csc_lut != display->color.glk_linear_degamma_lut);
2277
+
drm_WARN_ON(display->drm,
2285
2278
!ilk_lut_limited_range(crtc_state) &&
2286
2279
crtc_state->post_csc_lut != NULL &&
2287
2280
crtc_state->post_csc_lut != crtc_state->hw.gamma_lut);
2288
2281
} else if (crtc_state->gamma_mode != GAMMA_MODE_MODE_SPLIT) {
2289
-
drm_WARN_ON(&i915->drm,
2282
+
drm_WARN_ON(display->drm,
2290
2283
crtc_state->pre_csc_lut != crtc_state->hw.degamma_lut &&
2291
2284
crtc_state->pre_csc_lut != crtc_state->hw.gamma_lut);
2292
-
drm_WARN_ON(&i915->drm,
2285
+
drm_WARN_ON(display->drm,
2293
2286
!ilk_lut_limited_range(crtc_state) &&
2294
2287
crtc_state->post_csc_lut != crtc_state->hw.degamma_lut &&
2295
2288
crtc_state->post_csc_lut != crtc_state->hw.gamma_lut);
···
2307
2300
static int i9xx_color_check(struct intel_atomic_state *state,
2308
2301
struct intel_crtc *crtc)
2309
2302
{
2310
-
struct drm_i915_private *i915 = to_i915(state->base.dev);
2303
+
struct intel_display *display = to_intel_display(state);
2311
2304
struct intel_crtc_state *crtc_state =
2312
2305
intel_atomic_get_new_crtc_state(state, crtc);
2313
2306
int ret;
···
2322
2315
2323
2316
crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state);
2324
2317
2325
-
if (DISPLAY_VER(i915) < 4 &&
2318
+
if (DISPLAY_VER(display) < 4 &&
2326
2319
crtc_state->gamma_mode == GAMMA_MODE_MODE_10BIT) {
2327
-
ret = i9xx_check_lut_10(i915, crtc_state->hw.gamma_lut);
2320
+
ret = i9xx_check_lut_10(crtc, crtc_state->hw.gamma_lut);
2328
2321
if (ret)
2329
2322
return ret;
2330
2323
}
···
2491
2484
2492
2485
static int ilk_assign_luts(struct intel_crtc_state *crtc_state)
2493
2486
{
2494
-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2487
+
struct intel_display *display = to_intel_display(crtc_state);
2495
2488
2496
2489
if (ilk_lut_limited_range(crtc_state)) {
2497
2490
struct drm_property_blob *gamma_lut;
2498
2491
2499
-
gamma_lut = create_resized_lut(i915, crtc_state->hw.gamma_lut,
2492
+
gamma_lut = create_resized_lut(display, crtc_state->hw.gamma_lut,
2500
2493
drm_color_lut_size(crtc_state->hw.gamma_lut),
2501
2494
true);
2502
2495
if (IS_ERR(gamma_lut))
···
2530
2523
static int ilk_color_check(struct intel_atomic_state *state,
2531
2524
struct intel_crtc *crtc)
2532
2525
{
2533
-
struct drm_i915_private *i915 = to_i915(state->base.dev);
2526
+
struct intel_display *display = to_intel_display(state);
2534
2527
struct intel_crtc_state *crtc_state =
2535
2528
intel_atomic_get_new_crtc_state(state, crtc);
2536
2529
int ret;
···
2540
2533
return ret;
2541
2534
2542
2535
if (crtc_state->hw.degamma_lut && crtc_state->hw.gamma_lut) {
2543
-
drm_dbg_kms(&i915->drm,
2544
-
"Degamma and gamma together are not possible\n");
2536
+
drm_dbg_kms(display->drm,
2537
+
"[CRTC:%d:%s] Degamma and gamma together are not possible\n",
2538
+
crtc->base.base.id, crtc->base.name);
2545
2539
return -EINVAL;
2546
2540
}
2547
2541
2548
2542
if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
2549
2543
crtc_state->hw.ctm) {
2550
-
drm_dbg_kms(&i915->drm,
2551
-
"YCbCr and CTM together are not possible\n");
2544
+
drm_dbg_kms(display->drm,
2545
+
"[CRTC:%d:%s] YCbCr and CTM together are not possible\n",
2546
+
crtc->base.base.id, crtc->base.name);
2552
2547
return -EINVAL;
2553
2548
}
2554
2549
···
2603
2594
2604
2595
static int ivb_assign_luts(struct intel_crtc_state *crtc_state)
2605
2596
{
2606
-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2597
+
struct intel_display *display = to_intel_display(crtc_state);
2607
2598
struct drm_property_blob *degamma_lut, *gamma_lut;
2608
2599
2609
2600
if (crtc_state->gamma_mode != GAMMA_MODE_MODE_SPLIT)
2610
2601
return ilk_assign_luts(crtc_state);
2611
2602
2612
-
drm_WARN_ON(&i915->drm, drm_color_lut_size(crtc_state->hw.degamma_lut) != 1024);
2613
-
drm_WARN_ON(&i915->drm, drm_color_lut_size(crtc_state->hw.gamma_lut) != 1024);
2603
+
drm_WARN_ON(display->drm, drm_color_lut_size(crtc_state->hw.degamma_lut) != 1024);
2604
+
drm_WARN_ON(display->drm, drm_color_lut_size(crtc_state->hw.gamma_lut) != 1024);
2614
2605
2615
-
degamma_lut = create_resized_lut(i915, crtc_state->hw.degamma_lut, 512,
2606
+
degamma_lut = create_resized_lut(display, crtc_state->hw.degamma_lut, 512,
2616
2607
false);
2617
2608
if (IS_ERR(degamma_lut))
2618
2609
return PTR_ERR(degamma_lut);
2619
2610
2620
-
gamma_lut = create_resized_lut(i915, crtc_state->hw.gamma_lut, 512,
2611
+
gamma_lut = create_resized_lut(display, crtc_state->hw.gamma_lut, 512,
2621
2612
ilk_lut_limited_range(crtc_state));
2622
2613
if (IS_ERR(gamma_lut)) {
2623
2614
drm_property_blob_put(degamma_lut);
···
2636
2627
static int ivb_color_check(struct intel_atomic_state *state,
2637
2628
struct intel_crtc *crtc)
2638
2629
{
2639
-
struct drm_i915_private *i915 = to_i915(state->base.dev);
2630
+
struct intel_display *display = to_intel_display(state);
2640
2631
struct intel_crtc_state *crtc_state =
2641
2632
intel_atomic_get_new_crtc_state(state, crtc);
2642
2633
int ret;
···
2646
2637
return ret;
2647
2638
2648
2639
if (crtc_state->c8_planes && crtc_state->hw.degamma_lut) {
2649
-
drm_dbg_kms(&i915->drm,
2650
-
"C8 pixelformat and degamma together are not possible\n");
2640
+
drm_dbg_kms(display->drm,
2641
+
"[CRTC:%d:%s] C8 pixelformat and degamma together are not possible\n",
2642
+
crtc->base.base.id, crtc->base.name);
2651
2643
return -EINVAL;
2652
2644
}
2653
2645
2654
2646
if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
2655
2647
crtc_state->hw.ctm) {
2656
-
drm_dbg_kms(&i915->drm,
2657
-
"YCbCr and CTM together are not possible\n");
2648
+
drm_dbg_kms(display->drm,
2649
+
"[CRTC:%d:%s] YCbCr and CTM together are not possible\n",
2650
+
crtc->base.base.id, crtc->base.name);
2658
2651
return -EINVAL;
2659
2652
}
2660
2653
2661
2654
if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
2662
2655
crtc_state->hw.degamma_lut && crtc_state->hw.gamma_lut) {
2663
-
drm_dbg_kms(&i915->drm,
2664
-
"YCbCr and degamma+gamma together are not possible\n");
2656
+
drm_dbg_kms(display->drm,
2657
+
"[CRTC:%d:%s] YCbCr and degamma+gamma together are not possible\n",
2658
+
crtc->base.base.id, crtc->base.name);
2665
2659
return -EINVAL;
2666
2660
}
2667
2661
···
2709
2697
2710
2698
static int glk_assign_luts(struct intel_crtc_state *crtc_state)
2711
2699
{
2712
-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2700
+
struct intel_display *display = to_intel_display(crtc_state);
2713
2701
2714
2702
if (glk_use_pre_csc_lut_for_gamma(crtc_state)) {
2715
2703
struct drm_property_blob *gamma_lut;
2716
2704
2717
-
gamma_lut = create_resized_lut(i915, crtc_state->hw.gamma_lut,
2718
-
DISPLAY_INFO(i915)->color.degamma_lut_size,
2705
+
gamma_lut = create_resized_lut(display, crtc_state->hw.gamma_lut,
2706
+
DISPLAY_INFO(display)->color.degamma_lut_size,
2719
2707
false);
2720
2708
if (IS_ERR(gamma_lut))
2721
2709
return PTR_ERR(gamma_lut);
···
2731
2719
if (ilk_lut_limited_range(crtc_state)) {
2732
2720
struct drm_property_blob *gamma_lut;
2733
2721
2734
-
gamma_lut = create_resized_lut(i915, crtc_state->hw.gamma_lut,
2722
+
gamma_lut = create_resized_lut(display, crtc_state->hw.gamma_lut,
2735
2723
drm_color_lut_size(crtc_state->hw.gamma_lut),
2736
2724
true);
2737
2725
if (IS_ERR(gamma_lut))
···
2754
2742
*/
2755
2743
if (crtc_state->csc_enable && !crtc_state->pre_csc_lut)
2756
2744
drm_property_replace_blob(&crtc_state->pre_csc_lut,
2757
-
i915->display.color.glk_linear_degamma_lut);
2745
+
display->color.glk_linear_degamma_lut);
2758
2746
2759
2747
return 0;
2760
2748
}
···
2773
2761
static int glk_color_check(struct intel_atomic_state *state,
2774
2762
struct intel_crtc *crtc)
2775
2763
{
2776
-
struct drm_i915_private *i915 = to_i915(state->base.dev);
2764
+
struct intel_display *display = to_intel_display(state);
2777
2765
struct intel_crtc_state *crtc_state =
2778
2766
intel_atomic_get_new_crtc_state(state, crtc);
2779
2767
int ret;
···
2784
2772
2785
2773
if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
2786
2774
crtc_state->hw.ctm) {
2787
-
drm_dbg_kms(&i915->drm,
2788
-
"YCbCr and CTM together are not possible\n");
2775
+
drm_dbg_kms(display->drm,
2776
+
"[CRTC:%d:%s] YCbCr and CTM together are not possible\n",
2777
+
crtc->base.base.id, crtc->base.name);
2789
2778
return -EINVAL;
2790
2779
}
2791
2780
2792
2781
if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB &&
2793
2782
crtc_state->hw.degamma_lut && crtc_state->hw.gamma_lut) {
2794
-
drm_dbg_kms(&i915->drm,
2795
-
"YCbCr and degamma+gamma together are not possible\n");
2783
+
drm_dbg_kms(display->drm,
2784
+
"[CRTC:%d:%s] YCbCr and degamma+gamma together are not possible\n",
2785
+
crtc->base.base.id, crtc->base.name);
2796
2786
return -EINVAL;
2797
2787
}
2798
2788
···
2831
2817
2832
2818
static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state)
2833
2819
{
2834
-
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2835
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2820
+
struct intel_display *display = to_intel_display(crtc_state);
2836
2821
u32 gamma_mode = 0;
2837
2822
2838
2823
if (crtc_state->hw.degamma_lut)
···
2849
2836
* ToDo: Extend to Logarithmic Gamma once the new UAPI
2850
2837
* is accepted and implemented by a userspace consumer
2851
2838
*/
2852
-
else if (DISPLAY_VER(i915) >= 13)
2839
+
else if (DISPLAY_VER(display) >= 13)
2853
2840
gamma_mode |= GAMMA_MODE_MODE_10BIT;
2854
2841
else
2855
2842
gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEG;
···
3230
3217
3231
3218
static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc)
3232
3219
{
3233
-
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3220
+
struct intel_display *display = to_intel_display(crtc);
3234
3221
enum pipe pipe = crtc->pipe;
3235
3222
struct drm_property_blob *blob;
3236
3223
struct drm_color_lut *lut;
3237
3224
int i;
3238
3225
3239
-
blob = drm_property_create_blob(&dev_priv->drm,
3226
+
blob = drm_property_create_blob(display->drm,
3240
3227
sizeof(lut[0]) * LEGACY_LUT_LENGTH,
3241
3228
NULL);
3242
3229
if (IS_ERR(blob))
···
3245
3232
lut = blob->data;
3246
3233
3247
3234
for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
3248
-
u32 val = intel_de_read_fw(dev_priv,
3249
-
PALETTE(dev_priv, pipe, i));
3235
+
u32 val = intel_de_read_fw(display,
3236
+
PALETTE(display, pipe, i));
3250
3237
3251
3238
i9xx_lut_8_pack(&lut[i], val);
3252
3239
}
···
3256
3243
3257
3244
static struct drm_property_blob *i9xx_read_lut_10(struct intel_crtc *crtc)
3258
3245
{
3259
-
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3260
-
u32 lut_size = DISPLAY_INFO(dev_priv)->color.gamma_lut_size;
3246
+
struct intel_display *display = to_intel_display(crtc);
3247
+
u32 lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;
3261
3248
enum pipe pipe = crtc->pipe;
3262
3249
struct drm_property_blob *blob;
3263
3250
struct drm_color_lut *lut;
3264
3251
u32 ldw, udw;
3265
3252
int i;
3266
3253
3267
-
blob = drm_property_create_blob(&dev_priv->drm,
3254
+
blob = drm_property_create_blob(display->drm,
3268
3255
lut_size * sizeof(lut[0]), NULL);
3269
3256
if (IS_ERR(blob))
3270
3257
return NULL;
···
3272
3259
lut = blob->data;
3273
3260
3274
3261
for (i = 0; i < lut_size - 1; i++) {
3275
-
ldw = intel_de_read_fw(dev_priv,
3276
-
PALETTE(dev_priv, pipe, 2 * i + 0));
3277
-
udw = intel_de_read_fw(dev_priv,
3278
-
PALETTE(dev_priv, pipe, 2 * i + 1));
3262
+
ldw = intel_de_read_fw(display,
3263
+
PALETTE(display, pipe, 2 * i + 0));
3264
+
udw = intel_de_read_fw(display,
3265
+
PALETTE(display, pipe, 2 * i + 1));
3279
3266
3280
3267
i9xx_lut_10_pack(&lut[i], ldw, udw);
3281
3268
}
···
3307
3294
3308
3295
static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc)
3309
3296
{
3310
-
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3311
-
int i, lut_size = DISPLAY_INFO(dev_priv)->color.gamma_lut_size;
3297
+
struct intel_display *display = to_intel_display(crtc);
3298
+
int i, lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;
3312
3299
enum pipe pipe = crtc->pipe;
3313
3300
struct drm_property_blob *blob;
3314
3301
struct drm_color_lut *lut;
3315
3302
3316
-
blob = drm_property_create_blob(&dev_priv->drm,
3303
+
blob = drm_property_create_blob(display->drm,
3317
3304
sizeof(lut[0]) * lut_size,
3318
3305
NULL);
3319
3306
if (IS_ERR(blob))
···
3322
3309
lut = blob->data;
3323
3310
3324
3311
for (i = 0; i < lut_size - 1; i++) {
3325
-
u32 ldw = intel_de_read_fw(dev_priv,
3326
-
PALETTE(dev_priv, pipe, 2 * i + 0));
3327
-
u32 udw = intel_de_read_fw(dev_priv,
3328
-
PALETTE(dev_priv, pipe, 2 * i + 1));
3312
+
u32 ldw = intel_de_read_fw(display,
3313
+
PALETTE(display, pipe, 2 * i + 0));
3314
+
u32 udw = intel_de_read_fw(display,
3315
+
PALETTE(display, pipe, 2 * i + 1));
3329
3316
3330
3317
i965_lut_10p6_pack(&lut[i], ldw, udw);
3331
3318
}
3332
3319
3333
-
lut[i].red = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 0)));
3334
-
lut[i].green = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 1)));
3335
-
lut[i].blue = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 2)));
3320
+
lut[i].red = i965_lut_11p6_max_pack(intel_de_read_fw(display, PIPEGCMAX(display, pipe, 0)));
3321
+
lut[i].green = i965_lut_11p6_max_pack(intel_de_read_fw(display, PIPEGCMAX(display, pipe, 1)));
3322
+
lut[i].blue = i965_lut_11p6_max_pack(intel_de_read_fw(display, PIPEGCMAX(display, pipe, 2)));
3336
3323
3337
3324
return blob;
3338
3325
}
···
3359
3346
3360
3347
static struct drm_property_blob *chv_read_cgm_degamma(struct intel_crtc *crtc)
3361
3348
{
3362
-
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3363
-
int i, lut_size = DISPLAY_INFO(dev_priv)->color.degamma_lut_size;
3349
+
struct intel_display *display = to_intel_display(crtc);
3350
+
int i, lut_size = DISPLAY_INFO(display)->color.degamma_lut_size;
3364
3351
enum pipe pipe = crtc->pipe;
3365
3352
struct drm_property_blob *blob;
3366
3353
struct drm_color_lut *lut;
3367
3354
3368
-
blob = drm_property_create_blob(&dev_priv->drm,
3355
+
blob = drm_property_create_blob(display->drm,
3369
3356
sizeof(lut[0]) * lut_size,
3370
3357
NULL);
3371
3358
if (IS_ERR(blob))
···
3374
3361
lut = blob->data;
3375
3362
3376
3363
for (i = 0; i < lut_size; i++) {
3377
-
u32 ldw = intel_de_read_fw(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 0));
3378
-
u32 udw = intel_de_read_fw(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 1));
3364
+
u32 ldw = intel_de_read_fw(display, CGM_PIPE_DEGAMMA(pipe, i, 0));
3365
+
u32 udw = intel_de_read_fw(display, CGM_PIPE_DEGAMMA(pipe, i, 1));
3379
3366
3380
3367
chv_cgm_degamma_pack(&lut[i], ldw, udw);
3381
3368
}
···
3385
3372
3386
3373
static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc)
3387
3374
{
3388
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3389
-
int i, lut_size = DISPLAY_INFO(i915)->color.gamma_lut_size;
3375
+
struct intel_display *display = to_intel_display(crtc);
3376
+
int i, lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;
3390
3377
enum pipe pipe = crtc->pipe;
3391
3378
struct drm_property_blob *blob;
3392
3379
struct drm_color_lut *lut;
3393
3380
3394
-
blob = drm_property_create_blob(&i915->drm,
3381
+
blob = drm_property_create_blob(display->drm,
3395
3382
sizeof(lut[0]) * lut_size,
3396
3383
NULL);
3397
3384
if (IS_ERR(blob))
···
3400
3387
lut = blob->data;
3401
3388
3402
3389
for (i = 0; i < lut_size; i++) {
3403
-
u32 ldw = intel_de_read_fw(i915, CGM_PIPE_GAMMA(pipe, i, 0));
3404
-
u32 udw = intel_de_read_fw(i915, CGM_PIPE_GAMMA(pipe, i, 1));
3390
+
u32 ldw = intel_de_read_fw(display, CGM_PIPE_GAMMA(pipe, i, 0));
3391
+
u32 udw = intel_de_read_fw(display, CGM_PIPE_GAMMA(pipe, i, 1));
3405
3392
3406
3393
chv_cgm_gamma_pack(&lut[i], ldw, udw);
3407
3394
}
···
3411
3398
3412
3399
static void chv_get_config(struct intel_crtc_state *crtc_state)
3413
3400
{
3401
+
struct intel_display *display = to_intel_display(crtc_state);
3414
3402
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3415
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3416
3403
3417
-
crtc_state->cgm_mode = intel_de_read(i915, CGM_PIPE_MODE(crtc->pipe));
3404
+
crtc_state->cgm_mode = intel_de_read(display, CGM_PIPE_MODE(crtc->pipe));
3418
3405
3419
3406
i9xx_get_config(crtc_state);
3420
3407
}
···
3434
3421
3435
3422
static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc)
3436
3423
{
3437
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3424
+
struct intel_display *display = to_intel_display(crtc);
3438
3425
enum pipe pipe = crtc->pipe;
3439
3426
struct drm_property_blob *blob;
3440
3427
struct drm_color_lut *lut;
3441
3428
int i;
3442
3429
3443
-
blob = drm_property_create_blob(&i915->drm,
3430
+
blob = drm_property_create_blob(display->drm,
3444
3431
sizeof(lut[0]) * LEGACY_LUT_LENGTH,
3445
3432
NULL);
3446
3433
if (IS_ERR(blob))
···
3449
3436
lut = blob->data;
3450
3437
3451
3438
for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
3452
-
u32 val = intel_de_read_fw(i915, LGC_PALETTE(pipe, i));
3439
+
u32 val = intel_de_read_fw(display, LGC_PALETTE(pipe, i));
3453
3440
3454
3441
i9xx_lut_8_pack(&lut[i], val);
3455
3442
}
···
3459
3446
3460
3447
static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc)
3461
3448
{
3462
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3463
-
int i, lut_size = DISPLAY_INFO(i915)->color.gamma_lut_size;
3449
+
struct intel_display *display = to_intel_display(crtc);
3450
+
int i, lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;
3464
3451
enum pipe pipe = crtc->pipe;
3465
3452
struct drm_property_blob *blob;
3466
3453
struct drm_color_lut *lut;
3467
3454
3468
-
blob = drm_property_create_blob(&i915->drm,
3455
+
blob = drm_property_create_blob(display->drm,
3469
3456
sizeof(lut[0]) * lut_size,
3470
3457
NULL);
3471
3458
if (IS_ERR(blob))
···
3474
3461
lut = blob->data;
3475
3462
3476
3463
for (i = 0; i < lut_size; i++) {
3477
-
u32 val = intel_de_read_fw(i915, PREC_PALETTE(pipe, i));
3464
+
u32 val = intel_de_read_fw(display, PREC_PALETTE(pipe, i));
3478
3465
3479
3466
ilk_lut_10_pack(&lut[i], val);
3480
3467
}
···
3522
3509
static struct drm_property_blob *ivb_read_lut_10(struct intel_crtc *crtc,
3523
3510
u32 prec_index)
3524
3511
{
3525
-
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3512
+
struct intel_display *display = to_intel_display(crtc);
3526
3513
int i, lut_size = ivb_lut_10_size(prec_index);
3527
3514
enum pipe pipe = crtc->pipe;
3528
3515
struct drm_property_blob *blob;
3529
3516
struct drm_color_lut *lut;
3530
3517
3531
-
blob = drm_property_create_blob(&dev_priv->drm,
3518
+
blob = drm_property_create_blob(display->drm,
3532
3519
sizeof(lut[0]) * lut_size,
3533
3520
NULL);
3534
3521
if (IS_ERR(blob))
···
3539
3526
for (i = 0; i < lut_size; i++) {
3540
3527
u32 val;
3541
3528
3542
-
intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe),
3529
+
intel_de_write_fw(display, PREC_PAL_INDEX(pipe),
3543
3530
prec_index + i);
3544
-
val = intel_de_read_fw(dev_priv, PREC_PAL_DATA(pipe));
3531
+
val = intel_de_read_fw(display, PREC_PAL_DATA(pipe));
3545
3532
3546
3533
ilk_lut_10_pack(&lut[i], val);
3547
3534
}
3548
3535
3549
-
intel_de_write_fw(dev_priv, PREC_PAL_INDEX(pipe),
3536
+
intel_de_write_fw(display, PREC_PAL_INDEX(pipe),
3550
3537
PAL_PREC_INDEX_VALUE(0));
3551
3538
3552
3539
return blob;
···
3587
3574
static struct drm_property_blob *bdw_read_lut_10(struct intel_crtc *crtc,
3588
3575
u32 prec_index)
3589
3576
{
3590
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3577
+
struct intel_display *display = to_intel_display(crtc);
3591
3578
int i, lut_size = ivb_lut_10_size(prec_index);
3592
3579
enum pipe pipe = crtc->pipe;
3593
3580
struct drm_property_blob *blob;
3594
3581
struct drm_color_lut *lut;
3595
3582
3596
-
blob = drm_property_create_blob(&i915->drm,
3583
+
blob = drm_property_create_blob(display->drm,
3597
3584
sizeof(lut[0]) * lut_size,
3598
3585
NULL);
3599
3586
if (IS_ERR(blob))
···
3601
3588
3602
3589
lut = blob->data;
3603
3590
3604
-
intel_de_write_fw(i915, PREC_PAL_INDEX(pipe),
3591
+
intel_de_write_fw(display, PREC_PAL_INDEX(pipe),
3605
3592
prec_index);
3606
-
intel_de_write_fw(i915, PREC_PAL_INDEX(pipe),
3593
+
intel_de_write_fw(display, PREC_PAL_INDEX(pipe),
3607
3594
PAL_PREC_AUTO_INCREMENT |
3608
3595
prec_index);
3609
3596
3610
3597
for (i = 0; i < lut_size; i++) {
3611
-
u32 val = intel_de_read_fw(i915, PREC_PAL_DATA(pipe));
3598
+
u32 val = intel_de_read_fw(display, PREC_PAL_DATA(pipe));
3612
3599
3613
3600
ilk_lut_10_pack(&lut[i], val);
3614
3601
}
3615
3602
3616
-
intel_de_write_fw(i915, PREC_PAL_INDEX(pipe),
3603
+
intel_de_write_fw(display, PREC_PAL_INDEX(pipe),
3617
3604
PAL_PREC_INDEX_VALUE(0));
3618
3605
3619
3606
return blob;
···
3652
3639
3653
3640
static struct drm_property_blob *glk_read_degamma_lut(struct intel_crtc *crtc)
3654
3641
{
3655
-
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3656
-
int i, lut_size = DISPLAY_INFO(dev_priv)->color.degamma_lut_size;
3642
+
struct intel_display *display = to_intel_display(crtc);
3643
+
int i, lut_size = DISPLAY_INFO(display)->color.degamma_lut_size;
3657
3644
enum pipe pipe = crtc->pipe;
3658
3645
struct drm_property_blob *blob;
3659
3646
struct drm_color_lut *lut;
3660
3647
3661
-
blob = drm_property_create_blob(&dev_priv->drm,
3648
+
blob = drm_property_create_blob(display->drm,
3662
3649
sizeof(lut[0]) * lut_size,
3663
3650
NULL);
3664
3651
if (IS_ERR(blob))
···
3671
3658
* ignore the index bits, so we need to reset it to index 0
3672
3659
* separately.
3673
3660
*/
3674
-
intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe),
3661
+
intel_de_write_fw(display, PRE_CSC_GAMC_INDEX(pipe),
3675
3662
PRE_CSC_GAMC_INDEX_VALUE(0));
3676
-
intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe),
3663
+
intel_de_write_fw(display, PRE_CSC_GAMC_INDEX(pipe),
3677
3664
PRE_CSC_GAMC_AUTO_INCREMENT |
3678
3665
PRE_CSC_GAMC_INDEX_VALUE(0));
3679
3666
3680
3667
for (i = 0; i < lut_size; i++) {
3681
-
u32 val = intel_de_read_fw(dev_priv, PRE_CSC_GAMC_DATA(pipe));
3668
+
u32 val = intel_de_read_fw(display, PRE_CSC_GAMC_DATA(pipe));
3682
3669
3683
-
if (DISPLAY_VER(dev_priv) >= 14)
3670
+
if (DISPLAY_VER(display) >= 14)
3684
3671
mtl_degamma_lut_pack(&lut[i], val);
3685
3672
else
3686
3673
glk_degamma_lut_pack(&lut[i], val);
3687
3674
}
3688
3675
3689
-
intel_de_write_fw(dev_priv, PRE_CSC_GAMC_INDEX(pipe),
3676
+
intel_de_write_fw(display, PRE_CSC_GAMC_INDEX(pipe),
3690
3677
PRE_CSC_GAMC_INDEX_VALUE(0));
3691
3678
3692
3679
return blob;
···
3718
3705
static struct drm_property_blob *
3719
3706
icl_read_lut_multi_segment(struct intel_crtc *crtc)
3720
3707
{
3721
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3722
-
int i, lut_size = DISPLAY_INFO(i915)->color.gamma_lut_size;
3708
+
struct intel_display *display = to_intel_display(crtc);
3709
+
int i, lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;
3723
3710
enum pipe pipe = crtc->pipe;
3724
3711
struct drm_property_blob *blob;
3725
3712
struct drm_color_lut *lut;
3726
3713
3727
-
blob = drm_property_create_blob(&i915->drm,
3714
+
blob = drm_property_create_blob(display->drm,
3728
3715
sizeof(lut[0]) * lut_size,
3729
3716
NULL);
3730
3717
if (IS_ERR(blob))
···
3732
3719
3733
3720
lut = blob->data;
3734
3721
3735
-
intel_de_write_fw(i915, PREC_PAL_MULTI_SEG_INDEX(pipe),
3722
+
intel_de_write_fw(display, PREC_PAL_MULTI_SEG_INDEX(pipe),
3736
3723
PAL_PREC_MULTI_SEG_INDEX_VALUE(0));
3737
-
intel_de_write_fw(i915, PREC_PAL_MULTI_SEG_INDEX(pipe),
3724
+
intel_de_write_fw(display, PREC_PAL_MULTI_SEG_INDEX(pipe),
3738
3725
PAL_PREC_MULTI_SEG_AUTO_INCREMENT |
3739
3726
PAL_PREC_MULTI_SEG_INDEX_VALUE(0));
3740
3727
3741
3728
for (i = 0; i < 9; i++) {
3742
-
u32 ldw = intel_de_read_fw(i915, PREC_PAL_MULTI_SEG_DATA(pipe));
3743
-
u32 udw = intel_de_read_fw(i915, PREC_PAL_MULTI_SEG_DATA(pipe));
3729
+
u32 ldw = intel_de_read_fw(display, PREC_PAL_MULTI_SEG_DATA(pipe));
3730
+
u32 udw = intel_de_read_fw(display, PREC_PAL_MULTI_SEG_DATA(pipe));
3744
3731
3745
3732
ilk_lut_12p4_pack(&lut[i], ldw, udw);
3746
3733
}
3747
3734
3748
-
intel_de_write_fw(i915, PREC_PAL_MULTI_SEG_INDEX(pipe),
3735
+
intel_de_write_fw(display, PREC_PAL_MULTI_SEG_INDEX(pipe),
3749
3736
PAL_PREC_MULTI_SEG_INDEX_VALUE(0));
3750
3737
3751
3738
/*
···
3912
3899
3913
3900
void intel_color_crtc_init(struct intel_crtc *crtc)
3914
3901
{
3915
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3902
+
struct intel_display *display = to_intel_display(crtc);
3916
3903
int degamma_lut_size, gamma_lut_size;
3917
3904
bool has_ctm;
3918
3905
3919
3906
drm_mode_crtc_set_gamma_size(&crtc->base, 256);
3920
3907
3921
-
gamma_lut_size = DISPLAY_INFO(i915)->color.gamma_lut_size;
3922
-
degamma_lut_size = DISPLAY_INFO(i915)->color.degamma_lut_size;
3923
-
has_ctm = DISPLAY_VER(i915) >= 5;
3908
+
gamma_lut_size = DISPLAY_INFO(display)->color.gamma_lut_size;
3909
+
degamma_lut_size = DISPLAY_INFO(display)->color.degamma_lut_size;
3910
+
has_ctm = DISPLAY_VER(display) >= 5;
3924
3911
3925
3912
/*
3926
3913
* "DPALETTE_A: NOTE: The 8-bit (non-10-bit) mode is the
···
3930
3917
* Confirmed on alv,cst,pnv. Mobile gen2 parts (alm,mgm)
3931
3918
* are confirmed not to suffer from this restriction.
3932
3919
*/
3933
-
if (DISPLAY_VER(i915) == 3 && crtc->pipe == PIPE_A)
3920
+
if (DISPLAY_VER(display) == 3 && crtc->pipe == PIPE_A)
3934
3921
gamma_lut_size = 256;
3935
3922
3936
3923
drm_crtc_enable_color_mgmt(&crtc->base, degamma_lut_size,
3937
3924
has_ctm, gamma_lut_size);
3938
3925
}
3939
3926
3940
-
int intel_color_init(struct drm_i915_private *i915)
3927
+
int intel_color_init(struct intel_display *display)
3941
3928
{
3942
3929
struct drm_property_blob *blob;
3943
3930
3944
-
if (DISPLAY_VER(i915) != 10)
3931
+
if (DISPLAY_VER(display) != 10)
3945
3932
return 0;
3946
3933
3947
-
blob = create_linear_lut(i915,
3948
-
DISPLAY_INFO(i915)->color.degamma_lut_size);
3934
+
blob = create_linear_lut(display,
3935
+
DISPLAY_INFO(display)->color.degamma_lut_size);
3949
3936
if (IS_ERR(blob))
3950
3937
return PTR_ERR(blob);
3951
3938
3952
-
i915->display.color.glk_linear_degamma_lut = blob;
3939
+
display->color.glk_linear_degamma_lut = blob;
3953
3940
3954
3941
return 0;
3955
3942
}
3956
3943
3957
-
void intel_color_init_hooks(struct drm_i915_private *i915)
3944
+
void intel_color_init_hooks(struct intel_display *display)
3958
3945
{
3959
-
if (HAS_GMCH(i915)) {
3946
+
struct drm_i915_private *i915 = to_i915(display->drm);
3947
+
3948
+
if (HAS_GMCH(display)) {
3960
3949
if (IS_CHERRYVIEW(i915))
3961
-
i915->display.funcs.color = &chv_color_funcs;
3950
+
display->funcs.color = &chv_color_funcs;
3962
3951
else if (IS_VALLEYVIEW(i915))
3963
-
i915->display.funcs.color = &vlv_color_funcs;
3964
-
else if (DISPLAY_VER(i915) >= 4)
3965
-
i915->display.funcs.color = &i965_color_funcs;
3952
+
display->funcs.color = &vlv_color_funcs;
3953
+
else if (DISPLAY_VER(display) >= 4)
3954
+
display->funcs.color = &i965_color_funcs;
3966
3955
else
3967
-
i915->display.funcs.color = &i9xx_color_funcs;
3956
+
display->funcs.color = &i9xx_color_funcs;
3968
3957
} else {
3969
-
if (DISPLAY_VER(i915) >= 12)
3970
-
i915->display.funcs.color = &tgl_color_funcs;
3971
-
else if (DISPLAY_VER(i915) == 11)
3972
-
i915->display.funcs.color = &icl_color_funcs;
3973
-
else if (DISPLAY_VER(i915) == 10)
3974
-
i915->display.funcs.color = &glk_color_funcs;
3975
-
else if (DISPLAY_VER(i915) == 9)
3976
-
i915->display.funcs.color = &skl_color_funcs;
3977
-
else if (DISPLAY_VER(i915) == 8)
3978
-
i915->display.funcs.color = &bdw_color_funcs;
3958
+
if (DISPLAY_VER(display) >= 12)
3959
+
display->funcs.color = &tgl_color_funcs;
3960
+
else if (DISPLAY_VER(display) == 11)
3961
+
display->funcs.color = &icl_color_funcs;
3962
+
else if (DISPLAY_VER(display) == 10)
3963
+
display->funcs.color = &glk_color_funcs;
3964
+
else if (DISPLAY_VER(display) == 9)
3965
+
display->funcs.color = &skl_color_funcs;
3966
+
else if (DISPLAY_VER(display) == 8)
3967
+
display->funcs.color = &bdw_color_funcs;
3979
3968
else if (IS_HASWELL(i915))
3980
-
i915->display.funcs.color = &hsw_color_funcs;
3981
-
else if (DISPLAY_VER(i915) == 7)
3982
-
i915->display.funcs.color = &ivb_color_funcs;
3969
+
display->funcs.color = &hsw_color_funcs;
3970
+
else if (DISPLAY_VER(display) == 7)
3971
+
display->funcs.color = &ivb_color_funcs;
3983
3972
else
3984
-
i915->display.funcs.color = &ilk_color_funcs;
3973
+
display->funcs.color = &ilk_color_funcs;
3985
3974
}
3986
3975
}
+3
-3
drivers/gpu/drm/i915/display/intel_color.h
+3
-3
drivers/gpu/drm/i915/display/intel_color.h
···
11
11
struct intel_atomic_state;
12
12
struct intel_crtc_state;
13
13
struct intel_crtc;
14
+
struct intel_display;
14
15
struct intel_dsb;
15
-
struct drm_i915_private;
16
16
struct drm_property_blob;
17
17
18
-
void intel_color_init_hooks(struct drm_i915_private *i915);
19
-
int intel_color_init(struct drm_i915_private *i915);
18
+
void intel_color_init_hooks(struct intel_display *display);
19
+
int intel_color_init(struct intel_display *display);
20
20
void intel_color_crtc_init(struct intel_crtc *crtc);
21
21
int intel_color_check(struct intel_atomic_state *state,
22
22
struct intel_crtc *crtc);
+113
-100
drivers/gpu/drm/i915/display/intel_crt.c
+113
-100
drivers/gpu/drm/i915/display/intel_crt.c
···
81
81
return intel_encoder_to_crt(intel_attached_encoder(connector));
82
82
}
83
83
84
-
bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
84
+
bool intel_crt_port_enabled(struct intel_display *display,
85
85
i915_reg_t adpa_reg, enum pipe *pipe)
86
86
{
87
+
struct drm_i915_private *dev_priv = to_i915(display->drm);
87
88
u32 val;
88
89
89
-
val = intel_de_read(dev_priv, adpa_reg);
90
+
val = intel_de_read(display, adpa_reg);
90
91
91
92
/* asserts want to know the pipe even if the port is disabled */
92
93
if (HAS_PCH_CPT(dev_priv))
···
101
100
static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
102
101
enum pipe *pipe)
103
102
{
103
+
struct intel_display *display = to_intel_display(encoder);
104
104
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
105
105
struct intel_crt *crt = intel_encoder_to_crt(encoder);
106
106
intel_wakeref_t wakeref;
···
112
110
if (!wakeref)
113
111
return false;
114
112
115
-
ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
113
+
ret = intel_crt_port_enabled(display, crt->adpa_reg, pipe);
116
114
117
115
intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
118
116
···
121
119
122
120
static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
123
121
{
124
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
122
+
struct intel_display *display = to_intel_display(encoder);
125
123
struct intel_crt *crt = intel_encoder_to_crt(encoder);
126
124
u32 tmp, flags = 0;
127
125
128
-
tmp = intel_de_read(dev_priv, crt->adpa_reg);
126
+
tmp = intel_de_read(display, crt->adpa_reg);
129
127
130
128
if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
131
129
flags |= DRM_MODE_FLAG_PHSYNC;
···
170
168
const struct intel_crtc_state *crtc_state,
171
169
int mode)
172
170
{
171
+
struct intel_display *display = to_intel_display(encoder);
173
172
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
174
173
struct intel_crt *crt = intel_encoder_to_crt(encoder);
175
174
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
176
175
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
177
176
u32 adpa;
178
177
179
-
if (DISPLAY_VER(dev_priv) >= 5)
178
+
if (DISPLAY_VER(display) >= 5)
180
179
adpa = ADPA_HOTPLUG_BITS;
181
180
else
182
181
adpa = 0;
···
196
193
adpa |= ADPA_PIPE_SEL(crtc->pipe);
197
194
198
195
if (!HAS_PCH_SPLIT(dev_priv))
199
-
intel_de_write(dev_priv, BCLRPAT(dev_priv, crtc->pipe), 0);
196
+
intel_de_write(display, BCLRPAT(display, crtc->pipe), 0);
200
197
201
198
switch (mode) {
202
199
case DRM_MODE_DPMS_ON:
···
213
210
break;
214
211
}
215
212
216
-
intel_de_write(dev_priv, crt->adpa_reg, adpa);
213
+
intel_de_write(display, crt->adpa_reg, adpa);
217
214
}
218
215
219
216
static void intel_disable_crt(struct intel_atomic_state *state,
···
244
241
const struct intel_crtc_state *old_crtc_state,
245
242
const struct drm_connector_state *old_conn_state)
246
243
{
244
+
struct intel_display *display = to_intel_display(state);
247
245
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
248
246
249
-
drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
247
+
drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder);
250
248
251
249
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
252
250
}
···
257
253
const struct intel_crtc_state *old_crtc_state,
258
254
const struct drm_connector_state *old_conn_state)
259
255
{
256
+
struct intel_display *display = to_intel_display(state);
260
257
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
261
258
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
262
259
···
277
272
278
273
hsw_fdi_disable(encoder);
279
274
280
-
drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
275
+
drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder);
281
276
282
277
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
283
278
}
···
287
282
const struct intel_crtc_state *crtc_state,
288
283
const struct drm_connector_state *conn_state)
289
284
{
285
+
struct intel_display *display = to_intel_display(state);
290
286
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
291
287
292
-
drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
288
+
drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
293
289
294
290
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
295
291
}
···
300
294
const struct intel_crtc_state *crtc_state,
301
295
const struct drm_connector_state *conn_state)
302
296
{
297
+
struct intel_display *display = to_intel_display(state);
303
298
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
304
299
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
305
300
enum pipe pipe = crtc->pipe;
306
301
307
-
drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
302
+
drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
308
303
309
304
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
310
305
···
319
312
const struct intel_crtc_state *crtc_state,
320
313
const struct drm_connector_state *conn_state)
321
314
{
315
+
struct intel_display *display = to_intel_display(state);
322
316
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
323
317
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
324
318
enum pipe pipe = crtc->pipe;
325
319
326
-
drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
320
+
drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
327
321
328
322
intel_ddi_enable_transcoder_func(encoder, crtc_state);
329
323
···
354
346
intel_crt_mode_valid(struct drm_connector *connector,
355
347
struct drm_display_mode *mode)
356
348
{
349
+
struct intel_display *display = to_intel_display(connector->dev);
357
350
struct drm_device *dev = connector->dev;
358
351
struct drm_i915_private *dev_priv = to_i915(dev);
359
-
int max_dotclk = dev_priv->display.cdclk.max_dotclk_freq;
352
+
int max_dotclk = display->cdclk.max_dotclk_freq;
360
353
enum drm_mode_status status;
361
354
int max_clock;
362
355
···
376
367
* DAC limit supposedly 355 MHz.
377
368
*/
378
369
max_clock = 270000;
379
-
else if (IS_DISPLAY_VER(dev_priv, 3, 4))
370
+
else if (IS_DISPLAY_VER(display, 3, 4))
380
371
max_clock = 400000;
381
372
else
382
373
max_clock = 350000;
···
437
428
struct intel_crtc_state *pipe_config,
438
429
struct drm_connector_state *conn_state)
439
430
{
431
+
struct intel_display *display = to_intel_display(encoder);
440
432
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
441
433
struct drm_display_mode *adjusted_mode =
442
434
&pipe_config->hw.adjusted_mode;
···
460
450
if (HAS_PCH_LPT(dev_priv)) {
461
451
/* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */
462
452
if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
463
-
drm_dbg_kms(&dev_priv->drm,
453
+
drm_dbg_kms(display->drm,
464
454
"LPT only supports 24bpp\n");
465
455
return -EINVAL;
466
456
}
···
480
470
481
471
static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
482
472
{
473
+
struct intel_display *display = to_intel_display(connector->dev);
483
474
struct drm_device *dev = connector->dev;
484
475
struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
485
476
struct drm_i915_private *dev_priv = to_i915(dev);
···
494
483
495
484
crt->force_hotplug_required = false;
496
485
497
-
save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
498
-
drm_dbg_kms(&dev_priv->drm,
486
+
save_adpa = adpa = intel_de_read(display, crt->adpa_reg);
487
+
drm_dbg_kms(display->drm,
499
488
"trigger hotplug detect cycle: adpa=0x%x\n", adpa);
500
489
501
490
adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
502
491
if (turn_off_dac)
503
492
adpa &= ~ADPA_DAC_ENABLE;
504
493
505
-
intel_de_write(dev_priv, crt->adpa_reg, adpa);
494
+
intel_de_write(display, crt->adpa_reg, adpa);
506
495
507
-
if (intel_de_wait_for_clear(dev_priv,
496
+
if (intel_de_wait_for_clear(display,
508
497
crt->adpa_reg,
509
498
ADPA_CRT_HOTPLUG_FORCE_TRIGGER,
510
499
1000))
511
-
drm_dbg_kms(&dev_priv->drm,
500
+
drm_dbg_kms(display->drm,
512
501
"timed out waiting for FORCE_TRIGGER");
513
502
514
503
if (turn_off_dac) {
515
-
intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
516
-
intel_de_posting_read(dev_priv, crt->adpa_reg);
504
+
intel_de_write(display, crt->adpa_reg, save_adpa);
505
+
intel_de_posting_read(display, crt->adpa_reg);
517
506
}
518
507
}
519
508
520
509
/* Check the status to see if both blue and green are on now */
521
-
adpa = intel_de_read(dev_priv, crt->adpa_reg);
510
+
adpa = intel_de_read(display, crt->adpa_reg);
522
511
if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
523
512
ret = true;
524
513
else
525
514
ret = false;
526
-
drm_dbg_kms(&dev_priv->drm, "ironlake hotplug adpa=0x%x, result %d\n",
515
+
drm_dbg_kms(display->drm, "ironlake hotplug adpa=0x%x, result %d\n",
527
516
adpa, ret);
528
517
529
518
return ret;
···
531
520
532
521
static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
533
522
{
523
+
struct intel_display *display = to_intel_display(connector->dev);
534
524
struct drm_device *dev = connector->dev;
535
525
struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
536
526
struct drm_i915_private *dev_priv = to_i915(dev);
···
554
542
*/
555
543
reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
556
544
557
-
save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
558
-
drm_dbg_kms(&dev_priv->drm,
545
+
save_adpa = adpa = intel_de_read(display, crt->adpa_reg);
546
+
drm_dbg_kms(display->drm,
559
547
"trigger hotplug detect cycle: adpa=0x%x\n", adpa);
560
548
561
549
adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
562
550
563
-
intel_de_write(dev_priv, crt->adpa_reg, adpa);
551
+
intel_de_write(display, crt->adpa_reg, adpa);
564
552
565
-
if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg,
553
+
if (intel_de_wait_for_clear(display, crt->adpa_reg,
566
554
ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) {
567
-
drm_dbg_kms(&dev_priv->drm,
555
+
drm_dbg_kms(display->drm,
568
556
"timed out waiting for FORCE_TRIGGER");
569
-
intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
557
+
intel_de_write(display, crt->adpa_reg, save_adpa);
570
558
}
571
559
572
560
/* Check the status to see if both blue and green are on now */
573
-
adpa = intel_de_read(dev_priv, crt->adpa_reg);
561
+
adpa = intel_de_read(display, crt->adpa_reg);
574
562
if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
575
563
ret = true;
576
564
else
577
565
ret = false;
578
566
579
-
drm_dbg_kms(&dev_priv->drm,
567
+
drm_dbg_kms(display->drm,
580
568
"valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
581
569
582
570
if (reenable_hpd)
···
587
575
588
576
static bool intel_crt_detect_hotplug(struct drm_connector *connector)
589
577
{
578
+
struct intel_display *display = to_intel_display(connector->dev);
590
579
struct drm_device *dev = connector->dev;
591
580
struct drm_i915_private *dev_priv = to_i915(dev);
592
581
u32 stat;
···
616
603
CRT_HOTPLUG_FORCE_DETECT,
617
604
CRT_HOTPLUG_FORCE_DETECT);
618
605
/* wait for FORCE_DETECT to go off */
619
-
if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN(dev_priv),
606
+
if (intel_de_wait_for_clear(display, PORT_HOTPLUG_EN(display),
620
607
CRT_HOTPLUG_FORCE_DETECT, 1000))
621
-
drm_dbg_kms(&dev_priv->drm,
608
+
drm_dbg_kms(display->drm,
622
609
"timed out waiting for FORCE_DETECT to go off");
623
610
}
624
611
625
-
stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT(dev_priv));
612
+
stat = intel_de_read(display, PORT_HOTPLUG_STAT(display));
626
613
if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
627
614
ret = true;
628
615
629
616
/* clear the interrupt we just generated, if any */
630
-
intel_de_write(dev_priv, PORT_HOTPLUG_STAT(dev_priv),
617
+
intel_de_write(display, PORT_HOTPLUG_STAT(display),
631
618
CRT_HOTPLUG_INT_STATUS);
632
619
633
620
i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
···
673
660
674
661
static bool intel_crt_detect_ddc(struct drm_connector *connector)
675
662
{
676
-
struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
677
-
struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev);
663
+
struct intel_display *display = to_intel_display(connector->dev);
678
664
const struct drm_edid *drm_edid;
679
665
bool ret = false;
680
666
···
686
674
* have to check the EDID input spec of the attached device.
687
675
*/
688
676
if (drm_edid_is_digital(drm_edid)) {
689
-
drm_dbg_kms(&dev_priv->drm,
677
+
drm_dbg_kms(display->drm,
690
678
"CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
691
679
} else {
692
-
drm_dbg_kms(&dev_priv->drm,
680
+
drm_dbg_kms(display->drm,
693
681
"CRT detected via DDC:0x50 [EDID]\n");
694
682
ret = true;
695
683
}
696
684
} else {
697
-
drm_dbg_kms(&dev_priv->drm,
685
+
drm_dbg_kms(display->drm,
698
686
"CRT not detected via DDC:0x50 [no valid EDID found]\n");
699
687
}
700
688
···
707
695
intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
708
696
{
709
697
struct intel_display *display = to_intel_display(&crt->base);
710
-
struct drm_device *dev = crt->base.base.dev;
711
-
struct drm_i915_private *dev_priv = to_i915(dev);
712
698
enum transcoder cpu_transcoder = (enum transcoder)pipe;
713
699
u32 save_bclrpat;
714
700
u32 save_vtotal;
···
717
707
u8 st00;
718
708
enum drm_connector_status status;
719
709
720
-
drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n");
710
+
drm_dbg_kms(display->drm, "starting load-detect on CRT\n");
721
711
722
-
save_bclrpat = intel_de_read(dev_priv,
723
-
BCLRPAT(dev_priv, cpu_transcoder));
724
-
save_vtotal = intel_de_read(dev_priv,
725
-
TRANS_VTOTAL(dev_priv, cpu_transcoder));
726
-
vblank = intel_de_read(dev_priv,
727
-
TRANS_VBLANK(dev_priv, cpu_transcoder));
712
+
save_bclrpat = intel_de_read(display,
713
+
BCLRPAT(display, cpu_transcoder));
714
+
save_vtotal = intel_de_read(display,
715
+
TRANS_VTOTAL(display, cpu_transcoder));
716
+
vblank = intel_de_read(display,
717
+
TRANS_VBLANK(display, cpu_transcoder));
728
718
729
719
vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1;
730
720
vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1;
···
733
723
vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1;
734
724
735
725
/* Set the border color to purple. */
736
-
intel_de_write(dev_priv, BCLRPAT(dev_priv, cpu_transcoder), 0x500050);
726
+
intel_de_write(display, BCLRPAT(display, cpu_transcoder), 0x500050);
737
727
738
-
if (DISPLAY_VER(dev_priv) != 2) {
739
-
u32 transconf = intel_de_read(dev_priv,
740
-
TRANSCONF(dev_priv, cpu_transcoder));
728
+
if (DISPLAY_VER(display) != 2) {
729
+
u32 transconf = intel_de_read(display,
730
+
TRANSCONF(display, cpu_transcoder));
741
731
742
-
intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
732
+
intel_de_write(display, TRANSCONF(display, cpu_transcoder),
743
733
transconf | TRANSCONF_FORCE_BORDER);
744
-
intel_de_posting_read(dev_priv,
745
-
TRANSCONF(dev_priv, cpu_transcoder));
734
+
intel_de_posting_read(display,
735
+
TRANSCONF(display, cpu_transcoder));
746
736
/* Wait for next Vblank to substitue
747
737
* border color for Color info */
748
738
intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe));
749
-
st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE);
739
+
st00 = intel_de_read8(display, _VGA_MSR_WRITE);
750
740
status = ((st00 & (1 << 4)) != 0) ?
751
741
connector_status_connected :
752
742
connector_status_disconnected;
753
743
754
-
intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
744
+
intel_de_write(display, TRANSCONF(display, cpu_transcoder),
755
745
transconf);
756
746
} else {
757
747
bool restore_vblank = false;
···
762
752
* Yes, this will flicker
763
753
*/
764
754
if (vblank_start <= vactive && vblank_end >= vtotal) {
765
-
u32 vsync = intel_de_read(dev_priv,
766
-
TRANS_VSYNC(dev_priv, cpu_transcoder));
755
+
u32 vsync = intel_de_read(display,
756
+
TRANS_VSYNC(display, cpu_transcoder));
767
757
u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1;
768
758
769
759
vblank_start = vsync_start;
770
-
intel_de_write(dev_priv,
771
-
TRANS_VBLANK(dev_priv, cpu_transcoder),
760
+
intel_de_write(display,
761
+
TRANS_VBLANK(display, cpu_transcoder),
772
762
VBLANK_START(vblank_start - 1) |
773
763
VBLANK_END(vblank_end - 1));
774
764
restore_vblank = true;
···
782
772
/*
783
773
* Wait for the border to be displayed
784
774
*/
785
-
while (intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe)) >= vactive)
775
+
while (intel_de_read(display, PIPEDSL(display, pipe)) >= vactive)
786
776
;
787
-
while ((dsl = intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe))) <= vsample)
777
+
while ((dsl = intel_de_read(display, PIPEDSL(display, pipe))) <= vsample)
788
778
;
789
779
/*
790
780
* Watch ST00 for an entire scanline
···
794
784
do {
795
785
count++;
796
786
/* Read the ST00 VGA status register */
797
-
st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE);
787
+
st00 = intel_de_read8(display, _VGA_MSR_WRITE);
798
788
if (st00 & (1 << 4))
799
789
detect++;
800
-
} while ((intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe)) == dsl));
790
+
} while ((intel_de_read(display, PIPEDSL(display, pipe)) == dsl));
801
791
802
792
/* restore vblank if necessary */
803
793
if (restore_vblank)
804
-
intel_de_write(dev_priv,
805
-
TRANS_VBLANK(dev_priv, cpu_transcoder),
794
+
intel_de_write(display,
795
+
TRANS_VBLANK(display, cpu_transcoder),
806
796
vblank);
807
797
/*
808
798
* If more than 3/4 of the scanline detected a monitor,
···
816
806
}
817
807
818
808
/* Restore previous settings */
819
-
intel_de_write(dev_priv, BCLRPAT(dev_priv, cpu_transcoder),
809
+
intel_de_write(display, BCLRPAT(display, cpu_transcoder),
820
810
save_bclrpat);
821
811
822
812
return status;
···
853
843
struct drm_modeset_acquire_ctx *ctx,
854
844
bool force)
855
845
{
846
+
struct intel_display *display = to_intel_display(connector->dev);
856
847
struct drm_i915_private *dev_priv = to_i915(connector->dev);
857
848
struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
858
849
struct intel_encoder *intel_encoder = &crt->base;
···
861
850
intel_wakeref_t wakeref;
862
851
int status;
863
852
864
-
drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s] force=%d\n",
853
+
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] force=%d\n",
865
854
connector->base.id, connector->name,
866
855
force);
867
856
···
871
860
if (!intel_display_driver_check_access(dev_priv))
872
861
return connector->status;
873
862
874
-
if (dev_priv->display.params.load_detect_test) {
863
+
if (display->params.load_detect_test) {
875
864
wakeref = intel_display_power_get(dev_priv,
876
865
intel_encoder->power_domain);
877
866
goto load_detect;
···
884
873
wakeref = intel_display_power_get(dev_priv,
885
874
intel_encoder->power_domain);
886
875
887
-
if (I915_HAS_HOTPLUG(dev_priv)) {
876
+
if (I915_HAS_HOTPLUG(display)) {
888
877
/* We can not rely on the HPD pin always being correctly wired
889
878
* up, for example many KVM do not pass it through, and so
890
879
* only trust an assertion that the monitor is connected.
891
880
*/
892
881
if (intel_crt_detect_hotplug(connector)) {
893
-
drm_dbg_kms(&dev_priv->drm,
882
+
drm_dbg_kms(display->drm,
894
883
"CRT detected via hotplug\n");
895
884
status = connector_status_connected;
896
885
goto out;
897
886
} else
898
-
drm_dbg_kms(&dev_priv->drm,
887
+
drm_dbg_kms(display->drm,
899
888
"CRT not detected via hotplug\n");
900
889
}
901
890
···
908
897
* broken monitor (without edid) to work behind a broken kvm (that fails
909
898
* to have the right resistors for HP detection) needs to fix this up.
910
899
* For now just bail out. */
911
-
if (I915_HAS_HOTPLUG(dev_priv)) {
900
+
if (I915_HAS_HOTPLUG(display)) {
912
901
status = connector_status_disconnected;
913
902
goto out;
914
903
}
···
928
917
} else {
929
918
if (intel_crt_detect_ddc(connector))
930
919
status = connector_status_connected;
931
-
else if (DISPLAY_VER(dev_priv) < 4)
920
+
else if (DISPLAY_VER(display) < 4)
932
921
status = intel_crt_load_detect(crt,
933
922
to_intel_crtc(connector->state->crtc)->pipe);
934
-
else if (dev_priv->display.params.load_detect_test)
923
+
else if (display->params.load_detect_test)
935
924
status = connector_status_disconnected;
936
925
else
937
926
status = connector_status_unknown;
···
946
935
947
936
static int intel_crt_get_modes(struct drm_connector *connector)
948
937
{
938
+
struct intel_display *display = to_intel_display(connector->dev);
949
939
struct drm_device *dev = connector->dev;
950
940
struct drm_i915_private *dev_priv = to_i915(dev);
951
941
struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
···
966
954
goto out;
967
955
968
956
/* Try to probe digital port for output in DVI-I -> VGA mode. */
969
-
ddc = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
957
+
ddc = intel_gmbus_get_adapter(display, GMBUS_PIN_DPB);
970
958
ret = intel_crt_ddc_get_modes(connector, ddc);
971
959
972
960
out:
···
977
965
978
966
void intel_crt_reset(struct drm_encoder *encoder)
979
967
{
980
-
struct drm_i915_private *dev_priv = to_i915(encoder->dev);
968
+
struct intel_display *display = to_intel_display(encoder->dev);
981
969
struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
982
970
983
-
if (DISPLAY_VER(dev_priv) >= 5) {
971
+
if (DISPLAY_VER(display) >= 5) {
984
972
u32 adpa;
985
973
986
-
adpa = intel_de_read(dev_priv, crt->adpa_reg);
974
+
adpa = intel_de_read(display, crt->adpa_reg);
987
975
adpa &= ~ADPA_CRT_HOTPLUG_MASK;
988
976
adpa |= ADPA_HOTPLUG_BITS;
989
-
intel_de_write(dev_priv, crt->adpa_reg, adpa);
990
-
intel_de_posting_read(dev_priv, crt->adpa_reg);
977
+
intel_de_write(display, crt->adpa_reg, adpa);
978
+
intel_de_posting_read(display, crt->adpa_reg);
991
979
992
-
drm_dbg_kms(&dev_priv->drm, "crt adpa set to 0x%x\n", adpa);
980
+
drm_dbg_kms(display->drm, "crt adpa set to 0x%x\n", adpa);
993
981
crt->force_hotplug_required = true;
994
982
}
995
983
···
1019
1007
.destroy = intel_encoder_destroy,
1020
1008
};
1021
1009
1022
-
void intel_crt_init(struct drm_i915_private *dev_priv)
1010
+
void intel_crt_init(struct intel_display *display)
1023
1011
{
1012
+
struct drm_i915_private *dev_priv = to_i915(display->drm);
1024
1013
struct drm_connector *connector;
1025
1014
struct intel_crt *crt;
1026
1015
struct intel_connector *intel_connector;
···
1036
1023
else
1037
1024
adpa_reg = ADPA;
1038
1025
1039
-
adpa = intel_de_read(dev_priv, adpa_reg);
1026
+
adpa = intel_de_read(display, adpa_reg);
1040
1027
if ((adpa & ADPA_DAC_ENABLE) == 0) {
1041
1028
/*
1042
1029
* On some machines (some IVB at least) CRT can be
···
1046
1033
* take. So the only way to tell is attempt to enable
1047
1034
* it and see what happens.
1048
1035
*/
1049
-
intel_de_write(dev_priv, adpa_reg,
1036
+
intel_de_write(display, adpa_reg,
1050
1037
adpa | ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
1051
-
if ((intel_de_read(dev_priv, adpa_reg) & ADPA_DAC_ENABLE) == 0)
1038
+
if ((intel_de_read(display, adpa_reg) & ADPA_DAC_ENABLE) == 0)
1052
1039
return;
1053
-
intel_de_write(dev_priv, adpa_reg, adpa);
1040
+
intel_de_write(display, adpa_reg, adpa);
1054
1041
}
1055
1042
1056
1043
crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
···
1063
1050
return;
1064
1051
}
1065
1052
1066
-
ddc_pin = dev_priv->display.vbt.crt_ddc_pin;
1053
+
ddc_pin = display->vbt.crt_ddc_pin;
1067
1054
1068
1055
connector = &intel_connector->base;
1069
1056
crt->connector = intel_connector;
1070
-
drm_connector_init_with_ddc(&dev_priv->drm, connector,
1057
+
drm_connector_init_with_ddc(display->drm, connector,
1071
1058
&intel_crt_connector_funcs,
1072
1059
DRM_MODE_CONNECTOR_VGA,
1073
-
intel_gmbus_get_adapter(dev_priv, ddc_pin));
1060
+
intel_gmbus_get_adapter(display, ddc_pin));
1074
1061
1075
-
drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
1062
+
drm_encoder_init(display->drm, &crt->base.base, &intel_crt_enc_funcs,
1076
1063
DRM_MODE_ENCODER_DAC, "CRT");
1077
1064
1078
1065
intel_connector_attach_encoder(intel_connector, &crt->base);
···
1084
1071
else
1085
1072
crt->base.pipe_mask = ~0;
1086
1073
1087
-
if (DISPLAY_VER(dev_priv) != 2)
1074
+
if (DISPLAY_VER(display) != 2)
1088
1075
connector->interlace_allowed = true;
1089
1076
1090
1077
crt->adpa_reg = adpa_reg;
1091
1078
1092
1079
crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
1093
1080
1094
-
if (I915_HAS_HOTPLUG(dev_priv) &&
1081
+
if (I915_HAS_HOTPLUG(display) &&
1095
1082
!dmi_check_system(intel_spurious_crt_detect)) {
1096
1083
crt->base.hpd_pin = HPD_CRT;
1097
1084
crt->base.hotplug = intel_encoder_hotplug;
···
1101
1088
}
1102
1089
intel_connector->base.polled = intel_connector->polled;
1103
1090
1104
-
if (HAS_DDI(dev_priv)) {
1091
+
if (HAS_DDI(display)) {
1105
1092
assert_port_valid(dev_priv, PORT_E);
1106
1093
1107
1094
crt->base.port = PORT_E;
···
1145
1132
u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
1146
1133
FDI_RX_LINK_REVERSAL_OVERRIDE;
1147
1134
1148
-
dev_priv->display.fdi.rx_config = intel_de_read(dev_priv,
1149
-
FDI_RX_CTL(PIPE_A)) & fdi_config;
1135
+
display->fdi.rx_config = intel_de_read(display,
1136
+
FDI_RX_CTL(PIPE_A)) & fdi_config;
1150
1137
}
1151
1138
1152
1139
intel_crt_reset(&crt->base.base);
+5
-5
drivers/gpu/drm/i915/display/intel_crt.h
+5
-5
drivers/gpu/drm/i915/display/intel_crt.h
···
10
10
11
11
enum pipe;
12
12
struct drm_encoder;
13
-
struct drm_i915_private;
13
+
struct intel_display;
14
14
15
15
#ifdef I915
16
-
bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
16
+
bool intel_crt_port_enabled(struct intel_display *display,
17
17
i915_reg_t adpa_reg, enum pipe *pipe);
18
-
void intel_crt_init(struct drm_i915_private *dev_priv);
18
+
void intel_crt_init(struct intel_display *display);
19
19
void intel_crt_reset(struct drm_encoder *encoder);
20
20
#else
21
-
static inline bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
21
+
static inline bool intel_crt_port_enabled(struct intel_display *display,
22
22
i915_reg_t adpa_reg, enum pipe *pipe)
23
23
{
24
24
return false;
25
25
}
26
-
static inline void intel_crt_init(struct drm_i915_private *dev_priv)
26
+
static inline void intel_crt_init(struct intel_display *display)
27
27
{
28
28
}
29
29
static inline void intel_crt_reset(struct drm_encoder *encoder)
+4
-4
drivers/gpu/drm/i915/display/intel_crtc.c
+4
-4
drivers/gpu/drm/i915/display/intel_crtc.c
···
36
36
37
37
static void assert_vblank_disabled(struct drm_crtc *crtc)
38
38
{
39
-
struct drm_i915_private *i915 = to_i915(crtc->dev);
39
+
struct intel_display *display = to_intel_display(crtc->dev);
40
40
41
-
if (I915_STATE_WARN(i915, drm_crtc_vblank_get(crtc) == 0,
42
-
"[CRTC:%d:%s] vblank assertion failure (expected off, current on)\n",
43
-
crtc->base.id, crtc->name))
41
+
if (INTEL_DISPLAY_STATE_WARN(display, drm_crtc_vblank_get(crtc) == 0,
42
+
"[CRTC:%d:%s] vblank assertion failure (expected off, current on)\n",
43
+
crtc->base.id, crtc->name))
44
44
drm_crtc_vblank_put(crtc);
45
45
}
46
46
+264
-202
drivers/gpu/drm/i915/display/intel_cx0_phy.c
+264
-202
drivers/gpu/drm/i915/display/intel_cx0_phy.c
···
34
34
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
35
35
enum phy phy = intel_encoder_to_phy(encoder);
36
36
37
+
if (IS_PANTHERLAKE(i915) && phy == PHY_A)
38
+
return true;
39
+
37
40
if ((IS_LUNARLAKE(i915) || IS_METEORLAKE(i915)) && phy < PHY_C)
38
41
return true;
39
42
···
68
65
}
69
66
70
67
static void
71
-
assert_dc_off(struct drm_i915_private *i915)
68
+
assert_dc_off(struct intel_display *display)
72
69
{
70
+
struct drm_i915_private *i915 = to_i915(display->drm);
73
71
bool enabled;
74
72
75
73
enabled = intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF);
76
-
drm_WARN_ON(&i915->drm, !enabled);
74
+
drm_WARN_ON(display->drm, !enabled);
77
75
}
78
76
79
77
static void intel_cx0_program_msgbus_timer(struct intel_encoder *encoder)
80
78
{
79
+
struct intel_display *display = to_intel_display(encoder);
81
80
int lane;
82
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
83
81
84
82
for_each_cx0_lane_in_mask(INTEL_CX0_BOTH_LANES, lane)
85
-
intel_de_rmw(i915,
86
-
XELPDP_PORT_MSGBUS_TIMER(i915, encoder->port, lane),
83
+
intel_de_rmw(display,
84
+
XELPDP_PORT_MSGBUS_TIMER(display, encoder->port, lane),
87
85
XELPDP_PORT_MSGBUS_TIMER_VAL_MASK,
88
86
XELPDP_PORT_MSGBUS_TIMER_VAL);
89
87
}
···
123
119
static void intel_clear_response_ready_flag(struct intel_encoder *encoder,
124
120
int lane)
125
121
{
126
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
122
+
struct intel_display *display = to_intel_display(encoder);
127
123
128
-
intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, encoder->port, lane),
124
+
intel_de_rmw(display,
125
+
XELPDP_PORT_P2M_MSGBUS_STATUS(display, encoder->port, lane),
129
126
0, XELPDP_PORT_P2M_RESPONSE_READY | XELPDP_PORT_P2M_ERROR_SET);
130
127
}
131
128
132
129
static void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane)
133
130
{
134
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
131
+
struct intel_display *display = to_intel_display(encoder);
135
132
enum port port = encoder->port;
136
133
enum phy phy = intel_encoder_to_phy(encoder);
137
134
138
-
intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
135
+
intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
139
136
XELPDP_PORT_M2P_TRANSACTION_RESET);
140
137
141
-
if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
138
+
if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
142
139
XELPDP_PORT_M2P_TRANSACTION_RESET,
143
140
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
144
-
drm_err_once(&i915->drm, "Failed to bring PHY %c to idle.\n", phy_name(phy));
141
+
drm_err_once(display->drm,
142
+
"Failed to bring PHY %c to idle.\n",
143
+
phy_name(phy));
145
144
return;
146
145
}
147
146
···
154
147
static int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
155
148
int command, int lane, u32 *val)
156
149
{
157
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
150
+
struct intel_display *display = to_intel_display(encoder);
158
151
enum port port = encoder->port;
159
152
enum phy phy = intel_encoder_to_phy(encoder);
160
153
161
-
if (intel_de_wait_custom(i915,
162
-
XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane),
154
+
if (intel_de_wait_custom(display,
155
+
XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane),
163
156
XELPDP_PORT_P2M_RESPONSE_READY,
164
157
XELPDP_PORT_P2M_RESPONSE_READY,
165
158
XELPDP_MSGBUS_TIMEOUT_FAST_US,
166
159
XELPDP_MSGBUS_TIMEOUT_SLOW, val)) {
167
-
drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for message ACK. Status: 0x%x\n",
160
+
drm_dbg_kms(display->drm,
161
+
"PHY %c Timeout waiting for message ACK. Status: 0x%x\n",
168
162
phy_name(phy), *val);
169
163
170
-
if (!(intel_de_read(i915, XELPDP_PORT_MSGBUS_TIMER(i915, port, lane)) &
164
+
if (!(intel_de_read(display, XELPDP_PORT_MSGBUS_TIMER(display, port, lane)) &
171
165
XELPDP_PORT_MSGBUS_TIMER_TIMED_OUT))
172
-
drm_dbg_kms(&i915->drm,
166
+
drm_dbg_kms(display->drm,
173
167
"PHY %c Hardware did not detect a timeout\n",
174
168
phy_name(phy));
175
169
···
179
171
}
180
172
181
173
if (*val & XELPDP_PORT_P2M_ERROR_SET) {
182
-
drm_dbg_kms(&i915->drm, "PHY %c Error occurred during %s command. Status: 0x%x\n", phy_name(phy),
174
+
drm_dbg_kms(display->drm,
175
+
"PHY %c Error occurred during %s command. Status: 0x%x\n",
176
+
phy_name(phy),
183
177
command == XELPDP_PORT_P2M_COMMAND_READ_ACK ? "read" : "write", *val);
184
178
intel_cx0_bus_reset(encoder, lane);
185
179
return -EINVAL;
186
180
}
187
181
188
182
if (REG_FIELD_GET(XELPDP_PORT_P2M_COMMAND_TYPE_MASK, *val) != command) {
189
-
drm_dbg_kms(&i915->drm, "PHY %c Not a %s response. MSGBUS Status: 0x%x.\n", phy_name(phy),
183
+
drm_dbg_kms(display->drm,
184
+
"PHY %c Not a %s response. MSGBUS Status: 0x%x.\n",
185
+
phy_name(phy),
190
186
command == XELPDP_PORT_P2M_COMMAND_READ_ACK ? "read" : "write", *val);
191
187
intel_cx0_bus_reset(encoder, lane);
192
188
return -EINVAL;
···
202
190
static int __intel_cx0_read_once(struct intel_encoder *encoder,
203
191
int lane, u16 addr)
204
192
{
205
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
193
+
struct intel_display *display = to_intel_display(encoder);
206
194
enum port port = encoder->port;
207
195
enum phy phy = intel_encoder_to_phy(encoder);
208
196
int ack;
209
197
u32 val;
210
198
211
-
if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
199
+
if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
212
200
XELPDP_PORT_M2P_TRANSACTION_PENDING,
213
201
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
214
-
drm_dbg_kms(&i915->drm,
202
+
drm_dbg_kms(display->drm,
215
203
"PHY %c Timeout waiting for previous transaction to complete. Reset the bus and retry.\n", phy_name(phy));
216
204
intel_cx0_bus_reset(encoder, lane);
217
205
return -ETIMEDOUT;
218
206
}
219
207
220
-
intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
208
+
intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
221
209
XELPDP_PORT_M2P_TRANSACTION_PENDING |
222
210
XELPDP_PORT_M2P_COMMAND_READ |
223
211
XELPDP_PORT_M2P_ADDRESS(addr));
···
233
221
* down and let the message bus to end up
234
222
* in a known state
235
223
*/
236
-
intel_cx0_bus_reset(encoder, lane);
224
+
if (DISPLAY_VER(display) < 30)
225
+
intel_cx0_bus_reset(encoder, lane);
237
226
238
227
return REG_FIELD_GET(XELPDP_PORT_P2M_DATA_MASK, val);
239
228
}
···
242
229
static u8 __intel_cx0_read(struct intel_encoder *encoder,
243
230
int lane, u16 addr)
244
231
{
245
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
232
+
struct intel_display *display = to_intel_display(encoder);
246
233
enum phy phy = intel_encoder_to_phy(encoder);
247
234
int i, status;
248
235
249
-
assert_dc_off(i915);
236
+
assert_dc_off(display);
250
237
251
238
/* 3 tries is assumed to be enough to read successfully */
252
239
for (i = 0; i < 3; i++) {
···
256
243
return status;
257
244
}
258
245
259
-
drm_err_once(&i915->drm, "PHY %c Read %04x failed after %d retries.\n",
246
+
drm_err_once(display->drm,
247
+
"PHY %c Read %04x failed after %d retries.\n",
260
248
phy_name(phy), addr, i);
261
249
262
250
return 0;
···
274
260
static int __intel_cx0_write_once(struct intel_encoder *encoder,
275
261
int lane, u16 addr, u8 data, bool committed)
276
262
{
277
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
263
+
struct intel_display *display = to_intel_display(encoder);
278
264
enum port port = encoder->port;
279
265
enum phy phy = intel_encoder_to_phy(encoder);
280
266
int ack;
281
267
u32 val;
282
268
283
-
if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
269
+
if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
284
270
XELPDP_PORT_M2P_TRANSACTION_PENDING,
285
271
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
286
-
drm_dbg_kms(&i915->drm,
272
+
drm_dbg_kms(display->drm,
287
273
"PHY %c Timeout waiting for previous transaction to complete. Resetting the bus.\n", phy_name(phy));
288
274
intel_cx0_bus_reset(encoder, lane);
289
275
return -ETIMEDOUT;
290
276
}
291
277
292
-
intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
278
+
intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
293
279
XELPDP_PORT_M2P_TRANSACTION_PENDING |
294
280
(committed ? XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED :
295
281
XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED) |
296
282
XELPDP_PORT_M2P_DATA(data) |
297
283
XELPDP_PORT_M2P_ADDRESS(addr));
298
284
299
-
if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
285
+
if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
300
286
XELPDP_PORT_M2P_TRANSACTION_PENDING,
301
287
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
302
-
drm_dbg_kms(&i915->drm,
288
+
drm_dbg_kms(display->drm,
303
289
"PHY %c Timeout waiting for write to complete. Resetting the bus.\n", phy_name(phy));
304
290
intel_cx0_bus_reset(encoder, lane);
305
291
return -ETIMEDOUT;
···
309
295
ack = intel_cx0_wait_for_ack(encoder, XELPDP_PORT_P2M_COMMAND_WRITE_ACK, lane, &val);
310
296
if (ack < 0)
311
297
return ack;
312
-
} else if ((intel_de_read(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane)) &
298
+
} else if ((intel_de_read(display, XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane)) &
313
299
XELPDP_PORT_P2M_ERROR_SET)) {
314
-
drm_dbg_kms(&i915->drm,
300
+
drm_dbg_kms(display->drm,
315
301
"PHY %c Error occurred during write command.\n", phy_name(phy));
316
302
intel_cx0_bus_reset(encoder, lane);
317
303
return -EINVAL;
···
324
310
* down and let the message bus to end up
325
311
* in a known state
326
312
*/
327
-
intel_cx0_bus_reset(encoder, lane);
313
+
if (DISPLAY_VER(display) < 30)
314
+
intel_cx0_bus_reset(encoder, lane);
328
315
329
316
return 0;
330
317
}
···
333
318
static void __intel_cx0_write(struct intel_encoder *encoder,
334
319
int lane, u16 addr, u8 data, bool committed)
335
320
{
336
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
321
+
struct intel_display *display = to_intel_display(encoder);
337
322
enum phy phy = intel_encoder_to_phy(encoder);
338
323
int i, status;
339
324
340
-
assert_dc_off(i915);
325
+
assert_dc_off(display);
341
326
342
327
/* 3 tries is assumed to be enough to write successfully */
343
328
for (i = 0; i < 3; i++) {
···
347
332
return;
348
333
}
349
334
350
-
drm_err_once(&i915->drm,
335
+
drm_err_once(display->drm,
351
336
"PHY %c Write %04x failed after %d retries.\n", phy_name(phy), addr, i);
352
337
}
353
338
···
363
348
static void intel_c20_sram_write(struct intel_encoder *encoder,
364
349
int lane, u16 addr, u16 data)
365
350
{
366
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
351
+
struct intel_display *display = to_intel_display(encoder);
367
352
368
-
assert_dc_off(i915);
353
+
assert_dc_off(display);
369
354
370
355
intel_cx0_write(encoder, lane, PHY_C20_WR_ADDRESS_H, addr >> 8, 0);
371
356
intel_cx0_write(encoder, lane, PHY_C20_WR_ADDRESS_L, addr & 0xff, 0);
···
377
362
static u16 intel_c20_sram_read(struct intel_encoder *encoder,
378
363
int lane, u16 addr)
379
364
{
380
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
365
+
struct intel_display *display = to_intel_display(encoder);
381
366
u16 val;
382
367
383
-
assert_dc_off(i915);
368
+
assert_dc_off(display);
384
369
385
370
intel_cx0_write(encoder, lane, PHY_C20_RD_ADDRESS_H, addr >> 8, 0);
386
371
intel_cx0_write(encoder, lane, PHY_C20_RD_ADDRESS_L, addr & 0xff, 1);
···
444
429
void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
445
430
const struct intel_crtc_state *crtc_state)
446
431
{
447
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
432
+
struct intel_display *display = to_intel_display(encoder);
448
433
const struct intel_ddi_buf_trans *trans;
449
434
u8 owned_lane_mask;
450
435
intel_wakeref_t wakeref;
···
459
444
wakeref = intel_cx0_phy_transaction_begin(encoder);
460
445
461
446
trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
462
-
if (drm_WARN_ON_ONCE(&i915->drm, !trans)) {
447
+
if (drm_WARN_ON_ONCE(display->drm, !trans)) {
463
448
intel_cx0_phy_transaction_end(encoder, wakeref);
464
449
return;
465
450
}
···
1134
1119
&mtl_c20_dp_hbr3,
1135
1120
&mtl_c20_dp_uhbr10,
1136
1121
&xe2hpd_c20_dp_uhbr13_5,
1122
+
NULL,
1123
+
};
1124
+
1125
+
static const struct intel_c20pll_state * const xe3lpd_c20_dp_edp_tables[] = {
1126
+
&mtl_c20_dp_rbr,
1127
+
&xe2hpd_c20_edp_r216,
1128
+
&xe2hpd_c20_edp_r243,
1129
+
&mtl_c20_dp_hbr1,
1130
+
&xe2hpd_c20_edp_r324,
1131
+
&xe2hpd_c20_edp_r432,
1132
+
&mtl_c20_dp_hbr2,
1133
+
&xe2hpd_c20_edp_r675,
1134
+
&mtl_c20_dp_hbr3,
1135
+
&mtl_c20_dp_uhbr10,
1136
+
&xe2hpd_c20_dp_uhbr13_5,
1137
+
&mtl_c20_dp_uhbr20,
1137
1138
NULL,
1138
1139
};
1139
1140
···
2034
2003
static void intel_c10pll_update_pll(struct intel_crtc_state *crtc_state,
2035
2004
struct intel_encoder *encoder)
2036
2005
{
2037
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2006
+
struct intel_display *display = to_intel_display(encoder);
2038
2007
struct intel_cx0pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll;
2039
2008
int i;
2040
2009
2041
2010
if (intel_crtc_has_dp_encoder(crtc_state)) {
2042
-
if (intel_panel_use_ssc(i915)) {
2011
+
if (intel_panel_use_ssc(display)) {
2043
2012
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2044
2013
2045
2014
pll_state->ssc_enabled =
···
2050
2019
if (pll_state->ssc_enabled)
2051
2020
return;
2052
2021
2053
-
drm_WARN_ON(&i915->drm, ARRAY_SIZE(pll_state->c10.pll) < 9);
2022
+
drm_WARN_ON(display->drm, ARRAY_SIZE(pll_state->c10.pll) < 9);
2054
2023
for (i = 4; i < 9; i++)
2055
2024
pll_state->c10.pll[i] = 0;
2056
2025
}
···
2104
2073
intel_cx0_phy_transaction_end(encoder, wakeref);
2105
2074
}
2106
2075
2107
-
static void intel_c10_pll_program(struct drm_i915_private *i915,
2076
+
static void intel_c10_pll_program(struct intel_display *display,
2108
2077
const struct intel_crtc_state *crtc_state,
2109
2078
struct intel_encoder *encoder)
2110
2079
{
···
2137
2106
MB_WRITE_COMMITTED);
2138
2107
}
2139
2108
2140
-
static void intel_c10pll_dump_hw_state(struct drm_i915_private *i915,
2109
+
static void intel_c10pll_dump_hw_state(struct intel_display *display,
2141
2110
const struct intel_c10pll_state *hw_state)
2142
2111
{
2143
2112
bool fracen;
···
2146
2115
unsigned int multiplier, tx_clk_div;
2147
2116
2148
2117
fracen = hw_state->pll[0] & C10_PLL0_FRACEN;
2149
-
drm_dbg_kms(&i915->drm, "c10pll_hw_state: fracen: %s, ",
2118
+
drm_dbg_kms(display->drm, "c10pll_hw_state: fracen: %s, ",
2150
2119
str_yes_no(fracen));
2151
2120
2152
2121
if (fracen) {
2153
2122
frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11];
2154
2123
frac_rem = hw_state->pll[14] << 8 | hw_state->pll[13];
2155
2124
frac_den = hw_state->pll[10] << 8 | hw_state->pll[9];
2156
-
drm_dbg_kms(&i915->drm, "quot: %u, rem: %u, den: %u,\n",
2125
+
drm_dbg_kms(display->drm, "quot: %u, rem: %u, den: %u,\n",
2157
2126
frac_quot, frac_rem, frac_den);
2158
2127
}
2159
2128
2160
2129
multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, hw_state->pll[3]) << 8 |
2161
2130
hw_state->pll[2]) / 2 + 16;
2162
2131
tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, hw_state->pll[15]);
2163
-
drm_dbg_kms(&i915->drm,
2132
+
drm_dbg_kms(display->drm,
2164
2133
"multiplier: %u, tx_clk_div: %u.\n", multiplier, tx_clk_div);
2165
2134
2166
-
drm_dbg_kms(&i915->drm, "c10pll_rawhw_state:");
2167
-
drm_dbg_kms(&i915->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx, hw_state->cmn);
2135
+
drm_dbg_kms(display->drm, "c10pll_rawhw_state:");
2136
+
drm_dbg_kms(display->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx,
2137
+
hw_state->cmn);
2168
2138
2169
2139
BUILD_BUG_ON(ARRAY_SIZE(hw_state->pll) % 4);
2170
2140
for (i = 0; i < ARRAY_SIZE(hw_state->pll); i = i + 4)
2171
-
drm_dbg_kms(&i915->drm, "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n",
2141
+
drm_dbg_kms(display->drm,
2142
+
"pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n",
2172
2143
i, hw_state->pll[i], i + 1, hw_state->pll[i + 1],
2173
2144
i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
2174
2145
}
2175
2146
2176
-
static int intel_c20_compute_hdmi_tmds_pll(u64 pixel_clock, struct intel_c20pll_state *pll_state)
2147
+
static int intel_c20_compute_hdmi_tmds_pll(struct intel_crtc_state *crtc_state)
2177
2148
{
2149
+
struct intel_display *display = to_intel_display(crtc_state);
2150
+
struct intel_c20pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c20;
2178
2151
u64 datarate;
2179
2152
u64 mpll_tx_clk_div;
2180
2153
u64 vco_freq_shift;
···
2187
2152
u64 mpll_multiplier;
2188
2153
u64 mpll_fracn_quot;
2189
2154
u64 mpll_fracn_rem;
2155
+
u16 tx_misc;
2190
2156
u8 mpllb_ana_freq_vco;
2191
2157
u8 mpll_div_multiplier;
2192
2158
2193
-
if (pixel_clock < 25175 || pixel_clock > 600000)
2159
+
if (crtc_state->port_clock < 25175 || crtc_state->port_clock > 600000)
2194
2160
return -EINVAL;
2195
2161
2196
-
datarate = ((u64)pixel_clock * 1000) * 10;
2162
+
datarate = ((u64)crtc_state->port_clock * 1000) * 10;
2197
2163
mpll_tx_clk_div = ilog2(div64_u64((u64)CLOCK_9999MHZ, (u64)datarate));
2198
2164
vco_freq_shift = ilog2(div64_u64((u64)CLOCK_4999MHZ * (u64)256, (u64)datarate));
2199
2165
vco_freq = (datarate << vco_freq_shift) >> 8;
···
2207
2171
mpll_div_multiplier = min_t(u8, div64_u64((vco_freq * 16 + (datarate >> 1)),
2208
2172
datarate), 255);
2209
2173
2174
+
if (DISPLAY_VER(display) >= 20)
2175
+
tx_misc = 0x5;
2176
+
else
2177
+
tx_misc = 0x0;
2178
+
2210
2179
if (vco_freq <= DATARATE_3000000000)
2211
2180
mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_3;
2212
2181
else if (vco_freq <= DATARATE_3500000000)
···
2221
2180
else
2222
2181
mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_0;
2223
2182
2224
-
pll_state->clock = pixel_clock;
2183
+
pll_state->clock = crtc_state->port_clock;
2225
2184
pll_state->tx[0] = 0xbe88;
2226
-
pll_state->tx[1] = 0x9800;
2185
+
pll_state->tx[1] = 0x9800 | C20_PHY_TX_MISC(tx_misc);
2227
2186
pll_state->tx[2] = 0x0000;
2228
2187
pll_state->cmn[0] = 0x0500;
2229
2188
pll_state->cmn[1] = 0x0005;
···
2280
2239
intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state,
2281
2240
struct intel_encoder *encoder)
2282
2241
{
2283
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2242
+
struct intel_display *display = to_intel_display(crtc_state);
2284
2243
2285
2244
if (intel_crtc_has_dp_encoder(crtc_state)) {
2286
-
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2287
-
return xe2hpd_c20_edp_tables;
2245
+
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
2246
+
if (DISPLAY_RUNTIME_INFO(display)->edp_typec_support)
2247
+
return xe3lpd_c20_dp_edp_tables;
2248
+
if (DISPLAY_VERx100(display) == 1401)
2249
+
return xe2hpd_c20_edp_tables;
2250
+
}
2288
2251
2289
-
if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1))
2252
+
if (DISPLAY_VER(display) >= 30)
2253
+
return xe3lpd_c20_dp_edp_tables;
2254
+
else if (DISPLAY_VERx100(display) == 1401)
2290
2255
return xe2hpd_c20_dp_tables;
2291
2256
else
2292
2257
return mtl_c20_dp_tables;
···
2313
2266
2314
2267
/* try computed C20 HDMI tables before using consolidated tables */
2315
2268
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
2316
-
if (intel_c20_compute_hdmi_tmds_pll(crtc_state->port_clock,
2317
-
&crtc_state->dpll_hw_state.cx0pll.c20) == 0)
2269
+
if (intel_c20_compute_hdmi_tmds_pll(crtc_state) == 0)
2318
2270
return 0;
2319
2271
}
2320
2272
···
2393
2347
static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
2394
2348
struct intel_c20pll_state *pll_state)
2395
2349
{
2350
+
struct intel_display *display = to_intel_display(encoder);
2396
2351
bool cntx;
2397
2352
intel_wakeref_t wakeref;
2398
2353
int i;
2399
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2400
2354
2401
2355
wakeref = intel_cx0_phy_transaction_begin(encoder);
2402
2356
···
2408
2362
if (cntx)
2409
2363
pll_state->tx[i] = intel_c20_sram_read(encoder,
2410
2364
INTEL_CX0_LANE0,
2411
-
PHY_C20_B_TX_CNTX_CFG(i915, i));
2365
+
PHY_C20_B_TX_CNTX_CFG(display, i));
2412
2366
else
2413
2367
pll_state->tx[i] = intel_c20_sram_read(encoder,
2414
2368
INTEL_CX0_LANE0,
2415
-
PHY_C20_A_TX_CNTX_CFG(i915, i));
2369
+
PHY_C20_A_TX_CNTX_CFG(display, i));
2416
2370
}
2417
2371
2418
2372
/* Read common configuration */
···
2420
2374
if (cntx)
2421
2375
pll_state->cmn[i] = intel_c20_sram_read(encoder,
2422
2376
INTEL_CX0_LANE0,
2423
-
PHY_C20_B_CMN_CNTX_CFG(i915, i));
2377
+
PHY_C20_B_CMN_CNTX_CFG(display, i));
2424
2378
else
2425
2379
pll_state->cmn[i] = intel_c20_sram_read(encoder,
2426
2380
INTEL_CX0_LANE0,
2427
-
PHY_C20_A_CMN_CNTX_CFG(i915, i));
2381
+
PHY_C20_A_CMN_CNTX_CFG(display, i));
2428
2382
}
2429
2383
2430
2384
if (intel_c20phy_use_mpllb(pll_state)) {
···
2433
2387
if (cntx)
2434
2388
pll_state->mpllb[i] = intel_c20_sram_read(encoder,
2435
2389
INTEL_CX0_LANE0,
2436
-
PHY_C20_B_MPLLB_CNTX_CFG(i915, i));
2390
+
PHY_C20_B_MPLLB_CNTX_CFG(display, i));
2437
2391
else
2438
2392
pll_state->mpllb[i] = intel_c20_sram_read(encoder,
2439
2393
INTEL_CX0_LANE0,
2440
-
PHY_C20_A_MPLLB_CNTX_CFG(i915, i));
2394
+
PHY_C20_A_MPLLB_CNTX_CFG(display, i));
2441
2395
}
2442
2396
} else {
2443
2397
/* MPLLA configuration */
···
2445
2399
if (cntx)
2446
2400
pll_state->mplla[i] = intel_c20_sram_read(encoder,
2447
2401
INTEL_CX0_LANE0,
2448
-
PHY_C20_B_MPLLA_CNTX_CFG(i915, i));
2402
+
PHY_C20_B_MPLLA_CNTX_CFG(display, i));
2449
2403
else
2450
2404
pll_state->mplla[i] = intel_c20_sram_read(encoder,
2451
2405
INTEL_CX0_LANE0,
2452
-
PHY_C20_A_MPLLA_CNTX_CFG(i915, i));
2406
+
PHY_C20_A_MPLLA_CNTX_CFG(display, i));
2453
2407
}
2454
2408
}
2455
2409
···
2458
2412
intel_cx0_phy_transaction_end(encoder, wakeref);
2459
2413
}
2460
2414
2461
-
static void intel_c20pll_dump_hw_state(struct drm_i915_private *i915,
2415
+
static void intel_c20pll_dump_hw_state(struct intel_display *display,
2462
2416
const struct intel_c20pll_state *hw_state)
2463
2417
{
2464
2418
int i;
2465
2419
2466
-
drm_dbg_kms(&i915->drm, "c20pll_hw_state:\n");
2467
-
drm_dbg_kms(&i915->drm, "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",
2420
+
drm_dbg_kms(display->drm, "c20pll_hw_state:\n");
2421
+
drm_dbg_kms(display->drm,
2422
+
"tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",
2468
2423
hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]);
2469
-
drm_dbg_kms(&i915->drm, "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n",
2424
+
drm_dbg_kms(display->drm,
2425
+
"cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n",
2470
2426
hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]);
2471
2427
2472
2428
if (intel_c20phy_use_mpllb(hw_state)) {
2473
2429
for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++)
2474
-
drm_dbg_kms(&i915->drm, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]);
2430
+
drm_dbg_kms(display->drm, "mpllb[%d] = 0x%.4x\n", i,
2431
+
hw_state->mpllb[i]);
2475
2432
} else {
2476
2433
for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++)
2477
-
drm_dbg_kms(&i915->drm, "mplla[%d] = 0x%.4x\n", i, hw_state->mplla[i]);
2434
+
drm_dbg_kms(display->drm, "mplla[%d] = 0x%.4x\n", i,
2435
+
hw_state->mplla[i]);
2478
2436
}
2479
2437
}
2480
2438
2481
-
void intel_cx0pll_dump_hw_state(struct drm_i915_private *i915,
2439
+
void intel_cx0pll_dump_hw_state(struct intel_display *display,
2482
2440
const struct intel_cx0pll_state *hw_state)
2483
2441
{
2484
2442
if (hw_state->use_c10)
2485
-
intel_c10pll_dump_hw_state(i915, &hw_state->c10);
2443
+
intel_c10pll_dump_hw_state(display, &hw_state->c10);
2486
2444
else
2487
-
intel_c20pll_dump_hw_state(i915, &hw_state->c20);
2445
+
intel_c20pll_dump_hw_state(display, &hw_state->c20);
2488
2446
}
2489
2447
2490
2448
static u8 intel_c20_get_dp_rate(u32 clock)
···
2588
2538
return 0;
2589
2539
}
2590
2540
2591
-
static void intel_c20_pll_program(struct drm_i915_private *i915,
2541
+
static void intel_c20_pll_program(struct intel_display *display,
2592
2542
const struct intel_crtc_state *crtc_state,
2593
2543
struct intel_encoder *encoder)
2594
2544
{
···
2621
2571
for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
2622
2572
if (cntx)
2623
2573
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
2624
-
PHY_C20_A_TX_CNTX_CFG(i915, i),
2574
+
PHY_C20_A_TX_CNTX_CFG(display, i),
2625
2575
pll_state->tx[i]);
2626
2576
else
2627
2577
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
2628
-
PHY_C20_B_TX_CNTX_CFG(i915, i),
2578
+
PHY_C20_B_TX_CNTX_CFG(display, i),
2629
2579
pll_state->tx[i]);
2630
2580
}
2631
2581
···
2633
2583
for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {
2634
2584
if (cntx)
2635
2585
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
2636
-
PHY_C20_A_CMN_CNTX_CFG(i915, i),
2586
+
PHY_C20_A_CMN_CNTX_CFG(display, i),
2637
2587
pll_state->cmn[i]);
2638
2588
else
2639
2589
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
2640
-
PHY_C20_B_CMN_CNTX_CFG(i915, i),
2590
+
PHY_C20_B_CMN_CNTX_CFG(display, i),
2641
2591
pll_state->cmn[i]);
2642
2592
}
2643
2593
···
2646
2596
for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
2647
2597
if (cntx)
2648
2598
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
2649
-
PHY_C20_A_MPLLB_CNTX_CFG(i915, i),
2599
+
PHY_C20_A_MPLLB_CNTX_CFG(display, i),
2650
2600
pll_state->mpllb[i]);
2651
2601
else
2652
2602
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
2653
-
PHY_C20_B_MPLLB_CNTX_CFG(i915, i),
2603
+
PHY_C20_B_MPLLB_CNTX_CFG(display, i),
2654
2604
pll_state->mpllb[i]);
2655
2605
}
2656
2606
} else {
2657
2607
for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
2658
2608
if (cntx)
2659
2609
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
2660
-
PHY_C20_A_MPLLA_CNTX_CFG(i915, i),
2610
+
PHY_C20_A_MPLLA_CNTX_CFG(display, i),
2661
2611
pll_state->mplla[i]);
2662
2612
else
2663
2613
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
2664
-
PHY_C20_B_MPLLA_CNTX_CFG(i915, i),
2614
+
PHY_C20_B_MPLLA_CNTX_CFG(display, i),
2665
2615
pll_state->mplla[i]);
2666
2616
}
2667
2617
}
···
2728
2678
const struct intel_crtc_state *crtc_state,
2729
2679
bool lane_reversal)
2730
2680
{
2731
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2681
+
struct intel_display *display = to_intel_display(encoder);
2732
2682
u32 val = 0;
2733
2683
2734
-
intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port),
2684
+
intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port),
2735
2685
XELPDP_PORT_REVERSAL,
2736
2686
lane_reversal ? XELPDP_PORT_REVERSAL : 0);
2737
2687
···
2753
2703
else
2754
2704
val |= crtc_state->dpll_hw_state.cx0pll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
2755
2705
2756
-
intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
2706
+
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
2757
2707
XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
2758
2708
XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_SSC_ENABLE_PLLA |
2759
2709
XELPDP_SSC_ENABLE_PLLB, val);
···
2784
2734
static void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
2785
2735
u8 lane_mask, u8 state)
2786
2736
{
2787
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2737
+
struct intel_display *display = to_intel_display(encoder);
2788
2738
enum port port = encoder->port;
2789
2739
enum phy phy = intel_encoder_to_phy(encoder);
2790
-
i915_reg_t buf_ctl2_reg = XELPDP_PORT_BUF_CTL2(i915, port);
2740
+
i915_reg_t buf_ctl2_reg = XELPDP_PORT_BUF_CTL2(display, port);
2791
2741
int lane;
2792
2742
2793
-
intel_de_rmw(i915, buf_ctl2_reg,
2743
+
intel_de_rmw(display, buf_ctl2_reg,
2794
2744
intel_cx0_get_powerdown_state(INTEL_CX0_BOTH_LANES, XELPDP_LANE_POWERDOWN_NEW_STATE_MASK),
2795
2745
intel_cx0_get_powerdown_state(lane_mask, state));
2796
2746
2797
2747
/* Wait for pending transactions.*/
2798
2748
for_each_cx0_lane_in_mask(lane_mask, lane)
2799
-
if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
2749
+
if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
2800
2750
XELPDP_PORT_M2P_TRANSACTION_PENDING,
2801
2751
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
2802
-
drm_dbg_kms(&i915->drm,
2752
+
drm_dbg_kms(display->drm,
2803
2753
"PHY %c Timeout waiting for previous transaction to complete. Reset the bus.\n",
2804
2754
phy_name(phy));
2805
2755
intel_cx0_bus_reset(encoder, lane);
2806
2756
}
2807
2757
2808
-
intel_de_rmw(i915, buf_ctl2_reg,
2758
+
intel_de_rmw(display, buf_ctl2_reg,
2809
2759
intel_cx0_get_powerdown_update(INTEL_CX0_BOTH_LANES),
2810
2760
intel_cx0_get_powerdown_update(lane_mask));
2811
2761
2812
2762
/* Update Timeout Value */
2813
-
if (intel_de_wait_custom(i915, buf_ctl2_reg,
2763
+
if (intel_de_wait_custom(display, buf_ctl2_reg,
2814
2764
intel_cx0_get_powerdown_update(lane_mask), 0,
2815
2765
XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
2816
-
drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
2766
+
drm_warn(display->drm,
2767
+
"PHY %c failed to bring out of Lane reset after %dus.\n",
2817
2768
phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
2818
2769
}
2819
2770
2820
2771
static void intel_cx0_setup_powerdown(struct intel_encoder *encoder)
2821
2772
{
2822
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2773
+
struct intel_display *display = to_intel_display(encoder);
2823
2774
enum port port = encoder->port;
2824
2775
2825
-
intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port),
2776
+
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
2826
2777
XELPDP_POWER_STATE_READY_MASK,
2827
2778
XELPDP_POWER_STATE_READY(CX0_P2_STATE_READY));
2828
-
intel_de_rmw(i915, XELPDP_PORT_BUF_CTL3(i915, port),
2779
+
intel_de_rmw(display, XELPDP_PORT_BUF_CTL3(display, port),
2829
2780
XELPDP_POWER_STATE_ACTIVE_MASK |
2830
2781
XELPDP_PLL_LANE_STAGGERING_DELAY_MASK,
2831
2782
XELPDP_POWER_STATE_ACTIVE(CX0_P0_STATE_ACTIVE) |
···
2858
2807
static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,
2859
2808
bool lane_reversal)
2860
2809
{
2861
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2810
+
struct intel_display *display = to_intel_display(encoder);
2862
2811
enum port port = encoder->port;
2863
2812
enum phy phy = intel_encoder_to_phy(encoder);
2864
2813
u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
···
2871
2820
XELPDP_LANE_PHY_CURRENT_STATUS(1))
2872
2821
: XELPDP_LANE_PHY_CURRENT_STATUS(0);
2873
2822
2874
-
if (intel_de_wait_custom(i915, XELPDP_PORT_BUF_CTL1(i915, port),
2823
+
if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL1(display, port),
2875
2824
XELPDP_PORT_BUF_SOC_PHY_READY,
2876
2825
XELPDP_PORT_BUF_SOC_PHY_READY,
2877
2826
XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL))
2878
-
drm_warn(&i915->drm, "PHY %c failed to bring out of SOC reset after %dus.\n",
2827
+
drm_warn(display->drm,
2828
+
"PHY %c failed to bring out of SOC reset after %dus.\n",
2879
2829
phy_name(phy), XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US);
2880
2830
2881
-
intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port), lane_pipe_reset,
2831
+
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset,
2882
2832
lane_pipe_reset);
2883
2833
2884
-
if (intel_de_wait_custom(i915, XELPDP_PORT_BUF_CTL2(i915, port),
2834
+
if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
2885
2835
lane_phy_current_status, lane_phy_current_status,
2886
2836
XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL))
2887
-
drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
2837
+
drm_warn(display->drm,
2838
+
"PHY %c failed to bring out of Lane reset after %dus.\n",
2888
2839
phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
2889
2840
2890
-
intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, port),
2841
+
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
2891
2842
intel_cx0_get_pclk_refclk_request(owned_lane_mask),
2892
2843
intel_cx0_get_pclk_refclk_request(lane_mask));
2893
2844
2894
-
if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, port),
2845
+
if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
2895
2846
intel_cx0_get_pclk_refclk_ack(owned_lane_mask),
2896
2847
intel_cx0_get_pclk_refclk_ack(lane_mask),
2897
2848
XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL))
2898
-
drm_warn(&i915->drm, "PHY %c failed to request refclk after %dus.\n",
2849
+
drm_warn(display->drm,
2850
+
"PHY %c failed to request refclk after %dus.\n",
2899
2851
phy_name(phy), XELPDP_REFCLK_ENABLE_TIMEOUT_US);
2900
2852
2901
2853
intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
2902
2854
CX0_P2_STATE_RESET);
2903
2855
intel_cx0_setup_powerdown(encoder);
2904
2856
2905
-
intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port), lane_pipe_reset, 0);
2857
+
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset, 0);
2906
2858
2907
-
if (intel_de_wait_for_clear(i915, XELPDP_PORT_BUF_CTL2(i915, port),
2859
+
if (intel_de_wait_for_clear(display, XELPDP_PORT_BUF_CTL2(display, port),
2908
2860
lane_phy_current_status,
2909
2861
XELPDP_PORT_RESET_END_TIMEOUT))
2910
-
drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dms.\n",
2862
+
drm_warn(display->drm,
2863
+
"PHY %c failed to bring out of Lane reset after %dms.\n",
2911
2864
phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT);
2912
2865
}
2913
2866
2914
-
static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
2915
-
struct intel_encoder *encoder, int lane_count,
2867
+
static void intel_cx0_program_phy_lane(struct intel_encoder *encoder, int lane_count,
2916
2868
bool lane_reversal)
2917
2869
{
2918
2870
int i;
···
2984
2930
static void intel_cx0pll_enable(struct intel_encoder *encoder,
2985
2931
const struct intel_crtc_state *crtc_state)
2986
2932
{
2987
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2933
+
struct intel_display *display = to_intel_display(encoder);
2988
2934
enum phy phy = intel_encoder_to_phy(encoder);
2989
2935
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2990
2936
bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
···
3016
2962
3017
2963
/* 5. Program PHY internal PLL internal registers. */
3018
2964
if (intel_encoder_is_c10phy(encoder))
3019
-
intel_c10_pll_program(i915, crtc_state, encoder);
2965
+
intel_c10_pll_program(display, crtc_state, encoder);
3020
2966
else
3021
-
intel_c20_pll_program(i915, crtc_state, encoder);
2967
+
intel_c20_pll_program(display, crtc_state, encoder);
3022
2968
3023
2969
/*
3024
2970
* 6. Program the enabled and disabled owned PHY lane
3025
2971
* transmitters over message bus
3026
2972
*/
3027
-
intel_cx0_program_phy_lane(i915, encoder, crtc_state->lane_count, lane_reversal);
2973
+
intel_cx0_program_phy_lane(encoder, crtc_state->lane_count, lane_reversal);
3028
2974
3029
2975
/*
3030
2976
* 7. Follow the Display Voltage Frequency Switching - Sequence
···
3035
2981
* 8. Program DDI_CLK_VALFREQ to match intended DDI
3036
2982
* clock frequency.
3037
2983
*/
3038
-
intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port),
2984
+
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
3039
2985
crtc_state->port_clock);
3040
2986
3041
2987
/*
3042
2988
* 9. Set PORT_CLOCK_CTL register PCLK PLL Request
3043
2989
* LN<Lane for maxPCLK> to "1" to enable PLL.
3044
2990
*/
3045
-
intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
2991
+
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3046
2992
intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES),
3047
2993
intel_cx0_get_pclk_pll_request(maxpclk_lane));
3048
2994
3049
2995
/* 10. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */
3050
-
if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
2996
+
if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3051
2997
intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
3052
2998
intel_cx0_get_pclk_pll_ack(maxpclk_lane),
3053
2999
XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL))
3054
-
drm_warn(&i915->drm, "Port %c PLL not locked after %dus.\n",
3000
+
drm_warn(display->drm, "Port %c PLL not locked after %dus.\n",
3055
3001
phy_name(phy), XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US);
3056
3002
3057
3003
/*
···
3065
3011
3066
3012
int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)
3067
3013
{
3068
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3069
-
u32 clock;
3070
-
u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port));
3014
+
struct intel_display *display = to_intel_display(encoder);
3015
+
u32 clock, val;
3016
+
3017
+
val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));
3071
3018
3072
3019
clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
3073
3020
3074
-
drm_WARN_ON(&i915->drm, !(val & XELPDP_FORWARD_CLOCK_UNGATE));
3075
-
drm_WARN_ON(&i915->drm, !(val & XELPDP_TBT_CLOCK_REQUEST));
3076
-
drm_WARN_ON(&i915->drm, !(val & XELPDP_TBT_CLOCK_ACK));
3021
+
drm_WARN_ON(display->drm, !(val & XELPDP_FORWARD_CLOCK_UNGATE));
3022
+
drm_WARN_ON(display->drm, !(val & XELPDP_TBT_CLOCK_REQUEST));
3023
+
drm_WARN_ON(display->drm, !(val & XELPDP_TBT_CLOCK_ACK));
3077
3024
3078
3025
switch (clock) {
3079
3026
case XELPDP_DDI_CLOCK_SELECT_TBT_162:
···
3091
3036
}
3092
3037
}
3093
3038
3094
-
static int intel_mtl_tbt_clock_select(struct drm_i915_private *i915, int clock)
3039
+
static int intel_mtl_tbt_clock_select(int clock)
3095
3040
{
3096
3041
switch (clock) {
3097
3042
case 162000:
···
3111
3056
static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
3112
3057
const struct intel_crtc_state *crtc_state)
3113
3058
{
3114
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3059
+
struct intel_display *display = to_intel_display(encoder);
3115
3060
enum phy phy = intel_encoder_to_phy(encoder);
3116
3061
u32 val = 0;
3117
3062
···
3119
3064
* 1. Program PORT_CLOCK_CTL REGISTER to configure
3120
3065
* clock muxes, gating and SSC
3121
3066
*/
3122
-
val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(i915, crtc_state->port_clock));
3067
+
val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(crtc_state->port_clock));
3123
3068
val |= XELPDP_FORWARD_CLOCK_UNGATE;
3124
-
intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
3069
+
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3125
3070
XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_FORWARD_CLOCK_UNGATE, val);
3126
3071
3127
3072
/* 2. Read back PORT_CLOCK_CTL REGISTER */
3128
-
val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port));
3073
+
val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));
3129
3074
3130
3075
/*
3131
3076
* 3. Follow the Display Voltage Frequency Switching - Sequence
···
3136
3081
* 4. Set PORT_CLOCK_CTL register TBT CLOCK Request to "1" to enable PLL.
3137
3082
*/
3138
3083
val |= XELPDP_TBT_CLOCK_REQUEST;
3139
-
intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), val);
3084
+
intel_de_write(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), val);
3140
3085
3141
3086
/* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */
3142
-
if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
3087
+
if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3143
3088
XELPDP_TBT_CLOCK_ACK,
3144
3089
XELPDP_TBT_CLOCK_ACK,
3145
3090
100, 0, NULL))
3146
-
drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not locked after 100us.\n",
3091
+
drm_warn(display->drm,
3092
+
"[ENCODER:%d:%s][%c] PHY PLL not locked after 100us.\n",
3147
3093
encoder->base.base.id, encoder->base.name, phy_name(phy));
3148
3094
3149
3095
/*
···
3156
3100
* 7. Program DDI_CLK_VALFREQ to match intended DDI
3157
3101
* clock frequency.
3158
3102
*/
3159
-
intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port),
3103
+
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
3160
3104
crtc_state->port_clock);
3161
3105
}
3162
3106
···
3173
3117
3174
3118
static u8 cx0_power_control_disable_val(struct intel_encoder *encoder)
3175
3119
{
3120
+
struct intel_display *display = to_intel_display(encoder);
3176
3121
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3177
3122
3178
3123
if (intel_encoder_is_c10phy(encoder))
3179
3124
return CX0_P2PG_STATE_DISABLE;
3180
3125
3181
-
if (IS_BATTLEMAGE(i915) && encoder->port == PORT_A)
3126
+
if ((IS_BATTLEMAGE(i915) && encoder->port == PORT_A) ||
3127
+
(DISPLAY_VER(display) >= 30 && encoder->type == INTEL_OUTPUT_EDP))
3182
3128
return CX0_P2PG_STATE_DISABLE;
3183
3129
3184
3130
return CX0_P4PG_STATE_DISABLE;
···
3188
3130
3189
3131
static void intel_cx0pll_disable(struct intel_encoder *encoder)
3190
3132
{
3191
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3133
+
struct intel_display *display = to_intel_display(encoder);
3192
3134
enum phy phy = intel_encoder_to_phy(encoder);
3193
3135
intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder);
3194
3136
···
3205
3147
* 3. Set PORT_CLOCK_CTL register PCLK PLL Request LN<Lane for maxPCLK>
3206
3148
* to "0" to disable PLL.
3207
3149
*/
3208
-
intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
3150
+
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3209
3151
intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES) |
3210
3152
intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES), 0);
3211
3153
3212
3154
/* 4. Program DDI_CLK_VALFREQ to 0. */
3213
-
intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0);
3155
+
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0);
3214
3156
3215
3157
/*
3216
3158
* 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0".
3217
3159
*/
3218
-
if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
3160
+
if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3219
3161
intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
3220
3162
intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0,
3221
3163
XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL))
3222
-
drm_warn(&i915->drm, "Port %c PLL not unlocked after %dus.\n",
3164
+
drm_warn(display->drm,
3165
+
"Port %c PLL not unlocked after %dus.\n",
3223
3166
phy_name(phy), XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US);
3224
3167
3225
3168
/*
···
3229
3170
*/
3230
3171
3231
3172
/* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */
3232
-
intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
3173
+
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3233
3174
XELPDP_DDI_CLOCK_SELECT_MASK, 0);
3234
-
intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
3175
+
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3235
3176
XELPDP_FORWARD_CLOCK_UNGATE, 0);
3236
3177
3237
3178
intel_cx0_phy_transaction_end(encoder, wakeref);
···
3239
3180
3240
3181
static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
3241
3182
{
3242
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3183
+
struct intel_display *display = to_intel_display(encoder);
3243
3184
enum phy phy = intel_encoder_to_phy(encoder);
3244
3185
3245
3186
/*
···
3250
3191
/*
3251
3192
* 2. Set PORT_CLOCK_CTL register TBT CLOCK Request to "0" to disable PLL.
3252
3193
*/
3253
-
intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
3194
+
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3254
3195
XELPDP_TBT_CLOCK_REQUEST, 0);
3255
3196
3256
3197
/* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */
3257
-
if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
3198
+
if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3258
3199
XELPDP_TBT_CLOCK_ACK, 0, 10, 0, NULL))
3259
-
drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n",
3200
+
drm_warn(display->drm,
3201
+
"[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n",
3260
3202
encoder->base.base.id, encoder->base.name, phy_name(phy));
3261
3203
3262
3204
/*
···
3268
3208
/*
3269
3209
* 5. Program PORT CLOCK CTRL register to disable and gate clocks
3270
3210
*/
3271
-
intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
3211
+
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3272
3212
XELPDP_DDI_CLOCK_SELECT_MASK |
3273
3213
XELPDP_FORWARD_CLOCK_UNGATE, 0);
3274
3214
3275
3215
/* 6. Program DDI_CLK_VALFREQ to 0. */
3276
-
intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0);
3216
+
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0);
3277
3217
}
3278
3218
3279
3219
void intel_mtl_pll_disable(struct intel_encoder *encoder)
···
3290
3230
intel_mtl_port_pll_type(struct intel_encoder *encoder,
3291
3231
const struct intel_crtc_state *crtc_state)
3292
3232
{
3293
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3233
+
struct intel_display *display = to_intel_display(encoder);
3234
+
u32 val, clock;
3235
+
3294
3236
/*
3295
3237
* TODO: Determine the PLL type from the SW state, once MTL PLL
3296
3238
* handling is done via the standard shared DPLL framework.
3297
3239
*/
3298
-
u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port));
3299
-
u32 clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
3240
+
val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));
3241
+
clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
3300
3242
3301
3243
if (clock == XELPDP_DDI_CLOCK_SELECT_MAXPCLK ||
3302
3244
clock == XELPDP_DDI_CLOCK_SELECT_DIV18CLK)
···
3312
3250
struct intel_encoder *encoder,
3313
3251
struct intel_c10pll_state *mpllb_hw_state)
3314
3252
{
3315
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3253
+
struct intel_display *display = to_intel_display(state);
3316
3254
const struct intel_c10pll_state *mpllb_sw_state = &state->dpll_hw_state.cx0pll.c10;
3317
3255
int i;
3318
3256
3319
3257
for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) {
3320
3258
u8 expected = mpllb_sw_state->pll[i];
3321
3259
3322
-
I915_STATE_WARN(i915, mpllb_hw_state->pll[i] != expected,
3323
-
"[CRTC:%d:%s] mismatch in C10MPLLB: Register[%d] (expected 0x%02x, found 0x%02x)",
3324
-
crtc->base.base.id, crtc->base.name, i,
3325
-
expected, mpllb_hw_state->pll[i]);
3260
+
INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->pll[i] != expected,
3261
+
"[CRTC:%d:%s] mismatch in C10MPLLB: Register[%d] (expected 0x%02x, found 0x%02x)",
3262
+
crtc->base.base.id, crtc->base.name, i,
3263
+
expected, mpllb_hw_state->pll[i]);
3326
3264
}
3327
3265
3328
-
I915_STATE_WARN(i915, mpllb_hw_state->tx != mpllb_sw_state->tx,
3329
-
"[CRTC:%d:%s] mismatch in C10MPLLB: Register TX0 (expected 0x%02x, found 0x%02x)",
3330
-
crtc->base.base.id, crtc->base.name,
3331
-
mpllb_sw_state->tx, mpllb_hw_state->tx);
3266
+
INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->tx != mpllb_sw_state->tx,
3267
+
"[CRTC:%d:%s] mismatch in C10MPLLB: Register TX0 (expected 0x%02x, found 0x%02x)",
3268
+
crtc->base.base.id, crtc->base.name,
3269
+
mpllb_sw_state->tx, mpllb_hw_state->tx);
3332
3270
3333
-
I915_STATE_WARN(i915, mpllb_hw_state->cmn != mpllb_sw_state->cmn,
3334
-
"[CRTC:%d:%s] mismatch in C10MPLLB: Register CMN0 (expected 0x%02x, found 0x%02x)",
3335
-
crtc->base.base.id, crtc->base.name,
3336
-
mpllb_sw_state->cmn, mpllb_hw_state->cmn);
3271
+
INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->cmn != mpllb_sw_state->cmn,
3272
+
"[CRTC:%d:%s] mismatch in C10MPLLB: Register CMN0 (expected 0x%02x, found 0x%02x)",
3273
+
crtc->base.base.id, crtc->base.name,
3274
+
mpllb_sw_state->cmn, mpllb_hw_state->cmn);
3337
3275
}
3338
3276
3339
3277
void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
···
3419
3357
struct intel_encoder *encoder,
3420
3358
struct intel_c20pll_state *mpll_hw_state)
3421
3359
{
3422
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3360
+
struct intel_display *display = to_intel_display(state);
3423
3361
const struct intel_c20pll_state *mpll_sw_state = &state->dpll_hw_state.cx0pll.c20;
3424
3362
bool sw_use_mpllb = intel_c20phy_use_mpllb(mpll_sw_state);
3425
3363
bool hw_use_mpllb = intel_c20phy_use_mpllb(mpll_hw_state);
3426
3364
int clock = intel_c20pll_calc_port_clock(encoder, mpll_sw_state);
3427
3365
int i;
3428
3366
3429
-
I915_STATE_WARN(i915, mpll_hw_state->clock != clock,
3430
-
"[CRTC:%d:%s] mismatch in C20: Register CLOCK (expected %d, found %d)",
3431
-
crtc->base.base.id, crtc->base.name,
3432
-
mpll_sw_state->clock, mpll_hw_state->clock);
3367
+
INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->clock != clock,
3368
+
"[CRTC:%d:%s] mismatch in C20: Register CLOCK (expected %d, found %d)",
3369
+
crtc->base.base.id, crtc->base.name,
3370
+
mpll_sw_state->clock, mpll_hw_state->clock);
3433
3371
3434
-
I915_STATE_WARN(i915, sw_use_mpllb != hw_use_mpllb,
3435
-
"[CRTC:%d:%s] mismatch in C20: Register MPLLB selection (expected %d, found %d)",
3436
-
crtc->base.base.id, crtc->base.name,
3437
-
sw_use_mpllb, hw_use_mpllb);
3372
+
INTEL_DISPLAY_STATE_WARN(display, sw_use_mpllb != hw_use_mpllb,
3373
+
"[CRTC:%d:%s] mismatch in C20: Register MPLLB selection (expected %d, found %d)",
3374
+
crtc->base.base.id, crtc->base.name,
3375
+
sw_use_mpllb, hw_use_mpllb);
3438
3376
3439
3377
if (hw_use_mpllb) {
3440
3378
for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mpllb); i++) {
3441
-
I915_STATE_WARN(i915, mpll_hw_state->mpllb[i] != mpll_sw_state->mpllb[i],
3442
-
"[CRTC:%d:%s] mismatch in C20MPLLB: Register[%d] (expected 0x%04x, found 0x%04x)",
3443
-
crtc->base.base.id, crtc->base.name, i,
3444
-
mpll_sw_state->mpllb[i], mpll_hw_state->mpllb[i]);
3379
+
INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->mpllb[i] != mpll_sw_state->mpllb[i],
3380
+
"[CRTC:%d:%s] mismatch in C20MPLLB: Register[%d] (expected 0x%04x, found 0x%04x)",
3381
+
crtc->base.base.id, crtc->base.name, i,
3382
+
mpll_sw_state->mpllb[i], mpll_hw_state->mpllb[i]);
3445
3383
}
3446
3384
} else {
3447
3385
for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mplla); i++) {
3448
-
I915_STATE_WARN(i915, mpll_hw_state->mplla[i] != mpll_sw_state->mplla[i],
3449
-
"[CRTC:%d:%s] mismatch in C20MPLLA: Register[%d] (expected 0x%04x, found 0x%04x)",
3450
-
crtc->base.base.id, crtc->base.name, i,
3451
-
mpll_sw_state->mplla[i], mpll_hw_state->mplla[i]);
3386
+
INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->mplla[i] != mpll_sw_state->mplla[i],
3387
+
"[CRTC:%d:%s] mismatch in C20MPLLA: Register[%d] (expected 0x%04x, found 0x%04x)",
3388
+
crtc->base.base.id, crtc->base.name, i,
3389
+
mpll_sw_state->mplla[i], mpll_hw_state->mplla[i]);
3452
3390
}
3453
3391
}
3454
3392
3455
3393
for (i = 0; i < ARRAY_SIZE(mpll_sw_state->tx); i++) {
3456
-
I915_STATE_WARN(i915, mpll_hw_state->tx[i] != mpll_sw_state->tx[i],
3457
-
"[CRTC:%d:%s] mismatch in C20: Register TX[%i] (expected 0x%04x, found 0x%04x)",
3458
-
crtc->base.base.id, crtc->base.name, i,
3459
-
mpll_sw_state->tx[i], mpll_hw_state->tx[i]);
3394
+
INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->tx[i] != mpll_sw_state->tx[i],
3395
+
"[CRTC:%d:%s] mismatch in C20: Register TX[%i] (expected 0x%04x, found 0x%04x)",
3396
+
crtc->base.base.id, crtc->base.name, i,
3397
+
mpll_sw_state->tx[i], mpll_hw_state->tx[i]);
3460
3398
}
3461
3399
3462
3400
for (i = 0; i < ARRAY_SIZE(mpll_sw_state->cmn); i++) {
3463
-
I915_STATE_WARN(i915, mpll_hw_state->cmn[i] != mpll_sw_state->cmn[i],
3464
-
"[CRTC:%d:%s] mismatch in C20: Register CMN[%i] (expected 0x%04x, found 0x%04x)",
3465
-
crtc->base.base.id, crtc->base.name, i,
3466
-
mpll_sw_state->cmn[i], mpll_hw_state->cmn[i]);
3401
+
INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->cmn[i] != mpll_sw_state->cmn[i],
3402
+
"[CRTC:%d:%s] mismatch in C20: Register CMN[%i] (expected 0x%04x, found 0x%04x)",
3403
+
crtc->base.base.id, crtc->base.name, i,
3404
+
mpll_sw_state->cmn[i], mpll_hw_state->cmn[i]);
3467
3405
}
3468
3406
}
3469
3407
3470
3408
void intel_cx0pll_state_verify(struct intel_atomic_state *state,
3471
3409
struct intel_crtc *crtc)
3472
3410
{
3473
-
struct drm_i915_private *i915 = to_i915(state->base.dev);
3411
+
struct intel_display *display = to_intel_display(state);
3474
3412
const struct intel_crtc_state *new_crtc_state =
3475
3413
intel_atomic_get_new_crtc_state(state, crtc);
3476
3414
struct intel_encoder *encoder;
3477
3415
struct intel_cx0pll_state mpll_hw_state = {};
3478
3416
3479
-
if (DISPLAY_VER(i915) < 14)
3417
+
if (DISPLAY_VER(display) < 14)
3480
3418
return;
3481
3419
3482
3420
if (!new_crtc_state->hw.active)
+3
-5
drivers/gpu/drm/i915/display/intel_cx0_phy.h
+3
-5
drivers/gpu/drm/i915/display/intel_cx0_phy.h
···
7
7
#define __INTEL_CX0_PHY_H__
8
8
9
9
#include <linux/types.h>
10
-
#include <linux/bitfield.h>
11
-
#include <linux/bits.h>
12
10
13
11
enum icl_port_dpll_id;
14
-
struct drm_i915_private;
15
12
struct intel_atomic_state;
16
13
struct intel_c10pll_state;
17
14
struct intel_c20pll_state;
18
-
struct intel_cx0pll_state;
19
15
struct intel_crtc;
20
16
struct intel_crtc_state;
17
+
struct intel_cx0pll_state;
18
+
struct intel_display;
21
19
struct intel_encoder;
22
20
struct intel_hdmi;
23
21
···
33
35
int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
34
36
const struct intel_cx0pll_state *pll_state);
35
37
36
-
void intel_cx0pll_dump_hw_state(struct drm_i915_private *dev_priv,
38
+
void intel_cx0pll_dump_hw_state(struct intel_display *display,
37
39
const struct intel_cx0pll_state *hw_state);
38
40
void intel_cx0pll_state_verify(struct intel_atomic_state *state,
39
41
struct intel_crtc *crtc);
+6
-1
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+6
-1
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
···
273
273
#define _XE2HPD_C20_A_MPLLB_CFG 0xCCC2
274
274
#define _XE2HPD_C20_B_MPLLB_CFG 0xCCB6
275
275
276
-
#define _IS_XE2HPD_C20(i915) (DISPLAY_VER_FULL(i915) == IP_VER(14, 1))
276
+
#define _IS_XE2HPD_C20(i915) (DISPLAY_VERx100(i915) == 1401)
277
277
278
278
#define PHY_C20_A_TX_CNTX_CFG(i915, idx) \
279
279
((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_TX_CNTX_CFG : _MTL_C20_A_TX_CNTX_CFG) - (idx))
280
280
#define PHY_C20_B_TX_CNTX_CFG(i915, idx) \
281
281
((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_TX_CNTX_CFG : _MTL_C20_B_TX_CNTX_CFG) - (idx))
282
282
#define C20_PHY_TX_RATE REG_GENMASK(2, 0)
283
+
#define C20_PHY_TX_MISC_MASK REG_GENMASK16(7, 0)
284
+
#define C20_PHY_TX_MISC(val) REG_FIELD_PREP16(C20_PHY_TX_MISC_MASK, (val))
283
285
284
286
#define PHY_C20_A_CMN_CNTX_CFG(i915, idx) \
285
287
((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_CMN_CNTX_CFG : _MTL_C20_A_CMN_CNTX_CFG) - (idx))
···
364
362
#define HDMI_DIV_1 1
365
363
#define HDMI_DIV_MASK REG_GENMASK16(2, 0)
366
364
#define HDMI_DIV(val) REG_FIELD_PREP16(HDMI_DIV_MASK, val)
365
+
366
+
#define PICA_PHY_CONFIG_CONTROL _MMIO(0x16FE68)
367
+
#define EDP_ON_TYPEC REG_BIT(31)
367
368
368
369
#endif /* __INTEL_CX0_REG_DEFS_H__ */
+72
-25
drivers/gpu/drm/i915/display/intel_ddi.c
+72
-25
drivers/gpu/drm/i915/display/intel_ddi.c
···
2236
2236
if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION,
2237
2237
enable ? DP_FEC_READY : 0) <= 0)
2238
2238
drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n",
2239
-
enable ? "enabled" : "disabled");
2239
+
str_enabled_disabled(enable));
2240
2240
2241
2241
if (enable &&
2242
2242
drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS,
···
2256
2256
return status;
2257
2257
}
2258
2258
2259
-
static void wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled)
2259
+
static int wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled)
2260
2260
{
2261
-
struct drm_i915_private *i915 = to_i915(aux->drm_dev);
2261
+
struct intel_display *display = to_intel_display(aux->drm_dev);
2262
2262
int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED;
2263
2263
int status;
2264
2264
int err;
···
2267
2267
status & mask || status < 0,
2268
2268
10000, 200000);
2269
2269
2270
-
if (!err && status >= 0)
2271
-
return;
2270
+
if (err || status < 0) {
2271
+
drm_dbg_kms(display->drm,
2272
+
"Failed waiting for FEC %s to get detected: %d (status %d)\n",
2273
+
str_enabled_disabled(enabled), err, status);
2274
+
return err ? err : status;
2275
+
}
2272
2276
2273
-
if (err == -ETIMEDOUT)
2274
-
drm_dbg_kms(&i915->drm, "Timeout waiting for FEC %s to get detected\n",
2275
-
str_enabled_disabled(enabled));
2276
-
else
2277
-
drm_dbg_kms(&i915->drm, "FEC detected status read error: %d\n", status);
2277
+
return 0;
2278
2278
}
2279
2279
2280
-
void intel_ddi_wait_for_fec_status(struct intel_encoder *encoder,
2281
-
const struct intel_crtc_state *crtc_state,
2282
-
bool enabled)
2280
+
int intel_ddi_wait_for_fec_status(struct intel_encoder *encoder,
2281
+
const struct intel_crtc_state *crtc_state,
2282
+
bool enabled)
2283
2283
{
2284
-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2284
+
struct intel_display *display = to_intel_display(encoder);
2285
2285
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2286
2286
int ret;
2287
2287
2288
2288
if (!crtc_state->fec_enable)
2289
-
return;
2289
+
return 0;
2290
2290
2291
2291
if (enabled)
2292
-
ret = intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state),
2292
+
ret = intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state),
2293
2293
DP_TP_STATUS_FEC_ENABLE_LIVE, 1);
2294
2294
else
2295
-
ret = intel_de_wait_for_clear(i915, dp_tp_status_reg(encoder, crtc_state),
2295
+
ret = intel_de_wait_for_clear(display, dp_tp_status_reg(encoder, crtc_state),
2296
2296
DP_TP_STATUS_FEC_ENABLE_LIVE, 1);
2297
2297
2298
-
if (ret)
2299
-
drm_err(&i915->drm,
2298
+
if (ret) {
2299
+
drm_err(display->drm,
2300
2300
"Timeout waiting for FEC live state to get %s\n",
2301
2301
str_enabled_disabled(enabled));
2302
-
2302
+
return ret;
2303
+
}
2303
2304
/*
2304
2305
* At least the Synoptics MST hub doesn't set the detected flag for
2305
2306
* FEC decoding disabling so skip waiting for that.
2306
2307
*/
2307
-
if (enabled)
2308
-
wait_for_fec_detected(&intel_dp->aux, enabled);
2308
+
if (enabled) {
2309
+
ret = wait_for_fec_detected(&intel_dp->aux, enabled);
2310
+
if (ret)
2311
+
return ret;
2312
+
}
2313
+
2314
+
return 0;
2309
2315
}
2310
2316
2311
2317
static void intel_ddi_enable_fec(struct intel_encoder *encoder,
2312
2318
const struct intel_crtc_state *crtc_state)
2313
2319
{
2314
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2320
+
struct intel_display *display = to_intel_display(encoder);
2321
+
int i;
2322
+
int ret;
2315
2323
2316
2324
if (!crtc_state->fec_enable)
2317
2325
return;
2318
2326
2319
-
intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
2327
+
intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
2320
2328
0, DP_TP_CTL_FEC_ENABLE);
2329
+
2330
+
if (DISPLAY_VER(display) < 30)
2331
+
return;
2332
+
2333
+
ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true);
2334
+
if (!ret)
2335
+
return;
2336
+
2337
+
for (i = 0; i < 3; i++) {
2338
+
drm_dbg_kms(display->drm, "Retry FEC enabling\n");
2339
+
2340
+
intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
2341
+
DP_TP_CTL_FEC_ENABLE, 0);
2342
+
2343
+
ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, false);
2344
+
if (ret)
2345
+
continue;
2346
+
2347
+
intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
2348
+
0, DP_TP_CTL_FEC_ENABLE);
2349
+
2350
+
ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true);
2351
+
if (!ret)
2352
+
return;
2353
+
}
2354
+
2355
+
drm_err(display->drm, "Failed to enable FEC after retries\n");
2321
2356
}
2322
2357
2323
2358
static void intel_ddi_disable_fec(struct intel_encoder *encoder,
···
3513
3478
drm_connector_update_privacy_screen(conn_state);
3514
3479
}
3515
3480
3481
+
static void intel_ddi_update_pipe_hdmi(struct intel_encoder *encoder,
3482
+
const struct intel_crtc_state *crtc_state,
3483
+
const struct drm_connector_state *conn_state)
3484
+
{
3485
+
intel_hdmi_fastset_infoframes(encoder, crtc_state, conn_state);
3486
+
}
3487
+
3516
3488
void intel_ddi_update_pipe(struct intel_atomic_state *state,
3517
3489
struct intel_encoder *encoder,
3518
3490
const struct intel_crtc_state *crtc_state,
···
3530
3488
!intel_encoder_is_mst(encoder))
3531
3489
intel_ddi_update_pipe_dp(state, encoder, crtc_state,
3532
3490
conn_state);
3491
+
3492
+
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3493
+
intel_ddi_update_pipe_hdmi(encoder, crtc_state,
3494
+
conn_state);
3533
3495
3534
3496
intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state);
3535
3497
}
···
4438
4392
struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4439
4393
4440
4394
intel_dp->reset_link_params = true;
4395
+
intel_dp_invalidate_source_oui(intel_dp);
4441
4396
4442
4397
intel_pps_encoder_reset(intel_dp);
4443
4398
···
4932
4885
if (!assert_has_icl_dsi(dev_priv))
4933
4886
return;
4934
4887
4935
-
icl_dsi_init(dev_priv, devdata);
4888
+
icl_dsi_init(display, devdata);
4936
4889
return;
4937
4890
}
4938
4891
+3
-3
drivers/gpu/drm/i915/display/intel_ddi.h
+3
-3
drivers/gpu/drm/i915/display/intel_ddi.h
···
63
63
void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder,
64
64
const struct intel_crtc_state *crtc_state);
65
65
void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state);
66
-
void intel_ddi_wait_for_fec_status(struct intel_encoder *encoder,
67
-
const struct intel_crtc_state *crtc_state,
68
-
bool enabled);
66
+
int intel_ddi_wait_for_fec_status(struct intel_encoder *encoder,
67
+
const struct intel_crtc_state *crtc_state,
68
+
bool enabled);
69
69
void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
70
70
const struct drm_connector_state *conn_state);
71
71
bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
+18
-28
drivers/gpu/drm/i915/display/intel_de.h
+18
-28
drivers/gpu/drm/i915/display/intel_de.h
···
32
32
#define intel_de_read(p,...) __intel_de_read(__to_intel_display(p), __VA_ARGS__)
33
33
34
34
static inline u8
35
-
__intel_de_read8(struct intel_display *display, i915_reg_t reg)
35
+
intel_de_read8(struct intel_display *display, i915_reg_t reg)
36
36
{
37
37
u8 val;
38
38
···
44
44
45
45
return val;
46
46
}
47
-
#define intel_de_read8(p,...) __intel_de_read8(__to_intel_display(p), __VA_ARGS__)
48
47
49
48
static inline u64
50
-
__intel_de_read64_2x32(struct intel_display *display,
51
-
i915_reg_t lower_reg, i915_reg_t upper_reg)
49
+
intel_de_read64_2x32(struct intel_display *display,
50
+
i915_reg_t lower_reg, i915_reg_t upper_reg)
52
51
{
53
52
u64 val;
54
53
···
62
63
63
64
return val;
64
65
}
65
-
#define intel_de_read64_2x32(p,...) __intel_de_read64_2x32(__to_intel_display(p), __VA_ARGS__)
66
66
67
67
static inline void
68
68
__intel_de_posting_read(struct intel_display *display, i915_reg_t reg)
···
86
88
#define intel_de_write(p,...) __intel_de_write(__to_intel_display(p), __VA_ARGS__)
87
89
88
90
static inline u32
89
-
____intel_de_rmw_nowl(struct intel_display *display, i915_reg_t reg,
90
-
u32 clear, u32 set)
91
+
__intel_de_rmw_nowl(struct intel_display *display, i915_reg_t reg,
92
+
u32 clear, u32 set)
91
93
{
92
94
return intel_uncore_rmw(__to_uncore(display), reg, clear, set);
93
95
}
94
-
#define __intel_de_rmw_nowl(p,...) ____intel_de_rmw_nowl(__to_intel_display(p), __VA_ARGS__)
95
96
96
97
static inline u32
97
98
__intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear,
···
109
112
#define intel_de_rmw(p,...) __intel_de_rmw(__to_intel_display(p), __VA_ARGS__)
110
113
111
114
static inline int
112
-
____intel_de_wait_for_register_nowl(struct intel_display *display,
113
-
i915_reg_t reg,
114
-
u32 mask, u32 value, unsigned int timeout)
115
+
__intel_de_wait_for_register_nowl(struct intel_display *display,
116
+
i915_reg_t reg,
117
+
u32 mask, u32 value, unsigned int timeout)
115
118
{
116
119
return intel_wait_for_register(__to_uncore(display), reg, mask,
117
120
value, timeout);
118
121
}
119
-
#define __intel_de_wait_for_register_nowl(p,...) ____intel_de_wait_for_register_nowl(__to_intel_display(p), __VA_ARGS__)
120
122
121
123
static inline int
122
-
__intel_de_wait(struct intel_display *display, i915_reg_t reg,
123
-
u32 mask, u32 value, unsigned int timeout)
124
+
intel_de_wait(struct intel_display *display, i915_reg_t reg,
125
+
u32 mask, u32 value, unsigned int timeout)
124
126
{
125
127
int ret;
126
128
···
132
136
133
137
return ret;
134
138
}
135
-
#define intel_de_wait(p,...) __intel_de_wait(__to_intel_display(p), __VA_ARGS__)
136
139
137
140
static inline int
138
-
__intel_de_wait_fw(struct intel_display *display, i915_reg_t reg,
139
-
u32 mask, u32 value, unsigned int timeout)
141
+
intel_de_wait_fw(struct intel_display *display, i915_reg_t reg,
142
+
u32 mask, u32 value, unsigned int timeout)
140
143
{
141
144
int ret;
142
145
···
148
153
149
154
return ret;
150
155
}
151
-
#define intel_de_wait_fw(p,...) __intel_de_wait_fw(__to_intel_display(p), __VA_ARGS__)
152
156
153
157
static inline int
154
-
__intel_de_wait_custom(struct intel_display *display, i915_reg_t reg,
155
-
u32 mask, u32 value,
156
-
unsigned int fast_timeout_us,
157
-
unsigned int slow_timeout_ms, u32 *out_value)
158
+
intel_de_wait_custom(struct intel_display *display, i915_reg_t reg,
159
+
u32 mask, u32 value,
160
+
unsigned int fast_timeout_us,
161
+
unsigned int slow_timeout_ms, u32 *out_value)
158
162
{
159
163
int ret;
160
164
···
167
173
168
174
return ret;
169
175
}
170
-
#define intel_de_wait_custom(p,...) __intel_de_wait_custom(__to_intel_display(p), __VA_ARGS__)
171
176
172
177
static inline int
173
178
__intel_de_wait_for_set(struct intel_display *display, i915_reg_t reg,
···
213
220
#define intel_de_write_fw(p,...) __intel_de_write_fw(__to_intel_display(p), __VA_ARGS__)
214
221
215
222
static inline u32
216
-
__intel_de_read_notrace(struct intel_display *display, i915_reg_t reg)
223
+
intel_de_read_notrace(struct intel_display *display, i915_reg_t reg)
217
224
{
218
225
return intel_uncore_read_notrace(__to_uncore(display), reg);
219
226
}
220
-
#define intel_de_read_notrace(p,...) __intel_de_read_notrace(__to_intel_display(p), __VA_ARGS__)
221
227
222
228
static inline void
223
-
__intel_de_write_notrace(struct intel_display *display, i915_reg_t reg,
224
-
u32 val)
229
+
intel_de_write_notrace(struct intel_display *display, i915_reg_t reg, u32 val)
225
230
{
226
231
intel_uncore_write_notrace(__to_uncore(display), reg, val);
227
232
}
228
-
#define intel_de_write_notrace(p,...) __intel_de_write_notrace(__to_intel_display(p), __VA_ARGS__)
229
233
230
234
static __always_inline void
231
235
intel_de_write_dsb(struct intel_display *display, struct intel_dsb *dsb,
+50
-27
drivers/gpu/drm/i915/display/intel_display.c
+50
-27
drivers/gpu/drm/i915/display/intel_display.c
···
422
422
void assert_transcoder(struct drm_i915_private *dev_priv,
423
423
enum transcoder cpu_transcoder, bool state)
424
424
{
425
+
struct intel_display *display = &dev_priv->display;
425
426
bool cur_state;
426
427
enum intel_display_power_domain power_domain;
427
428
intel_wakeref_t wakeref;
···
443
442
cur_state = false;
444
443
}
445
444
446
-
I915_STATE_WARN(dev_priv, cur_state != state,
447
-
"transcoder %s assertion failure (expected %s, current %s)\n",
448
-
transcoder_name(cpu_transcoder), str_on_off(state),
449
-
str_on_off(cur_state));
445
+
INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
446
+
"transcoder %s assertion failure (expected %s, current %s)\n",
447
+
transcoder_name(cpu_transcoder), str_on_off(state),
448
+
str_on_off(cur_state));
450
449
}
451
450
452
451
static void assert_plane(struct intel_plane *plane, bool state)
453
452
{
454
-
struct drm_i915_private *i915 = to_i915(plane->base.dev);
453
+
struct intel_display *display = to_intel_display(plane->base.dev);
455
454
enum pipe pipe;
456
455
bool cur_state;
457
456
458
457
cur_state = plane->get_hw_state(plane, &pipe);
459
458
460
-
I915_STATE_WARN(i915, cur_state != state,
461
-
"%s assertion failure (expected %s, current %s)\n",
462
-
plane->base.name, str_on_off(state),
463
-
str_on_off(cur_state));
459
+
INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
460
+
"%s assertion failure (expected %s, current %s)\n",
461
+
plane->base.name, str_on_off(state),
462
+
str_on_off(cur_state));
464
463
}
465
464
466
465
#define assert_plane_enabled(p) assert_plane(p, true)
···
475
474
assert_plane_disabled(plane);
476
475
}
477
476
478
-
void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
477
+
void vlv_wait_port_ready(struct intel_display *display,
479
478
struct intel_digital_port *dig_port,
480
479
unsigned int expected_mask)
481
480
{
···
488
487
fallthrough;
489
488
case PORT_B:
490
489
port_mask = DPLL_PORTB_READY_MASK;
491
-
dpll_reg = DPLL(dev_priv, 0);
490
+
dpll_reg = DPLL(display, 0);
492
491
break;
493
492
case PORT_C:
494
493
port_mask = DPLL_PORTC_READY_MASK;
495
-
dpll_reg = DPLL(dev_priv, 0);
494
+
dpll_reg = DPLL(display, 0);
496
495
expected_mask <<= 4;
497
496
break;
498
497
case PORT_D:
···
501
500
break;
502
501
}
503
502
504
-
if (intel_de_wait(dev_priv, dpll_reg, port_mask, expected_mask, 1000))
505
-
drm_WARN(&dev_priv->drm, 1,
503
+
if (intel_de_wait(display, dpll_reg, port_mask, expected_mask, 1000))
504
+
drm_WARN(display->drm, 1,
506
505
"timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
507
506
dig_port->base.base.base.id, dig_port->base.base.name,
508
-
intel_de_read(dev_priv, dpll_reg) & port_mask,
507
+
intel_de_read(display, dpll_reg) & port_mask,
509
508
expected_mask);
510
509
}
511
510
···
862
861
*/
863
862
if (IS_DG2(dev_priv))
864
863
tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2;
865
-
else if (DISPLAY_VER(dev_priv) >= 13)
864
+
else if ((DISPLAY_VER(dev_priv) >= 13) && (DISPLAY_VER(dev_priv) < 30))
866
865
tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
867
866
868
867
/* Wa_14010547955:dg2 */
···
2610
2609
return 0;
2611
2610
}
2612
2611
2612
+
static bool intel_crtc_needs_wa_14015401596(struct intel_crtc_state *crtc_state)
2613
+
{
2614
+
struct intel_display *display = to_intel_display(crtc_state);
2615
+
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2616
+
2617
+
return intel_vrr_possible(crtc_state) && crtc_state->has_psr &&
2618
+
adjusted_mode->crtc_vblank_start == adjusted_mode->crtc_vdisplay &&
2619
+
IS_DISPLAY_VER(display, 13, 14);
2620
+
}
2621
+
2613
2622
static int intel_crtc_compute_config(struct intel_atomic_state *state,
2614
2623
struct intel_crtc *crtc)
2615
2624
{
2616
2625
struct intel_crtc_state *crtc_state =
2617
2626
intel_atomic_get_new_crtc_state(state, crtc);
2627
+
struct drm_display_mode *adjusted_mode =
2628
+
&crtc_state->hw.adjusted_mode;
2618
2629
int ret;
2630
+
2631
+
/* Wa_14015401596 */
2632
+
if (intel_crtc_needs_wa_14015401596(crtc_state))
2633
+
adjusted_mode->crtc_vblank_start += 1;
2619
2634
2620
2635
ret = intel_dpll_crtc_compute_clock(state, crtc);
2621
2636
if (ret)
···
5067
5050
struct drm_connector *connector;
5068
5051
int i;
5069
5052
5053
+
intel_vrr_compute_config_late(crtc_state);
5054
+
5070
5055
for_each_new_connector_in_state(&state->base, connector,
5071
5056
conn_state, i) {
5072
5057
struct intel_encoder *encoder =
···
5306
5287
const struct intel_cx0pll_state *a,
5307
5288
const struct intel_cx0pll_state *b)
5308
5289
{
5309
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
5290
+
struct intel_display *display = to_intel_display(crtc);
5310
5291
char *chipname = a->use_c10 ? "C10" : "C20";
5311
5292
5312
5293
pipe_config_mismatch(p, fastset, crtc, name, chipname);
5313
5294
5314
5295
drm_printf(p, "expected:\n");
5315
-
intel_cx0pll_dump_hw_state(i915, a);
5296
+
intel_cx0pll_dump_hw_state(display, a);
5316
5297
drm_printf(p, "found:\n");
5317
-
intel_cx0pll_dump_hw_state(i915, b);
5298
+
intel_cx0pll_dump_hw_state(display, b);
5318
5299
}
5319
5300
5320
5301
bool
···
5702
5683
PIPE_CONF_CHECK_INFOFRAME(avi);
5703
5684
PIPE_CONF_CHECK_INFOFRAME(spd);
5704
5685
PIPE_CONF_CHECK_INFOFRAME(hdmi);
5705
-
PIPE_CONF_CHECK_INFOFRAME(drm);
5686
+
if (!fastset)
5687
+
PIPE_CONF_CHECK_INFOFRAME(drm);
5706
5688
PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
5707
5689
PIPE_CONF_CHECK_DP_AS_SDP(as_sdp);
5708
5690
···
8149
8129
8150
8130
if (HAS_DDI(dev_priv)) {
8151
8131
if (intel_ddi_crt_present(dev_priv))
8152
-
intel_crt_init(dev_priv);
8132
+
intel_crt_init(display);
8153
8133
8154
8134
intel_bios_for_each_encoder(display, intel_ddi_init);
8155
8135
···
8164
8144
* incorrect sharing of the PPS.
8165
8145
*/
8166
8146
intel_lvds_init(dev_priv);
8167
-
intel_crt_init(dev_priv);
8147
+
intel_crt_init(display);
8168
8148
8169
8149
dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
8170
8150
···
8195
8175
bool has_edp, has_port;
8196
8176
8197
8177
if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support)
8198
-
intel_crt_init(dev_priv);
8178
+
intel_crt_init(display);
8199
8179
8200
8180
/*
8201
8181
* The DP_DETECTED bit is the latched state of the DDC
···
8241
8221
vlv_dsi_init(dev_priv);
8242
8222
} else if (IS_PINEVIEW(dev_priv)) {
8243
8223
intel_lvds_init(dev_priv);
8244
-
intel_crt_init(dev_priv);
8224
+
intel_crt_init(display);
8245
8225
} else if (IS_DISPLAY_VER(dev_priv, 3, 4)) {
8246
8226
bool found = false;
8247
8227
8248
8228
if (IS_MOBILE(dev_priv))
8249
8229
intel_lvds_init(dev_priv);
8250
8230
8251
-
intel_crt_init(dev_priv);
8231
+
intel_crt_init(display);
8252
8232
8253
8233
if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
8254
8234
drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
···
8290
8270
if (IS_I85X(dev_priv))
8291
8271
intel_lvds_init(dev_priv);
8292
8272
8293
-
intel_crt_init(dev_priv);
8273
+
intel_crt_init(display);
8294
8274
intel_dvo_init(dev_priv);
8295
8275
}
8296
8276
···
8452
8432
* plane so let's not advertize modes that are
8453
8433
* too big for that.
8454
8434
*/
8455
-
if (DISPLAY_VER(dev_priv) >= 11) {
8435
+
if (DISPLAY_VER(dev_priv) >= 30) {
8436
+
plane_width_max = 6144 * num_joined_pipes;
8437
+
plane_height_max = 4800;
8438
+
} else if (DISPLAY_VER(dev_priv) >= 11) {
8456
8439
plane_width_max = 5120 * num_joined_pipes;
8457
8440
plane_height_max = 4320;
8458
8441
} else {
+9
-10
drivers/gpu/drm/i915/display/intel_display.h
+9
-10
drivers/gpu/drm/i915/display/intel_display.h
···
492
492
enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder);
493
493
494
494
int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
495
-
void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
495
+
void vlv_wait_port_ready(struct intel_display *display,
496
496
struct intel_digital_port *dig_port,
497
497
unsigned int expected_mask);
498
498
···
585
585
bool assert_port_valid(struct drm_i915_private *i915, enum port port);
586
586
587
587
/*
588
-
* Use I915_STATE_WARN(x) (rather than WARN() and WARN_ON()) for hw state sanity
589
-
* checks to check for unexpected conditions which may not necessarily be a user
590
-
* visible problem. This will either WARN() or DRM_ERROR() depending on the
591
-
* verbose_state_checks module param, to enable distros and users to tailor
592
-
* their preferred amount of i915 abrt spam.
588
+
* Use INTEL_DISPLAY_STATE_WARN(x) (rather than WARN() and WARN_ON()) for hw
589
+
* state sanity checks to check for unexpected conditions which may not
590
+
* necessarily be a user visible problem. This will either drm_WARN() or
591
+
* drm_err() depending on the verbose_state_checks module param, to enable
592
+
* distros and users to tailor their preferred amount of i915 abrt spam.
593
593
*/
594
-
#define I915_STATE_WARN(__i915, condition, format...) ({ \
595
-
struct drm_device *drm = &(__i915)->drm; \
594
+
#define INTEL_DISPLAY_STATE_WARN(__display, condition, format...) ({ \
596
595
int __ret_warn_on = !!(condition); \
597
596
if (unlikely(__ret_warn_on)) \
598
-
if (!drm_WARN(drm, __i915->display.params.verbose_state_checks, format)) \
599
-
drm_err(drm, format); \
597
+
if (!drm_WARN((__display)->drm, (__display)->params.verbose_state_checks, format)) \
598
+
drm_err((__display)->drm, format); \
600
599
unlikely(__ret_warn_on); \
601
600
})
602
601
+5
drivers/gpu/drm/i915/display/intel_display_core.h
+5
drivers/gpu/drm/i915/display/intel_display_core.h
···
284
284
/* drm device backpointer */
285
285
struct drm_device *drm;
286
286
287
+
/* Platform (and subplatform, if any) identification */
288
+
struct intel_display_platforms platform;
289
+
287
290
/* Display functions */
288
291
struct {
289
292
/* Top level crtc-ish functions */
···
457
454
458
455
/* For i915gm/i945gm vblank irq workaround */
459
456
u8 vblank_enabled;
457
+
458
+
int vblank_wa_num_pipes;
460
459
461
460
struct work_struct vblank_dc_work;
462
461
+212
-79
drivers/gpu/drm/i915/display/intel_display_device.c
+212
-79
drivers/gpu/drm/i915/display/intel_display_device.c
···
3
3
* Copyright © 2023 Intel Corporation
4
4
*/
5
5
6
-
#include <drm/intel/i915_pciids.h>
6
+
#include <drm/intel/pciids.h>
7
7
#include <drm/drm_color_mgmt.h>
8
8
#include <linux/pci.h>
9
9
10
10
#include "i915_drv.h"
11
11
#include "i915_reg.h"
12
+
#include "intel_cx0_phy_regs.h"
12
13
#include "intel_de.h"
13
14
#include "intel_display.h"
14
15
#include "intel_display_device.h"
···
32
31
.step_info.size = ARRAY_SIZE(_map)
33
32
34
33
struct subplatform_desc {
35
-
enum intel_display_subplatform subplatform;
34
+
struct intel_display_platforms platforms;
36
35
const char *name;
37
36
const u16 *pciidlist;
38
37
struct stepping_desc step_info;
39
38
};
40
39
40
+
#define SUBPLATFORM(_platform, _subplatform) \
41
+
.platforms._platform##_##_subplatform = 1, \
42
+
.name = #_subplatform
43
+
44
+
/*
45
+
* Group subplatform alias that matches multiple subplatforms. For making ult
46
+
* cover both ult and ulx on HSW/BDW.
47
+
*/
48
+
#define SUBPLATFORM_GROUP(_platform, _subplatform) \
49
+
.platforms._platform##_##_subplatform = 1
50
+
41
51
struct platform_desc {
42
-
enum intel_display_platform platform;
52
+
struct intel_display_platforms platforms;
43
53
const char *name;
44
54
const struct subplatform_desc *subplatforms;
45
55
const struct intel_display_device_info *info; /* NULL for GMD ID */
···
58
46
};
59
47
60
48
#define PLATFORM(_platform) \
61
-
.platform = (INTEL_DISPLAY_##_platform), \
49
+
.platforms._platform = 1, \
62
50
.name = #_platform
51
+
52
+
/*
53
+
* Group platform alias that matches multiple platforms. For aliases such as g4x
54
+
* that covers both g45 and gm45.
55
+
*/
56
+
#define PLATFORM_GROUP(_platform) \
57
+
.platforms._platform = 1
63
58
64
59
#define ID(id) (id)
65
60
···
251
232
.__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A)
252
233
253
234
static const struct platform_desc i830_desc = {
254
-
PLATFORM(I830),
235
+
PLATFORM(i830),
255
236
.info = &(const struct intel_display_device_info) {
256
237
I830_DISPLAY,
257
238
···
260
241
};
261
242
262
243
static const struct platform_desc i845_desc = {
263
-
PLATFORM(I845G),
244
+
PLATFORM(i845g),
264
245
.info = &(const struct intel_display_device_info) {
265
246
I845_DISPLAY,
266
247
···
269
250
};
270
251
271
252
static const struct platform_desc i85x_desc = {
272
-
PLATFORM(I85X),
253
+
PLATFORM(i85x),
273
254
.info = &(const struct intel_display_device_info) {
274
255
I830_DISPLAY,
275
256
···
279
260
};
280
261
281
262
static const struct platform_desc i865g_desc = {
282
-
PLATFORM(I865G),
263
+
PLATFORM(i865g),
283
264
.info = &(const struct intel_display_device_info) {
284
265
I845_DISPLAY,
285
266
···
301
282
.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) /* SDVO B/C */
302
283
303
284
static const struct platform_desc i915g_desc = {
304
-
PLATFORM(I915G),
285
+
PLATFORM(i915g),
305
286
.info = &(const struct intel_display_device_info) {
306
287
GEN3_DISPLAY,
307
288
I845_COLORS,
···
311
292
};
312
293
313
294
static const struct platform_desc i915gm_desc = {
314
-
PLATFORM(I915GM),
295
+
PLATFORM(i915gm),
315
296
.info = &(const struct intel_display_device_info) {
316
297
GEN3_DISPLAY,
317
298
I9XX_COLORS,
···
324
305
};
325
306
326
307
static const struct platform_desc i945g_desc = {
327
-
PLATFORM(I945G),
308
+
PLATFORM(i945g),
328
309
.info = &(const struct intel_display_device_info) {
329
310
GEN3_DISPLAY,
330
311
I845_COLORS,
···
335
316
};
336
317
337
318
static const struct platform_desc i945gm_desc = {
338
-
PLATFORM(I915GM),
319
+
PLATFORM(i915gm),
339
320
.info = &(const struct intel_display_device_info) {
340
321
GEN3_DISPLAY,
341
322
I9XX_COLORS,
···
349
330
};
350
331
351
332
static const struct platform_desc g33_desc = {
352
-
PLATFORM(G33),
333
+
PLATFORM(g33),
353
334
.info = &(const struct intel_display_device_info) {
354
335
GEN3_DISPLAY,
355
336
I845_COLORS,
···
358
339
};
359
340
360
341
static const struct platform_desc pnv_desc = {
361
-
PLATFORM(PINEVIEW),
342
+
PLATFORM(pineview),
362
343
.info = &(const struct intel_display_device_info) {
363
344
GEN3_DISPLAY,
364
345
I9XX_COLORS,
···
379
360
BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
380
361
381
362
static const struct platform_desc i965g_desc = {
382
-
PLATFORM(I965G),
363
+
PLATFORM(i965g),
383
364
.info = &(const struct intel_display_device_info) {
384
365
GEN4_DISPLAY,
385
366
.has_overlay = 1,
···
389
370
};
390
371
391
372
static const struct platform_desc i965gm_desc = {
392
-
PLATFORM(I965GM),
373
+
PLATFORM(i965gm),
393
374
.info = &(const struct intel_display_device_info) {
394
375
GEN4_DISPLAY,
395
376
.has_overlay = 1,
···
401
382
};
402
383
403
384
static const struct platform_desc g45_desc = {
404
-
PLATFORM(G45),
385
+
PLATFORM(g45),
386
+
PLATFORM_GROUP(g4x),
405
387
.info = &(const struct intel_display_device_info) {
406
388
GEN4_DISPLAY,
407
389
···
411
391
};
412
392
413
393
static const struct platform_desc gm45_desc = {
414
-
PLATFORM(GM45),
394
+
PLATFORM(gm45),
395
+
PLATFORM_GROUP(g4x),
415
396
.info = &(const struct intel_display_device_info) {
416
397
GEN4_DISPLAY,
417
398
.supports_tv = 1,
···
435
414
.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */
436
415
437
416
static const struct platform_desc ilk_d_desc = {
438
-
PLATFORM(IRONLAKE),
417
+
PLATFORM(ironlake),
439
418
.info = &(const struct intel_display_device_info) {
440
419
ILK_DISPLAY,
441
420
},
442
421
};
443
422
444
423
static const struct platform_desc ilk_m_desc = {
445
-
PLATFORM(IRONLAKE),
424
+
PLATFORM(ironlake),
446
425
.info = &(const struct intel_display_device_info) {
447
426
ILK_DISPLAY,
448
427
···
451
430
};
452
431
453
432
static const struct platform_desc snb_desc = {
454
-
PLATFORM(SANDYBRIDGE),
433
+
PLATFORM(sandybridge),
455
434
.info = &(const struct intel_display_device_info) {
456
435
.has_hotplug = 1,
457
436
I9XX_PIPE_OFFSETS,
···
468
447
};
469
448
470
449
static const struct platform_desc ivb_desc = {
471
-
PLATFORM(IVYBRIDGE),
450
+
PLATFORM(ivybridge),
472
451
.info = &(const struct intel_display_device_info) {
473
452
.has_hotplug = 1,
474
453
IVB_PIPE_OFFSETS,
···
485
464
};
486
465
487
466
static const struct platform_desc vlv_desc = {
488
-
PLATFORM(VALLEYVIEW),
467
+
PLATFORM(valleyview),
489
468
.info = &(const struct intel_display_device_info) {
490
469
.has_gmch = 1,
491
470
.has_hotplug = 1,
···
516
495
};
517
496
518
497
static const struct platform_desc hsw_desc = {
519
-
PLATFORM(HASWELL),
498
+
PLATFORM(haswell),
520
499
.subplatforms = (const struct subplatform_desc[]) {
521
-
{ INTEL_DISPLAY_HASWELL_ULT, "ULT", hsw_ult_ids },
522
-
{ INTEL_DISPLAY_HASWELL_ULX, "ULX", hsw_ulx_ids },
500
+
/* Special case: Use ult both as group and subplatform. */
501
+
{
502
+
SUBPLATFORM(haswell, ult),
503
+
SUBPLATFORM_GROUP(haswell, ult),
504
+
.pciidlist = hsw_ult_ids,
505
+
},
506
+
{
507
+
SUBPLATFORM(haswell, ulx),
508
+
SUBPLATFORM_GROUP(haswell, ult),
509
+
.pciidlist = hsw_ulx_ids,
510
+
},
523
511
{},
524
512
},
525
513
.info = &(const struct intel_display_device_info) {
···
569
539
};
570
540
571
541
static const struct platform_desc bdw_desc = {
572
-
PLATFORM(BROADWELL),
542
+
PLATFORM(broadwell),
573
543
.subplatforms = (const struct subplatform_desc[]) {
574
-
{ INTEL_DISPLAY_BROADWELL_ULT, "ULT", bdw_ult_ids },
575
-
{ INTEL_DISPLAY_BROADWELL_ULX, "ULX", bdw_ulx_ids },
544
+
/* Special case: Use ult both as group and subplatform. */
545
+
{
546
+
SUBPLATFORM(broadwell, ult),
547
+
SUBPLATFORM_GROUP(broadwell, ult),
548
+
.pciidlist = bdw_ult_ids,
549
+
},
550
+
{
551
+
SUBPLATFORM(broadwell, ulx),
552
+
SUBPLATFORM_GROUP(broadwell, ult),
553
+
.pciidlist = bdw_ulx_ids,
554
+
},
576
555
{},
577
556
},
578
557
.info = &(const struct intel_display_device_info) {
···
606
567
};
607
568
608
569
static const struct platform_desc chv_desc = {
609
-
PLATFORM(CHERRYVIEW),
570
+
PLATFORM(cherryview),
610
571
.info = &(const struct intel_display_device_info) {
611
572
.has_hotplug = 1,
612
573
.has_gmch = 1,
···
669
630
};
670
631
671
632
static const struct platform_desc skl_desc = {
672
-
PLATFORM(SKYLAKE),
633
+
PLATFORM(skylake),
673
634
.subplatforms = (const struct subplatform_desc[]) {
674
-
{ INTEL_DISPLAY_SKYLAKE_ULT, "ULT", skl_ult_ids },
675
-
{ INTEL_DISPLAY_SKYLAKE_ULX, "ULX", skl_ulx_ids },
635
+
{
636
+
SUBPLATFORM(skylake, ult),
637
+
.pciidlist = skl_ult_ids,
638
+
},
639
+
{
640
+
SUBPLATFORM(skylake, ulx),
641
+
.pciidlist = skl_ulx_ids,
642
+
},
676
643
{},
677
644
},
678
645
.info = &skl_display,
···
710
665
};
711
666
712
667
static const struct platform_desc kbl_desc = {
713
-
PLATFORM(KABYLAKE),
668
+
PLATFORM(kabylake),
714
669
.subplatforms = (const struct subplatform_desc[]) {
715
-
{ INTEL_DISPLAY_KABYLAKE_ULT, "ULT", kbl_ult_ids },
716
-
{ INTEL_DISPLAY_KABYLAKE_ULX, "ULX", kbl_ulx_ids },
670
+
{
671
+
SUBPLATFORM(kabylake, ult),
672
+
.pciidlist = kbl_ult_ids,
673
+
},
674
+
{
675
+
SUBPLATFORM(kabylake, ulx),
676
+
.pciidlist = kbl_ulx_ids,
677
+
},
717
678
{},
718
679
},
719
680
.info = &skl_display,
···
741
690
};
742
691
743
692
static const struct platform_desc cfl_desc = {
744
-
PLATFORM(COFFEELAKE),
693
+
PLATFORM(coffeelake),
745
694
.subplatforms = (const struct subplatform_desc[]) {
746
-
{ INTEL_DISPLAY_COFFEELAKE_ULT, "ULT", cfl_ult_ids },
747
-
{ INTEL_DISPLAY_COFFEELAKE_ULX, "ULX", cfl_ulx_ids },
695
+
{
696
+
SUBPLATFORM(coffeelake, ult),
697
+
.pciidlist = cfl_ult_ids,
698
+
},
699
+
{
700
+
SUBPLATFORM(coffeelake, ulx),
701
+
.pciidlist = cfl_ulx_ids,
702
+
},
748
703
{},
749
704
},
750
705
.info = &skl_display,
···
763
706
};
764
707
765
708
static const struct platform_desc cml_desc = {
766
-
PLATFORM(COMETLAKE),
709
+
PLATFORM(cometlake),
767
710
.subplatforms = (const struct subplatform_desc[]) {
768
-
{ INTEL_DISPLAY_COMETLAKE_ULT, "ULT", cml_ult_ids },
711
+
{
712
+
SUBPLATFORM(cometlake, ult),
713
+
.pciidlist = cml_ult_ids,
714
+
},
769
715
{},
770
716
},
771
717
.info = &skl_display,
···
805
745
};
806
746
807
747
static const struct platform_desc bxt_desc = {
808
-
PLATFORM(BROXTON),
748
+
PLATFORM(broxton),
809
749
.info = &(const struct intel_display_device_info) {
810
750
GEN9_LP_DISPLAY,
811
751
.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
···
820
760
};
821
761
822
762
static const struct platform_desc glk_desc = {
823
-
PLATFORM(GEMINILAKE),
763
+
PLATFORM(geminilake),
824
764
.info = &(const struct intel_display_device_info) {
825
765
GEN9_LP_DISPLAY,
826
766
.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
···
882
822
};
883
823
884
824
static const struct platform_desc icl_desc = {
885
-
PLATFORM(ICELAKE),
825
+
PLATFORM(icelake),
886
826
.subplatforms = (const struct subplatform_desc[]) {
887
-
{ INTEL_DISPLAY_ICELAKE_PORT_F, "Port F", icl_port_f_ids },
827
+
{
828
+
SUBPLATFORM(icelake, port_f),
829
+
.pciidlist = icl_port_f_ids,
830
+
},
888
831
{},
889
832
},
890
833
.info = &(const struct intel_display_device_info) {
···
910
847
};
911
848
912
849
static const struct platform_desc jsl_desc = {
913
-
PLATFORM(JASPERLAKE),
850
+
PLATFORM(jasperlake),
914
851
.info = &jsl_ehl_display,
915
852
STEP_INFO(jsl_ehl_steppings),
916
853
};
917
854
918
855
static const struct platform_desc ehl_desc = {
919
-
PLATFORM(ELKHARTLAKE),
856
+
PLATFORM(elkhartlake),
920
857
.info = &jsl_ehl_display,
921
858
STEP_INFO(jsl_ehl_steppings),
922
859
};
···
982
919
};
983
920
984
921
static const struct platform_desc tgl_desc = {
985
-
PLATFORM(TIGERLAKE),
922
+
PLATFORM(tigerlake),
986
923
.subplatforms = (const struct subplatform_desc[]) {
987
-
{ INTEL_DISPLAY_TIGERLAKE_UY, "UY", tgl_uy_ids,
988
-
STEP_INFO(tgl_uy_steppings) },
924
+
{
925
+
SUBPLATFORM(tigerlake, uy),
926
+
.pciidlist = tgl_uy_ids,
927
+
STEP_INFO(tgl_uy_steppings),
928
+
},
989
929
{},
990
930
},
991
931
.info = &(const struct intel_display_device_info) {
···
1010
944
};
1011
945
1012
946
static const struct platform_desc dg1_desc = {
1013
-
PLATFORM(DG1),
947
+
PLATFORM(dg1),
1014
948
.info = &(const struct intel_display_device_info) {
1015
949
XE_D_DISPLAY,
1016
950
···
1027
961
};
1028
962
1029
963
static const struct platform_desc rkl_desc = {
1030
-
PLATFORM(ROCKETLAKE),
964
+
PLATFORM(rocketlake),
1031
965
.info = &(const struct intel_display_device_info) {
1032
966
XE_D_DISPLAY,
1033
967
.abox_mask = BIT(0),
···
1062
996
};
1063
997
1064
998
static const struct platform_desc adl_s_desc = {
1065
-
PLATFORM(ALDERLAKE_S),
999
+
PLATFORM(alderlake_s),
1066
1000
.subplatforms = (const struct subplatform_desc[]) {
1067
-
{ INTEL_DISPLAY_ALDERLAKE_S_RAPTORLAKE_S, "RPL-S", adls_rpls_ids,
1068
-
STEP_INFO(adl_s_rpl_s_steppings) },
1001
+
{
1002
+
SUBPLATFORM(alderlake_s, raptorlake_s),
1003
+
.pciidlist = adls_rpls_ids,
1004
+
STEP_INFO(adl_s_rpl_s_steppings),
1005
+
},
1069
1006
{},
1070
1007
},
1071
1008
.info = &(const struct intel_display_device_info) {
···
1169
1100
};
1170
1101
1171
1102
static const struct platform_desc adl_p_desc = {
1172
-
PLATFORM(ALDERLAKE_P),
1103
+
PLATFORM(alderlake_p),
1173
1104
.subplatforms = (const struct subplatform_desc[]) {
1174
-
{ INTEL_DISPLAY_ALDERLAKE_P_ALDERLAKE_N, "ADL-N", adlp_adln_ids,
1175
-
STEP_INFO(adl_p_adl_n_steppings) },
1176
-
{ INTEL_DISPLAY_ALDERLAKE_P_RAPTORLAKE_P, "RPL-P", adlp_rplp_ids,
1177
-
STEP_INFO(adl_p_rpl_pu_steppings) },
1178
-
{ INTEL_DISPLAY_ALDERLAKE_P_RAPTORLAKE_U, "RPL-U", adlp_rplu_ids,
1179
-
STEP_INFO(adl_p_rpl_pu_steppings) },
1105
+
{
1106
+
SUBPLATFORM(alderlake_p, alderlake_n),
1107
+
.pciidlist = adlp_adln_ids,
1108
+
STEP_INFO(adl_p_adl_n_steppings),
1109
+
},
1110
+
{
1111
+
SUBPLATFORM(alderlake_p, raptorlake_p),
1112
+
.pciidlist = adlp_rplp_ids,
1113
+
STEP_INFO(adl_p_rpl_pu_steppings),
1114
+
},
1115
+
{
1116
+
SUBPLATFORM(alderlake_p, raptorlake_u),
1117
+
.pciidlist = adlp_rplu_ids,
1118
+
STEP_INFO(adl_p_rpl_pu_steppings),
1119
+
},
1180
1120
{},
1181
1121
},
1182
1122
.info = &xe_lpd_display,
···
1237
1159
};
1238
1160
1239
1161
static const struct platform_desc dg2_desc = {
1240
-
PLATFORM(DG2),
1162
+
PLATFORM(dg2),
1241
1163
.subplatforms = (const struct subplatform_desc[]) {
1242
-
{ INTEL_DISPLAY_DG2_G10, "G10", dg2_g10_ids,
1243
-
STEP_INFO(dg2_g10_steppings) },
1244
-
{ INTEL_DISPLAY_DG2_G11, "G11", dg2_g11_ids,
1245
-
STEP_INFO(dg2_g11_steppings) },
1246
-
{ INTEL_DISPLAY_DG2_G12, "G12", dg2_g12_ids,
1247
-
STEP_INFO(dg2_g12_steppings) },
1164
+
{
1165
+
SUBPLATFORM(dg2, g10),
1166
+
.pciidlist = dg2_g10_ids,
1167
+
STEP_INFO(dg2_g10_steppings),
1168
+
},
1169
+
{
1170
+
SUBPLATFORM(dg2, g11),
1171
+
.pciidlist = dg2_g11_ids,
1172
+
STEP_INFO(dg2_g11_steppings),
1173
+
},
1174
+
{
1175
+
SUBPLATFORM(dg2, g12),
1176
+
.pciidlist = dg2_g12_ids,
1177
+
STEP_INFO(dg2_g12_steppings),
1178
+
},
1248
1179
{},
1249
1180
},
1250
1181
.info = &xe_hpd_display,
···
1314
1227
.__runtime_defaults.fbc_mask =
1315
1228
BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) |
1316
1229
BIT(INTEL_FBC_C) | BIT(INTEL_FBC_D),
1230
+
.__runtime_defaults.has_dbuf_overlap_detection = true,
1317
1231
};
1318
1232
1319
1233
static const struct intel_display_device_info xe2_hpd_display = {
···
1329
1241
* reported by the hardware.
1330
1242
*/
1331
1243
static const struct platform_desc mtl_desc = {
1332
-
PLATFORM(METEORLAKE),
1244
+
PLATFORM(meteorlake),
1333
1245
};
1334
1246
1335
1247
static const struct platform_desc lnl_desc = {
1336
-
PLATFORM(LUNARLAKE),
1248
+
PLATFORM(lunarlake),
1337
1249
};
1338
1250
1339
1251
static const struct platform_desc bmg_desc = {
1340
-
PLATFORM(BATTLEMAGE),
1252
+
PLATFORM(battlemage),
1253
+
};
1254
+
1255
+
static const struct platform_desc ptl_desc = {
1256
+
PLATFORM(pantherlake),
1341
1257
};
1342
1258
1343
1259
__diag_pop();
···
1414
1322
INTEL_MTL_IDS(INTEL_DISPLAY_DEVICE, &mtl_desc),
1415
1323
INTEL_LNL_IDS(INTEL_DISPLAY_DEVICE, &lnl_desc),
1416
1324
INTEL_BMG_IDS(INTEL_DISPLAY_DEVICE, &bmg_desc),
1325
+
INTEL_PTL_IDS(INTEL_DISPLAY_DEVICE, &ptl_desc),
1417
1326
};
1418
1327
1419
1328
static const struct {
···
1425
1332
{ 14, 0, &xe_lpdp_display },
1426
1333
{ 14, 1, &xe2_hpd_display },
1427
1334
{ 20, 0, &xe2_lpd_display },
1335
+
{ 30, 0, &xe2_lpd_display },
1428
1336
};
1429
1337
1430
1338
static const struct intel_display_device_info *
···
1486
1392
const struct subplatform_desc *sp;
1487
1393
const u16 *id;
1488
1394
1489
-
for (sp = desc->subplatforms; sp && sp->subplatform; sp++)
1395
+
for (sp = desc->subplatforms; sp && sp->pciidlist; sp++)
1490
1396
for (id = sp->pciidlist; *id; id++)
1491
1397
if (*id == pdev->device)
1492
1398
return sp;
···
1545
1451
return step;
1546
1452
}
1547
1453
1454
+
/* Size of the entire bitmap, not the number of platforms */
1455
+
static unsigned int display_platforms_num_bits(void)
1456
+
{
1457
+
return sizeof(((struct intel_display_platforms *)0)->bitmap) * BITS_PER_BYTE;
1458
+
}
1459
+
1460
+
/* Number of platform bits set */
1461
+
static unsigned int display_platforms_weight(const struct intel_display_platforms *p)
1462
+
{
1463
+
return bitmap_weight(p->bitmap, display_platforms_num_bits());
1464
+
}
1465
+
1466
+
/* Merge the subplatform information from src to dst */
1467
+
static void display_platforms_or(struct intel_display_platforms *dst,
1468
+
const struct intel_display_platforms *src)
1469
+
{
1470
+
bitmap_or(dst->bitmap, dst->bitmap, src->bitmap, display_platforms_num_bits());
1471
+
}
1472
+
1548
1473
void intel_display_device_probe(struct drm_i915_private *i915)
1549
1474
{
1550
1475
struct intel_display *display = &i915->display;
···
1603
1490
&DISPLAY_INFO(i915)->__runtime_defaults,
1604
1491
sizeof(*DISPLAY_RUNTIME_INFO(i915)));
1605
1492
1606
-
drm_WARN_ON(&i915->drm, !desc->platform || !desc->name);
1607
-
DISPLAY_RUNTIME_INFO(i915)->platform = desc->platform;
1493
+
drm_WARN_ON(&i915->drm, !desc->name ||
1494
+
!display_platforms_weight(&desc->platforms));
1495
+
1496
+
display->platform = desc->platforms;
1608
1497
1609
1498
subdesc = find_subplatform_desc(pdev, desc);
1610
1499
if (subdesc) {
1611
-
drm_WARN_ON(&i915->drm, !subdesc->subplatform || !subdesc->name);
1612
-
DISPLAY_RUNTIME_INFO(i915)->subplatform = subdesc->subplatform;
1500
+
drm_WARN_ON(&i915->drm, !subdesc->name ||
1501
+
!display_platforms_weight(&subdesc->platforms));
1502
+
1503
+
display_platforms_or(&display->platform, &subdesc->platforms);
1504
+
1505
+
/* Ensure platform and subplatform are distinct */
1506
+
drm_WARN_ON(&i915->drm,
1507
+
display_platforms_weight(&display->platform) !=
1508
+
display_platforms_weight(&desc->platforms) +
1509
+
display_platforms_weight(&subdesc->platforms));
1613
1510
}
1614
1511
1615
1512
if (ip_ver.ver || ip_ver.rel || ip_ver.step) {
···
1776
1653
if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
1777
1654
display_runtime->has_hdcp = 0;
1778
1655
1779
-
if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
1780
-
display_runtime->fbc_mask = 0;
1656
+
if (IS_DG2(i915) || DISPLAY_VER(i915) < 13) {
1657
+
if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
1658
+
display_runtime->fbc_mask = 0;
1659
+
}
1781
1660
1782
1661
if (DISPLAY_VER(i915) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
1783
1662
display_runtime->has_dmc = 0;
···
1787
1662
if (IS_DISPLAY_VER(i915, 10, 12) &&
1788
1663
(dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE))
1789
1664
display_runtime->has_dsc = 0;
1665
+
1666
+
if (DISPLAY_VER(display) >= 20 &&
1667
+
(dfsm & XE2LPD_DFSM_DBUF_OVERLAP_DISABLE))
1668
+
display_runtime->has_dbuf_overlap_detection = false;
1790
1669
}
1791
1670
1792
1671
if (DISPLAY_VER(i915) >= 20) {
···
1807
1678
display_runtime->num_scalers[pipe] = 1;
1808
1679
}
1809
1680
}
1681
+
1682
+
if (DISPLAY_VER(i915) >= 30)
1683
+
display_runtime->edp_typec_support =
1684
+
intel_de_read(display, PICA_PHY_CONFIG_CONTROL) & EDP_ON_TYPEC;
1810
1685
1811
1686
display_runtime->rawclk_freq = intel_read_rawclk(display);
1812
1687
drm_dbg_kms(&i915->drm, "rawclk rate: %d kHz\n", display_runtime->rawclk_freq);
+113
-93
drivers/gpu/drm/i915/display/intel_display_device.h
+113
-93
drivers/gpu/drm/i915/display/intel_display_device.h
···
6
6
#ifndef __INTEL_DISPLAY_DEVICE_H__
7
7
#define __INTEL_DISPLAY_DEVICE_H__
8
8
9
+
#include <linux/bitops.h>
9
10
#include <linux/types.h>
10
11
11
12
#include "intel_display_conversion.h"
···
15
14
struct drm_i915_private;
16
15
struct drm_printer;
17
16
18
-
/* Keep in gen based order, and chronological order within a gen */
19
-
enum intel_display_platform {
20
-
INTEL_DISPLAY_PLATFORM_UNINITIALIZED = 0,
21
-
/* Display ver 2 */
22
-
INTEL_DISPLAY_I830,
23
-
INTEL_DISPLAY_I845G,
24
-
INTEL_DISPLAY_I85X,
25
-
INTEL_DISPLAY_I865G,
26
-
/* Display ver 3 */
27
-
INTEL_DISPLAY_I915G,
28
-
INTEL_DISPLAY_I915GM,
29
-
INTEL_DISPLAY_I945G,
30
-
INTEL_DISPLAY_I945GM,
31
-
INTEL_DISPLAY_G33,
32
-
INTEL_DISPLAY_PINEVIEW,
33
-
/* Display ver 4 */
34
-
INTEL_DISPLAY_I965G,
35
-
INTEL_DISPLAY_I965GM,
36
-
INTEL_DISPLAY_G45,
37
-
INTEL_DISPLAY_GM45,
38
-
/* Display ver 5 */
39
-
INTEL_DISPLAY_IRONLAKE,
40
-
/* Display ver 6 */
41
-
INTEL_DISPLAY_SANDYBRIDGE,
42
-
/* Display ver 7 */
43
-
INTEL_DISPLAY_IVYBRIDGE,
44
-
INTEL_DISPLAY_VALLEYVIEW,
45
-
INTEL_DISPLAY_HASWELL,
46
-
/* Display ver 8 */
47
-
INTEL_DISPLAY_BROADWELL,
48
-
INTEL_DISPLAY_CHERRYVIEW,
49
-
/* Display ver 9 */
50
-
INTEL_DISPLAY_SKYLAKE,
51
-
INTEL_DISPLAY_BROXTON,
52
-
INTEL_DISPLAY_KABYLAKE,
53
-
INTEL_DISPLAY_GEMINILAKE,
54
-
INTEL_DISPLAY_COFFEELAKE,
55
-
INTEL_DISPLAY_COMETLAKE,
56
-
/* Display ver 11 */
57
-
INTEL_DISPLAY_ICELAKE,
58
-
INTEL_DISPLAY_JASPERLAKE,
59
-
INTEL_DISPLAY_ELKHARTLAKE,
60
-
/* Display ver 12 */
61
-
INTEL_DISPLAY_TIGERLAKE,
62
-
INTEL_DISPLAY_ROCKETLAKE,
63
-
INTEL_DISPLAY_DG1,
64
-
INTEL_DISPLAY_ALDERLAKE_S,
65
-
/* Display ver 13 */
66
-
INTEL_DISPLAY_ALDERLAKE_P,
67
-
INTEL_DISPLAY_DG2,
68
-
/* Display ver 14 (based on GMD ID) */
69
-
INTEL_DISPLAY_METEORLAKE,
70
-
/* Display ver 20 (based on GMD ID) */
71
-
INTEL_DISPLAY_LUNARLAKE,
72
-
/* Display ver 14.1 (based on GMD ID) */
73
-
INTEL_DISPLAY_BATTLEMAGE,
17
+
/*
18
+
* Display platforms and subplatforms. Keep platforms in display version based
19
+
* order, chronological order within a version, and subplatforms next to the
20
+
* platform.
21
+
*/
22
+
#define INTEL_DISPLAY_PLATFORMS(func) \
23
+
/* Display ver 2 */ \
24
+
func(i830) \
25
+
func(i845g) \
26
+
func(i85x) \
27
+
func(i865g) \
28
+
/* Display ver 3 */ \
29
+
func(i915g) \
30
+
func(i915gm) \
31
+
func(i945g) \
32
+
func(i945gm) \
33
+
func(g33) \
34
+
func(pineview) \
35
+
/* Display ver 4 */ \
36
+
func(i965g) \
37
+
func(i965gm) \
38
+
func(g45) \
39
+
func(gm45) \
40
+
func(g4x) /* group alias for g45 and gm45 */ \
41
+
/* Display ver 5 */ \
42
+
func(ironlake) \
43
+
/* Display ver 6 */ \
44
+
func(sandybridge) \
45
+
/* Display ver 7 */ \
46
+
func(ivybridge) \
47
+
func(valleyview) \
48
+
func(haswell) \
49
+
func(haswell_ult) \
50
+
func(haswell_ulx) \
51
+
/* Display ver 8 */ \
52
+
func(broadwell) \
53
+
func(broadwell_ult) \
54
+
func(broadwell_ulx) \
55
+
func(cherryview) \
56
+
/* Display ver 9 */ \
57
+
func(skylake) \
58
+
func(skylake_ult) \
59
+
func(skylake_ulx) \
60
+
func(broxton) \
61
+
func(kabylake) \
62
+
func(kabylake_ult) \
63
+
func(kabylake_ulx) \
64
+
func(geminilake) \
65
+
func(coffeelake) \
66
+
func(coffeelake_ult) \
67
+
func(coffeelake_ulx) \
68
+
func(cometlake) \
69
+
func(cometlake_ult) \
70
+
func(cometlake_ulx) \
71
+
/* Display ver 11 */ \
72
+
func(icelake) \
73
+
func(icelake_port_f) \
74
+
func(jasperlake) \
75
+
func(elkhartlake) \
76
+
/* Display ver 12 */ \
77
+
func(tigerlake) \
78
+
func(tigerlake_uy) \
79
+
func(rocketlake) \
80
+
func(dg1) \
81
+
func(alderlake_s) \
82
+
func(alderlake_s_raptorlake_s) \
83
+
/* Display ver 13 */ \
84
+
func(alderlake_p) \
85
+
func(alderlake_p_alderlake_n) \
86
+
func(alderlake_p_raptorlake_p) \
87
+
func(alderlake_p_raptorlake_u) \
88
+
func(dg2) \
89
+
func(dg2_g10) \
90
+
func(dg2_g11) \
91
+
func(dg2_g12) \
92
+
/* Display ver 14 (based on GMD ID) */ \
93
+
func(meteorlake) \
94
+
/* Display ver 20 (based on GMD ID) */ \
95
+
func(lunarlake) \
96
+
/* Display ver 14.1 (based on GMD ID) */ \
97
+
func(battlemage) \
98
+
/* Display ver 30 (based on GMD ID) */ \
99
+
func(pantherlake)
100
+
101
+
#define __MEMBER(name) unsigned long name:1;
102
+
#define __COUNT(x) 1 +
103
+
104
+
#define __NUM_PLATFORMS (INTEL_DISPLAY_PLATFORMS(__COUNT) 0)
105
+
106
+
struct intel_display_platforms {
107
+
union {
108
+
struct {
109
+
INTEL_DISPLAY_PLATFORMS(__MEMBER);
110
+
};
111
+
DECLARE_BITMAP(bitmap, __NUM_PLATFORMS);
112
+
};
74
113
};
75
114
76
-
enum intel_display_subplatform {
77
-
INTEL_DISPLAY_SUBPLATFORM_UNINITIALIZED = 0,
78
-
INTEL_DISPLAY_HASWELL_ULT,
79
-
INTEL_DISPLAY_HASWELL_ULX,
80
-
INTEL_DISPLAY_BROADWELL_ULT,
81
-
INTEL_DISPLAY_BROADWELL_ULX,
82
-
INTEL_DISPLAY_SKYLAKE_ULT,
83
-
INTEL_DISPLAY_SKYLAKE_ULX,
84
-
INTEL_DISPLAY_KABYLAKE_ULT,
85
-
INTEL_DISPLAY_KABYLAKE_ULX,
86
-
INTEL_DISPLAY_COFFEELAKE_ULT,
87
-
INTEL_DISPLAY_COFFEELAKE_ULX,
88
-
INTEL_DISPLAY_COMETLAKE_ULT,
89
-
INTEL_DISPLAY_COMETLAKE_ULX,
90
-
INTEL_DISPLAY_ICELAKE_PORT_F,
91
-
INTEL_DISPLAY_TIGERLAKE_UY,
92
-
INTEL_DISPLAY_ALDERLAKE_S_RAPTORLAKE_S,
93
-
INTEL_DISPLAY_ALDERLAKE_P_ALDERLAKE_N,
94
-
INTEL_DISPLAY_ALDERLAKE_P_RAPTORLAKE_P,
95
-
INTEL_DISPLAY_ALDERLAKE_P_RAPTORLAKE_U,
96
-
INTEL_DISPLAY_DG2_G10,
97
-
INTEL_DISPLAY_DG2_G11,
98
-
INTEL_DISPLAY_DG2_G12,
99
-
};
115
+
#undef __MEMBER
116
+
#undef __COUNT
117
+
#undef __NUM_PLATFORMS
100
118
101
119
#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
102
120
/* Keep in alphabetical order */ \
···
143
123
#define HAS_CDCLK_SQUASH(i915) (DISPLAY_INFO(i915)->has_cdclk_squash)
144
124
#define HAS_CUR_FBC(i915) (!HAS_GMCH(i915) && IS_DISPLAY_VER(i915, 7, 13))
145
125
#define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || IS_ALDERLAKE_S(i915))
126
+
#define HAS_DBUF_OVERLAP_DETECTION(__i915) (DISPLAY_RUNTIME_INFO(__i915)->has_dbuf_overlap_detection)
146
127
#define HAS_DDI(i915) (DISPLAY_INFO(i915)->has_ddi)
147
128
#define HAS_DISPLAY(i915) (DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0)
148
129
#define HAS_DMC(i915) (DISPLAY_RUNTIME_INFO(i915)->has_dmc)
···
187
166
#define SUPPORTS_TV(i915) (DISPLAY_INFO(i915)->supports_tv)
188
167
189
168
/* Check that device has a display IP version within the specific range. */
190
-
#define IS_DISPLAY_VER_FULL(__i915, from, until) ( \
191
-
BUILD_BUG_ON_ZERO((from) < IP_VER(2, 0)) + \
192
-
(DISPLAY_VER_FULL(__i915) >= (from) && \
193
-
DISPLAY_VER_FULL(__i915) <= (until)))
169
+
#define IS_DISPLAY_VERx100(__i915, from, until) ( \
170
+
BUILD_BUG_ON_ZERO((from) < 200) + \
171
+
(DISPLAY_VERx100(__i915) >= (from) && \
172
+
DISPLAY_VERx100(__i915) <= (until)))
194
173
195
174
/*
196
175
* Check if a device has a specific IP version as well as a stepping within the
···
201
180
* hardware fix is present and the software workaround is no longer necessary.
202
181
* E.g.,
203
182
*
204
-
* IS_DISPLAY_VER_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_B2)
205
-
* IS_DISPLAY_VER_STEP(i915, IP_VER(14, 0), STEP_C0, STEP_FOREVER)
183
+
* IS_DISPLAY_VERx100_STEP(i915, 1400, STEP_A0, STEP_B2)
184
+
* IS_DISPLAY_VERx100_STEP(i915, 1400, STEP_C0, STEP_FOREVER)
206
185
*
207
186
* "STEP_FOREVER" can be passed as "until" for workarounds that have no upper
208
187
* stepping bound for the specified IP version.
209
188
*/
210
-
#define IS_DISPLAY_VER_STEP(__i915, ipver, from, until) \
211
-
(IS_DISPLAY_VER_FULL((__i915), (ipver), (ipver)) && \
189
+
#define IS_DISPLAY_VERx100_STEP(__i915, ipver, from, until) \
190
+
(IS_DISPLAY_VERx100((__i915), (ipver), (ipver)) && \
212
191
IS_DISPLAY_STEP((__i915), (from), (until)))
213
192
214
193
#define DISPLAY_INFO(i915) (__to_intel_display(i915)->info.__device_info)
215
194
#define DISPLAY_RUNTIME_INFO(i915) (&__to_intel_display(i915)->info.__runtime_info)
216
195
217
196
#define DISPLAY_VER(i915) (DISPLAY_RUNTIME_INFO(i915)->ip.ver)
218
-
#define DISPLAY_VER_FULL(i915) IP_VER(DISPLAY_RUNTIME_INFO(i915)->ip.ver, \
219
-
DISPLAY_RUNTIME_INFO(i915)->ip.rel)
197
+
#define DISPLAY_VERx100(i915) (DISPLAY_RUNTIME_INFO(i915)->ip.ver * 100 + \
198
+
DISPLAY_RUNTIME_INFO(i915)->ip.rel)
220
199
#define IS_DISPLAY_VER(i915, from, until) \
221
200
(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
222
201
···
227
206
INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until))
228
207
229
208
struct intel_display_runtime_info {
230
-
enum intel_display_platform platform;
231
-
enum intel_display_subplatform subplatform;
232
-
233
209
struct intel_display_ip_ver {
234
210
u16 ver;
235
211
u16 rel;
···
248
230
bool has_hdcp;
249
231
bool has_dmc;
250
232
bool has_dsc;
233
+
bool edp_typec_support;
234
+
bool has_dbuf_overlap_detection;
251
235
};
252
236
253
237
struct intel_display_device_info {
+8
-7
drivers/gpu/drm/i915/display/intel_display_driver.c
+8
-7
drivers/gpu/drm/i915/display/intel_display_driver.c
···
194
194
195
195
intel_display_irq_init(i915);
196
196
intel_dkl_phy_init(i915);
197
-
intel_color_init_hooks(i915);
197
+
intel_color_init_hooks(&i915->display);
198
198
intel_init_cdclk_hooks(&i915->display);
199
199
intel_audio_hooks_init(i915);
200
200
intel_dpll_init_clock_hook(i915);
···
249
249
if (ret)
250
250
goto cleanup_vga_client_pw_domain_dmc;
251
251
252
-
ret = intel_color_init(i915);
252
+
ret = intel_color_init(display);
253
253
if (ret)
254
254
goto cleanup_vga_client_pw_domain_dmc;
255
255
···
432
432
433
433
intel_pps_setup(display);
434
434
435
-
intel_gmbus_setup(i915);
435
+
intel_gmbus_setup(display);
436
436
437
437
drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
438
438
INTEL_NUM_PIPES(i915),
···
485
485
return 0;
486
486
487
487
err_hdcp:
488
-
intel_hdcp_component_fini(i915);
488
+
intel_hdcp_component_fini(display);
489
489
err_mode_config:
490
490
intel_mode_config_cleanup(i915);
491
491
···
495
495
/* part #3: call after gem init */
496
496
int intel_display_driver_probe(struct drm_i915_private *i915)
497
497
{
498
+
struct intel_display *display = &i915->display;
498
499
int ret;
499
500
500
501
if (!HAS_DISPLAY(i915))
···
506
505
* the BIOS fb takeover and whatever else magic ggtt reservations
507
506
* happen during gem/ggtt init.
508
507
*/
509
-
intel_hdcp_component_init(i915);
508
+
intel_hdcp_component_init(display);
510
509
511
510
/*
512
511
* Force all active planes to recompute their states. So that on
···
601
600
/* flush any delayed tasks or pending work */
602
601
flush_workqueue(i915->unordered_wq);
603
602
604
-
intel_hdcp_component_fini(i915);
603
+
intel_hdcp_component_fini(display);
605
604
606
605
intel_mode_config_cleanup(i915);
607
606
···
609
608
610
609
intel_overlay_cleanup(i915);
611
610
612
-
intel_gmbus_teardown(i915);
611
+
intel_gmbus_teardown(display);
613
612
614
613
destroy_workqueue(i915->display.wq.flip);
615
614
destroy_workqueue(i915->display.wq.modeset);
+48
-50
drivers/gpu/drm/i915/display/intel_display_irq.c
+48
-50
drivers/gpu/drm/i915/display/intel_display_irq.c
···
543
543
intel_opregion_asle_intr(display);
544
544
545
545
if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
546
-
intel_gmbus_irq_handler(dev_priv);
546
+
intel_gmbus_irq_handler(display);
547
547
}
548
548
549
549
void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
550
550
u32 pipe_stats[I915_MAX_PIPES])
551
551
{
552
+
struct intel_display *display = &dev_priv->display;
552
553
enum pipe pipe;
553
554
554
555
for_each_pipe(dev_priv, pipe) {
···
567
566
}
568
567
569
568
if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
570
-
intel_gmbus_irq_handler(dev_priv);
569
+
intel_gmbus_irq_handler(display);
571
570
}
572
571
573
572
static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
···
589
588
intel_dp_aux_irq_handler(display);
590
589
591
590
if (pch_iir & SDE_GMBUS)
592
-
intel_gmbus_irq_handler(dev_priv);
591
+
intel_gmbus_irq_handler(display);
593
592
594
593
if (pch_iir & SDE_AUDIO_HDCP_MASK)
595
594
drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n");
···
678
677
intel_dp_aux_irq_handler(display);
679
678
680
679
if (pch_iir & SDE_GMBUS_CPT)
681
-
intel_gmbus_irq_handler(dev_priv);
680
+
intel_gmbus_irq_handler(display);
682
681
683
682
if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
684
683
drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n");
···
903
902
struct intel_display *display = &dev_priv->display;
904
903
bool found = false;
905
904
905
+
if (HAS_DBUF_OVERLAP_DETECTION(display)) {
906
+
if (iir & XE2LPD_DBUF_OVERLAP_DETECTED) {
907
+
drm_warn(display->drm, "DBuf overlap detected\n");
908
+
found = true;
909
+
}
910
+
}
911
+
906
912
if (DISPLAY_VER(dev_priv) >= 14) {
907
913
if (iir & (XELPDP_PMDEMAND_RSP |
908
914
XELPDP_PMDEMAND_RSPTOUT_ERR)) {
···
1029
1021
return GEN8_PIPE_PRIMARY_FLIP_DONE;
1030
1022
}
1031
1023
1032
-
u32 gen8_de_pipe_underrun_mask(struct drm_i915_private *dev_priv)
1033
-
{
1034
-
u32 mask = GEN8_PIPE_FIFO_UNDERRUN;
1035
-
1036
-
if (DISPLAY_VER(dev_priv) >= 13)
1037
-
mask |= XELPD_PIPE_SOFT_UNDERRUN |
1038
-
XELPD_PIPE_HARD_UNDERRUN;
1039
-
1040
-
return mask;
1041
-
}
1042
-
1043
1024
static void gen8_read_and_ack_pch_irqs(struct drm_i915_private *i915, u32 *pch_iir, u32 *pica_iir)
1044
1025
{
1045
1026
u32 pica_ier = 0;
···
1117
1120
1118
1121
if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1119
1122
(iir & BXT_DE_PORT_GMBUS)) {
1120
-
intel_gmbus_irq_handler(dev_priv);
1123
+
intel_gmbus_irq_handler(display);
1121
1124
found = true;
1122
1125
}
1123
1126
···
1174
1177
if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
1175
1178
hsw_pipe_crc_irq_handler(dev_priv, pipe);
1176
1179
1177
-
if (iir & gen8_de_pipe_underrun_mask(dev_priv))
1180
+
if (iir & GEN8_PIPE_FIFO_UNDERRUN)
1178
1181
intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1179
1182
1180
1183
fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);
···
1421
1424
struct intel_display *display =
1422
1425
container_of(work, typeof(*display), irq.vblank_dc_work);
1423
1426
struct drm_i915_private *i915 = to_i915(display->drm);
1424
-
u8 vblank_enabled = READ_ONCE(display->irq.vblank_enabled);
1427
+
int vblank_wa_num_pipes = READ_ONCE(display->irq.vblank_wa_num_pipes);
1425
1428
1426
1429
/*
1427
1430
* NOTE: intel_display_power_set_target_dc_state is used only by PSR
···
1429
1432
* PSR code. If DC3CO is taken into use we need take that into account
1430
1433
* here as well.
1431
1434
*/
1432
-
intel_display_power_set_target_dc_state(i915, vblank_enabled ? DC_STATE_DISABLE :
1435
+
intel_display_power_set_target_dc_state(i915, vblank_wa_num_pipes ? DC_STATE_DISABLE :
1433
1436
DC_STATE_EN_UPTO_DC6);
1434
1437
}
1435
1438
···
1444
1447
if (gen11_dsi_configure_te(crtc, true))
1445
1448
return 0;
1446
1449
1447
-
if (display->irq.vblank_enabled++ == 0 && crtc->block_dc_for_vblank)
1450
+
if (crtc->block_dc_for_vblank && display->irq.vblank_wa_num_pipes++ == 0)
1448
1451
schedule_work(&display->irq.vblank_dc_work);
1449
1452
1450
1453
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
···
1475
1478
bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
1476
1479
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1477
1480
1478
-
if (--display->irq.vblank_enabled == 0 && crtc->block_dc_for_vblank)
1481
+
if (crtc->block_dc_for_vblank && --display->irq.vblank_wa_num_pipes == 0)
1479
1482
schedule_work(&display->irq.vblank_dc_work);
1480
1483
}
1481
1484
···
1493
1496
1494
1497
i9xx_pipestat_irq_reset(dev_priv);
1495
1498
1496
-
gen3_irq_reset(uncore, VLV_IRQ_REGS);
1499
+
gen2_irq_reset(uncore, VLV_IRQ_REGS);
1497
1500
dev_priv->irq_mask = ~0u;
1498
1501
}
1499
1502
···
1536
1539
1537
1540
dev_priv->irq_mask = ~enable_mask;
1538
1541
1539
-
gen3_irq_init(uncore, VLV_IRQ_REGS, dev_priv->irq_mask, enable_mask);
1542
+
gen2_irq_init(uncore, VLV_IRQ_REGS, dev_priv->irq_mask, enable_mask);
1540
1543
}
1541
1544
1542
1545
void gen8_display_irq_reset(struct drm_i915_private *dev_priv)
···
1553
1556
for_each_pipe(dev_priv, pipe)
1554
1557
if (intel_display_power_is_enabled(dev_priv,
1555
1558
POWER_DOMAIN_PIPE(pipe)))
1556
-
gen3_irq_reset(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe));
1559
+
gen2_irq_reset(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe));
1557
1560
1558
-
gen3_irq_reset(uncore, GEN8_DE_PORT_IRQ_REGS);
1559
-
gen3_irq_reset(uncore, GEN8_DE_MISC_IRQ_REGS);
1561
+
gen2_irq_reset(uncore, GEN8_DE_PORT_IRQ_REGS);
1562
+
gen2_irq_reset(uncore, GEN8_DE_MISC_IRQ_REGS);
1560
1563
}
1561
1564
1562
1565
void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
···
1596
1599
for_each_pipe(dev_priv, pipe)
1597
1600
if (intel_display_power_is_enabled(dev_priv,
1598
1601
POWER_DOMAIN_PIPE(pipe)))
1599
-
gen3_irq_reset(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe));
1602
+
gen2_irq_reset(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe));
1600
1603
1601
-
gen3_irq_reset(uncore, GEN8_DE_PORT_IRQ_REGS);
1602
-
gen3_irq_reset(uncore, GEN8_DE_MISC_IRQ_REGS);
1604
+
gen2_irq_reset(uncore, GEN8_DE_PORT_IRQ_REGS);
1605
+
gen2_irq_reset(uncore, GEN8_DE_MISC_IRQ_REGS);
1603
1606
1604
1607
if (DISPLAY_VER(dev_priv) >= 14)
1605
-
gen3_irq_reset(uncore, PICAINTERRUPT_IRQ_REGS);
1608
+
gen2_irq_reset(uncore, PICAINTERRUPT_IRQ_REGS);
1606
1609
else
1607
-
gen3_irq_reset(uncore, GEN11_DE_HPD_IRQ_REGS);
1610
+
gen2_irq_reset(uncore, GEN11_DE_HPD_IRQ_REGS);
1608
1611
1609
1612
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
1610
-
gen3_irq_reset(uncore, SDE_IRQ_REGS);
1613
+
gen2_irq_reset(uncore, SDE_IRQ_REGS);
1611
1614
}
1612
1615
1613
1616
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1614
1617
u8 pipe_mask)
1615
1618
{
1616
1619
struct intel_uncore *uncore = &dev_priv->uncore;
1617
-
u32 extra_ier = GEN8_PIPE_VBLANK |
1618
-
gen8_de_pipe_underrun_mask(dev_priv) |
1620
+
u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN |
1619
1621
gen8_de_pipe_flip_done_mask(dev_priv);
1620
1622
enum pipe pipe;
1621
1623
···
1626
1630
}
1627
1631
1628
1632
for_each_pipe_masked(dev_priv, pipe, pipe_mask)
1629
-
gen3_irq_init(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe),
1633
+
gen2_irq_init(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe),
1630
1634
dev_priv->display.irq.de_irq_mask[pipe],
1631
1635
~dev_priv->display.irq.de_irq_mask[pipe] | extra_ier);
1632
1636
···
1647
1651
}
1648
1652
1649
1653
for_each_pipe_masked(dev_priv, pipe, pipe_mask)
1650
-
gen3_irq_reset(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe));
1654
+
gen2_irq_reset(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe));
1651
1655
1652
1656
spin_unlock_irq(&dev_priv->irq_lock);
1653
1657
···
1681
1685
else
1682
1686
mask = SDE_GMBUS_CPT;
1683
1687
1684
-
gen3_irq_init(uncore, SDE_IRQ_REGS, ~mask, 0xffffffff);
1688
+
gen2_irq_init(uncore, SDE_IRQ_REGS, ~mask, 0xffffffff);
1685
1689
}
1686
1690
1687
1691
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
···
1738
1742
}
1739
1743
1740
1744
if (IS_HASWELL(i915)) {
1741
-
gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
1745
+
gen2_assert_iir_is_zero(uncore, EDP_PSR_IIR);
1742
1746
display_mask |= DE_EDP_PSR_INT_HSW;
1743
1747
}
1744
1748
···
1749
1753
1750
1754
ibx_irq_postinstall(i915);
1751
1755
1752
-
gen3_irq_init(uncore, DE_IRQ_REGS, i915->irq_mask,
1756
+
gen2_irq_init(uncore, DE_IRQ_REGS, i915->irq_mask,
1753
1757
display_mask | extra_mask);
1754
1758
}
1755
1759
···
1797
1801
de_port_masked |= DSI0_TE | DSI1_TE;
1798
1802
}
1799
1803
1804
+
if (HAS_DBUF_OVERLAP_DETECTION(display))
1805
+
de_misc_masked |= XE2LPD_DBUF_OVERLAP_DETECTED;
1806
+
1800
1807
if (HAS_DSB(dev_priv))
1801
1808
de_pipe_masked |= GEN12_DSB_INT(INTEL_DSB_0) |
1802
1809
GEN12_DSB_INT(INTEL_DSB_1) |
1803
1810
GEN12_DSB_INT(INTEL_DSB_2);
1804
1811
1805
1812
de_pipe_enables = de_pipe_masked |
1806
-
GEN8_PIPE_VBLANK |
1807
-
gen8_de_pipe_underrun_mask(dev_priv) |
1813
+
GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN |
1808
1814
gen8_de_pipe_flip_done_mask(dev_priv);
1809
1815
1810
1816
de_port_enables = de_port_masked;
···
1825
1827
if (!intel_display_power_is_enabled(dev_priv, domain))
1826
1828
continue;
1827
1829
1828
-
gen3_assert_iir_is_zero(uncore,
1830
+
gen2_assert_iir_is_zero(uncore,
1829
1831
TRANS_PSR_IIR(dev_priv, trans));
1830
1832
}
1831
1833
} else {
1832
-
gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
1834
+
gen2_assert_iir_is_zero(uncore, EDP_PSR_IIR);
1833
1835
}
1834
1836
1835
1837
for_each_pipe(dev_priv, pipe) {
···
1837
1839
1838
1840
if (intel_display_power_is_enabled(dev_priv,
1839
1841
POWER_DOMAIN_PIPE(pipe)))
1840
-
gen3_irq_init(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe),
1842
+
gen2_irq_init(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe),
1841
1843
dev_priv->display.irq.de_irq_mask[pipe],
1842
1844
de_pipe_enables);
1843
1845
}
1844
1846
1845
-
gen3_irq_init(uncore, GEN8_DE_PORT_IRQ_REGS, ~de_port_masked, de_port_enables);
1846
-
gen3_irq_init(uncore, GEN8_DE_MISC_IRQ_REGS, ~de_misc_masked, de_misc_masked);
1847
+
gen2_irq_init(uncore, GEN8_DE_PORT_IRQ_REGS, ~de_port_masked, de_port_enables);
1848
+
gen2_irq_init(uncore, GEN8_DE_MISC_IRQ_REGS, ~de_misc_masked, de_misc_masked);
1847
1849
1848
1850
if (IS_DISPLAY_VER(dev_priv, 11, 13)) {
1849
1851
u32 de_hpd_masked = 0;
1850
1852
u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK |
1851
1853
GEN11_DE_TBT_HOTPLUG_MASK;
1852
1854
1853
-
gen3_irq_init(uncore, GEN11_DE_HPD_IRQ_REGS, ~de_hpd_masked,
1855
+
gen2_irq_init(uncore, GEN11_DE_HPD_IRQ_REGS, ~de_hpd_masked,
1854
1856
de_hpd_enables);
1855
1857
}
1856
1858
}
···
1863
1865
u32 de_hpd_enables = de_hpd_mask | XELPDP_DP_ALT_HOTPLUG_MASK |
1864
1866
XELPDP_TBT_HOTPLUG_MASK;
1865
1867
1866
-
gen3_irq_init(uncore, PICAINTERRUPT_IRQ_REGS, ~de_hpd_mask,
1868
+
gen2_irq_init(uncore, PICAINTERRUPT_IRQ_REGS, ~de_hpd_mask,
1867
1869
de_hpd_enables);
1868
1870
1869
-
gen3_irq_init(uncore, SDE_IRQ_REGS, ~sde_mask, 0xffffffff);
1871
+
gen2_irq_init(uncore, SDE_IRQ_REGS, ~sde_mask, 0xffffffff);
1870
1872
}
1871
1873
1872
1874
static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
···
1874
1876
struct intel_uncore *uncore = &dev_priv->uncore;
1875
1877
u32 mask = SDE_GMBUS_ICP;
1876
1878
1877
-
gen3_irq_init(uncore, SDE_IRQ_REGS, ~mask, 0xffffffff);
1879
+
gen2_irq_init(uncore, SDE_IRQ_REGS, ~mask, 0xffffffff);
1878
1880
}
1879
1881
1880
1882
void gen11_de_irq_postinstall(struct drm_i915_private *dev_priv)
-1
drivers/gpu/drm/i915/display/intel_display_irq.h
-1
drivers/gpu/drm/i915/display/intel_display_irq.h
···
33
33
34
34
void gen8_irq_power_well_post_enable(struct drm_i915_private *i915, u8 pipe_mask);
35
35
void gen8_irq_power_well_pre_disable(struct drm_i915_private *i915, u8 pipe_mask);
36
-
u32 gen8_de_pipe_underrun_mask(struct drm_i915_private *i915);
37
36
38
37
int i8xx_enable_vblank(struct drm_crtc *crtc);
39
38
int i915gm_enable_vblank(struct drm_crtc *crtc);
+38
-37
drivers/gpu/drm/i915/display/intel_display_power.c
+38
-37
drivers/gpu/drm/i915/display/intel_display_power.c
···
1176
1176
1177
1177
static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
1178
1178
{
1179
+
struct intel_display *display = &dev_priv->display;
1179
1180
struct intel_crtc *crtc;
1180
1181
1181
-
for_each_intel_crtc(&dev_priv->drm, crtc)
1182
-
I915_STATE_WARN(dev_priv, crtc->active,
1183
-
"CRTC for pipe %c enabled\n",
1184
-
pipe_name(crtc->pipe));
1182
+
for_each_intel_crtc(display->drm, crtc)
1183
+
INTEL_DISPLAY_STATE_WARN(display, crtc->active,
1184
+
"CRTC for pipe %c enabled\n",
1185
+
pipe_name(crtc->pipe));
1185
1186
1186
-
I915_STATE_WARN(dev_priv, intel_de_read(dev_priv, HSW_PWR_WELL_CTL2),
1187
-
"Display power well on\n");
1188
-
I915_STATE_WARN(dev_priv,
1189
-
intel_de_read(dev_priv, SPLL_CTL) & SPLL_PLL_ENABLE,
1190
-
"SPLL enabled\n");
1191
-
I915_STATE_WARN(dev_priv,
1192
-
intel_de_read(dev_priv, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE,
1193
-
"WRPLL1 enabled\n");
1194
-
I915_STATE_WARN(dev_priv,
1195
-
intel_de_read(dev_priv, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE,
1196
-
"WRPLL2 enabled\n");
1197
-
I915_STATE_WARN(dev_priv,
1198
-
intel_de_read(dev_priv, PP_STATUS(dev_priv, 0)) & PP_ON,
1199
-
"Panel power on\n");
1200
-
I915_STATE_WARN(dev_priv,
1201
-
intel_de_read(dev_priv, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
1202
-
"CPU PWM1 enabled\n");
1187
+
INTEL_DISPLAY_STATE_WARN(display, intel_de_read(display, HSW_PWR_WELL_CTL2),
1188
+
"Display power well on\n");
1189
+
INTEL_DISPLAY_STATE_WARN(display,
1190
+
intel_de_read(display, SPLL_CTL) & SPLL_PLL_ENABLE,
1191
+
"SPLL enabled\n");
1192
+
INTEL_DISPLAY_STATE_WARN(display,
1193
+
intel_de_read(display, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE,
1194
+
"WRPLL1 enabled\n");
1195
+
INTEL_DISPLAY_STATE_WARN(display,
1196
+
intel_de_read(display, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE,
1197
+
"WRPLL2 enabled\n");
1198
+
INTEL_DISPLAY_STATE_WARN(display,
1199
+
intel_de_read(display, PP_STATUS(display, 0)) & PP_ON,
1200
+
"Panel power on\n");
1201
+
INTEL_DISPLAY_STATE_WARN(display,
1202
+
intel_de_read(display, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
1203
+
"CPU PWM1 enabled\n");
1203
1204
if (IS_HASWELL(dev_priv))
1204
-
I915_STATE_WARN(dev_priv,
1205
-
intel_de_read(dev_priv, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
1206
-
"CPU PWM2 enabled\n");
1207
-
I915_STATE_WARN(dev_priv,
1208
-
intel_de_read(dev_priv, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
1209
-
"PCH PWM1 enabled\n");
1210
-
I915_STATE_WARN(dev_priv,
1211
-
(intel_de_read(dev_priv, UTIL_PIN_CTL) & (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM),
1212
-
"Utility pin enabled in PWM mode\n");
1213
-
I915_STATE_WARN(dev_priv,
1214
-
intel_de_read(dev_priv, PCH_GTC_CTL) & PCH_GTC_ENABLE,
1215
-
"PCH GTC enabled\n");
1205
+
INTEL_DISPLAY_STATE_WARN(display,
1206
+
intel_de_read(display, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
1207
+
"CPU PWM2 enabled\n");
1208
+
INTEL_DISPLAY_STATE_WARN(display,
1209
+
intel_de_read(display, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
1210
+
"PCH PWM1 enabled\n");
1211
+
INTEL_DISPLAY_STATE_WARN(display,
1212
+
(intel_de_read(display, UTIL_PIN_CTL) & (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM),
1213
+
"Utility pin enabled in PWM mode\n");
1214
+
INTEL_DISPLAY_STATE_WARN(display,
1215
+
intel_de_read(display, PCH_GTC_CTL) & PCH_GTC_ENABLE,
1216
+
"PCH GTC enabled\n");
1216
1217
1217
1218
/*
1218
1219
* In theory we can still leave IRQs enabled, as long as only the HPD
···
1221
1220
* gen-specific and since we only disable LCPLL after we fully disable
1222
1221
* the interrupts, the check below should be enough.
1223
1222
*/
1224
-
I915_STATE_WARN(dev_priv, intel_irqs_enabled(dev_priv),
1225
-
"IRQs enabled\n");
1223
+
INTEL_DISPLAY_STATE_WARN(display, intel_irqs_enabled(dev_priv),
1224
+
"IRQs enabled\n");
1226
1225
}
1227
1226
1228
1227
static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv)
···
1684
1683
intel_snps_phy_wait_for_calibration(dev_priv);
1685
1684
1686
1685
/* 9. XE2_HPD: Program CHICKEN_MISC_2 before any cursor or planes are enabled */
1687
-
if (DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 1))
1686
+
if (DISPLAY_VERx100(dev_priv) == 1401)
1688
1687
intel_de_rmw(dev_priv, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1);
1689
1688
1690
1689
if (resume)
1691
1690
intel_dmc_load_program(display);
1692
1691
1693
1692
/* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p,dg2 */
1694
-
if (IS_DISPLAY_VER_FULL(dev_priv, IP_VER(12, 0), IP_VER(13, 0)))
1693
+
if (IS_DISPLAY_VERx100(dev_priv, 1200, 1300))
1695
1694
intel_de_rmw(dev_priv, GEN11_CHICKEN_DCPR_2, 0,
1696
1695
DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM |
1697
1696
DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR);
+133
-1
drivers/gpu/drm/i915/display/intel_display_power_map.c
+133
-1
drivers/gpu/drm/i915/display/intel_display_power_map.c
···
1586
1586
I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
1587
1587
};
1588
1588
1589
+
/*
1590
+
* Xe3 changes the power well hierarchy slightly from Xe_LPD+; PGB now
1591
+
* depends on PG1 instead of PG2:
1592
+
*
1593
+
* PG0
1594
+
* |
1595
+
* --PG1--
1596
+
* / | \
1597
+
* PGA PGB PG2
1598
+
* / \
1599
+
* PGC PGD
1600
+
*/
1601
+
1602
+
#define XE3LPD_PW_C_POWER_DOMAINS \
1603
+
POWER_DOMAIN_PIPE_C, \
1604
+
POWER_DOMAIN_PIPE_PANEL_FITTER_C
1605
+
1606
+
#define XE3LPD_PW_D_POWER_DOMAINS \
1607
+
POWER_DOMAIN_PIPE_D, \
1608
+
POWER_DOMAIN_PIPE_PANEL_FITTER_D
1609
+
1610
+
#define XE3LPD_PW_2_POWER_DOMAINS \
1611
+
XE3LPD_PW_C_POWER_DOMAINS, \
1612
+
XE3LPD_PW_D_POWER_DOMAINS, \
1613
+
POWER_DOMAIN_TRANSCODER_C, \
1614
+
POWER_DOMAIN_TRANSCODER_D, \
1615
+
POWER_DOMAIN_VGA, \
1616
+
POWER_DOMAIN_PORT_DDI_LANES_TC1, \
1617
+
POWER_DOMAIN_PORT_DDI_LANES_TC2, \
1618
+
POWER_DOMAIN_PORT_DDI_LANES_TC3, \
1619
+
POWER_DOMAIN_PORT_DDI_LANES_TC4
1620
+
1621
+
I915_DECL_PW_DOMAINS(xe3lpd_pwdoms_pw_2,
1622
+
XE3LPD_PW_2_POWER_DOMAINS,
1623
+
POWER_DOMAIN_INIT);
1624
+
1625
+
I915_DECL_PW_DOMAINS(xe3lpd_pwdoms_pw_b,
1626
+
POWER_DOMAIN_PIPE_B,
1627
+
POWER_DOMAIN_PIPE_PANEL_FITTER_B,
1628
+
POWER_DOMAIN_INIT);
1629
+
1630
+
I915_DECL_PW_DOMAINS(xe3lpd_pwdoms_pw_c,
1631
+
XE3LPD_PW_C_POWER_DOMAINS,
1632
+
POWER_DOMAIN_INIT);
1633
+
1634
+
I915_DECL_PW_DOMAINS(xe3lpd_pwdoms_pw_d,
1635
+
XE3LPD_PW_D_POWER_DOMAINS,
1636
+
POWER_DOMAIN_INIT);
1637
+
1638
+
static const struct i915_power_well_desc xe3lpd_power_wells_main[] = {
1639
+
{
1640
+
.instances = &I915_PW_INSTANCES(
1641
+
I915_PW("PW_2", &xe3lpd_pwdoms_pw_2,
1642
+
.hsw.idx = ICL_PW_CTL_IDX_PW_2,
1643
+
.id = SKL_DISP_PW_2),
1644
+
),
1645
+
.ops = &hsw_power_well_ops,
1646
+
.has_vga = true,
1647
+
.has_fuses = true,
1648
+
}, {
1649
+
.instances = &I915_PW_INSTANCES(
1650
+
I915_PW("PW_A", &xelpd_pwdoms_pw_a,
1651
+
.hsw.idx = XELPD_PW_CTL_IDX_PW_A),
1652
+
),
1653
+
.ops = &hsw_power_well_ops,
1654
+
.irq_pipe_mask = BIT(PIPE_A),
1655
+
.has_fuses = true,
1656
+
}, {
1657
+
.instances = &I915_PW_INSTANCES(
1658
+
I915_PW("PW_B", &xe3lpd_pwdoms_pw_b,
1659
+
.hsw.idx = XELPD_PW_CTL_IDX_PW_B),
1660
+
),
1661
+
.ops = &hsw_power_well_ops,
1662
+
.irq_pipe_mask = BIT(PIPE_B),
1663
+
.has_fuses = true,
1664
+
}, {
1665
+
.instances = &I915_PW_INSTANCES(
1666
+
I915_PW("PW_C", &xe3lpd_pwdoms_pw_c,
1667
+
.hsw.idx = XELPD_PW_CTL_IDX_PW_C),
1668
+
),
1669
+
.ops = &hsw_power_well_ops,
1670
+
.irq_pipe_mask = BIT(PIPE_C),
1671
+
.has_fuses = true,
1672
+
}, {
1673
+
.instances = &I915_PW_INSTANCES(
1674
+
I915_PW("PW_D", &xe3lpd_pwdoms_pw_d,
1675
+
.hsw.idx = XELPD_PW_CTL_IDX_PW_D),
1676
+
),
1677
+
.ops = &hsw_power_well_ops,
1678
+
.irq_pipe_mask = BIT(PIPE_D),
1679
+
.has_fuses = true,
1680
+
}, {
1681
+
.instances = &I915_PW_INSTANCES(
1682
+
I915_PW("AUX_A", &icl_pwdoms_aux_a, .xelpdp.aux_ch = AUX_CH_A),
1683
+
I915_PW("AUX_B", &icl_pwdoms_aux_b, .xelpdp.aux_ch = AUX_CH_B),
1684
+
I915_PW("AUX_TC1", &xelpdp_pwdoms_aux_tc1, .xelpdp.aux_ch = AUX_CH_USBC1),
1685
+
I915_PW("AUX_TC2", &xelpdp_pwdoms_aux_tc2, .xelpdp.aux_ch = AUX_CH_USBC2),
1686
+
I915_PW("AUX_TC3", &xelpdp_pwdoms_aux_tc3, .xelpdp.aux_ch = AUX_CH_USBC3),
1687
+
I915_PW("AUX_TC4", &xelpdp_pwdoms_aux_tc4, .xelpdp.aux_ch = AUX_CH_USBC4),
1688
+
),
1689
+
.ops = &xelpdp_aux_power_well_ops,
1690
+
},
1691
+
};
1692
+
1693
+
I915_DECL_PW_DOMAINS(xe3lpd_pwdoms_dc_off,
1694
+
POWER_DOMAIN_DC_OFF,
1695
+
XE3LPD_PW_2_POWER_DOMAINS,
1696
+
XE3LPD_PW_C_POWER_DOMAINS,
1697
+
XE3LPD_PW_D_POWER_DOMAINS,
1698
+
POWER_DOMAIN_AUDIO_MMIO,
1699
+
POWER_DOMAIN_INIT);
1700
+
1701
+
static const struct i915_power_well_desc xe3lpd_power_wells_dcoff[] = {
1702
+
{
1703
+
.instances = &I915_PW_INSTANCES(
1704
+
I915_PW("DC_off", &xe3lpd_pwdoms_dc_off,
1705
+
.id = SKL_DISP_DC_OFF),
1706
+
),
1707
+
.ops = &gen9_dc_off_power_well_ops,
1708
+
},
1709
+
};
1710
+
1711
+
static const struct i915_power_well_desc_list xe3lpd_power_wells[] = {
1712
+
I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
1713
+
I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
1714
+
I915_PW_DESCRIPTORS(xe3lpd_power_wells_dcoff),
1715
+
I915_PW_DESCRIPTORS(xe3lpd_power_wells_main),
1716
+
I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
1717
+
};
1718
+
1589
1719
static void init_power_well_domains(const struct i915_power_well_instance *inst,
1590
1720
struct i915_power_well *power_well)
1591
1721
{
···
1823
1693
return 0;
1824
1694
}
1825
1695
1826
-
if (DISPLAY_VER(i915) >= 20)
1696
+
if (DISPLAY_VER(i915) >= 30)
1697
+
return set_power_wells(power_domains, xe3lpd_power_wells);
1698
+
else if (DISPLAY_VER(i915) >= 20)
1827
1699
return set_power_wells(power_domains, xe2lpd_power_wells);
1828
1700
else if (DISPLAY_VER(i915) >= 14)
1829
1701
return set_power_wells(power_domains, xelpdp_power_wells);
+63
-51
drivers/gpu/drm/i915/display/intel_display_power_well.c
+63
-51
drivers/gpu/drm/i915/display/intel_display_power_well.c
···
919
919
static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
920
920
struct i915_power_well *power_well)
921
921
{
922
-
bxt_dpio_phy_init(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
922
+
struct intel_display *display = &dev_priv->display;
923
+
924
+
bxt_dpio_phy_init(display, i915_power_well_instance(power_well)->bxt.phy);
923
925
}
924
926
925
927
static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
926
928
struct i915_power_well *power_well)
927
929
{
928
-
bxt_dpio_phy_uninit(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
930
+
struct intel_display *display = &dev_priv->display;
931
+
932
+
bxt_dpio_phy_uninit(display, i915_power_well_instance(power_well)->bxt.phy);
929
933
}
930
934
931
935
static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
932
936
struct i915_power_well *power_well)
933
937
{
934
-
return bxt_dpio_phy_is_enabled(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
938
+
struct intel_display *display = &dev_priv->display;
939
+
940
+
return bxt_dpio_phy_is_enabled(display, i915_power_well_instance(power_well)->bxt.phy);
935
941
}
936
942
937
943
static void bxt_verify_dpio_phy_power_wells(struct drm_i915_private *dev_priv)
938
944
{
945
+
struct intel_display *display = &dev_priv->display;
939
946
struct i915_power_well *power_well;
940
947
941
948
power_well = lookup_power_well(dev_priv, BXT_DISP_PW_DPIO_CMN_A);
942
949
if (intel_power_well_refcount(power_well) > 0)
943
-
bxt_dpio_phy_verify_state(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
950
+
bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy);
944
951
945
952
power_well = lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
946
953
if (intel_power_well_refcount(power_well) > 0)
947
-
bxt_dpio_phy_verify_state(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
954
+
bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy);
948
955
949
956
if (IS_GEMINILAKE(dev_priv)) {
950
957
power_well = lookup_power_well(dev_priv,
951
958
GLK_DISP_PW_DPIO_CMN_C);
952
959
if (intel_power_well_refcount(power_well) > 0)
953
-
bxt_dpio_phy_verify_state(dev_priv,
960
+
bxt_dpio_phy_verify_state(display,
954
961
i915_power_well_instance(power_well)->bxt.phy);
955
962
}
956
963
}
···
1337
1330
1338
1331
#define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1339
1332
1340
-
static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1333
+
static void assert_chv_phy_status(struct intel_display *display)
1341
1334
{
1335
+
struct drm_i915_private *dev_priv = to_i915(display->drm);
1342
1336
struct i915_power_well *cmn_bc =
1343
1337
lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
1344
1338
struct i915_power_well *cmn_d =
1345
1339
lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
1346
-
u32 phy_control = dev_priv->display.power.chv_phy_control;
1340
+
u32 phy_control = display->power.chv_phy_control;
1347
1341
u32 phy_status = 0;
1348
1342
u32 phy_status_mask = 0xffffffff;
1349
1343
···
1355
1347
* reset (ie. the power well has been disabled at
1356
1348
* least once).
1357
1349
*/
1358
-
if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY0])
1350
+
if (!display->power.chv_phy_assert[DPIO_PHY0])
1359
1351
phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1360
1352
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1361
1353
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
···
1363
1355
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1364
1356
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1365
1357
1366
-
if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY1])
1358
+
if (!display->power.chv_phy_assert[DPIO_PHY1])
1367
1359
phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1368
1360
PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1369
1361
PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
···
1391
1383
*/
1392
1384
if (BITS_SET(phy_control,
1393
1385
PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1394
-
(intel_de_read(dev_priv, DPLL(dev_priv, PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1386
+
(intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1395
1387
phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1396
1388
1397
1389
if (BITS_SET(phy_control,
···
1434
1426
* The PHY may be busy with some initial calibration and whatnot,
1435
1427
* so the power state can take a while to actually change.
1436
1428
*/
1437
-
if (intel_de_wait(dev_priv, DISPLAY_PHY_STATUS,
1429
+
if (intel_de_wait(display, DISPLAY_PHY_STATUS,
1438
1430
phy_status_mask, phy_status, 10))
1439
-
drm_err(&dev_priv->drm,
1431
+
drm_err(display->drm,
1440
1432
"Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1441
-
intel_de_read(dev_priv, DISPLAY_PHY_STATUS) & phy_status_mask,
1442
-
phy_status, dev_priv->display.power.chv_phy_control);
1433
+
intel_de_read(display, DISPLAY_PHY_STATUS) & phy_status_mask,
1434
+
phy_status, display->power.chv_phy_control);
1443
1435
}
1444
1436
1445
1437
#undef BITS_SET
···
1447
1439
static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1448
1440
struct i915_power_well *power_well)
1449
1441
{
1442
+
struct intel_display *display = &dev_priv->display;
1450
1443
enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
1451
1444
enum dpio_phy phy;
1452
1445
u32 tmp;
1453
1446
1454
-
drm_WARN_ON_ONCE(&dev_priv->drm,
1447
+
drm_WARN_ON_ONCE(display->drm,
1455
1448
id != VLV_DISP_PW_DPIO_CMN_BC &&
1456
1449
id != CHV_DISP_PW_DPIO_CMN_D);
1457
1450
···
1466
1457
vlv_set_power_well(dev_priv, power_well, true);
1467
1458
1468
1459
/* Poll for phypwrgood signal */
1469
-
if (intel_de_wait_for_set(dev_priv, DISPLAY_PHY_STATUS,
1460
+
if (intel_de_wait_for_set(display, DISPLAY_PHY_STATUS,
1470
1461
PHY_POWERGOOD(phy), 1))
1471
-
drm_err(&dev_priv->drm, "Display PHY %d is not power up\n",
1462
+
drm_err(display->drm, "Display PHY %d is not power up\n",
1472
1463
phy);
1473
1464
1474
1465
vlv_dpio_get(dev_priv);
···
1496
1487
1497
1488
vlv_dpio_put(dev_priv);
1498
1489
1499
-
dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1500
-
intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
1501
-
dev_priv->display.power.chv_phy_control);
1490
+
display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1491
+
intel_de_write(display, DISPLAY_PHY_CONTROL,
1492
+
display->power.chv_phy_control);
1502
1493
1503
-
drm_dbg_kms(&dev_priv->drm,
1494
+
drm_dbg_kms(display->drm,
1504
1495
"Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1505
-
phy, dev_priv->display.power.chv_phy_control);
1496
+
phy, display->power.chv_phy_control);
1506
1497
1507
-
assert_chv_phy_status(dev_priv);
1498
+
assert_chv_phy_status(display);
1508
1499
}
1509
1500
1510
1501
static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1511
1502
struct i915_power_well *power_well)
1512
1503
{
1504
+
struct intel_display *display = &dev_priv->display;
1513
1505
enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
1514
1506
enum dpio_phy phy;
1515
1507
1516
-
drm_WARN_ON_ONCE(&dev_priv->drm,
1508
+
drm_WARN_ON_ONCE(display->drm,
1517
1509
id != VLV_DISP_PW_DPIO_CMN_BC &&
1518
1510
id != CHV_DISP_PW_DPIO_CMN_D);
1519
1511
···
1527
1517
assert_pll_disabled(dev_priv, PIPE_C);
1528
1518
}
1529
1519
1530
-
dev_priv->display.power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1531
-
intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
1532
-
dev_priv->display.power.chv_phy_control);
1520
+
display->power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1521
+
intel_de_write(display, DISPLAY_PHY_CONTROL,
1522
+
display->power.chv_phy_control);
1533
1523
1534
1524
vlv_set_power_well(dev_priv, power_well, false);
1535
1525
1536
-
drm_dbg_kms(&dev_priv->drm,
1526
+
drm_dbg_kms(display->drm,
1537
1527
"Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1538
-
phy, dev_priv->display.power.chv_phy_control);
1528
+
phy, display->power.chv_phy_control);
1539
1529
1540
1530
/* PHY is fully reset now, so we can enable the PHY state asserts */
1541
-
dev_priv->display.power.chv_phy_assert[phy] = true;
1531
+
display->power.chv_phy_assert[phy] = true;
1542
1532
1543
-
assert_chv_phy_status(dev_priv);
1533
+
assert_chv_phy_status(display);
1544
1534
}
1545
1535
1546
1536
static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
···
1610
1600
bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1611
1601
enum dpio_channel ch, bool override)
1612
1602
{
1613
-
struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1603
+
struct intel_display *display = &dev_priv->display;
1604
+
struct i915_power_domains *power_domains = &display->power.domains;
1614
1605
bool was_override;
1615
1606
1616
1607
mutex_lock(&power_domains->lock);
1617
1608
1618
-
was_override = dev_priv->display.power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1609
+
was_override = display->power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1619
1610
1620
1611
if (override == was_override)
1621
1612
goto out;
1622
1613
1623
1614
if (override)
1624
-
dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1615
+
display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1625
1616
else
1626
-
dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1617
+
display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1627
1618
1628
-
intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
1629
-
dev_priv->display.power.chv_phy_control);
1619
+
intel_de_write(display, DISPLAY_PHY_CONTROL,
1620
+
display->power.chv_phy_control);
1630
1621
1631
-
drm_dbg_kms(&dev_priv->drm,
1622
+
drm_dbg_kms(display->drm,
1632
1623
"Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1633
-
phy, ch, dev_priv->display.power.chv_phy_control);
1624
+
phy, ch, display->power.chv_phy_control);
1634
1625
1635
-
assert_chv_phy_status(dev_priv);
1626
+
assert_chv_phy_status(display);
1636
1627
1637
1628
out:
1638
1629
mutex_unlock(&power_domains->lock);
···
1644
1633
void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1645
1634
bool override, unsigned int mask)
1646
1635
{
1636
+
struct intel_display *display = to_intel_display(encoder);
1647
1637
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1648
-
struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1638
+
struct i915_power_domains *power_domains = &display->power.domains;
1649
1639
enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder));
1650
1640
enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder));
1651
1641
1652
1642
mutex_lock(&power_domains->lock);
1653
1643
1654
-
dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1655
-
dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1644
+
display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1645
+
display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1656
1646
1657
1647
if (override)
1658
-
dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1648
+
display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1659
1649
else
1660
-
dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1650
+
display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1661
1651
1662
-
intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
1663
-
dev_priv->display.power.chv_phy_control);
1652
+
intel_de_write(display, DISPLAY_PHY_CONTROL,
1653
+
display->power.chv_phy_control);
1664
1654
1665
-
drm_dbg_kms(&dev_priv->drm,
1655
+
drm_dbg_kms(display->drm,
1666
1656
"Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1667
-
phy, ch, mask, dev_priv->display.power.chv_phy_control);
1657
+
phy, ch, mask, display->power.chv_phy_control);
1668
1658
1669
-
assert_chv_phy_status(dev_priv);
1659
+
assert_chv_phy_status(display);
1670
1660
1671
1661
assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1672
1662
+125
-81
drivers/gpu/drm/i915/display/intel_display_trace.h
+125
-81
drivers/gpu/drm/i915/display/intel_display_trace.h
···
9
9
#if !defined(__INTEL_DISPLAY_TRACE_H__) || defined(TRACE_HEADER_MULTI_READ)
10
10
#define __INTEL_DISPLAY_TRACE_H__
11
11
12
+
#include <linux/string.h>
12
13
#include <linux/string_helpers.h>
13
14
#include <linux/types.h>
14
15
#include <linux/tracepoint.h>
15
16
16
17
#include "i915_drv.h"
17
18
#include "intel_crtc.h"
19
+
#include "intel_display_limits.h"
18
20
#include "intel_display_types.h"
19
21
#include "intel_vblank.h"
20
22
21
23
#define __dev_name_display(display) dev_name((display)->drm->dev)
22
24
#define __dev_name_kms(obj) dev_name((obj)->base.dev->dev)
25
+
26
+
/*
27
+
* Using identifiers from enum pipe in TP_printk() will confuse tools that
28
+
* parse /sys/kernel/debug/tracing/{xe,i915}/<event>/format. So we use CPP
29
+
* macros instead.
30
+
*/
31
+
#define _TRACE_PIPE_A 0
32
+
#define _TRACE_PIPE_B 1
33
+
#define _TRACE_PIPE_C 2
34
+
#define _TRACE_PIPE_D 3
35
+
36
+
/*
37
+
* FIXME: Several TP_printk() calls below display frame and scanline numbers for
38
+
* all possible pipes (regardless of whether they are available) and that is
39
+
* done with a constant format string. A better approach would be to generate
40
+
* that info dynamically based on available pipes, but, while we do not have
41
+
* that implemented yet, let's assert that the constant format string indeed
42
+
* covers all possible pipes.
43
+
*/
44
+
static_assert(I915_MAX_PIPES - 1 == _TRACE_PIPE_D);
45
+
46
+
#define _PIPES_FRAME_AND_SCANLINE_FMT \
47
+
"pipe A: frame=%u, scanline=%u" \
48
+
", pipe B: frame=%u, scanline=%u" \
49
+
", pipe C: frame=%u, scanline=%u" \
50
+
", pipe D: frame=%u, scanline=%u"
51
+
52
+
#define _PIPES_FRAME_AND_SCANLINE_VALUES \
53
+
__entry->frame[_TRACE_PIPE_A], __entry->scanline[_TRACE_PIPE_A] \
54
+
, __entry->frame[_TRACE_PIPE_B], __entry->scanline[_TRACE_PIPE_B] \
55
+
, __entry->frame[_TRACE_PIPE_C], __entry->scanline[_TRACE_PIPE_C] \
56
+
, __entry->frame[_TRACE_PIPE_D], __entry->scanline[_TRACE_PIPE_D]
57
+
58
+
/*
59
+
* Paranoid sanity check that at least the enumeration starts at the
60
+
* same value as _TRACE_PIPE_A.
61
+
*/
62
+
static_assert(PIPE_A == _TRACE_PIPE_A);
23
63
24
64
TRACE_EVENT(intel_pipe_enable,
25
65
TP_PROTO(struct intel_crtc *crtc),
···
67
27
68
28
TP_STRUCT__entry(
69
29
__string(dev, __dev_name_kms(crtc))
70
-
__array(u32, frame, 3)
71
-
__array(u32, scanline, 3)
72
-
__field(enum pipe, pipe)
30
+
__array(u32, frame, I915_MAX_PIPES)
31
+
__array(u32, scanline, I915_MAX_PIPES)
32
+
__field(char, pipe_name)
73
33
),
74
34
TP_fast_assign(
75
35
struct intel_display *display = to_intel_display(crtc);
76
36
struct intel_crtc *it__;
77
37
__assign_str(dev);
38
+
memset(__entry->frame, 0,
39
+
sizeof(__entry->frame[0]) * I915_MAX_PIPES);
40
+
memset(__entry->scanline, 0,
41
+
sizeof(__entry->scanline[0]) * I915_MAX_PIPES);
78
42
for_each_intel_crtc(display->drm, it__) {
79
43
__entry->frame[it__->pipe] = intel_crtc_get_vblank_counter(it__);
80
44
__entry->scanline[it__->pipe] = intel_get_crtc_scanline(it__);
81
45
}
82
-
__entry->pipe = crtc->pipe;
46
+
__entry->pipe_name = pipe_name(crtc->pipe);
83
47
),
84
48
85
-
TP_printk("dev %s, pipe %c enable, pipe A: frame=%u, scanline=%u, pipe B: frame=%u, scanline=%u, pipe C: frame=%u, scanline=%u",
86
-
__get_str(dev), pipe_name(__entry->pipe),
87
-
__entry->frame[PIPE_A], __entry->scanline[PIPE_A],
88
-
__entry->frame[PIPE_B], __entry->scanline[PIPE_B],
89
-
__entry->frame[PIPE_C], __entry->scanline[PIPE_C])
49
+
TP_printk("dev %s, pipe %c enable, " _PIPES_FRAME_AND_SCANLINE_FMT,
50
+
__get_str(dev), __entry->pipe_name, _PIPES_FRAME_AND_SCANLINE_VALUES)
90
51
);
91
52
92
53
TRACE_EVENT(intel_pipe_disable,
···
96
55
97
56
TP_STRUCT__entry(
98
57
__string(dev, __dev_name_kms(crtc))
99
-
__array(u32, frame, 3)
100
-
__array(u32, scanline, 3)
101
-
__field(enum pipe, pipe)
58
+
__array(u32, frame, I915_MAX_PIPES)
59
+
__array(u32, scanline, I915_MAX_PIPES)
60
+
__field(char, pipe_name)
102
61
),
103
62
104
63
TP_fast_assign(
105
64
struct intel_display *display = to_intel_display(crtc);
106
65
struct intel_crtc *it__;
107
66
__assign_str(dev);
67
+
memset(__entry->frame, 0,
68
+
sizeof(__entry->frame[0]) * I915_MAX_PIPES);
69
+
memset(__entry->scanline, 0,
70
+
sizeof(__entry->scanline[0]) * I915_MAX_PIPES);
108
71
for_each_intel_crtc(display->drm, it__) {
109
72
__entry->frame[it__->pipe] = intel_crtc_get_vblank_counter(it__);
110
73
__entry->scanline[it__->pipe] = intel_get_crtc_scanline(it__);
111
74
}
112
-
__entry->pipe = crtc->pipe;
75
+
__entry->pipe_name = pipe_name(crtc->pipe);
113
76
),
114
77
115
-
TP_printk("dev %s, pipe %c disable, pipe A: frame=%u, scanline=%u, pipe B: frame=%u, scanline=%u, pipe C: frame=%u, scanline=%u",
116
-
__get_str(dev), pipe_name(__entry->pipe),
117
-
__entry->frame[PIPE_A], __entry->scanline[PIPE_A],
118
-
__entry->frame[PIPE_B], __entry->scanline[PIPE_B],
119
-
__entry->frame[PIPE_C], __entry->scanline[PIPE_C])
78
+
TP_printk("dev %s, pipe %c disable, " _PIPES_FRAME_AND_SCANLINE_FMT,
79
+
__get_str(dev), __entry->pipe_name, _PIPES_FRAME_AND_SCANLINE_VALUES)
120
80
);
121
81
122
82
TRACE_EVENT(intel_crtc_flip_done,
···
126
84
127
85
TP_STRUCT__entry(
128
86
__string(dev, __dev_name_kms(crtc))
129
-
__field(enum pipe, pipe)
87
+
__field(char, pipe_name)
130
88
__field(u32, frame)
131
89
__field(u32, scanline)
132
90
),
133
91
134
92
TP_fast_assign(
135
93
__assign_str(dev);
136
-
__entry->pipe = crtc->pipe;
94
+
__entry->pipe_name = pipe_name(crtc->pipe);
137
95
__entry->frame = intel_crtc_get_vblank_counter(crtc);
138
96
__entry->scanline = intel_get_crtc_scanline(crtc);
139
97
),
140
98
141
99
TP_printk("dev %s, pipe %c, frame=%u, scanline=%u",
142
-
__get_str(dev), pipe_name(__entry->pipe),
100
+
__get_str(dev), __entry->pipe_name,
143
101
__entry->frame, __entry->scanline)
144
102
);
145
103
···
149
107
150
108
TP_STRUCT__entry(
151
109
__string(dev, __dev_name_kms(crtc))
152
-
__field(enum pipe, pipe)
110
+
__field(char, pipe_name)
153
111
__field(u32, frame)
154
112
__field(u32, scanline)
155
113
__array(u32, crcs, 5)
···
157
115
158
116
TP_fast_assign(
159
117
__assign_str(dev);
160
-
__entry->pipe = crtc->pipe;
118
+
__entry->pipe_name = pipe_name(crtc->pipe);
161
119
__entry->frame = intel_crtc_get_vblank_counter(crtc);
162
120
__entry->scanline = intel_get_crtc_scanline(crtc);
163
121
memcpy(__entry->crcs, crcs, sizeof(__entry->crcs));
164
122
),
165
123
166
124
TP_printk("dev %s, pipe %c, frame=%u, scanline=%u crc=%08x %08x %08x %08x %08x",
167
-
__get_str(dev), pipe_name(__entry->pipe),
125
+
__get_str(dev), __entry->pipe_name,
168
126
__entry->frame, __entry->scanline,
169
127
__entry->crcs[0], __entry->crcs[1],
170
128
__entry->crcs[2], __entry->crcs[3],
···
177
135
178
136
TP_STRUCT__entry(
179
137
__string(dev, __dev_name_display(display))
180
-
__field(enum pipe, pipe)
138
+
__field(char, pipe_name)
181
139
__field(u32, frame)
182
140
__field(u32, scanline)
183
141
),
···
185
143
TP_fast_assign(
186
144
struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
187
145
__assign_str(dev);
188
-
__entry->pipe = pipe;
146
+
__entry->pipe_name = pipe_name(pipe);
189
147
__entry->frame = intel_crtc_get_vblank_counter(crtc);
190
148
__entry->scanline = intel_get_crtc_scanline(crtc);
191
149
),
192
150
193
151
TP_printk("dev %s, pipe %c, frame=%u, scanline=%u",
194
-
__get_str(dev), pipe_name(__entry->pipe),
152
+
__get_str(dev), __entry->pipe_name,
195
153
__entry->frame, __entry->scanline)
196
154
);
197
155
···
201
159
202
160
TP_STRUCT__entry(
203
161
__string(dev, __dev_name_display(display))
204
-
__field(enum pipe, pipe)
162
+
__field(char, pipe_name)
205
163
__field(u32, frame)
206
164
__field(u32, scanline)
207
165
),
···
210
168
enum pipe pipe = pch_transcoder;
211
169
struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
212
170
__assign_str(dev);
213
-
__entry->pipe = pipe;
171
+
__entry->pipe_name = pipe_name(pipe);
214
172
__entry->frame = intel_crtc_get_vblank_counter(crtc);
215
173
__entry->scanline = intel_get_crtc_scanline(crtc);
216
174
),
217
175
218
176
TP_printk("dev %s, pch transcoder %c, frame=%u, scanline=%u",
219
-
__get_str(dev), pipe_name(__entry->pipe),
177
+
__get_str(dev), __entry->pipe_name,
220
178
__entry->frame, __entry->scanline)
221
179
);
222
180
···
226
184
227
185
TP_STRUCT__entry(
228
186
__string(dev, __dev_name_display(display))
229
-
__array(u32, frame, 3)
230
-
__array(u32, scanline, 3)
187
+
__array(u32, frame, I915_MAX_PIPES)
188
+
__array(u32, scanline, I915_MAX_PIPES)
231
189
__field(bool, old)
232
190
__field(bool, new)
233
191
),
···
235
193
TP_fast_assign(
236
194
struct intel_crtc *crtc;
237
195
__assign_str(dev);
196
+
memset(__entry->frame, 0,
197
+
sizeof(__entry->frame[0]) * I915_MAX_PIPES);
198
+
memset(__entry->scanline, 0,
199
+
sizeof(__entry->scanline[0]) * I915_MAX_PIPES);
238
200
for_each_intel_crtc(display->drm, crtc) {
239
201
__entry->frame[crtc->pipe] = intel_crtc_get_vblank_counter(crtc);
240
202
__entry->scanline[crtc->pipe] = intel_get_crtc_scanline(crtc);
···
247
201
__entry->new = new;
248
202
),
249
203
250
-
TP_printk("dev %s, cxsr %s->%s, pipe A: frame=%u, scanline=%u, pipe B: frame=%u, scanline=%u, pipe C: frame=%u, scanline=%u",
204
+
TP_printk("dev %s, cxsr %s->%s, " _PIPES_FRAME_AND_SCANLINE_FMT,
251
205
__get_str(dev), str_on_off(__entry->old), str_on_off(__entry->new),
252
-
__entry->frame[PIPE_A], __entry->scanline[PIPE_A],
253
-
__entry->frame[PIPE_B], __entry->scanline[PIPE_B],
254
-
__entry->frame[PIPE_C], __entry->scanline[PIPE_C])
206
+
_PIPES_FRAME_AND_SCANLINE_VALUES)
255
207
);
256
208
257
209
TRACE_EVENT(g4x_wm,
···
258
214
259
215
TP_STRUCT__entry(
260
216
__string(dev, __dev_name_kms(crtc))
261
-
__field(enum pipe, pipe)
217
+
__field(char, pipe_name)
262
218
__field(u32, frame)
263
219
__field(u32, scanline)
264
220
__field(u16, primary)
···
277
233
278
234
TP_fast_assign(
279
235
__assign_str(dev);
280
-
__entry->pipe = crtc->pipe;
236
+
__entry->pipe_name = pipe_name(crtc->pipe);
281
237
__entry->frame = intel_crtc_get_vblank_counter(crtc);
282
238
__entry->scanline = intel_get_crtc_scanline(crtc);
283
239
__entry->primary = wm->pipe[crtc->pipe].plane[PLANE_PRIMARY];
···
295
251
),
296
252
297
253
TP_printk("dev %s, pipe %c, frame=%u, scanline=%u, wm %d/%d/%d, sr %s/%d/%d/%d, hpll %s/%d/%d/%d, fbc %s",
298
-
__get_str(dev), pipe_name(__entry->pipe),
254
+
__get_str(dev), __entry->pipe_name,
299
255
__entry->frame, __entry->scanline,
300
256
__entry->primary, __entry->sprite, __entry->cursor,
301
257
str_yes_no(__entry->cxsr), __entry->sr_plane, __entry->sr_cursor, __entry->sr_fbc,
···
309
265
310
266
TP_STRUCT__entry(
311
267
__string(dev, __dev_name_kms(crtc))
312
-
__field(enum pipe, pipe)
268
+
__field(char, pipe_name)
313
269
__field(u32, frame)
314
270
__field(u32, scanline)
315
271
__field(u32, level)
···
324
280
325
281
TP_fast_assign(
326
282
__assign_str(dev);
327
-
__entry->pipe = crtc->pipe;
283
+
__entry->pipe_name = pipe_name(crtc->pipe);
328
284
__entry->frame = intel_crtc_get_vblank_counter(crtc);
329
285
__entry->scanline = intel_get_crtc_scanline(crtc);
330
286
__entry->level = wm->level;
···
338
294
),
339
295
340
296
TP_printk("dev %s, pipe %c, frame=%u, scanline=%u, level=%d, cxsr=%d, wm %d/%d/%d/%d, sr %d/%d",
341
-
__get_str(dev), pipe_name(__entry->pipe),
297
+
__get_str(dev), __entry->pipe_name,
342
298
__entry->frame, __entry->scanline,
343
299
__entry->level, __entry->cxsr,
344
300
__entry->primary, __entry->sprite0, __entry->sprite1, __entry->cursor,
···
351
307
352
308
TP_STRUCT__entry(
353
309
__string(dev, __dev_name_kms(crtc))
354
-
__field(enum pipe, pipe)
310
+
__field(char, pipe_name)
355
311
__field(u32, frame)
356
312
__field(u32, scanline)
357
313
__field(u32, sprite0_start)
···
361
317
362
318
TP_fast_assign(
363
319
__assign_str(dev);
364
-
__entry->pipe = crtc->pipe;
320
+
__entry->pipe_name = pipe_name(crtc->pipe);
365
321
__entry->frame = intel_crtc_get_vblank_counter(crtc);
366
322
__entry->scanline = intel_get_crtc_scanline(crtc);
367
323
__entry->sprite0_start = sprite0_start;
···
370
326
),
371
327
372
328
TP_printk("dev %s, pipe %c, frame=%u, scanline=%u, %d/%d/%d",
373
-
__get_str(dev), pipe_name(__entry->pipe),
329
+
__get_str(dev), __entry->pipe_name,
374
330
__entry->frame, __entry->scanline,
375
331
__entry->sprite0_start, __entry->sprite1_start, __entry->fifo_size)
376
332
);
···
381
337
382
338
TP_STRUCT__entry(
383
339
__string(dev, __dev_name_kms(plane))
384
-
__field(enum pipe, pipe)
340
+
__field(char, pipe_name)
385
341
__field(u32, frame)
386
342
__field(u32, scanline)
387
343
__field(bool, async_flip)
···
391
347
TP_fast_assign(
392
348
__assign_str(dev);
393
349
__assign_str(name);
394
-
__entry->pipe = crtc->pipe;
350
+
__entry->pipe_name = pipe_name(crtc->pipe);
395
351
__entry->frame = intel_crtc_get_vblank_counter(crtc);
396
352
__entry->scanline = intel_get_crtc_scanline(crtc);
397
353
__entry->async_flip = async_flip;
398
354
),
399
355
400
356
TP_printk("dev %s, pipe %c, plane %s, frame=%u, scanline=%u, async_flip=%s",
401
-
__get_str(dev), pipe_name(__entry->pipe), __get_str(name),
357
+
__get_str(dev), __entry->pipe_name, __get_str(name),
402
358
__entry->frame, __entry->scanline, str_yes_no(__entry->async_flip))
403
359
);
404
360
···
408
364
409
365
TP_STRUCT__entry(
410
366
__string(dev, __dev_name_kms(plane))
411
-
__field(enum pipe, pipe)
367
+
__field(char, pipe_name)
412
368
__field(u32, frame)
413
369
__field(u32, scanline)
414
370
__array(int, src, 4)
···
419
375
TP_fast_assign(
420
376
__assign_str(dev);
421
377
__assign_str(name);
422
-
__entry->pipe = crtc->pipe;
378
+
__entry->pipe_name = pipe_name(crtc->pipe);
423
379
__entry->frame = intel_crtc_get_vblank_counter(crtc);
424
380
__entry->scanline = intel_get_crtc_scanline(crtc);
425
381
memcpy(__entry->src, &plane->base.state->src, sizeof(__entry->src));
···
427
383
),
428
384
429
385
TP_printk("dev %s, pipe %c, plane %s, frame=%u, scanline=%u, " DRM_RECT_FP_FMT " -> " DRM_RECT_FMT,
430
-
__get_str(dev), pipe_name(__entry->pipe), __get_str(name),
386
+
__get_str(dev), __entry->pipe_name, __get_str(name),
431
387
__entry->frame, __entry->scanline,
432
388
DRM_RECT_FP_ARG((const struct drm_rect *)__entry->src),
433
389
DRM_RECT_ARG((const struct drm_rect *)__entry->dst))
···
439
395
440
396
TP_STRUCT__entry(
441
397
__string(dev, __dev_name_kms(plane))
442
-
__field(enum pipe, pipe)
398
+
__field(char, pipe_name)
443
399
__field(u32, frame)
444
400
__field(u32, scanline)
445
401
__array(int, src, 4)
···
450
406
TP_fast_assign(
451
407
__assign_str(dev);
452
408
__assign_str(name);
453
-
__entry->pipe = crtc->pipe;
409
+
__entry->pipe_name = pipe_name(crtc->pipe);
454
410
__entry->frame = intel_crtc_get_vblank_counter(crtc);
455
411
__entry->scanline = intel_get_crtc_scanline(crtc);
456
412
memcpy(__entry->src, &plane->base.state->src, sizeof(__entry->src));
···
458
414
),
459
415
460
416
TP_printk("dev %s, pipe %c, plane %s, frame=%u, scanline=%u, " DRM_RECT_FP_FMT " -> " DRM_RECT_FMT,
461
-
__get_str(dev), pipe_name(__entry->pipe), __get_str(name),
417
+
__get_str(dev), __entry->pipe_name, __get_str(name),
462
418
__entry->frame, __entry->scanline,
463
419
DRM_RECT_FP_ARG((const struct drm_rect *)__entry->src),
464
420
DRM_RECT_ARG((const struct drm_rect *)__entry->dst))
···
470
426
471
427
TP_STRUCT__entry(
472
428
__string(dev, __dev_name_kms(plane))
473
-
__field(enum pipe, pipe)
429
+
__field(char, pipe_name)
474
430
__field(u32, frame)
475
431
__field(u32, scanline)
476
432
__string(name, plane->base.name)
···
479
435
TP_fast_assign(
480
436
__assign_str(dev);
481
437
__assign_str(name);
482
-
__entry->pipe = crtc->pipe;
438
+
__entry->pipe_name = pipe_name(crtc->pipe);
483
439
__entry->frame = intel_crtc_get_vblank_counter(crtc);
484
440
__entry->scanline = intel_get_crtc_scanline(crtc);
485
441
),
486
442
487
443
TP_printk("dev %s, pipe %c, plane %s, frame=%u, scanline=%u",
488
-
__get_str(dev), pipe_name(__entry->pipe), __get_str(name),
444
+
__get_str(dev), __entry->pipe_name, __get_str(name),
489
445
__entry->frame, __entry->scanline)
490
446
);
491
447
···
496
452
TP_STRUCT__entry(
497
453
__string(dev, __dev_name_kms(plane))
498
454
__string(name, plane->base.name)
499
-
__field(enum pipe, pipe)
455
+
__field(char, pipe_name)
500
456
__field(u32, frame)
501
457
__field(u32, scanline)
502
458
),
···
507
463
plane->pipe);
508
464
__assign_str(dev);
509
465
__assign_str(name);
510
-
__entry->pipe = crtc->pipe;
466
+
__entry->pipe_name = pipe_name(crtc->pipe);
511
467
__entry->frame = intel_crtc_get_vblank_counter(crtc);
512
468
__entry->scanline = intel_get_crtc_scanline(crtc);
513
469
),
514
470
515
471
TP_printk("dev %s, pipe %c, plane %s, frame=%u, scanline=%u",
516
-
__get_str(dev), pipe_name(__entry->pipe), __get_str(name),
472
+
__get_str(dev), __entry->pipe_name, __get_str(name),
517
473
__entry->frame, __entry->scanline)
518
474
);
519
475
···
524
480
TP_STRUCT__entry(
525
481
__string(dev, __dev_name_kms(plane))
526
482
__string(name, plane->base.name)
527
-
__field(enum pipe, pipe)
483
+
__field(char, pipe_name)
528
484
__field(u32, frame)
529
485
__field(u32, scanline)
530
486
),
···
535
491
plane->pipe);
536
492
__assign_str(dev);
537
493
__assign_str(name);
538
-
__entry->pipe = crtc->pipe;
494
+
__entry->pipe_name = pipe_name(crtc->pipe);
539
495
__entry->frame = intel_crtc_get_vblank_counter(crtc);
540
496
__entry->scanline = intel_get_crtc_scanline(crtc);
541
497
),
542
498
543
499
TP_printk("dev %s, pipe %c, plane %s, frame=%u, scanline=%u",
544
-
__get_str(dev), pipe_name(__entry->pipe), __get_str(name),
500
+
__get_str(dev), __entry->pipe_name, __get_str(name),
545
501
__entry->frame, __entry->scanline)
546
502
);
547
503
···
552
508
TP_STRUCT__entry(
553
509
__string(dev, __dev_name_kms(plane))
554
510
__string(name, plane->base.name)
555
-
__field(enum pipe, pipe)
511
+
__field(char, pipe_name)
556
512
__field(u32, frame)
557
513
__field(u32, scanline)
558
514
),
···
563
519
plane->pipe);
564
520
__assign_str(dev);
565
521
__assign_str(name);
566
-
__entry->pipe = crtc->pipe;
522
+
__entry->pipe_name = pipe_name(crtc->pipe);
567
523
__entry->frame = intel_crtc_get_vblank_counter(crtc);
568
524
__entry->scanline = intel_get_crtc_scanline(crtc);
569
525
),
570
526
571
527
TP_printk("dev %s, pipe %c, plane %s, frame=%u, scanline=%u",
572
-
__get_str(dev), pipe_name(__entry->pipe), __get_str(name),
528
+
__get_str(dev), __entry->pipe_name, __get_str(name),
573
529
__entry->frame, __entry->scanline)
574
530
);
575
531
···
579
535
580
536
TP_STRUCT__entry(
581
537
__string(dev, __dev_name_kms(crtc))
582
-
__field(enum pipe, pipe)
538
+
__field(char, pipe_name)
583
539
__field(u32, frame)
584
540
__field(u32, scanline)
585
541
),
586
542
587
543
TP_fast_assign(
588
544
__assign_str(dev);
589
-
__entry->pipe = crtc->pipe;
545
+
__entry->pipe_name = pipe_name(crtc->pipe);
590
546
__entry->frame = intel_crtc_get_vblank_counter(crtc);
591
547
__entry->scanline = intel_get_crtc_scanline(crtc);
592
548
),
593
549
594
550
TP_printk("dev %s, pipe %c, frame=%u, scanline=%u",
595
-
__get_str(dev), pipe_name(__entry->pipe),
551
+
__get_str(dev), __entry->pipe_name,
596
552
__entry->frame, __entry->scanline)
597
553
);
598
554
···
602
558
603
559
TP_STRUCT__entry(
604
560
__string(dev, __dev_name_kms(crtc))
605
-
__field(enum pipe, pipe)
561
+
__field(char, pipe_name)
606
562
__field(u32, frame)
607
563
__field(u32, scanline)
608
564
),
609
565
610
566
TP_fast_assign(
611
567
__assign_str(dev);
612
-
__entry->pipe = crtc->pipe;
568
+
__entry->pipe_name = pipe_name(crtc->pipe);
613
569
__entry->frame = intel_crtc_get_vblank_counter(crtc);
614
570
__entry->scanline = intel_get_crtc_scanline(crtc);
615
571
),
616
572
617
573
TP_printk("dev %s, pipe %c, frame=%u, scanline=%u",
618
-
__get_str(dev), pipe_name(__entry->pipe),
574
+
__get_str(dev), __entry->pipe_name,
619
575
__entry->frame, __entry->scanline)
620
576
);
621
577
···
625
581
626
582
TP_STRUCT__entry(
627
583
__string(dev, __dev_name_kms(crtc))
628
-
__field(enum pipe, pipe)
584
+
__field(char, pipe_name)
629
585
__field(u32, frame)
630
586
__field(u32, scanline)
631
587
__field(u32, min)
···
634
590
635
591
TP_fast_assign(
636
592
__assign_str(dev);
637
-
__entry->pipe = crtc->pipe;
593
+
__entry->pipe_name = pipe_name(crtc->pipe);
638
594
__entry->frame = intel_crtc_get_vblank_counter(crtc);
639
595
__entry->scanline = intel_get_crtc_scanline(crtc);
640
596
__entry->min = crtc->debug.min_vbl;
···
642
598
),
643
599
644
600
TP_printk("dev %s, pipe %c, frame=%u, scanline=%u, min=%u, max=%u",
645
-
__get_str(dev), pipe_name(__entry->pipe),
601
+
__get_str(dev), __entry->pipe_name,
646
602
__entry->frame, __entry->scanline,
647
603
__entry->min, __entry->max)
648
604
);
···
653
609
654
610
TP_STRUCT__entry(
655
611
__string(dev, __dev_name_kms(crtc))
656
-
__field(enum pipe, pipe)
612
+
__field(char, pipe_name)
657
613
__field(u32, frame)
658
614
__field(u32, scanline)
659
615
__field(u32, min)
···
662
618
663
619
TP_fast_assign(
664
620
__assign_str(dev);
665
-
__entry->pipe = crtc->pipe;
621
+
__entry->pipe_name = pipe_name(crtc->pipe);
666
622
__entry->frame = crtc->debug.start_vbl_count;
667
623
__entry->scanline = crtc->debug.scanline_start;
668
624
__entry->min = crtc->debug.min_vbl;
···
670
626
),
671
627
672
628
TP_printk("dev %s, pipe %c, frame=%u, scanline=%u, min=%u, max=%u",
673
-
__get_str(dev), pipe_name(__entry->pipe),
629
+
__get_str(dev), __entry->pipe_name,
674
630
__entry->frame, __entry->scanline,
675
631
__entry->min, __entry->max)
676
632
);
···
681
637
682
638
TP_STRUCT__entry(
683
639
__string(dev, __dev_name_kms(crtc))
684
-
__field(enum pipe, pipe)
640
+
__field(char, pipe_name)
685
641
__field(u32, frame)
686
642
__field(u32, scanline)
687
643
),
688
644
689
645
TP_fast_assign(
690
646
__assign_str(dev);
691
-
__entry->pipe = crtc->pipe;
647
+
__entry->pipe_name = pipe_name(crtc->pipe);
692
648
__entry->frame = frame;
693
649
__entry->scanline = scanline_end;
694
650
),
695
651
696
652
TP_printk("dev %s, pipe %c, frame=%u, scanline=%u",
697
-
__get_str(dev), pipe_name(__entry->pipe),
653
+
__get_str(dev), __entry->pipe_name,
698
654
__entry->frame, __entry->scanline)
699
655
);
700
656
+10
-1
drivers/gpu/drm/i915/display/intel_display_types.h
+10
-1
drivers/gpu/drm/i915/display/intel_display_types.h
···
1618
1618
u32 dc3co_exit_delay;
1619
1619
struct delayed_work dc3co_work;
1620
1620
u8 entry_setup_frames;
1621
+
1622
+
bool link_ok;
1621
1623
};
1622
1624
1623
1625
struct intel_dp {
···
1767
1765
1768
1766
/* When we last wrote the OUI for eDP */
1769
1767
unsigned long last_oui_write;
1768
+
bool oui_valid;
1770
1769
1771
1770
bool colorimetry_support;
1772
1771
···
2107
2104
__drm_device_to_intel_display((p)->base.dev)
2108
2105
#define __intel_hdmi_to_intel_display(p) \
2109
2106
__drm_device_to_intel_display(hdmi_to_dig_port(p)->base.base.dev)
2107
+
#define __intel_plane_to_intel_display(p) \
2108
+
__drm_device_to_intel_display((p)->base.dev)
2109
+
#define __intel_plane_state_to_intel_display(p) \
2110
+
__drm_device_to_intel_display((p)->uapi.plane->dev)
2110
2111
2111
2112
/* Helper for generic association. Map types to conversion functions/macros. */
2112
2113
#define __assoc(type, p) \
···
2129
2122
__assoc(intel_digital_port, p), \
2130
2123
__assoc(intel_dp, p), \
2131
2124
__assoc(intel_encoder, p), \
2132
-
__assoc(intel_hdmi, p))
2125
+
__assoc(intel_hdmi, p), \
2126
+
__assoc(intel_plane, p), \
2127
+
__assoc(intel_plane_state, p))
2133
2128
2134
2129
#endif /* __INTEL_DISPLAY_TYPES_H__ */
+9
-3
drivers/gpu/drm/i915/display/intel_dmc.c
+9
-3
drivers/gpu/drm/i915/display/intel_dmc.c
···
113
113
#define DISPLAY_VER13_DMC_MAX_FW_SIZE 0x20000
114
114
#define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE
115
115
116
+
#define XE3LPD_DMC_PATH DMC_PATH(xe3lpd)
117
+
MODULE_FIRMWARE(XE3LPD_DMC_PATH);
118
+
116
119
#define XE2LPD_DMC_PATH DMC_PATH(xe2lpd)
117
120
MODULE_FIRMWARE(XE2LPD_DMC_PATH);
118
121
···
171
168
const char *fw_path = NULL;
172
169
u32 max_fw_size = 0;
173
170
174
-
if (DISPLAY_VER_FULL(display) == IP_VER(20, 0)) {
171
+
if (DISPLAY_VERx100(display) == 3000) {
172
+
fw_path = XE3LPD_DMC_PATH;
173
+
max_fw_size = XE2LPD_DMC_MAX_FW_SIZE;
174
+
} else if (DISPLAY_VERx100(display) == 2000) {
175
175
fw_path = XE2LPD_DMC_PATH;
176
176
max_fw_size = XE2LPD_DMC_MAX_FW_SIZE;
177
-
} else if (DISPLAY_VER_FULL(display) == IP_VER(14, 1)) {
177
+
} else if (DISPLAY_VERx100(display) == 1401) {
178
178
fw_path = BMG_DMC_PATH;
179
179
max_fw_size = XELPDP_DMC_MAX_FW_SIZE;
180
-
} else if (DISPLAY_VER_FULL(display) == IP_VER(14, 0)) {
180
+
} else if (DISPLAY_VERx100(display) == 1400) {
181
181
fw_path = MTL_DMC_PATH;
182
182
max_fw_size = XELPDP_DMC_MAX_FW_SIZE;
183
183
} else if (IS_DG2(i915)) {
+108
-55
drivers/gpu/drm/i915/display/intel_dp.c
+108
-55
drivers/gpu/drm/i915/display/intel_dp.c
···
83
83
#include "intel_modeset_lock.h"
84
84
#include "intel_panel.h"
85
85
#include "intel_pch_display.h"
86
+
#include "intel_pfit.h"
86
87
#include "intel_pps.h"
87
88
#include "intel_psr.h"
89
+
#include "intel_runtime_pm.h"
88
90
#include "intel_quirks.h"
89
91
#include "intel_tc.h"
90
92
#include "intel_vdsc.h"
···
497
495
if (intel_encoder_is_c10phy(encoder))
498
496
return 810000;
499
497
500
-
if (DISPLAY_VER_FULL(to_i915(encoder->base.dev)) == IP_VER(14, 1))
498
+
if (DISPLAY_VERx100(to_i915(encoder->base.dev)) == 1401)
501
499
return 1350000;
502
500
503
501
return 2000000;
···
1315
1313
int num_joined_pipes)
1316
1314
{
1317
1315
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1316
+
int hdisplay_limit;
1318
1317
1319
1318
if (!intel_dp_has_joiner(intel_dp))
1320
1319
return false;
1321
1320
1322
1321
num_joined_pipes /= 2;
1323
1322
1323
+
hdisplay_limit = DISPLAY_VER(i915) >= 30 ? 6144 : 5120;
1324
+
1324
1325
return clock > num_joined_pipes * i915->display.cdclk.max_dotclk_freq ||
1325
-
hdisplay > num_joined_pipes * 5120;
1326
+
hdisplay > num_joined_pipes * hdisplay_limit;
1326
1327
}
1327
1328
1328
1329
int intel_dp_num_joined_pipes(struct intel_dp *intel_dp,
···
2480
2475
encoder->base.base.id, encoder->base.name,
2481
2476
crtc->base.base.id, crtc->base.name,
2482
2477
adjusted_mode->crtc_clock,
2483
-
dsc ? "on" : "off",
2478
+
str_on_off(dsc),
2484
2479
limits->max_lane_count,
2485
2480
limits->max_rate,
2486
2481
limits->pipe.max_bpp,
···
3404
3399
}
3405
3400
3406
3401
static void
3407
-
intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
3402
+
intel_dp_init_source_oui(struct intel_dp *intel_dp)
3408
3403
{
3409
3404
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3410
3405
u8 oui[] = { 0x00, 0xaa, 0x01 };
3411
3406
u8 buf[3] = {};
3412
3407
3408
+
if (READ_ONCE(intel_dp->oui_valid))
3409
+
return;
3410
+
3411
+
WRITE_ONCE(intel_dp->oui_valid, true);
3412
+
3413
3413
/*
3414
3414
* During driver init, we want to be careful and avoid changing the source OUI if it's
3415
3415
* already set to what we want, so as to avoid clearing any state by accident
3416
3416
*/
3417
-
if (careful) {
3418
-
if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
3419
-
drm_err(&i915->drm, "Failed to read source OUI\n");
3417
+
if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
3418
+
drm_err(&i915->drm, "Failed to read source OUI\n");
3420
3419
3421
-
if (memcmp(oui, buf, sizeof(oui)) == 0)
3422
-
return;
3420
+
if (memcmp(oui, buf, sizeof(oui)) == 0) {
3421
+
/* Assume the OUI was written now. */
3422
+
intel_dp->last_oui_write = jiffies;
3423
+
return;
3423
3424
}
3424
3425
3425
-
if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
3426
-
drm_err(&i915->drm, "Failed to write source OUI\n");
3426
+
if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) {
3427
+
drm_info(&i915->drm, "Failed to write source OUI\n");
3428
+
WRITE_ONCE(intel_dp->oui_valid, false);
3429
+
}
3427
3430
3428
3431
intel_dp->last_oui_write = jiffies;
3432
+
}
3433
+
3434
+
void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp)
3435
+
{
3436
+
WRITE_ONCE(intel_dp->oui_valid, false);
3429
3437
}
3430
3438
3431
3439
void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
···
3476
3458
lspcon_resume(dp_to_dig_port(intel_dp));
3477
3459
3478
3460
/* Write the source OUI as early as possible */
3479
-
if (intel_dp_is_edp(intel_dp))
3480
-
intel_edp_init_source_oui(intel_dp, false);
3461
+
intel_dp_init_source_oui(intel_dp);
3481
3462
3482
3463
/*
3483
3464
* When turning on, we need to retry for 1ms to give the sink
···
4014
3997
intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd);
4015
3998
}
4016
3999
4000
+
static void
4001
+
intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector)
4002
+
{
4003
+
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4004
+
4005
+
/* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
4006
+
if (!HAS_DSC(i915))
4007
+
return;
4008
+
4009
+
if (intel_dp_is_edp(intel_dp))
4010
+
intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],
4011
+
connector);
4012
+
else
4013
+
intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV],
4014
+
connector);
4015
+
}
4016
+
4017
4017
static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
4018
4018
struct drm_display_mode *mode)
4019
4019
{
···
4197
4163
}
4198
4164
4199
4165
/*
4166
+
* If needed, program our source OUI so we can make various Intel-specific AUX services
4167
+
* available (such as HDR backlight controls)
4168
+
*/
4169
+
intel_dp_init_source_oui(intel_dp);
4170
+
4171
+
/*
4200
4172
* This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4201
4173
* for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4202
4174
*/
···
4212
4172
intel_dp_set_max_sink_lane_count(intel_dp);
4213
4173
4214
4174
/* Read the eDP DSC DPCD registers */
4215
-
if (HAS_DSC(dev_priv))
4216
-
intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],
4217
-
connector);
4218
-
4219
-
/*
4220
-
* If needed, program our source OUI so we can make various Intel-specific AUX services
4221
-
* available (such as HDR backlight controls)
4222
-
*/
4223
-
intel_edp_init_source_oui(intel_dp, true);
4175
+
intel_dp_detect_dsc_caps(intel_dp, connector);
4224
4176
4225
4177
return true;
4226
4178
}
···
5038
5006
return true;
5039
5007
5040
5008
/* Retrain if link not ok */
5041
-
return !intel_dp_link_ok(intel_dp, link_status);
5009
+
return !intel_dp_link_ok(intel_dp, link_status) &&
5010
+
!intel_psr_link_ok(intel_dp);
5042
5011
}
5043
5012
5044
5013
bool intel_dp_has_connector(struct intel_dp *intel_dp,
···
5065
5032
}
5066
5033
5067
5034
return false;
5035
+
}
5036
+
5037
+
static void wait_for_connector_hw_done(const struct drm_connector_state *conn_state)
5038
+
{
5039
+
struct intel_connector *connector = to_intel_connector(conn_state->connector);
5040
+
struct intel_display *display = to_intel_display(connector);
5041
+
5042
+
drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex);
5043
+
5044
+
if (!conn_state->commit)
5045
+
return;
5046
+
5047
+
drm_WARN_ON(display->drm,
5048
+
!wait_for_completion_timeout(&conn_state->commit->hw_done,
5049
+
msecs_to_jiffies(5000)));
5068
5050
}
5069
5051
5070
5052
int intel_dp_get_active_pipes(struct intel_dp *intel_dp,
···
5118
5070
if (!crtc_state->hw.active)
5119
5071
continue;
5120
5072
5121
-
if (conn_state->commit)
5122
-
drm_WARN_ON(&i915->drm,
5123
-
!wait_for_completion_timeout(&conn_state->commit->hw_done,
5124
-
msecs_to_jiffies(5000)));
5073
+
wait_for_connector_hw_done(conn_state);
5125
5074
5126
5075
*pipe_mask |= BIT(crtc->pipe);
5127
5076
}
5128
5077
drm_connector_list_iter_end(&conn_iter);
5129
5078
5130
5079
return ret;
5080
+
}
5081
+
5082
+
void intel_dp_flush_connector_commits(struct intel_connector *connector)
5083
+
{
5084
+
wait_for_connector_hw_done(connector->base.state);
5131
5085
}
5132
5086
5133
5087
static bool intel_dp_is_connected(struct intel_dp *intel_dp)
···
5595
5545
}
5596
5546
5597
5547
static void
5598
-
intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector)
5599
-
{
5600
-
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5601
-
5602
-
/* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
5603
-
if (!HAS_DSC(i915))
5604
-
return;
5605
-
5606
-
if (intel_dp_is_edp(intel_dp))
5607
-
intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],
5608
-
connector);
5609
-
else
5610
-
intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV],
5611
-
connector);
5612
-
}
5613
-
5614
-
static void
5615
5548
intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
5616
5549
{
5617
5550
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
···
5628
5595
if (!intel_display_driver_check_access(dev_priv))
5629
5596
return connector->status;
5630
5597
5598
+
intel_dp_flush_connector_commits(intel_connector);
5599
+
5600
+
intel_pps_vdd_on(intel_dp);
5601
+
5631
5602
/* Can't disconnect eDP */
5632
5603
if (intel_dp_is_edp(intel_dp))
5633
5604
status = edp_detect(intel_dp);
···
5662
5625
5663
5626
intel_dp_tunnel_disconnect(intel_dp);
5664
5627
5665
-
goto out;
5628
+
goto out_unset_edid;
5666
5629
}
5667
5630
5631
+
intel_dp_init_source_oui(intel_dp);
5632
+
5668
5633
ret = intel_dp_tunnel_detect(intel_dp, ctx);
5669
-
if (ret == -EDEADLK)
5670
-
return ret;
5634
+
if (ret == -EDEADLK) {
5635
+
status = ret;
5636
+
5637
+
goto out_vdd_off;
5638
+
}
5671
5639
5672
5640
if (ret == 1)
5673
5641
intel_connector->base.epoch_counter++;
···
5700
5658
* with EDID on it
5701
5659
*/
5702
5660
status = connector_status_disconnected;
5703
-
goto out;
5661
+
goto out_unset_edid;
5704
5662
}
5705
5663
5706
5664
/*
···
5729
5687
5730
5688
intel_dp_check_device_service_irq(intel_dp);
5731
5689
5732
-
out:
5690
+
out_unset_edid:
5733
5691
if (status != connector_status_connected && !intel_dp->is_mst)
5734
5692
intel_dp_unset_edid(intel_dp);
5735
5693
···
5738
5696
status,
5739
5697
intel_dp->dpcd,
5740
5698
intel_dp->downstream_ports);
5699
+
out_vdd_off:
5700
+
intel_pps_vdd_off(intel_dp);
5701
+
5741
5702
return status;
5742
5703
}
5743
5704
···
6099
6054
u8 dpcd[DP_RECEIVER_CAP_SIZE];
6100
6055
6101
6056
if (dig_port->base.type == INTEL_OUTPUT_EDP &&
6102
-
(long_hpd || !intel_pps_have_panel_power_or_vdd(intel_dp))) {
6057
+
(long_hpd ||
6058
+
intel_runtime_pm_suspended(&i915->runtime_pm) ||
6059
+
!intel_pps_have_panel_power_or_vdd(intel_dp))) {
6103
6060
/*
6104
6061
* vdd off can generate a long/short pulse on eDP which
6105
6062
* would require vdd on to handle it, and thus we
···
6134
6087
6135
6088
if (long_hpd) {
6136
6089
intel_dp->reset_link_params = true;
6090
+
intel_dp_invalidate_source_oui(intel_dp);
6091
+
6137
6092
return IRQ_NONE;
6138
6093
}
6139
6094
···
6421
6372
6422
6373
out_vdd_off:
6423
6374
intel_pps_vdd_off_sync(intel_dp);
6375
+
intel_bios_fini_panel(&intel_connector->panel);
6424
6376
6425
6377
return false;
6426
6378
}
···
6461
6411
intel_dp_init_connector(struct intel_digital_port *dig_port,
6462
6412
struct intel_connector *intel_connector)
6463
6413
{
6414
+
struct intel_display *display = to_intel_display(dig_port);
6464
6415
struct drm_connector *connector = &intel_connector->base;
6465
6416
struct intel_dp *intel_dp = &dig_port->dp;
6466
6417
struct intel_encoder *intel_encoder = &dig_port->base;
···
6487
6436
6488
6437
if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {
6489
6438
/*
6490
-
* Currently we don't support eDP on TypeC ports, although in
6491
-
* theory it could work on TypeC legacy ports.
6439
+
* Currently we don't support eDP on TypeC ports for DISPLAY_VER < 30,
6440
+
* although in theory it could work on TypeC legacy ports.
6492
6441
*/
6493
-
drm_WARN_ON(dev, intel_encoder_is_tc(intel_encoder));
6442
+
drm_WARN_ON(dev, intel_encoder_is_tc(intel_encoder) &&
6443
+
DISPLAY_VER(dev_priv) < 30);
6494
6444
type = DRM_MODE_CONNECTOR_eDP;
6495
6445
intel_encoder->type = INTEL_OUTPUT_EDP;
6496
6446
···
6525
6473
if (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) < 12)
6526
6474
connector->interlace_allowed = true;
6527
6475
6528
-
intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
6476
+
if (type != DRM_MODE_CONNECTOR_eDP)
6477
+
intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
6529
6478
intel_connector->base.polled = intel_connector->polled;
6530
6479
6531
6480
intel_connector_attach_encoder(intel_connector, intel_encoder);
···
6552
6499
6553
6500
intel_dp_add_properties(intel_dp, connector);
6554
6501
6555
-
if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
6502
+
if (is_hdcp_supported(display, port) && !intel_dp_is_edp(intel_dp)) {
6556
6503
int ret = intel_dp_hdcp_init(dig_port, intel_connector);
6557
6504
if (ret)
6558
6505
drm_dbg_kms(&dev_priv->drm,
+2
drivers/gpu/drm/i915/display/intel_dp.h
+2
drivers/gpu/drm/i915/display/intel_dp.h
···
54
54
int intel_dp_get_active_pipes(struct intel_dp *intel_dp,
55
55
struct drm_modeset_acquire_ctx *ctx,
56
56
u8 *pipe_mask);
57
+
void intel_dp_flush_connector_commits(struct intel_connector *connector);
57
58
void intel_dp_link_check(struct intel_encoder *encoder);
58
59
void intel_dp_check_link_state(struct intel_dp *intel_dp);
59
60
void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode);
···
189
188
void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
190
189
const struct intel_crtc_state *crtc_state);
191
190
191
+
void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp);
192
192
void intel_dp_wait_source_oui(struct intel_dp *intel_dp);
193
193
int intel_dp_output_bpp(enum intel_output_format output_format, int bpp);
194
194
+49
-48
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+49
-48
drivers/gpu/drm/i915/display/intel_dp_hdcp.c
···
58
58
int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
59
59
u8 *an)
60
60
{
61
-
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
61
+
struct intel_display *display = to_intel_display(dig_port);
62
62
u8 aksv[DRM_HDCP_KSV_LEN] = {};
63
63
ssize_t dpcd_ret;
64
64
···
66
66
dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AN,
67
67
an, DRM_HDCP_AN_LEN);
68
68
if (dpcd_ret != DRM_HDCP_AN_LEN) {
69
-
drm_dbg_kms(&i915->drm,
69
+
drm_dbg_kms(display->drm,
70
70
"Failed to write An over DP/AUX (%zd)\n",
71
71
dpcd_ret);
72
72
return dpcd_ret >= 0 ? -EIO : dpcd_ret;
···
82
82
dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AKSV,
83
83
aksv, DRM_HDCP_KSV_LEN);
84
84
if (dpcd_ret != DRM_HDCP_KSV_LEN) {
85
-
drm_dbg_kms(&i915->drm,
85
+
drm_dbg_kms(display->drm,
86
86
"Failed to write Aksv over DP/AUX (%zd)\n",
87
87
dpcd_ret);
88
88
return dpcd_ret >= 0 ? -EIO : dpcd_ret;
···
93
93
static int intel_dp_hdcp_read_bksv(struct intel_digital_port *dig_port,
94
94
u8 *bksv)
95
95
{
96
-
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
96
+
struct intel_display *display = to_intel_display(dig_port);
97
97
ssize_t ret;
98
98
99
99
ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
100
100
DRM_HDCP_KSV_LEN);
101
101
if (ret != DRM_HDCP_KSV_LEN) {
102
-
drm_dbg_kms(&i915->drm,
102
+
drm_dbg_kms(display->drm,
103
103
"Read Bksv from DP/AUX failed (%zd)\n", ret);
104
104
return ret >= 0 ? -EIO : ret;
105
105
}
···
109
109
static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port,
110
110
u8 *bstatus)
111
111
{
112
-
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
112
+
struct intel_display *display = to_intel_display(dig_port);
113
113
ssize_t ret;
114
114
115
115
/*
···
120
120
ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BINFO,
121
121
bstatus, DRM_HDCP_BSTATUS_LEN);
122
122
if (ret != DRM_HDCP_BSTATUS_LEN) {
123
-
drm_dbg_kms(&i915->drm,
123
+
drm_dbg_kms(display->drm,
124
124
"Read bstatus from DP/AUX failed (%zd)\n", ret);
125
125
return ret >= 0 ? -EIO : ret;
126
126
}
···
129
129
130
130
static
131
131
int intel_dp_hdcp_read_bcaps(struct drm_dp_aux *aux,
132
-
struct drm_i915_private *i915,
132
+
struct intel_display *display,
133
133
u8 *bcaps)
134
134
{
135
135
ssize_t ret;
···
137
137
ret = drm_dp_dpcd_read(aux, DP_AUX_HDCP_BCAPS,
138
138
bcaps, 1);
139
139
if (ret != 1) {
140
-
drm_dbg_kms(&i915->drm,
140
+
drm_dbg_kms(display->drm,
141
141
"Read bcaps from DP/AUX failed (%zd)\n", ret);
142
142
return ret >= 0 ? -EIO : ret;
143
143
}
···
149
149
int intel_dp_hdcp_repeater_present(struct intel_digital_port *dig_port,
150
150
bool *repeater_present)
151
151
{
152
-
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
152
+
struct intel_display *display = to_intel_display(dig_port);
153
153
ssize_t ret;
154
154
u8 bcaps;
155
155
156
-
ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, i915, &bcaps);
156
+
ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, display, &bcaps);
157
157
if (ret)
158
158
return ret;
159
159
···
165
165
int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
166
166
u8 *ri_prime)
167
167
{
168
-
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
168
+
struct intel_display *display = to_intel_display(dig_port);
169
169
ssize_t ret;
170
170
171
171
ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
172
172
ri_prime, DRM_HDCP_RI_LEN);
173
173
if (ret != DRM_HDCP_RI_LEN) {
174
-
drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n",
174
+
drm_dbg_kms(display->drm,
175
+
"Read Ri' from DP/AUX failed (%zd)\n",
175
176
ret);
176
177
return ret >= 0 ? -EIO : ret;
177
178
}
···
183
182
int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
184
183
bool *ksv_ready)
185
184
{
186
-
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
185
+
struct intel_display *display = to_intel_display(dig_port);
187
186
ssize_t ret;
188
187
u8 bstatus;
189
188
190
189
ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
191
190
&bstatus, 1);
192
191
if (ret != 1) {
193
-
drm_dbg_kms(&i915->drm,
192
+
drm_dbg_kms(display->drm,
194
193
"Read bstatus from DP/AUX failed (%zd)\n", ret);
195
194
return ret >= 0 ? -EIO : ret;
196
195
}
···
202
201
int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
203
202
int num_downstream, u8 *ksv_fifo)
204
203
{
205
-
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
204
+
struct intel_display *display = to_intel_display(dig_port);
206
205
ssize_t ret;
207
206
int i;
208
207
···
214
213
ksv_fifo + i * DRM_HDCP_KSV_LEN,
215
214
len);
216
215
if (ret != len) {
217
-
drm_dbg_kms(&i915->drm,
216
+
drm_dbg_kms(display->drm,
218
217
"Read ksv[%d] from DP/AUX failed (%zd)\n",
219
218
i, ret);
220
219
return ret >= 0 ? -EIO : ret;
···
227
226
int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
228
227
int i, u32 *part)
229
228
{
230
-
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
229
+
struct intel_display *display = to_intel_display(dig_port);
231
230
ssize_t ret;
232
231
233
232
if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
···
237
236
DP_AUX_HDCP_V_PRIME(i), part,
238
237
DRM_HDCP_V_PRIME_PART_LEN);
239
238
if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
240
-
drm_dbg_kms(&i915->drm,
239
+
drm_dbg_kms(display->drm,
241
240
"Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
242
241
return ret >= 0 ? -EIO : ret;
243
242
}
···
257
256
bool intel_dp_hdcp_check_link(struct intel_digital_port *dig_port,
258
257
struct intel_connector *connector)
259
258
{
260
-
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
259
+
struct intel_display *display = to_intel_display(dig_port);
261
260
ssize_t ret;
262
261
u8 bstatus;
263
262
264
263
ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
265
264
&bstatus, 1);
266
265
if (ret != 1) {
267
-
drm_dbg_kms(&i915->drm,
266
+
drm_dbg_kms(display->drm,
268
267
"Read bstatus from DP/AUX failed (%zd)\n", ret);
269
268
return false;
270
269
}
···
276
275
int intel_dp_hdcp_get_capability(struct intel_digital_port *dig_port,
277
276
bool *hdcp_capable)
278
277
{
279
-
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
278
+
struct intel_display *display = to_intel_display(dig_port);
280
279
ssize_t ret;
281
280
u8 bcaps;
282
281
283
-
ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, i915, &bcaps);
282
+
ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, display, &bcaps);
284
283
if (ret)
285
284
return ret;
286
285
···
343
342
intel_dp_hdcp2_read_rx_status(struct intel_connector *connector,
344
343
u8 *rx_status)
345
344
{
346
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
345
+
struct intel_display *display = to_intel_display(connector);
347
346
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
348
347
struct drm_dp_aux *aux = &dig_port->dp.aux;
349
348
ssize_t ret;
···
352
351
DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
353
352
HDCP_2_2_DP_RXSTATUS_LEN);
354
353
if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
355
-
drm_dbg_kms(&i915->drm,
354
+
drm_dbg_kms(display->drm,
356
355
"Read bstatus from DP/AUX failed (%zd)\n", ret);
357
356
return ret >= 0 ? -EIO : ret;
358
357
}
···
398
397
intel_dp_hdcp2_wait_for_msg(struct intel_connector *connector,
399
398
const struct hdcp2_dp_msg_data *hdcp2_msg_data)
400
399
{
401
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
400
+
struct intel_display *display = to_intel_display(connector);
402
401
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
403
402
struct intel_dp *dp = &dig_port->dp;
404
403
struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
···
431
430
}
432
431
433
432
if (ret)
434
-
drm_dbg_kms(&i915->drm,
433
+
drm_dbg_kms(display->drm,
435
434
"msg_id %d, ret %d, timeout(mSec): %d\n",
436
435
hdcp2_msg_data->msg_id, ret, timeout);
437
436
···
515
514
int intel_dp_hdcp2_read_msg(struct intel_connector *connector,
516
515
u8 msg_id, void *buf, size_t size)
517
516
{
517
+
struct intel_display *display = to_intel_display(connector);
518
518
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
519
-
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
520
519
struct drm_dp_aux *aux = &dig_port->dp.aux;
521
520
struct intel_dp *dp = &dig_port->dp;
522
521
struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
···
569
568
ret = drm_dp_dpcd_read(aux, offset,
570
569
(void *)byte, len);
571
570
if (ret < 0) {
572
-
drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n",
571
+
drm_dbg_kms(display->drm, "msg_id %d, ret %zd\n",
573
572
msg_id, ret);
574
573
return ret;
575
574
}
···
582
581
if (hdcp2_msg_data->msg_read_timeout > 0) {
583
582
msg_expired = ktime_after(ktime_get_raw(), msg_end);
584
583
if (msg_expired) {
585
-
drm_dbg_kms(&i915->drm, "msg_id %d, entire msg read timeout(mSec): %d\n",
584
+
drm_dbg_kms(display->drm,
585
+
"msg_id %d, entire msg read timeout(mSec): %d\n",
586
586
msg_id, hdcp2_msg_data->msg_read_timeout);
587
587
return -ETIMEDOUT;
588
588
}
···
698
696
bool *hdcp_capable,
699
697
bool *hdcp2_capable)
700
698
{
701
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
699
+
struct intel_display *display = to_intel_display(connector);
702
700
struct drm_dp_aux *aux;
703
701
u8 bcaps;
704
702
int ret;
···
711
709
aux = &connector->port->aux;
712
710
ret = _intel_dp_hdcp2_get_capability(aux, hdcp2_capable);
713
711
if (ret)
714
-
drm_dbg_kms(&i915->drm,
712
+
drm_dbg_kms(display->drm,
715
713
"HDCP2 DPCD capability read failed err: %d\n", ret);
716
714
717
-
ret = intel_dp_hdcp_read_bcaps(aux, i915, &bcaps);
715
+
ret = intel_dp_hdcp_read_bcaps(aux, display, &bcaps);
718
716
if (ret)
719
717
return ret;
720
718
···
747
745
intel_dp_mst_toggle_hdcp_stream_select(struct intel_connector *connector,
748
746
bool enable)
749
747
{
748
+
struct intel_display *display = to_intel_display(connector);
750
749
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
751
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
752
750
struct intel_hdcp *hdcp = &connector->hdcp;
753
751
int ret;
754
752
···
756
754
hdcp->stream_transcoder, enable,
757
755
TRANS_DDI_HDCP_SELECT);
758
756
if (ret)
759
-
drm_err(&i915->drm, "%s HDCP stream select failed (%d)\n",
757
+
drm_err(display->drm, "%s HDCP stream select failed (%d)\n",
760
758
enable ? "Enable" : "Disable", ret);
761
759
return ret;
762
760
}
···
765
763
intel_dp_mst_hdcp_stream_encryption(struct intel_connector *connector,
766
764
bool enable)
767
765
{
766
+
struct intel_display *display = to_intel_display(connector);
768
767
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
769
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
770
768
struct intel_hdcp *hdcp = &connector->hdcp;
771
769
enum port port = dig_port->base.port;
772
770
enum transcoder cpu_transcoder = hdcp->stream_transcoder;
···
782
780
return -EINVAL;
783
781
784
782
/* Wait for encryption confirmation */
785
-
if (intel_de_wait(i915, HDCP_STATUS(i915, cpu_transcoder, port),
783
+
if (intel_de_wait(display, HDCP_STATUS(display, cpu_transcoder, port),
786
784
stream_enc_status, enable ? stream_enc_status : 0,
787
785
HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
788
-
drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
789
-
transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled");
786
+
drm_err(display->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
787
+
transcoder_name(cpu_transcoder), str_enabled_disabled(enable));
790
788
return -ETIMEDOUT;
791
789
}
792
790
···
797
795
intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector,
798
796
bool enable)
799
797
{
798
+
struct intel_display *display = to_intel_display(connector);
800
799
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
801
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
802
800
struct hdcp_port_data *data = &dig_port->hdcp_port_data;
803
801
struct intel_hdcp *hdcp = &connector->hdcp;
804
802
enum transcoder cpu_transcoder = hdcp->stream_transcoder;
···
806
804
enum port port = dig_port->base.port;
807
805
int ret;
808
806
809
-
drm_WARN_ON(&i915->drm, enable &&
810
-
!!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915, cpu_transcoder, port))
807
+
drm_WARN_ON(display->drm, enable &&
808
+
!!(intel_de_read(display, HDCP2_AUTH_STREAM(display, cpu_transcoder, port))
811
809
& AUTH_STREAM_TYPE) != data->streams[0].stream_type);
812
810
813
811
ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable);
···
815
813
return ret;
816
814
817
815
/* Wait for encryption confirmation */
818
-
if (intel_de_wait(i915, HDCP2_STREAM_STATUS(i915, cpu_transcoder, pipe),
816
+
if (intel_de_wait(display, HDCP2_STREAM_STATUS(display, cpu_transcoder, pipe),
819
817
STREAM_ENCRYPTION_STATUS,
820
818
enable ? STREAM_ENCRYPTION_STATUS : 0,
821
819
HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
822
-
drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
823
-
transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled");
820
+
drm_err(display->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
821
+
transcoder_name(cpu_transcoder), str_enabled_disabled(enable));
824
822
return -ETIMEDOUT;
825
823
}
826
824
···
875
873
int intel_dp_hdcp_init(struct intel_digital_port *dig_port,
876
874
struct intel_connector *intel_connector)
877
875
{
878
-
struct drm_device *dev = intel_connector->base.dev;
879
-
struct drm_i915_private *dev_priv = to_i915(dev);
876
+
struct intel_display *display = to_intel_display(dig_port);
880
877
struct intel_encoder *intel_encoder = &dig_port->base;
881
878
enum port port = intel_encoder->port;
882
879
struct intel_dp *intel_dp = &dig_port->dp;
883
880
884
-
if (!is_hdcp_supported(dev_priv, port))
881
+
if (!is_hdcp_supported(display, port))
885
882
return 0;
886
883
887
884
if (intel_connector->mst_port)
+3
-1
drivers/gpu/drm/i915/display/intel_dp_mst.c
+3
-1
drivers/gpu/drm/i915/display/intel_dp_mst.c
···
153
153
{
154
154
const struct drm_display_mode *adjusted_mode =
155
155
&crtc_state->hw.adjusted_mode;
156
-
int num_joined_pipes = crtc_state->joiner_pipes;
156
+
int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state);
157
157
158
158
return intel_dp_dsc_get_slice_count(connector,
159
159
adjusted_mode->clock,
···
1572
1572
1573
1573
if (!intel_display_driver_check_access(i915))
1574
1574
return connector->status;
1575
+
1576
+
intel_dp_flush_connector_commits(intel_connector);
1575
1577
1576
1578
return drm_dp_mst_detect_port(connector, ctx, &intel_dp->mst_mgr,
1577
1579
intel_connector->port);
+78
-80
drivers/gpu/drm/i915/display/intel_dpio_phy.c
+78
-80
drivers/gpu/drm/i915/display/intel_dpio_phy.c
···
219
219
};
220
220
221
221
static const struct bxt_dpio_phy_info *
222
-
bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count)
222
+
bxt_get_phy_list(struct intel_display *display, int *count)
223
223
{
224
+
struct drm_i915_private *dev_priv = to_i915(display->drm);
225
+
224
226
if (IS_GEMINILAKE(dev_priv)) {
225
227
*count = ARRAY_SIZE(glk_dpio_phy_info);
226
228
return glk_dpio_phy_info;
···
233
231
}
234
232
235
233
static const struct bxt_dpio_phy_info *
236
-
bxt_get_phy_info(struct drm_i915_private *dev_priv, enum dpio_phy phy)
234
+
bxt_get_phy_info(struct intel_display *display, enum dpio_phy phy)
237
235
{
238
236
int count;
239
237
const struct bxt_dpio_phy_info *phy_list =
240
-
bxt_get_phy_list(dev_priv, &count);
238
+
bxt_get_phy_list(display, &count);
241
239
242
240
return &phy_list[phy];
243
241
}
244
242
245
-
void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
243
+
void bxt_port_to_phy_channel(struct intel_display *display, enum port port,
246
244
enum dpio_phy *phy, enum dpio_channel *ch)
247
245
{
248
246
const struct bxt_dpio_phy_info *phy_info, *phys;
249
247
int i, count;
250
248
251
-
phys = bxt_get_phy_list(dev_priv, &count);
249
+
phys = bxt_get_phy_list(display, &count);
252
250
253
251
for (i = 0; i < count; i++) {
254
252
phy_info = &phys[i];
···
267
265
}
268
266
}
269
267
270
-
drm_WARN(&dev_priv->drm, 1, "PHY not found for PORT %c",
268
+
drm_WARN(display->drm, 1, "PHY not found for PORT %c",
271
269
port_name(port));
272
270
*phy = DPIO_PHY0;
273
271
*ch = DPIO_CH0;
···
277
275
* Like intel_de_rmw() but reads from a single per-lane register and
278
276
* writes to the group register to write the same value to all the lanes.
279
277
*/
280
-
static u32 bxt_dpio_phy_rmw_grp(struct drm_i915_private *i915,
278
+
static u32 bxt_dpio_phy_rmw_grp(struct intel_display *display,
281
279
i915_reg_t reg_single,
282
280
i915_reg_t reg_group,
283
281
u32 clear, u32 set)
284
282
{
285
283
u32 old, val;
286
284
287
-
old = intel_de_read(i915, reg_single);
285
+
old = intel_de_read(display, reg_single);
288
286
val = (old & ~clear) | set;
289
-
intel_de_write(i915, reg_group, val);
287
+
intel_de_write(display, reg_group, val);
290
288
291
289
return old;
292
290
}
···
294
292
void bxt_dpio_phy_set_signal_levels(struct intel_encoder *encoder,
295
293
const struct intel_crtc_state *crtc_state)
296
294
{
297
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
295
+
struct intel_display *display = to_intel_display(encoder);
298
296
const struct intel_ddi_buf_trans *trans;
299
297
enum dpio_channel ch;
300
298
enum dpio_phy phy;
301
299
int lane, n_entries;
302
300
303
301
trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
304
-
if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
302
+
if (drm_WARN_ON_ONCE(display->drm, !trans))
305
303
return;
306
304
307
-
bxt_port_to_phy_channel(dev_priv, encoder->port, &phy, &ch);
305
+
bxt_port_to_phy_channel(display, encoder->port, &phy, &ch);
308
306
309
307
/*
310
308
* While we write to the group register to program all lanes at once we
311
309
* can read only lane registers and we pick lanes 0/1 for that.
312
310
*/
313
-
bxt_dpio_phy_rmw_grp(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch),
311
+
bxt_dpio_phy_rmw_grp(display, BXT_PORT_PCS_DW10_LN01(phy, ch),
314
312
BXT_PORT_PCS_DW10_GRP(phy, ch),
315
313
TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT, 0);
316
314
317
315
for (lane = 0; lane < crtc_state->lane_count; lane++) {
318
316
int level = intel_ddi_level(encoder, crtc_state, lane);
319
317
320
-
intel_de_rmw(dev_priv, BXT_PORT_TX_DW2_LN(phy, ch, lane),
318
+
intel_de_rmw(display, BXT_PORT_TX_DW2_LN(phy, ch, lane),
321
319
MARGIN_000_MASK | UNIQ_TRANS_SCALE_MASK,
322
320
MARGIN_000(trans->entries[level].bxt.margin) |
323
321
UNIQ_TRANS_SCALE(trans->entries[level].bxt.scale));
···
327
325
int level = intel_ddi_level(encoder, crtc_state, lane);
328
326
u32 val;
329
327
330
-
intel_de_rmw(dev_priv, BXT_PORT_TX_DW3_LN(phy, ch, lane),
328
+
intel_de_rmw(display, BXT_PORT_TX_DW3_LN(phy, ch, lane),
331
329
SCALE_DCOMP_METHOD,
332
330
trans->entries[level].bxt.enable ?
333
331
SCALE_DCOMP_METHOD : 0);
334
332
335
-
val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN(phy, ch, lane));
333
+
val = intel_de_read(display, BXT_PORT_TX_DW3_LN(phy, ch, lane));
336
334
if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
337
-
drm_err(&dev_priv->drm,
335
+
drm_err(display->drm,
338
336
"Disabled scaling while ouniqetrangenmethod was set");
339
337
}
340
338
341
339
for (lane = 0; lane < crtc_state->lane_count; lane++) {
342
340
int level = intel_ddi_level(encoder, crtc_state, lane);
343
341
344
-
intel_de_rmw(dev_priv, BXT_PORT_TX_DW4_LN(phy, ch, lane),
342
+
intel_de_rmw(display, BXT_PORT_TX_DW4_LN(phy, ch, lane),
345
343
DE_EMPHASIS_MASK,
346
344
DE_EMPHASIS(trans->entries[level].bxt.deemphasis));
347
345
}
348
346
349
-
bxt_dpio_phy_rmw_grp(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch),
347
+
bxt_dpio_phy_rmw_grp(display, BXT_PORT_PCS_DW10_LN01(phy, ch),
350
348
BXT_PORT_PCS_DW10_GRP(phy, ch),
351
349
0, TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
352
350
}
353
351
354
-
bool bxt_dpio_phy_is_enabled(struct drm_i915_private *dev_priv,
352
+
bool bxt_dpio_phy_is_enabled(struct intel_display *display,
355
353
enum dpio_phy phy)
356
354
{
357
355
const struct bxt_dpio_phy_info *phy_info;
358
356
359
-
phy_info = bxt_get_phy_info(dev_priv, phy);
357
+
phy_info = bxt_get_phy_info(display, phy);
360
358
361
-
if (!(intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))
359
+
if (!(intel_de_read(display, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))
362
360
return false;
363
361
364
-
if ((intel_de_read(dev_priv, BXT_PORT_CL1CM_DW0(phy)) &
362
+
if ((intel_de_read(display, BXT_PORT_CL1CM_DW0(phy)) &
365
363
(PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
366
-
drm_dbg(&dev_priv->drm,
364
+
drm_dbg(display->drm,
367
365
"DDI PHY %d powered, but power hasn't settled\n", phy);
368
366
369
367
return false;
370
368
}
371
369
372
-
if (!(intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
373
-
drm_dbg(&dev_priv->drm,
370
+
if (!(intel_de_read(display, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
371
+
drm_dbg(display->drm,
374
372
"DDI PHY %d powered, but still in reset\n", phy);
375
373
376
374
return false;
···
379
377
return true;
380
378
}
381
379
382
-
static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
380
+
static u32 bxt_get_grc(struct intel_display *display, enum dpio_phy phy)
383
381
{
384
-
u32 val = intel_de_read(dev_priv, BXT_PORT_REF_DW6(phy));
382
+
u32 val = intel_de_read(display, BXT_PORT_REF_DW6(phy));
385
383
386
384
return REG_FIELD_GET(GRC_CODE_MASK, val);
387
385
}
388
386
389
-
static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
387
+
static void bxt_phy_wait_grc_done(struct intel_display *display,
390
388
enum dpio_phy phy)
391
389
{
392
-
if (intel_de_wait_for_set(dev_priv, BXT_PORT_REF_DW3(phy),
393
-
GRC_DONE, 10))
394
-
drm_err(&dev_priv->drm, "timeout waiting for PHY%d GRC\n",
395
-
phy);
390
+
if (intel_de_wait_for_set(display, BXT_PORT_REF_DW3(phy), GRC_DONE, 10))
391
+
drm_err(display->drm, "timeout waiting for PHY%d GRC\n", phy);
396
392
}
397
393
398
-
static void _bxt_dpio_phy_init(struct drm_i915_private *dev_priv,
399
-
enum dpio_phy phy)
394
+
static void _bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy)
400
395
{
401
396
const struct bxt_dpio_phy_info *phy_info;
402
397
u32 val;
403
398
404
-
phy_info = bxt_get_phy_info(dev_priv, phy);
399
+
phy_info = bxt_get_phy_info(display, phy);
405
400
406
-
if (bxt_dpio_phy_is_enabled(dev_priv, phy)) {
401
+
if (bxt_dpio_phy_is_enabled(display, phy)) {
407
402
/* Still read out the GRC value for state verification */
408
403
if (phy_info->rcomp_phy != -1)
409
-
dev_priv->display.state.bxt_phy_grc = bxt_get_grc(dev_priv, phy);
404
+
display->state.bxt_phy_grc = bxt_get_grc(display, phy);
410
405
411
-
if (bxt_dpio_phy_verify_state(dev_priv, phy)) {
412
-
drm_dbg(&dev_priv->drm, "DDI PHY %d already enabled, "
406
+
if (bxt_dpio_phy_verify_state(display, phy)) {
407
+
drm_dbg(display->drm, "DDI PHY %d already enabled, "
413
408
"won't reprogram it\n", phy);
414
409
return;
415
410
}
416
411
417
-
drm_dbg(&dev_priv->drm,
412
+
drm_dbg(display->drm,
418
413
"DDI PHY %d enabled with invalid state, "
419
414
"force reprogramming it\n", phy);
420
415
}
421
416
422
-
intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, 0, phy_info->pwron_mask);
417
+
intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, 0, phy_info->pwron_mask);
423
418
424
419
/*
425
420
* The PHY registers start out inaccessible and respond to reads with
···
426
427
* The flag should get set in 100us according to the HW team, but
427
428
* use 1ms due to occasional timeouts observed with that.
428
429
*/
429
-
if (intel_de_wait_fw(dev_priv, BXT_PORT_CL1CM_DW0(phy),
430
+
if (intel_de_wait_fw(display, BXT_PORT_CL1CM_DW0(phy),
430
431
PHY_RESERVED | PHY_POWER_GOOD, PHY_POWER_GOOD, 1))
431
-
drm_err(&dev_priv->drm, "timeout during PHY%d power on\n",
432
+
drm_err(display->drm, "timeout during PHY%d power on\n",
432
433
phy);
433
434
434
435
/* Program PLL Rcomp code offset */
435
-
intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW9(phy),
436
+
intel_de_rmw(display, BXT_PORT_CL1CM_DW9(phy),
436
437
IREF0RC_OFFSET_MASK, IREF0RC_OFFSET(0xE4));
437
438
438
-
intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW10(phy),
439
+
intel_de_rmw(display, BXT_PORT_CL1CM_DW10(phy),
439
440
IREF1RC_OFFSET_MASK, IREF1RC_OFFSET(0xE4));
440
441
441
442
/* Program power gating */
442
-
intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW28(phy), 0,
443
+
intel_de_rmw(display, BXT_PORT_CL1CM_DW28(phy), 0,
443
444
OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG);
444
445
445
446
if (phy_info->dual_channel)
446
-
intel_de_rmw(dev_priv, BXT_PORT_CL2CM_DW6(phy), 0,
447
+
intel_de_rmw(display, BXT_PORT_CL2CM_DW6(phy), 0,
447
448
DW6_OLDO_DYN_PWR_DOWN_EN);
448
449
449
450
if (phy_info->rcomp_phy != -1) {
450
451
u32 grc_code;
451
452
452
-
bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy);
453
+
bxt_phy_wait_grc_done(display, phy_info->rcomp_phy);
453
454
454
455
/*
455
456
* PHY0 isn't connected to an RCOMP resistor so copy over
456
457
* the corresponding calibrated value from PHY1, and disable
457
458
* the automatic calibration on PHY0.
458
459
*/
459
-
val = bxt_get_grc(dev_priv, phy_info->rcomp_phy);
460
-
dev_priv->display.state.bxt_phy_grc = val;
460
+
val = bxt_get_grc(display, phy_info->rcomp_phy);
461
+
display->state.bxt_phy_grc = val;
461
462
462
463
grc_code = GRC_CODE_FAST(val) |
463
464
GRC_CODE_SLOW(val) |
464
465
GRC_CODE_NOM(val);
465
-
intel_de_write(dev_priv, BXT_PORT_REF_DW6(phy), grc_code);
466
-
intel_de_rmw(dev_priv, BXT_PORT_REF_DW8(phy),
466
+
intel_de_write(display, BXT_PORT_REF_DW6(phy), grc_code);
467
+
intel_de_rmw(display, BXT_PORT_REF_DW8(phy),
467
468
0, GRC_DIS | GRC_RDY_OVRD);
468
469
}
469
470
470
471
if (phy_info->reset_delay)
471
472
udelay(phy_info->reset_delay);
472
473
473
-
intel_de_rmw(dev_priv, BXT_PHY_CTL_FAMILY(phy), 0, COMMON_RESET_DIS);
474
+
intel_de_rmw(display, BXT_PHY_CTL_FAMILY(phy), 0, COMMON_RESET_DIS);
474
475
}
475
476
476
-
void bxt_dpio_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
477
+
void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy)
477
478
{
478
479
const struct bxt_dpio_phy_info *phy_info;
479
480
480
-
phy_info = bxt_get_phy_info(dev_priv, phy);
481
+
phy_info = bxt_get_phy_info(display, phy);
481
482
482
-
intel_de_rmw(dev_priv, BXT_PHY_CTL_FAMILY(phy), COMMON_RESET_DIS, 0);
483
+
intel_de_rmw(display, BXT_PHY_CTL_FAMILY(phy), COMMON_RESET_DIS, 0);
483
484
484
-
intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, phy_info->pwron_mask, 0);
485
+
intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, phy_info->pwron_mask, 0);
485
486
}
486
487
487
-
void bxt_dpio_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
488
+
void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy)
488
489
{
489
-
const struct bxt_dpio_phy_info *phy_info =
490
-
bxt_get_phy_info(dev_priv, phy);
490
+
const struct bxt_dpio_phy_info *phy_info = bxt_get_phy_info(display, phy);
491
491
enum dpio_phy rcomp_phy = phy_info->rcomp_phy;
492
492
bool was_enabled;
493
493
494
-
lockdep_assert_held(&dev_priv->display.power.domains.lock);
494
+
lockdep_assert_held(&display->power.domains.lock);
495
495
496
496
was_enabled = true;
497
497
if (rcomp_phy != -1)
498
-
was_enabled = bxt_dpio_phy_is_enabled(dev_priv, rcomp_phy);
498
+
was_enabled = bxt_dpio_phy_is_enabled(display, rcomp_phy);
499
499
500
500
/*
501
501
* We need to copy the GRC calibration value from rcomp_phy,
502
502
* so make sure it's powered up.
503
503
*/
504
504
if (!was_enabled)
505
-
_bxt_dpio_phy_init(dev_priv, rcomp_phy);
505
+
_bxt_dpio_phy_init(display, rcomp_phy);
506
506
507
-
_bxt_dpio_phy_init(dev_priv, phy);
507
+
_bxt_dpio_phy_init(display, phy);
508
508
509
509
if (!was_enabled)
510
-
bxt_dpio_phy_uninit(dev_priv, rcomp_phy);
510
+
bxt_dpio_phy_uninit(display, rcomp_phy);
511
511
}
512
512
513
513
static bool __printf(6, 7)
514
-
__phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
514
+
__phy_reg_verify_state(struct intel_display *display, enum dpio_phy phy,
515
515
i915_reg_t reg, u32 mask, u32 expected,
516
516
const char *reg_fmt, ...)
517
517
{
···
518
520
va_list args;
519
521
u32 val;
520
522
521
-
val = intel_de_read(dev_priv, reg);
523
+
val = intel_de_read(display, reg);
522
524
if ((val & mask) == expected)
523
525
return true;
524
526
···
526
528
vaf.fmt = reg_fmt;
527
529
vaf.va = &args;
528
530
529
-
drm_dbg(&dev_priv->drm, "DDI PHY %d reg %pV [%08x] state mismatch: "
531
+
drm_dbg(display->drm, "DDI PHY %d reg %pV [%08x] state mismatch: "
530
532
"current %08x, expected %08x (mask %08x)\n",
531
533
phy, &vaf, reg.reg, val, (val & ~mask) | expected,
532
534
mask);
···
536
538
return false;
537
539
}
538
540
539
-
bool bxt_dpio_phy_verify_state(struct drm_i915_private *dev_priv,
541
+
bool bxt_dpio_phy_verify_state(struct intel_display *display,
540
542
enum dpio_phy phy)
541
543
{
542
544
const struct bxt_dpio_phy_info *phy_info;
543
545
u32 mask;
544
546
bool ok;
545
547
546
-
phy_info = bxt_get_phy_info(dev_priv, phy);
548
+
phy_info = bxt_get_phy_info(display, phy);
547
549
548
550
#define _CHK(reg, mask, exp, fmt, ...) \
549
-
__phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \
551
+
__phy_reg_verify_state(display, phy, reg, mask, exp, fmt, \
550
552
## __VA_ARGS__)
551
553
552
-
if (!bxt_dpio_phy_is_enabled(dev_priv, phy))
554
+
if (!bxt_dpio_phy_is_enabled(display, phy))
553
555
return false;
554
556
555
557
ok = true;
···
573
575
"BXT_PORT_CL2CM_DW6(%d)", phy);
574
576
575
577
if (phy_info->rcomp_phy != -1) {
576
-
u32 grc_code = dev_priv->display.state.bxt_phy_grc;
578
+
u32 grc_code = display->state.bxt_phy_grc;
577
579
578
580
grc_code = GRC_CODE_FAST(grc_code) |
579
581
GRC_CODE_SLOW(grc_code) |
···
612
614
void bxt_dpio_phy_set_lane_optim_mask(struct intel_encoder *encoder,
613
615
u8 lane_lat_optim_mask)
614
616
{
615
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
617
+
struct intel_display *display = to_intel_display(encoder);
616
618
enum port port = encoder->port;
617
619
enum dpio_phy phy;
618
620
enum dpio_channel ch;
619
621
int lane;
620
622
621
-
bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
623
+
bxt_port_to_phy_channel(display, port, &phy, &ch);
622
624
623
625
for (lane = 0; lane < 4; lane++) {
624
626
/*
625
627
* Note that on CHV this flag is called UPAR, but has
626
628
* the same function.
627
629
*/
628
-
intel_de_rmw(dev_priv, BXT_PORT_TX_DW14_LN(phy, ch, lane),
630
+
intel_de_rmw(display, BXT_PORT_TX_DW14_LN(phy, ch, lane),
629
631
LATENCY_OPTIM,
630
632
lane_lat_optim_mask & BIT(lane) ? LATENCY_OPTIM : 0);
631
633
}
···
634
636
u8
635
637
bxt_dpio_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
636
638
{
637
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
639
+
struct intel_display *display = to_intel_display(encoder);
638
640
enum port port = encoder->port;
639
641
enum dpio_phy phy;
640
642
enum dpio_channel ch;
641
643
int lane;
642
644
u8 mask;
643
645
644
-
bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
646
+
bxt_port_to_phy_channel(display, port, &phy, &ch);
645
647
646
648
mask = 0;
647
649
for (lane = 0; lane < 4; lane++) {
648
-
u32 val = intel_de_read(dev_priv,
650
+
u32 val = intel_de_read(display,
649
651
BXT_PORT_TX_DW14_LN(phy, ch, lane));
650
652
651
653
if (val & LATENCY_OPTIM)
+11
-11
drivers/gpu/drm/i915/display/intel_dpio_phy.h
+11
-11
drivers/gpu/drm/i915/display/intel_dpio_phy.h
···
10
10
11
11
enum pipe;
12
12
enum port;
13
-
struct drm_i915_private;
14
13
struct intel_crtc_state;
15
14
struct intel_digital_port;
15
+
struct intel_display;
16
16
struct intel_encoder;
17
17
18
18
enum dpio_channel {
···
27
27
};
28
28
29
29
#ifdef I915
30
-
void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
30
+
void bxt_port_to_phy_channel(struct intel_display *display, enum port port,
31
31
enum dpio_phy *phy, enum dpio_channel *ch);
32
32
void bxt_dpio_phy_set_signal_levels(struct intel_encoder *encoder,
33
33
const struct intel_crtc_state *crtc_state);
34
-
void bxt_dpio_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
35
-
void bxt_dpio_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
36
-
bool bxt_dpio_phy_is_enabled(struct drm_i915_private *dev_priv,
34
+
void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy);
35
+
void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy);
36
+
bool bxt_dpio_phy_is_enabled(struct intel_display *display,
37
37
enum dpio_phy phy);
38
-
bool bxt_dpio_phy_verify_state(struct drm_i915_private *dev_priv,
38
+
bool bxt_dpio_phy_verify_state(struct intel_display *display,
39
39
enum dpio_phy phy);
40
40
u8 bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count);
41
41
void bxt_dpio_phy_set_lane_optim_mask(struct intel_encoder *encoder,
···
73
73
void vlv_phy_reset_lanes(struct intel_encoder *encoder,
74
74
const struct intel_crtc_state *old_crtc_state);
75
75
#else
76
-
static inline void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
76
+
static inline void bxt_port_to_phy_channel(struct intel_display *display, enum port port,
77
77
enum dpio_phy *phy, enum dpio_channel *ch)
78
78
{
79
79
}
···
81
81
const struct intel_crtc_state *crtc_state)
82
82
{
83
83
}
84
-
static inline void bxt_dpio_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
84
+
static inline void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy)
85
85
{
86
86
}
87
-
static inline void bxt_dpio_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
87
+
static inline void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy)
88
88
{
89
89
}
90
-
static inline bool bxt_dpio_phy_is_enabled(struct drm_i915_private *dev_priv,
90
+
static inline bool bxt_dpio_phy_is_enabled(struct intel_display *display,
91
91
enum dpio_phy phy)
92
92
{
93
93
return false;
94
94
}
95
-
static inline bool bxt_dpio_phy_verify_state(struct drm_i915_private *dev_priv,
95
+
static inline bool bxt_dpio_phy_verify_state(struct intel_display *display,
96
96
enum dpio_phy phy)
97
97
{
98
98
return true;
+23
-13
drivers/gpu/drm/i915/display/intel_dpll.c
+23
-13
drivers/gpu/drm/i915/display/intel_dpll.c
···
1003
1003
const struct dpll *clock,
1004
1004
const struct dpll *reduced_clock)
1005
1005
{
1006
+
struct intel_display *display = to_intel_display(crtc_state);
1006
1007
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1007
1008
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1008
1009
u32 dpll;
···
1062
1061
if (crtc_state->sdvo_tv_clock)
1063
1062
dpll |= PLL_REF_INPUT_TVCLKINBC;
1064
1063
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
1065
-
intel_panel_use_ssc(dev_priv))
1064
+
intel_panel_use_ssc(display))
1066
1065
dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
1067
1066
else
1068
1067
dpll |= PLL_REF_INPUT_DREFCLK;
···
1096
1095
const struct dpll *clock,
1097
1096
const struct dpll *reduced_clock)
1098
1097
{
1098
+
struct intel_display *display = to_intel_display(crtc_state);
1099
1099
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1100
1100
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1101
1101
u32 dpll;
···
1133
1131
dpll |= DPLL_DVO_2X_MODE;
1134
1132
1135
1133
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
1136
-
intel_panel_use_ssc(dev_priv))
1134
+
intel_panel_use_ssc(display))
1137
1135
dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
1138
1136
else
1139
1137
dpll |= PLL_REF_INPUT_DREFCLK;
···
1239
1237
1240
1238
static int ilk_fb_cb_factor(const struct intel_crtc_state *crtc_state)
1241
1239
{
1240
+
struct intel_display *display = to_intel_display(crtc_state);
1242
1241
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1243
1242
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1244
1243
1245
1244
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
1246
-
((intel_panel_use_ssc(i915) && i915->display.vbt.lvds_ssc_freq == 100000) ||
1245
+
((intel_panel_use_ssc(display) && i915->display.vbt.lvds_ssc_freq == 100000) ||
1247
1246
(HAS_PCH_IBX(i915) && intel_is_dual_link_lvds(i915))))
1248
1247
return 25;
1249
1248
···
1274
1271
const struct dpll *clock,
1275
1272
const struct dpll *reduced_clock)
1276
1273
{
1274
+
struct intel_display *display = to_intel_display(crtc_state);
1277
1275
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1278
1276
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1279
1277
u32 dpll;
···
1336
1332
WARN_ON(reduced_clock->p2 != clock->p2);
1337
1333
1338
1334
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
1339
-
intel_panel_use_ssc(dev_priv))
1335
+
intel_panel_use_ssc(display))
1340
1336
dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
1341
1337
else
1342
1338
dpll |= PLL_REF_INPUT_DREFCLK;
···
1360
1356
static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
1361
1357
struct intel_crtc *crtc)
1362
1358
{
1359
+
struct intel_display *display = to_intel_display(state);
1363
1360
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1364
1361
struct intel_crtc_state *crtc_state =
1365
1362
intel_atomic_get_new_crtc_state(state, crtc);
···
1373
1368
return 0;
1374
1369
1375
1370
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1376
-
if (intel_panel_use_ssc(dev_priv)) {
1371
+
if (intel_panel_use_ssc(display)) {
1377
1372
drm_dbg_kms(&dev_priv->drm,
1378
1373
"using SSC reference clock of %d kHz\n",
1379
1374
dev_priv->display.vbt.lvds_ssc_freq);
···
1537
1532
static int g4x_crtc_compute_clock(struct intel_atomic_state *state,
1538
1533
struct intel_crtc *crtc)
1539
1534
{
1535
+
struct intel_display *display = to_intel_display(state);
1540
1536
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1541
1537
struct intel_crtc_state *crtc_state =
1542
1538
intel_atomic_get_new_crtc_state(state, crtc);
···
1545
1539
int refclk = 96000;
1546
1540
1547
1541
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1548
-
if (intel_panel_use_ssc(dev_priv)) {
1542
+
if (intel_panel_use_ssc(display)) {
1549
1543
refclk = dev_priv->display.vbt.lvds_ssc_freq;
1550
1544
drm_dbg_kms(&dev_priv->drm,
1551
1545
"using SSC reference clock of %d kHz\n",
···
1587
1581
static int pnv_crtc_compute_clock(struct intel_atomic_state *state,
1588
1582
struct intel_crtc *crtc)
1589
1583
{
1584
+
struct intel_display *display = to_intel_display(state);
1590
1585
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1591
1586
struct intel_crtc_state *crtc_state =
1592
1587
intel_atomic_get_new_crtc_state(state, crtc);
···
1595
1588
int refclk = 96000;
1596
1589
1597
1590
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1598
-
if (intel_panel_use_ssc(dev_priv)) {
1591
+
if (intel_panel_use_ssc(display)) {
1599
1592
refclk = dev_priv->display.vbt.lvds_ssc_freq;
1600
1593
drm_dbg_kms(&dev_priv->drm,
1601
1594
"using SSC reference clock of %d kHz\n",
···
1626
1619
static int i9xx_crtc_compute_clock(struct intel_atomic_state *state,
1627
1620
struct intel_crtc *crtc)
1628
1621
{
1622
+
struct intel_display *display = to_intel_display(state);
1629
1623
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1630
1624
struct intel_crtc_state *crtc_state =
1631
1625
intel_atomic_get_new_crtc_state(state, crtc);
···
1634
1626
int refclk = 96000;
1635
1627
1636
1628
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1637
-
if (intel_panel_use_ssc(dev_priv)) {
1629
+
if (intel_panel_use_ssc(display)) {
1638
1630
refclk = dev_priv->display.vbt.lvds_ssc_freq;
1639
1631
drm_dbg_kms(&dev_priv->drm,
1640
1632
"using SSC reference clock of %d kHz\n",
···
1667
1659
static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
1668
1660
struct intel_crtc *crtc)
1669
1661
{
1662
+
struct intel_display *display = to_intel_display(state);
1670
1663
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1671
1664
struct intel_crtc_state *crtc_state =
1672
1665
intel_atomic_get_new_crtc_state(state, crtc);
···
1675
1666
int refclk = 48000;
1676
1667
1677
1668
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1678
-
if (intel_panel_use_ssc(dev_priv)) {
1669
+
if (intel_panel_use_ssc(display)) {
1679
1670
refclk = dev_priv->display.vbt.lvds_ssc_freq;
1680
1671
drm_dbg_kms(&dev_priv->drm,
1681
1672
"using SSC reference clock of %d kHz\n",
···
2331
2322
static void assert_pll(struct drm_i915_private *dev_priv,
2332
2323
enum pipe pipe, bool state)
2333
2324
{
2325
+
struct intel_display *display = &dev_priv->display;
2334
2326
bool cur_state;
2335
2327
2336
-
cur_state = intel_de_read(dev_priv, DPLL(dev_priv, pipe)) & DPLL_VCO_ENABLE;
2337
-
I915_STATE_WARN(dev_priv, cur_state != state,
2338
-
"PLL state assertion failure (expected %s, current %s)\n",
2339
-
str_on_off(state), str_on_off(cur_state));
2328
+
cur_state = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE;
2329
+
INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
2330
+
"PLL state assertion failure (expected %s, current %s)\n",
2331
+
str_on_off(state), str_on_off(cur_state));
2340
2332
}
2341
2333
2342
2334
void assert_pll_enabled(struct drm_i915_private *i915, enum pipe pipe)
+51
-45
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+51
-45
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
···
173
173
struct intel_shared_dpll *pll,
174
174
bool state)
175
175
{
176
+
struct intel_display *display = &i915->display;
176
177
bool cur_state;
177
178
struct intel_dpll_hw_state hw_state;
178
179
179
-
if (drm_WARN(&i915->drm, !pll,
180
+
if (drm_WARN(display->drm, !pll,
180
181
"asserting DPLL %s with no DPLL\n", str_on_off(state)))
181
182
return;
182
183
183
184
cur_state = intel_dpll_get_hw_state(i915, pll, &hw_state);
184
-
I915_STATE_WARN(i915, cur_state != state,
185
-
"%s assertion failure (expected %s, current %s)\n",
186
-
pll->info->name, str_on_off(state),
187
-
str_on_off(cur_state));
185
+
INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
186
+
"%s assertion failure (expected %s, current %s)\n",
187
+
pll->info->name, str_on_off(state),
188
+
str_on_off(cur_state));
188
189
}
189
190
190
191
static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id)
···
546
545
547
546
static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *i915)
548
547
{
548
+
struct intel_display *display = &i915->display;
549
549
u32 val;
550
550
bool enabled;
551
551
552
-
val = intel_de_read(i915, PCH_DREF_CONTROL);
552
+
val = intel_de_read(display, PCH_DREF_CONTROL);
553
553
enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
554
554
DREF_SUPERSPREAD_SOURCE_MASK));
555
-
I915_STATE_WARN(i915, !enabled,
556
-
"PCH refclk assertion failure, should be active but is disabled\n");
555
+
INTEL_DISPLAY_STATE_WARN(display, !enabled,
556
+
"PCH refclk assertion failure, should be active but is disabled\n");
557
557
}
558
558
559
559
static void ibx_pch_dpll_enable(struct drm_i915_private *i915,
···
2037
2035
struct intel_shared_dpll *pll,
2038
2036
const struct intel_dpll_hw_state *dpll_hw_state)
2039
2037
{
2038
+
struct intel_display *display = &i915->display;
2040
2039
const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
2041
2040
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
2042
2041
enum dpio_phy phy;
2043
2042
enum dpio_channel ch;
2044
2043
u32 temp;
2045
2044
2046
-
bxt_port_to_phy_channel(i915, port, &phy, &ch);
2045
+
bxt_port_to_phy_channel(display, port, &phy, &ch);
2047
2046
2048
2047
/* Non-SSC reference */
2049
2048
intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL);
···
2160
2157
struct intel_shared_dpll *pll,
2161
2158
struct intel_dpll_hw_state *dpll_hw_state)
2162
2159
{
2160
+
struct intel_display *display = &i915->display;
2163
2161
struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
2164
2162
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
2165
2163
intel_wakeref_t wakeref;
···
2169
2165
u32 val;
2170
2166
bool ret;
2171
2167
2172
-
bxt_port_to_phy_channel(i915, port, &phy, &ch);
2168
+
bxt_port_to_phy_channel(display, port, &phy, &ch);
2173
2169
2174
2170
wakeref = intel_display_power_get_if_enabled(i915,
2175
2171
POWER_DOMAIN_DISPLAY_CORE);
···
4623
4619
struct intel_crtc *crtc,
4624
4620
const struct intel_crtc_state *new_crtc_state)
4625
4621
{
4622
+
struct intel_display *display = &i915->display;
4626
4623
struct intel_dpll_hw_state dpll_hw_state = {};
4627
4624
u8 pipe_mask;
4628
4625
bool active;
···
4631
4626
active = intel_dpll_get_hw_state(i915, pll, &dpll_hw_state);
4632
4627
4633
4628
if (!pll->info->always_on) {
4634
-
I915_STATE_WARN(i915, !pll->on && pll->active_mask,
4635
-
"%s: pll in active use but not on in sw tracking\n",
4636
-
pll->info->name);
4637
-
I915_STATE_WARN(i915, pll->on && !pll->active_mask,
4638
-
"%s: pll is on but not used by any active pipe\n",
4639
-
pll->info->name);
4640
-
I915_STATE_WARN(i915, pll->on != active,
4641
-
"%s: pll on state mismatch (expected %i, found %i)\n",
4642
-
pll->info->name, pll->on, active);
4629
+
INTEL_DISPLAY_STATE_WARN(display, !pll->on && pll->active_mask,
4630
+
"%s: pll in active use but not on in sw tracking\n",
4631
+
pll->info->name);
4632
+
INTEL_DISPLAY_STATE_WARN(display, pll->on && !pll->active_mask,
4633
+
"%s: pll is on but not used by any active pipe\n",
4634
+
pll->info->name);
4635
+
INTEL_DISPLAY_STATE_WARN(display, pll->on != active,
4636
+
"%s: pll on state mismatch (expected %i, found %i)\n",
4637
+
pll->info->name, pll->on, active);
4643
4638
}
4644
4639
4645
4640
if (!crtc) {
4646
-
I915_STATE_WARN(i915,
4647
-
pll->active_mask & ~pll->state.pipe_mask,
4648
-
"%s: more active pll users than references: 0x%x vs 0x%x\n",
4649
-
pll->info->name, pll->active_mask, pll->state.pipe_mask);
4641
+
INTEL_DISPLAY_STATE_WARN(display,
4642
+
pll->active_mask & ~pll->state.pipe_mask,
4643
+
"%s: more active pll users than references: 0x%x vs 0x%x\n",
4644
+
pll->info->name, pll->active_mask, pll->state.pipe_mask);
4650
4645
4651
4646
return;
4652
4647
}
···
4654
4649
pipe_mask = BIT(crtc->pipe);
4655
4650
4656
4651
if (new_crtc_state->hw.active)
4657
-
I915_STATE_WARN(i915, !(pll->active_mask & pipe_mask),
4658
-
"%s: pll active mismatch (expected pipe %c in active mask 0x%x)\n",
4659
-
pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
4652
+
INTEL_DISPLAY_STATE_WARN(display, !(pll->active_mask & pipe_mask),
4653
+
"%s: pll active mismatch (expected pipe %c in active mask 0x%x)\n",
4654
+
pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
4660
4655
else
4661
-
I915_STATE_WARN(i915, pll->active_mask & pipe_mask,
4662
-
"%s: pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n",
4663
-
pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
4656
+
INTEL_DISPLAY_STATE_WARN(display, pll->active_mask & pipe_mask,
4657
+
"%s: pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n",
4658
+
pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
4664
4659
4665
-
I915_STATE_WARN(i915, !(pll->state.pipe_mask & pipe_mask),
4666
-
"%s: pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n",
4667
-
pll->info->name, pipe_mask, pll->state.pipe_mask);
4660
+
INTEL_DISPLAY_STATE_WARN(display, !(pll->state.pipe_mask & pipe_mask),
4661
+
"%s: pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n",
4662
+
pll->info->name, pipe_mask, pll->state.pipe_mask);
4668
4663
4669
-
I915_STATE_WARN(i915,
4670
-
pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state,
4671
-
sizeof(dpll_hw_state)),
4672
-
"%s: pll hw state mismatch\n",
4673
-
pll->info->name);
4664
+
INTEL_DISPLAY_STATE_WARN(display,
4665
+
pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state,
4666
+
sizeof(dpll_hw_state)),
4667
+
"%s: pll hw state mismatch\n",
4668
+
pll->info->name);
4674
4669
}
4675
4670
4676
4671
static bool has_alt_port_dpll(const struct intel_shared_dpll *old_pll,
···
4683
4678
void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
4684
4679
struct intel_crtc *crtc)
4685
4680
{
4681
+
struct intel_display *display = to_intel_display(state);
4686
4682
struct drm_i915_private *i915 = to_i915(state->base.dev);
4687
4683
const struct intel_crtc_state *old_crtc_state =
4688
4684
intel_atomic_get_old_crtc_state(state, crtc);
···
4699
4693
u8 pipe_mask = BIT(crtc->pipe);
4700
4694
struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
4701
4695
4702
-
I915_STATE_WARN(i915, pll->active_mask & pipe_mask,
4703
-
"%s: pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
4704
-
pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
4696
+
INTEL_DISPLAY_STATE_WARN(display, pll->active_mask & pipe_mask,
4697
+
"%s: pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
4698
+
pll->info->name, pipe_name(crtc->pipe), pll->active_mask);
4705
4699
4706
4700
/* TC ports have both MG/TC and TBT PLL referenced simultaneously */
4707
-
I915_STATE_WARN(i915, !has_alt_port_dpll(old_crtc_state->shared_dpll,
4708
-
new_crtc_state->shared_dpll) &&
4709
-
pll->state.pipe_mask & pipe_mask,
4710
-
"%s: pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n",
4711
-
pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask);
4701
+
INTEL_DISPLAY_STATE_WARN(display, !has_alt_port_dpll(old_crtc_state->shared_dpll,
4702
+
new_crtc_state->shared_dpll) &&
4703
+
pll->state.pipe_mask & pipe_mask,
4704
+
"%s: pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n",
4705
+
pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask);
4712
4706
}
4713
4707
}
4714
4708
+3
-2
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+3
-2
drivers/gpu/drm/i915/display/intel_dsi_vbt.c
···
323
323
static void icl_native_gpio_set_value(struct drm_i915_private *dev_priv,
324
324
int gpio, bool value)
325
325
{
326
+
struct intel_display *display = &dev_priv->display;
326
327
int index;
327
328
328
329
if (drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 11 && gpio >= MIPI_RESET_2))
···
368
367
case MIPI_AVEE_EN_2:
369
368
index = gpio == MIPI_AVEE_EN_1 ? 1 : 2;
370
369
371
-
intel_de_rmw(dev_priv, GPIO(dev_priv, index),
370
+
intel_de_rmw(display, GPIO(display, index),
372
371
GPIO_CLOCK_VAL_OUT,
373
372
GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT |
374
373
GPIO_CLOCK_VAL_MASK | (value ? GPIO_CLOCK_VAL_OUT : 0));
···
377
376
case MIPI_VIO_EN_2:
378
377
index = gpio == MIPI_VIO_EN_1 ? 1 : 2;
379
378
380
-
intel_de_rmw(dev_priv, GPIO(dev_priv, index),
379
+
intel_de_rmw(display, GPIO(display, index),
381
380
GPIO_DATA_VAL_OUT,
382
381
GPIO_DATA_DIR_MASK | GPIO_DATA_DIR_OUT |
383
382
GPIO_DATA_VAL_MASK | (value ? GPIO_DATA_VAL_OUT : 0));
+5
-3
drivers/gpu/drm/i915/display/intel_dvo.c
+5
-3
drivers/gpu/drm/i915/display/intel_dvo.c
···
417
417
struct intel_dvo *intel_dvo,
418
418
const struct intel_dvo_device *dvo)
419
419
{
420
+
struct intel_display *display = &dev_priv->display;
420
421
struct i2c_adapter *i2c;
421
422
u32 dpll[I915_MAX_PIPES];
422
423
enum pipe pipe;
···
429
428
* special cases, but otherwise default to what's defined
430
429
* in the spec.
431
430
*/
432
-
if (intel_gmbus_is_valid_pin(dev_priv, dvo->gpio))
431
+
if (intel_gmbus_is_valid_pin(display, dvo->gpio))
433
432
gpio = dvo->gpio;
434
433
else if (dvo->type == INTEL_DVO_CHIP_LVDS)
435
434
gpio = GMBUS_PIN_SSC;
···
441
440
* It appears that everything is on GPIOE except for panels
442
441
* on i830 laptops, which are on GPIOB (DVOA).
443
442
*/
444
-
i2c = intel_gmbus_get_adapter(dev_priv, gpio);
443
+
i2c = intel_gmbus_get_adapter(display, gpio);
445
444
446
445
intel_dvo->dev = *dvo;
447
446
···
490
489
491
490
void intel_dvo_init(struct drm_i915_private *i915)
492
491
{
492
+
struct intel_display *display = &i915->display;
493
493
struct intel_connector *connector;
494
494
struct intel_encoder *encoder;
495
495
struct intel_dvo *intel_dvo;
···
551
549
drm_connector_init_with_ddc(&i915->drm, &connector->base,
552
550
&intel_dvo_connector_funcs,
553
551
intel_dvo_connector_type(&intel_dvo->dev),
554
-
intel_gmbus_get_adapter(i915, GMBUS_PIN_DPC));
552
+
intel_gmbus_get_adapter(display, GMBUS_PIN_DPC));
555
553
556
554
drm_connector_helper_add(&connector->base,
557
555
&intel_dvo_connector_helper_funcs);
+1
-1
drivers/gpu/drm/i915/display/intel_fb.c
+1
-1
drivers/gpu/drm/i915/display/intel_fb.c
+1
-1
drivers/gpu/drm/i915/display/intel_fbc.c
+1
-1
drivers/gpu/drm/i915/display/intel_fbc.c
···
1347
1347
1348
1348
/* Wa_14016291713 */
1349
1349
if ((IS_DISPLAY_VER(display, 12, 13) ||
1350
-
IS_DISPLAY_VER_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) &&
1350
+
IS_DISPLAY_VERx100_STEP(i915, 1400, STEP_A0, STEP_C0)) &&
1351
1351
crtc_state->has_psr && !crtc_state->has_panel_replay) {
1352
1352
plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
1353
1353
return 0;
+23
-19
drivers/gpu/drm/i915/display/intel_fdi.c
+23
-19
drivers/gpu/drm/i915/display/intel_fdi.c
···
26
26
static void assert_fdi_tx(struct drm_i915_private *dev_priv,
27
27
enum pipe pipe, bool state)
28
28
{
29
+
struct intel_display *display = &dev_priv->display;
29
30
bool cur_state;
30
31
31
-
if (HAS_DDI(dev_priv)) {
32
+
if (HAS_DDI(display)) {
32
33
/*
33
34
* DDI does not have a specific FDI_TX register.
34
35
*
···
37
36
* so pipe->transcoder cast is fine here.
38
37
*/
39
38
enum transcoder cpu_transcoder = (enum transcoder)pipe;
40
-
cur_state = intel_de_read(dev_priv,
41
-
TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE;
39
+
cur_state = intel_de_read(display,
40
+
TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE;
42
41
} else {
43
-
cur_state = intel_de_read(dev_priv, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE;
42
+
cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE;
44
43
}
45
-
I915_STATE_WARN(dev_priv, cur_state != state,
46
-
"FDI TX state assertion failure (expected %s, current %s)\n",
47
-
str_on_off(state), str_on_off(cur_state));
44
+
INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
45
+
"FDI TX state assertion failure (expected %s, current %s)\n",
46
+
str_on_off(state), str_on_off(cur_state));
48
47
}
49
48
50
49
void assert_fdi_tx_enabled(struct drm_i915_private *i915, enum pipe pipe)
···
60
59
static void assert_fdi_rx(struct drm_i915_private *dev_priv,
61
60
enum pipe pipe, bool state)
62
61
{
62
+
struct intel_display *display = &dev_priv->display;
63
63
bool cur_state;
64
64
65
-
cur_state = intel_de_read(dev_priv, FDI_RX_CTL(pipe)) & FDI_RX_ENABLE;
66
-
I915_STATE_WARN(dev_priv, cur_state != state,
67
-
"FDI RX state assertion failure (expected %s, current %s)\n",
68
-
str_on_off(state), str_on_off(cur_state));
65
+
cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_ENABLE;
66
+
INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
67
+
"FDI RX state assertion failure (expected %s, current %s)\n",
68
+
str_on_off(state), str_on_off(cur_state));
69
69
}
70
70
71
71
void assert_fdi_rx_enabled(struct drm_i915_private *i915, enum pipe pipe)
···
82
80
void assert_fdi_tx_pll_enabled(struct drm_i915_private *i915,
83
81
enum pipe pipe)
84
82
{
83
+
struct intel_display *display = &i915->display;
85
84
bool cur_state;
86
85
87
86
/* ILK FDI PLL is always enabled */
···
90
87
return;
91
88
92
89
/* On Haswell, DDI ports are responsible for the FDI PLL setup */
93
-
if (HAS_DDI(i915))
90
+
if (HAS_DDI(display))
94
91
return;
95
92
96
-
cur_state = intel_de_read(i915, FDI_TX_CTL(pipe)) & FDI_TX_PLL_ENABLE;
97
-
I915_STATE_WARN(i915, !cur_state,
98
-
"FDI TX PLL assertion failure, should be active but is disabled\n");
93
+
cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_PLL_ENABLE;
94
+
INTEL_DISPLAY_STATE_WARN(display, !cur_state,
95
+
"FDI TX PLL assertion failure, should be active but is disabled\n");
99
96
}
100
97
101
98
static void assert_fdi_rx_pll(struct drm_i915_private *i915,
102
99
enum pipe pipe, bool state)
103
100
{
101
+
struct intel_display *display = &i915->display;
104
102
bool cur_state;
105
103
106
-
cur_state = intel_de_read(i915, FDI_RX_CTL(pipe)) & FDI_RX_PLL_ENABLE;
107
-
I915_STATE_WARN(i915, cur_state != state,
108
-
"FDI RX PLL assertion failure (expected %s, current %s)\n",
109
-
str_on_off(state), str_on_off(cur_state));
104
+
cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_PLL_ENABLE;
105
+
INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
106
+
"FDI RX PLL assertion failure (expected %s, current %s)\n",
107
+
str_on_off(state), str_on_off(cur_state));
110
108
}
111
109
112
110
void assert_fdi_rx_pll_enabled(struct drm_i915_private *i915, enum pipe pipe)
+5
-53
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+5
-53
drivers/gpu/drm/i915/display/intel_fifo_underrun.c
···
192
192
}
193
193
}
194
194
195
-
static u32
196
-
icl_pipe_status_underrun_mask(struct drm_i915_private *dev_priv)
197
-
{
198
-
u32 mask = PIPE_STATUS_UNDERRUN;
199
-
200
-
if (DISPLAY_VER(dev_priv) >= 13)
201
-
mask |= PIPE_STATUS_SOFT_UNDERRUN_XELPD |
202
-
PIPE_STATUS_HARD_UNDERRUN_XELPD |
203
-
PIPE_STATUS_PORT_UNDERRUN_XELPD;
204
-
205
-
return mask;
206
-
}
207
-
208
195
static void bdw_set_fifo_underrun_reporting(struct drm_device *dev,
209
196
enum pipe pipe, bool enable)
210
197
{
211
198
struct drm_i915_private *dev_priv = to_i915(dev);
212
-
u32 mask = gen8_de_pipe_underrun_mask(dev_priv);
213
199
214
-
if (enable) {
215
-
if (DISPLAY_VER(dev_priv) >= 11)
216
-
intel_de_write(dev_priv,
217
-
ICL_PIPESTATUS(dev_priv, pipe),
218
-
icl_pipe_status_underrun_mask(dev_priv));
219
-
220
-
bdw_enable_pipe_irq(dev_priv, pipe, mask);
221
-
} else {
222
-
bdw_disable_pipe_irq(dev_priv, pipe, mask);
223
-
}
200
+
if (enable)
201
+
bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);
202
+
else
203
+
bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);
224
204
}
225
205
226
206
static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
···
384
404
{
385
405
struct intel_display *display = &dev_priv->display;
386
406
struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
387
-
u32 underruns = 0;
388
407
389
408
/* We may be called too early in init, thanks BIOS! */
390
409
if (crtc == NULL)
···
394
415
crtc->cpu_fifo_underrun_disabled)
395
416
return;
396
417
397
-
/*
398
-
* Starting with display version 11, the PIPE_STAT register records
399
-
* whether an underrun has happened, and on XELPD+, it will also record
400
-
* whether the underrun was soft/hard and whether it was triggered by
401
-
* the downstream port logic. We should clear these bits (which use
402
-
* write-1-to-clear logic) too.
403
-
*
404
-
* Note that although the IIR gives us the same underrun and soft/hard
405
-
* information, PIPE_STAT is the only place we can find out whether
406
-
* the underrun was caused by the downstream port.
407
-
*/
408
-
if (DISPLAY_VER(dev_priv) >= 11) {
409
-
underruns = intel_de_read(dev_priv,
410
-
ICL_PIPESTATUS(dev_priv, pipe)) &
411
-
icl_pipe_status_underrun_mask(dev_priv);
412
-
intel_de_write(dev_priv, ICL_PIPESTATUS(dev_priv, pipe),
413
-
underruns);
414
-
}
415
-
416
418
if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) {
417
419
trace_intel_cpu_fifo_underrun(display, pipe);
418
420
419
-
if (DISPLAY_VER(dev_priv) >= 11)
420
-
drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun: %s%s%s%s\n",
421
-
pipe_name(pipe),
422
-
underruns & PIPE_STATUS_SOFT_UNDERRUN_XELPD ? "soft," : "",
423
-
underruns & PIPE_STATUS_HARD_UNDERRUN_XELPD ? "hard," : "",
424
-
underruns & PIPE_STATUS_PORT_UNDERRUN_XELPD ? "port," : "",
425
-
underruns & PIPE_STATUS_UNDERRUN ? "transcoder," : "");
426
-
else
427
-
drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));
421
+
drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));
428
422
}
429
423
430
424
intel_fbc_handle_fifo_underrun_irq(&dev_priv->display);
+151
-139
drivers/gpu/drm/i915/display/intel_gmbus.c
+151
-139
drivers/gpu/drm/i915/display/intel_gmbus.c
···
48
48
u32 reg0;
49
49
i915_reg_t gpio_reg;
50
50
struct i2c_algo_bit_data bit_algo;
51
-
struct drm_i915_private *i915;
51
+
struct intel_display *display;
52
52
};
53
53
54
54
enum gmbus_gpio {
···
149
149
[GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
150
150
};
151
151
152
-
static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
152
+
static const struct gmbus_pin *get_gmbus_pin(struct intel_display *display,
153
153
unsigned int pin)
154
154
{
155
+
struct drm_i915_private *i915 = to_i915(display->drm);
155
156
const struct gmbus_pin *pins;
156
157
size_t size;
157
158
···
174
173
} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
175
174
pins = gmbus_pins_bxt;
176
175
size = ARRAY_SIZE(gmbus_pins_bxt);
177
-
} else if (DISPLAY_VER(i915) == 9) {
176
+
} else if (DISPLAY_VER(display) == 9) {
178
177
pins = gmbus_pins_skl;
179
178
size = ARRAY_SIZE(gmbus_pins_skl);
180
179
} else if (IS_BROADWELL(i915)) {
···
191
190
return &pins[pin];
192
191
}
193
192
194
-
bool intel_gmbus_is_valid_pin(struct drm_i915_private *i915, unsigned int pin)
193
+
bool intel_gmbus_is_valid_pin(struct intel_display *display, unsigned int pin)
195
194
{
196
-
return get_gmbus_pin(i915, pin);
195
+
return get_gmbus_pin(display, pin);
197
196
}
198
197
199
198
/* Intel GPIO access functions */
···
207
206
}
208
207
209
208
void
210
-
intel_gmbus_reset(struct drm_i915_private *i915)
209
+
intel_gmbus_reset(struct intel_display *display)
211
210
{
212
-
intel_de_write(i915, GMBUS0(i915), 0);
213
-
intel_de_write(i915, GMBUS4(i915), 0);
211
+
intel_de_write(display, GMBUS0(display), 0);
212
+
intel_de_write(display, GMBUS4(display), 0);
214
213
}
215
214
216
-
static void pnv_gmbus_clock_gating(struct drm_i915_private *i915,
215
+
static void pnv_gmbus_clock_gating(struct intel_display *display,
217
216
bool enable)
218
217
{
219
218
/* When using bit bashing for I2C, this bit needs to be set to 1 */
220
-
intel_de_rmw(i915, DSPCLK_GATE_D(i915), PNV_GMBUSUNIT_CLOCK_GATE_DISABLE,
219
+
intel_de_rmw(display, DSPCLK_GATE_D(display),
220
+
PNV_GMBUSUNIT_CLOCK_GATE_DISABLE,
221
221
!enable ? PNV_GMBUSUNIT_CLOCK_GATE_DISABLE : 0);
222
222
}
223
223
224
-
static void pch_gmbus_clock_gating(struct drm_i915_private *i915,
224
+
static void pch_gmbus_clock_gating(struct intel_display *display,
225
225
bool enable)
226
226
{
227
-
intel_de_rmw(i915, SOUTH_DSPCLK_GATE_D, PCH_GMBUSUNIT_CLOCK_GATE_DISABLE,
227
+
intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
228
+
PCH_GMBUSUNIT_CLOCK_GATE_DISABLE,
228
229
!enable ? PCH_GMBUSUNIT_CLOCK_GATE_DISABLE : 0);
229
230
}
230
231
231
-
static void bxt_gmbus_clock_gating(struct drm_i915_private *i915,
232
+
static void bxt_gmbus_clock_gating(struct intel_display *display,
232
233
bool enable)
233
234
{
234
-
intel_de_rmw(i915, GEN9_CLKGATE_DIS_4, BXT_GMBUS_GATING_DIS,
235
+
intel_de_rmw(display, GEN9_CLKGATE_DIS_4, BXT_GMBUS_GATING_DIS,
235
236
!enable ? BXT_GMBUS_GATING_DIS : 0);
236
237
}
237
238
238
239
static u32 get_reserved(struct intel_gmbus *bus)
239
240
{
240
-
struct drm_i915_private *i915 = bus->i915;
241
+
struct intel_display *display = bus->display;
242
+
struct drm_i915_private *i915 = to_i915(display->drm);
241
243
u32 reserved = 0;
242
244
243
245
/* On most chips, these bits must be preserved in software. */
244
246
if (!IS_I830(i915) && !IS_I845G(i915))
245
-
reserved = intel_de_read_notrace(i915, bus->gpio_reg) &
247
+
reserved = intel_de_read_notrace(display, bus->gpio_reg) &
246
248
(GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE);
247
249
248
250
return reserved;
···
254
250
static int get_clock(void *data)
255
251
{
256
252
struct intel_gmbus *bus = data;
257
-
struct drm_i915_private *i915 = bus->i915;
253
+
struct intel_display *display = bus->display;
258
254
u32 reserved = get_reserved(bus);
259
255
260
-
intel_de_write_notrace(i915, bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
261
-
intel_de_write_notrace(i915, bus->gpio_reg, reserved);
256
+
intel_de_write_notrace(display, bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
257
+
intel_de_write_notrace(display, bus->gpio_reg, reserved);
262
258
263
-
return (intel_de_read_notrace(i915, bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
259
+
return (intel_de_read_notrace(display, bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
264
260
}
265
261
266
262
static int get_data(void *data)
267
263
{
268
264
struct intel_gmbus *bus = data;
269
-
struct drm_i915_private *i915 = bus->i915;
265
+
struct intel_display *display = bus->display;
270
266
u32 reserved = get_reserved(bus);
271
267
272
-
intel_de_write_notrace(i915, bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
273
-
intel_de_write_notrace(i915, bus->gpio_reg, reserved);
268
+
intel_de_write_notrace(display, bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
269
+
intel_de_write_notrace(display, bus->gpio_reg, reserved);
274
270
275
-
return (intel_de_read_notrace(i915, bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
271
+
return (intel_de_read_notrace(display, bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
276
272
}
277
273
278
274
static void set_clock(void *data, int state_high)
279
275
{
280
276
struct intel_gmbus *bus = data;
281
-
struct drm_i915_private *i915 = bus->i915;
277
+
struct intel_display *display = bus->display;
282
278
u32 reserved = get_reserved(bus);
283
279
u32 clock_bits;
284
280
···
288
284
clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
289
285
GPIO_CLOCK_VAL_MASK;
290
286
291
-
intel_de_write_notrace(i915, bus->gpio_reg, reserved | clock_bits);
292
-
intel_de_posting_read(i915, bus->gpio_reg);
287
+
intel_de_write_notrace(display, bus->gpio_reg, reserved | clock_bits);
288
+
intel_de_posting_read(display, bus->gpio_reg);
293
289
}
294
290
295
291
static void set_data(void *data, int state_high)
296
292
{
297
293
struct intel_gmbus *bus = data;
298
-
struct drm_i915_private *i915 = bus->i915;
294
+
struct intel_display *display = bus->display;
299
295
u32 reserved = get_reserved(bus);
300
296
u32 data_bits;
301
297
···
305
301
data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
306
302
GPIO_DATA_VAL_MASK;
307
303
308
-
intel_de_write_notrace(i915, bus->gpio_reg, reserved | data_bits);
309
-
intel_de_posting_read(i915, bus->gpio_reg);
304
+
intel_de_write_notrace(display, bus->gpio_reg, reserved | data_bits);
305
+
intel_de_posting_read(display, bus->gpio_reg);
310
306
}
311
307
312
308
static int
313
309
intel_gpio_pre_xfer(struct i2c_adapter *adapter)
314
310
{
315
311
struct intel_gmbus *bus = to_intel_gmbus(adapter);
316
-
struct drm_i915_private *i915 = bus->i915;
312
+
struct intel_display *display = bus->display;
313
+
struct drm_i915_private *i915 = to_i915(display->drm);
317
314
318
-
intel_gmbus_reset(i915);
315
+
intel_gmbus_reset(display);
319
316
320
317
if (IS_PINEVIEW(i915))
321
-
pnv_gmbus_clock_gating(i915, false);
318
+
pnv_gmbus_clock_gating(display, false);
322
319
323
320
set_data(bus, 1);
324
321
set_clock(bus, 1);
···
331
326
intel_gpio_post_xfer(struct i2c_adapter *adapter)
332
327
{
333
328
struct intel_gmbus *bus = to_intel_gmbus(adapter);
334
-
struct drm_i915_private *i915 = bus->i915;
329
+
struct intel_display *display = bus->display;
330
+
struct drm_i915_private *i915 = to_i915(display->drm);
335
331
336
332
set_data(bus, 1);
337
333
set_clock(bus, 1);
338
334
339
335
if (IS_PINEVIEW(i915))
340
-
pnv_gmbus_clock_gating(i915, true);
336
+
pnv_gmbus_clock_gating(display, true);
341
337
}
342
338
343
339
static void
···
361
355
algo->data = bus;
362
356
}
363
357
364
-
static bool has_gmbus_irq(struct drm_i915_private *i915)
358
+
static bool has_gmbus_irq(struct intel_display *display)
365
359
{
360
+
struct drm_i915_private *i915 = to_i915(display->drm);
366
361
/*
367
362
* encoder->shutdown() may want to use GMBUS
368
363
* after irqs have already been disabled.
369
364
*/
370
-
return HAS_GMBUS_IRQ(i915) && intel_irqs_enabled(i915);
365
+
return HAS_GMBUS_IRQ(display) && intel_irqs_enabled(i915);
371
366
}
372
367
373
-
static int gmbus_wait(struct drm_i915_private *i915, u32 status, u32 irq_en)
368
+
static int gmbus_wait(struct intel_display *display, u32 status, u32 irq_en)
374
369
{
375
370
DEFINE_WAIT(wait);
376
371
u32 gmbus2;
···
381
374
* we also need to check for NAKs besides the hw ready/idle signal, we
382
375
* need to wake up periodically and check that ourselves.
383
376
*/
384
-
if (!has_gmbus_irq(i915))
377
+
if (!has_gmbus_irq(display))
385
378
irq_en = 0;
386
379
387
-
add_wait_queue(&i915->display.gmbus.wait_queue, &wait);
388
-
intel_de_write_fw(i915, GMBUS4(i915), irq_en);
380
+
add_wait_queue(&display->gmbus.wait_queue, &wait);
381
+
intel_de_write_fw(display, GMBUS4(display), irq_en);
389
382
390
383
status |= GMBUS_SATOER;
391
-
ret = wait_for_us((gmbus2 = intel_de_read_fw(i915, GMBUS2(i915))) & status,
384
+
ret = wait_for_us((gmbus2 = intel_de_read_fw(display, GMBUS2(display))) & status,
392
385
2);
393
386
if (ret)
394
-
ret = wait_for((gmbus2 = intel_de_read_fw(i915, GMBUS2(i915))) & status,
387
+
ret = wait_for((gmbus2 = intel_de_read_fw(display, GMBUS2(display))) & status,
395
388
50);
396
389
397
-
intel_de_write_fw(i915, GMBUS4(i915), 0);
398
-
remove_wait_queue(&i915->display.gmbus.wait_queue, &wait);
390
+
intel_de_write_fw(display, GMBUS4(display), 0);
391
+
remove_wait_queue(&display->gmbus.wait_queue, &wait);
399
392
400
393
if (gmbus2 & GMBUS_SATOER)
401
394
return -ENXIO;
···
404
397
}
405
398
406
399
static int
407
-
gmbus_wait_idle(struct drm_i915_private *i915)
400
+
gmbus_wait_idle(struct intel_display *display)
408
401
{
409
402
DEFINE_WAIT(wait);
410
403
u32 irq_enable;
···
412
405
413
406
/* Important: The hw handles only the first bit, so set only one! */
414
407
irq_enable = 0;
415
-
if (has_gmbus_irq(i915))
408
+
if (has_gmbus_irq(display))
416
409
irq_enable = GMBUS_IDLE_EN;
417
410
418
-
add_wait_queue(&i915->display.gmbus.wait_queue, &wait);
419
-
intel_de_write_fw(i915, GMBUS4(i915), irq_enable);
411
+
add_wait_queue(&display->gmbus.wait_queue, &wait);
412
+
intel_de_write_fw(display, GMBUS4(display), irq_enable);
420
413
421
-
ret = intel_de_wait_fw(i915, GMBUS2(i915), GMBUS_ACTIVE, 0, 10);
414
+
ret = intel_de_wait_fw(display, GMBUS2(display), GMBUS_ACTIVE, 0, 10);
422
415
423
-
intel_de_write_fw(i915, GMBUS4(i915), 0);
424
-
remove_wait_queue(&i915->display.gmbus.wait_queue, &wait);
416
+
intel_de_write_fw(display, GMBUS4(display), 0);
417
+
remove_wait_queue(&display->gmbus.wait_queue, &wait);
425
418
426
419
return ret;
427
420
}
428
421
429
-
static unsigned int gmbus_max_xfer_size(struct drm_i915_private *i915)
422
+
static unsigned int gmbus_max_xfer_size(struct intel_display *display)
430
423
{
431
-
return DISPLAY_VER(i915) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
424
+
return DISPLAY_VER(display) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
432
425
GMBUS_BYTE_COUNT_MAX;
433
426
}
434
427
435
428
static int
436
-
gmbus_xfer_read_chunk(struct drm_i915_private *i915,
429
+
gmbus_xfer_read_chunk(struct intel_display *display,
437
430
unsigned short addr, u8 *buf, unsigned int len,
438
431
u32 gmbus0_reg, u32 gmbus1_index)
439
432
{
440
433
unsigned int size = len;
441
-
bool burst_read = len > gmbus_max_xfer_size(i915);
434
+
bool burst_read = len > gmbus_max_xfer_size(display);
442
435
bool extra_byte_added = false;
443
436
444
437
if (burst_read) {
···
451
444
len++;
452
445
}
453
446
size = len % 256 + 256;
454
-
intel_de_write_fw(i915, GMBUS0(i915),
447
+
intel_de_write_fw(display, GMBUS0(display),
455
448
gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
456
449
}
457
450
458
-
intel_de_write_fw(i915, GMBUS1(i915),
451
+
intel_de_write_fw(display, GMBUS1(display),
459
452
gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY);
460
453
while (len) {
461
454
int ret;
462
455
u32 val, loop = 0;
463
456
464
-
ret = gmbus_wait(i915, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
457
+
ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
465
458
if (ret)
466
459
return ret;
467
460
468
-
val = intel_de_read_fw(i915, GMBUS3(i915));
461
+
val = intel_de_read_fw(display, GMBUS3(display));
469
462
do {
470
463
if (extra_byte_added && len == 1)
471
464
break;
···
476
469
477
470
if (burst_read && len == size - 4)
478
471
/* Reset the override bit */
479
-
intel_de_write_fw(i915, GMBUS0(i915), gmbus0_reg);
472
+
intel_de_write_fw(display, GMBUS0(display), gmbus0_reg);
480
473
}
481
474
482
475
return 0;
···
493
486
#define INTEL_GMBUS_BURST_READ_MAX_LEN 767U
494
487
495
488
static int
496
-
gmbus_xfer_read(struct drm_i915_private *i915, struct i2c_msg *msg,
489
+
gmbus_xfer_read(struct intel_display *display, struct i2c_msg *msg,
497
490
u32 gmbus0_reg, u32 gmbus1_index)
498
491
{
492
+
struct drm_i915_private *i915 = to_i915(display->drm);
499
493
u8 *buf = msg->buf;
500
494
unsigned int rx_size = msg->len;
501
495
unsigned int len;
···
506
498
if (HAS_GMBUS_BURST_READ(i915))
507
499
len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN);
508
500
else
509
-
len = min(rx_size, gmbus_max_xfer_size(i915));
501
+
len = min(rx_size, gmbus_max_xfer_size(display));
510
502
511
-
ret = gmbus_xfer_read_chunk(i915, msg->addr, buf, len,
503
+
ret = gmbus_xfer_read_chunk(display, msg->addr, buf, len,
512
504
gmbus0_reg, gmbus1_index);
513
505
if (ret)
514
506
return ret;
···
521
513
}
522
514
523
515
static int
524
-
gmbus_xfer_write_chunk(struct drm_i915_private *i915,
516
+
gmbus_xfer_write_chunk(struct intel_display *display,
525
517
unsigned short addr, u8 *buf, unsigned int len,
526
518
u32 gmbus1_index)
527
519
{
···
534
526
len -= 1;
535
527
}
536
528
537
-
intel_de_write_fw(i915, GMBUS3(i915), val);
538
-
intel_de_write_fw(i915, GMBUS1(i915),
529
+
intel_de_write_fw(display, GMBUS3(display), val);
530
+
intel_de_write_fw(display, GMBUS1(display),
539
531
gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
540
532
while (len) {
541
533
int ret;
···
545
537
val |= *buf++ << (8 * loop);
546
538
} while (--len && ++loop < 4);
547
539
548
-
intel_de_write_fw(i915, GMBUS3(i915), val);
540
+
intel_de_write_fw(display, GMBUS3(display), val);
549
541
550
-
ret = gmbus_wait(i915, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
542
+
ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
551
543
if (ret)
552
544
return ret;
553
545
}
···
556
548
}
557
549
558
550
static int
559
-
gmbus_xfer_write(struct drm_i915_private *i915, struct i2c_msg *msg,
551
+
gmbus_xfer_write(struct intel_display *display, struct i2c_msg *msg,
560
552
u32 gmbus1_index)
561
553
{
562
554
u8 *buf = msg->buf;
···
565
557
int ret;
566
558
567
559
do {
568
-
len = min(tx_size, gmbus_max_xfer_size(i915));
560
+
len = min(tx_size, gmbus_max_xfer_size(display));
569
561
570
-
ret = gmbus_xfer_write_chunk(i915, msg->addr, buf, len,
562
+
ret = gmbus_xfer_write_chunk(display, msg->addr, buf, len,
571
563
gmbus1_index);
572
564
if (ret)
573
565
return ret;
···
594
586
}
595
587
596
588
static int
597
-
gmbus_index_xfer(struct drm_i915_private *i915, struct i2c_msg *msgs,
589
+
gmbus_index_xfer(struct intel_display *display, struct i2c_msg *msgs,
598
590
u32 gmbus0_reg)
599
591
{
600
592
u32 gmbus1_index = 0;
···
610
602
611
603
/* GMBUS5 holds 16-bit index */
612
604
if (gmbus5)
613
-
intel_de_write_fw(i915, GMBUS5(i915), gmbus5);
605
+
intel_de_write_fw(display, GMBUS5(display), gmbus5);
614
606
615
607
if (msgs[1].flags & I2C_M_RD)
616
-
ret = gmbus_xfer_read(i915, &msgs[1], gmbus0_reg,
608
+
ret = gmbus_xfer_read(display, &msgs[1], gmbus0_reg,
617
609
gmbus1_index);
618
610
else
619
-
ret = gmbus_xfer_write(i915, &msgs[1], gmbus1_index);
611
+
ret = gmbus_xfer_write(display, &msgs[1], gmbus1_index);
620
612
621
613
/* Clear GMBUS5 after each index transfer */
622
614
if (gmbus5)
623
-
intel_de_write_fw(i915, GMBUS5(i915), 0);
615
+
intel_de_write_fw(display, GMBUS5(display), 0);
624
616
625
617
return ret;
626
618
}
···
630
622
u32 gmbus0_source)
631
623
{
632
624
struct intel_gmbus *bus = to_intel_gmbus(adapter);
633
-
struct drm_i915_private *i915 = bus->i915;
625
+
struct intel_display *display = bus->display;
626
+
struct drm_i915_private *i915 = to_i915(display->drm);
634
627
int i = 0, inc, try = 0;
635
628
int ret = 0;
636
629
637
630
/* Display WA #0868: skl,bxt,kbl,cfl,glk */
638
631
if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
639
-
bxt_gmbus_clock_gating(i915, false);
632
+
bxt_gmbus_clock_gating(display, false);
640
633
else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915))
641
-
pch_gmbus_clock_gating(i915, false);
634
+
pch_gmbus_clock_gating(display, false);
642
635
643
636
retry:
644
-
intel_de_write_fw(i915, GMBUS0(i915), gmbus0_source | bus->reg0);
637
+
intel_de_write_fw(display, GMBUS0(display), gmbus0_source | bus->reg0);
645
638
646
639
for (; i < num; i += inc) {
647
640
inc = 1;
648
641
if (gmbus_is_index_xfer(msgs, i, num)) {
649
-
ret = gmbus_index_xfer(i915, &msgs[i],
642
+
ret = gmbus_index_xfer(display, &msgs[i],
650
643
gmbus0_source | bus->reg0);
651
644
inc = 2; /* an index transmission is two msgs */
652
645
} else if (msgs[i].flags & I2C_M_RD) {
653
-
ret = gmbus_xfer_read(i915, &msgs[i],
646
+
ret = gmbus_xfer_read(display, &msgs[i],
654
647
gmbus0_source | bus->reg0, 0);
655
648
} else {
656
-
ret = gmbus_xfer_write(i915, &msgs[i], 0);
649
+
ret = gmbus_xfer_write(display, &msgs[i], 0);
657
650
}
658
651
659
652
if (!ret)
660
-
ret = gmbus_wait(i915,
653
+
ret = gmbus_wait(display,
661
654
GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN);
662
655
if (ret == -ETIMEDOUT)
663
656
goto timeout;
···
670
661
* a STOP on the very first cycle. To simplify the code we
671
662
* unconditionally generate the STOP condition with an additional gmbus
672
663
* cycle. */
673
-
intel_de_write_fw(i915, GMBUS1(i915), GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
664
+
intel_de_write_fw(display, GMBUS1(display), GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
674
665
675
666
/* Mark the GMBUS interface as disabled after waiting for idle.
676
667
* We will re-enable it at the start of the next xfer,
677
668
* till then let it sleep.
678
669
*/
679
-
if (gmbus_wait_idle(i915)) {
680
-
drm_dbg_kms(&i915->drm,
670
+
if (gmbus_wait_idle(display)) {
671
+
drm_dbg_kms(display->drm,
681
672
"GMBUS [%s] timed out waiting for idle\n",
682
673
adapter->name);
683
674
ret = -ETIMEDOUT;
684
675
}
685
-
intel_de_write_fw(i915, GMBUS0(i915), 0);
676
+
intel_de_write_fw(display, GMBUS0(display), 0);
686
677
ret = ret ?: i;
687
678
goto out;
688
679
···
701
692
* it's slow responding and only answers on the 2nd retry.
702
693
*/
703
694
ret = -ENXIO;
704
-
if (gmbus_wait_idle(i915)) {
705
-
drm_dbg_kms(&i915->drm,
695
+
if (gmbus_wait_idle(display)) {
696
+
drm_dbg_kms(display->drm,
706
697
"GMBUS [%s] timed out after NAK\n",
707
698
adapter->name);
708
699
ret = -ETIMEDOUT;
···
712
703
* of resetting the GMBUS controller and so clearing the
713
704
* BUS_ERROR raised by the target's NAK.
714
705
*/
715
-
intel_de_write_fw(i915, GMBUS1(i915), GMBUS_SW_CLR_INT);
716
-
intel_de_write_fw(i915, GMBUS1(i915), 0);
717
-
intel_de_write_fw(i915, GMBUS0(i915), 0);
706
+
intel_de_write_fw(display, GMBUS1(display), GMBUS_SW_CLR_INT);
707
+
intel_de_write_fw(display, GMBUS1(display), 0);
708
+
intel_de_write_fw(display, GMBUS0(display), 0);
718
709
719
-
drm_dbg_kms(&i915->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n",
710
+
drm_dbg_kms(display->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n",
720
711
adapter->name, msgs[i].addr,
721
712
(msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
722
713
···
727
718
* drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
728
719
*/
729
720
if (ret == -ENXIO && i == 0 && try++ == 0) {
730
-
drm_dbg_kms(&i915->drm,
721
+
drm_dbg_kms(display->drm,
731
722
"GMBUS [%s] NAK on first message, retry\n",
732
723
adapter->name);
733
724
goto retry;
···
736
727
goto out;
737
728
738
729
timeout:
739
-
drm_dbg_kms(&i915->drm,
730
+
drm_dbg_kms(display->drm,
740
731
"GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
741
732
bus->adapter.name, bus->reg0 & 0xff);
742
-
intel_de_write_fw(i915, GMBUS0(i915), 0);
733
+
intel_de_write_fw(display, GMBUS0(display), 0);
743
734
744
735
/*
745
736
* Hardware may not support GMBUS over these pins? Try GPIO bitbanging
···
750
741
out:
751
742
/* Display WA #0868: skl,bxt,kbl,cfl,glk */
752
743
if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
753
-
bxt_gmbus_clock_gating(i915, true);
744
+
bxt_gmbus_clock_gating(display, true);
754
745
else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915))
755
-
pch_gmbus_clock_gating(i915, true);
746
+
pch_gmbus_clock_gating(display, true);
756
747
757
748
return ret;
758
749
}
···
761
752
gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
762
753
{
763
754
struct intel_gmbus *bus = to_intel_gmbus(adapter);
764
-
struct drm_i915_private *i915 = bus->i915;
755
+
struct intel_display *display = bus->display;
756
+
struct drm_i915_private *i915 = to_i915(display->drm);
765
757
intel_wakeref_t wakeref;
766
758
int ret;
767
759
···
786
776
int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
787
777
{
788
778
struct intel_gmbus *bus = to_intel_gmbus(adapter);
789
-
struct drm_i915_private *i915 = bus->i915;
779
+
struct intel_display *display = bus->display;
780
+
struct drm_i915_private *i915 = to_i915(display->drm);
790
781
u8 cmd = DRM_HDCP_DDC_AKSV;
791
782
u8 buf[DRM_HDCP_KSV_LEN] = {};
792
783
struct i2c_msg msgs[] = {
···
808
797
int ret;
809
798
810
799
wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS);
811
-
mutex_lock(&i915->display.gmbus.mutex);
800
+
mutex_lock(&display->gmbus.mutex);
812
801
813
802
/*
814
803
* In order to output Aksv to the receiver, use an indexed write to
···
817
806
*/
818
807
ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT);
819
808
820
-
mutex_unlock(&i915->display.gmbus.mutex);
809
+
mutex_unlock(&display->gmbus.mutex);
821
810
intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref);
822
811
823
812
return ret;
···
841
830
unsigned int flags)
842
831
{
843
832
struct intel_gmbus *bus = to_intel_gmbus(adapter);
844
-
struct drm_i915_private *i915 = bus->i915;
833
+
struct intel_display *display = bus->display;
845
834
846
-
mutex_lock(&i915->display.gmbus.mutex);
835
+
mutex_lock(&display->gmbus.mutex);
847
836
}
848
837
849
838
static int gmbus_trylock_bus(struct i2c_adapter *adapter,
850
839
unsigned int flags)
851
840
{
852
841
struct intel_gmbus *bus = to_intel_gmbus(adapter);
853
-
struct drm_i915_private *i915 = bus->i915;
842
+
struct intel_display *display = bus->display;
854
843
855
-
return mutex_trylock(&i915->display.gmbus.mutex);
844
+
return mutex_trylock(&display->gmbus.mutex);
856
845
}
857
846
858
847
static void gmbus_unlock_bus(struct i2c_adapter *adapter,
859
848
unsigned int flags)
860
849
{
861
850
struct intel_gmbus *bus = to_intel_gmbus(adapter);
862
-
struct drm_i915_private *i915 = bus->i915;
851
+
struct intel_display *display = bus->display;
863
852
864
-
mutex_unlock(&i915->display.gmbus.mutex);
853
+
mutex_unlock(&display->gmbus.mutex);
865
854
}
866
855
867
856
static const struct i2c_lock_operations gmbus_lock_ops = {
···
872
861
873
862
/**
874
863
* intel_gmbus_setup - instantiate all Intel i2c GMBuses
875
-
* @i915: i915 device private
864
+
* @display: display device
876
865
*/
877
-
int intel_gmbus_setup(struct drm_i915_private *i915)
866
+
int intel_gmbus_setup(struct intel_display *display)
878
867
{
879
-
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
868
+
struct drm_i915_private *i915 = to_i915(display->drm);
869
+
struct pci_dev *pdev = to_pci_dev(display->drm->dev);
880
870
unsigned int pin;
881
871
int ret;
882
872
883
873
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
884
-
i915->display.gmbus.mmio_base = VLV_DISPLAY_BASE;
885
-
else if (!HAS_GMCH(i915))
874
+
display->gmbus.mmio_base = VLV_DISPLAY_BASE;
875
+
else if (!HAS_GMCH(display))
886
876
/*
887
877
* Broxton uses the same PCH offsets for South Display Engine,
888
878
* even though it doesn't have a PCH.
889
879
*/
890
-
i915->display.gmbus.mmio_base = PCH_DISPLAY_BASE;
880
+
display->gmbus.mmio_base = PCH_DISPLAY_BASE;
891
881
892
-
mutex_init(&i915->display.gmbus.mutex);
893
-
init_waitqueue_head(&i915->display.gmbus.wait_queue);
882
+
mutex_init(&display->gmbus.mutex);
883
+
init_waitqueue_head(&display->gmbus.wait_queue);
894
884
895
-
for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) {
885
+
for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) {
896
886
const struct gmbus_pin *gmbus_pin;
897
887
struct intel_gmbus *bus;
898
888
899
-
gmbus_pin = get_gmbus_pin(i915, pin);
889
+
gmbus_pin = get_gmbus_pin(display, pin);
900
890
if (!gmbus_pin)
901
891
continue;
902
892
···
913
901
"i915 gmbus %s", gmbus_pin->name);
914
902
915
903
bus->adapter.dev.parent = &pdev->dev;
916
-
bus->i915 = i915;
904
+
bus->display = display;
917
905
918
906
bus->adapter.algo = &gmbus_algorithm;
919
907
bus->adapter.lock_ops = &gmbus_lock_ops;
···
931
919
if (IS_I830(i915))
932
920
bus->force_bit = 1;
933
921
934
-
intel_gpio_setup(bus, GPIO(i915, gmbus_pin->gpio));
922
+
intel_gpio_setup(bus, GPIO(display, gmbus_pin->gpio));
935
923
936
924
ret = i2c_add_adapter(&bus->adapter);
937
925
if (ret) {
···
939
927
goto err;
940
928
}
941
929
942
-
i915->display.gmbus.bus[pin] = bus;
930
+
display->gmbus.bus[pin] = bus;
943
931
}
944
932
945
-
intel_gmbus_reset(i915);
933
+
intel_gmbus_reset(display);
946
934
947
935
return 0;
948
936
949
937
err:
950
-
intel_gmbus_teardown(i915);
938
+
intel_gmbus_teardown(display);
951
939
952
940
return ret;
953
941
}
954
942
955
-
struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *i915,
943
+
struct i2c_adapter *intel_gmbus_get_adapter(struct intel_display *display,
956
944
unsigned int pin)
957
945
{
958
-
if (drm_WARN_ON(&i915->drm, pin >= ARRAY_SIZE(i915->display.gmbus.bus) ||
959
-
!i915->display.gmbus.bus[pin]))
946
+
if (drm_WARN_ON(display->drm, pin >= ARRAY_SIZE(display->gmbus.bus) ||
947
+
!display->gmbus.bus[pin]))
960
948
return NULL;
961
949
962
-
return &i915->display.gmbus.bus[pin]->adapter;
950
+
return &display->gmbus.bus[pin]->adapter;
963
951
}
964
952
965
953
void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
966
954
{
967
955
struct intel_gmbus *bus = to_intel_gmbus(adapter);
968
-
struct drm_i915_private *i915 = bus->i915;
956
+
struct intel_display *display = bus->display;
969
957
970
-
mutex_lock(&i915->display.gmbus.mutex);
958
+
mutex_lock(&display->gmbus.mutex);
971
959
972
960
bus->force_bit += force_bit ? 1 : -1;
973
-
drm_dbg_kms(&i915->drm,
961
+
drm_dbg_kms(display->drm,
974
962
"%sabling bit-banging on %s. force bit now %d\n",
975
963
force_bit ? "en" : "dis", adapter->name,
976
964
bus->force_bit);
977
965
978
-
mutex_unlock(&i915->display.gmbus.mutex);
966
+
mutex_unlock(&display->gmbus.mutex);
979
967
}
980
968
981
969
bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
···
985
973
return bus->force_bit;
986
974
}
987
975
988
-
void intel_gmbus_teardown(struct drm_i915_private *i915)
976
+
void intel_gmbus_teardown(struct intel_display *display)
989
977
{
990
978
unsigned int pin;
991
979
992
-
for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) {
980
+
for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) {
993
981
struct intel_gmbus *bus;
994
982
995
-
bus = i915->display.gmbus.bus[pin];
983
+
bus = display->gmbus.bus[pin];
996
984
if (!bus)
997
985
continue;
998
986
999
987
i2c_del_adapter(&bus->adapter);
1000
988
1001
989
kfree(bus);
1002
-
i915->display.gmbus.bus[pin] = NULL;
990
+
display->gmbus.bus[pin] = NULL;
1003
991
}
1004
992
}
1005
993
1006
-
void intel_gmbus_irq_handler(struct drm_i915_private *i915)
994
+
void intel_gmbus_irq_handler(struct intel_display *display)
1007
995
{
1008
-
wake_up_all(&i915->display.gmbus.wait_queue);
996
+
wake_up_all(&display->gmbus.wait_queue);
1009
997
}
+7
-8
drivers/gpu/drm/i915/display/intel_gmbus.h
+7
-8
drivers/gpu/drm/i915/display/intel_gmbus.h
···
8
8
9
9
#include <linux/types.h>
10
10
11
-
struct drm_i915_private;
12
11
struct i2c_adapter;
12
+
struct intel_display;
13
13
14
14
#define GMBUS_PIN_DISABLED 0
15
15
#define GMBUS_PIN_SSC 1
···
34
34
35
35
#define GMBUS_NUM_PINS 15 /* including 0 */
36
36
37
-
int intel_gmbus_setup(struct drm_i915_private *dev_priv);
38
-
void intel_gmbus_teardown(struct drm_i915_private *dev_priv);
39
-
bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
40
-
unsigned int pin);
37
+
int intel_gmbus_setup(struct intel_display *display);
38
+
void intel_gmbus_teardown(struct intel_display *display);
39
+
bool intel_gmbus_is_valid_pin(struct intel_display *display, unsigned int pin);
41
40
int intel_gmbus_output_aksv(struct i2c_adapter *adapter);
42
41
43
42
struct i2c_adapter *
44
-
intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
43
+
intel_gmbus_get_adapter(struct intel_display *display, unsigned int pin);
45
44
void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
46
45
bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter);
47
-
void intel_gmbus_reset(struct drm_i915_private *dev_priv);
46
+
void intel_gmbus_reset(struct intel_display *display);
48
47
49
-
void intel_gmbus_irq_handler(struct drm_i915_private *i915);
48
+
void intel_gmbus_irq_handler(struct intel_display *display);
50
49
51
50
#endif /* __INTEL_GMBUS_H__ */
+8
-8
drivers/gpu/drm/i915/display/intel_gmbus_regs.h
+8
-8
drivers/gpu/drm/i915/display/intel_gmbus_regs.h
···
8
8
9
9
#include "i915_reg_defs.h"
10
10
11
-
#define GMBUS_MMIO_BASE(__i915) ((__i915)->display.gmbus.mmio_base)
11
+
#define __GMBUS_MMIO_BASE(__display) ((__display)->gmbus.mmio_base)
12
12
13
-
#define GPIO(__i915, gpio) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5010 + 4 * (gpio))
13
+
#define GPIO(__display, gpio) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5010 + 4 * (gpio))
14
14
#define GPIO_CLOCK_DIR_MASK (1 << 0)
15
15
#define GPIO_CLOCK_DIR_IN (0 << 1)
16
16
#define GPIO_CLOCK_DIR_OUT (1 << 1)
···
27
27
#define GPIO_DATA_PULLUP_DISABLE (1 << 13)
28
28
29
29
/* clock/port select */
30
-
#define GMBUS0(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5100)
30
+
#define GMBUS0(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5100)
31
31
#define GMBUS_AKSV_SELECT (1 << 11)
32
32
#define GMBUS_RATE_100KHZ (0 << 8)
33
33
#define GMBUS_RATE_50KHZ (1 << 8)
···
37
37
#define GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
38
38
39
39
/* command/status */
40
-
#define GMBUS1(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5104)
40
+
#define GMBUS1(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5104)
41
41
#define GMBUS_SW_CLR_INT (1 << 31)
42
42
#define GMBUS_SW_RDY (1 << 30)
43
43
#define GMBUS_ENT (1 << 29) /* enable timeout */
···
54
54
#define GMBUS_SLAVE_WRITE (0 << 0)
55
55
56
56
/* status */
57
-
#define GMBUS2(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5108)
57
+
#define GMBUS2(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5108)
58
58
#define GMBUS_INUSE (1 << 15)
59
59
#define GMBUS_HW_WAIT_PHASE (1 << 14)
60
60
#define GMBUS_STALL_TIMEOUT (1 << 13)
···
64
64
#define GMBUS_ACTIVE (1 << 9)
65
65
66
66
/* data buffer bytes 3-0 */
67
-
#define GMBUS3(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x510c)
67
+
#define GMBUS3(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x510c)
68
68
69
69
/* interrupt mask (Pineview+) */
70
-
#define GMBUS4(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5110)
70
+
#define GMBUS4(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5110)
71
71
#define GMBUS_SLAVE_TIMEOUT_EN (1 << 4)
72
72
#define GMBUS_NAK_EN (1 << 3)
73
73
#define GMBUS_IDLE_EN (1 << 2)
···
75
75
#define GMBUS_HW_RDY_EN (1 << 0)
76
76
77
77
/* byte index */
78
-
#define GMBUS5(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5120)
78
+
#define GMBUS5(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5120)
79
79
#define GMBUS_2BYTE_INDEX_EN (1 << 31)
80
80
81
81
#endif /* __INTEL_GMBUS_REGS_H__ */
+16
-20
drivers/gpu/drm/i915/display/intel_hdcp.c
+16
-20
drivers/gpu/drm/i915/display/intel_hdcp.c
···
43
43
return;
44
44
45
45
if (DISPLAY_VER(display) >= 14) {
46
-
if (IS_DISPLAY_VER_STEP(display, IP_VER(14, 0), STEP_D0, STEP_FOREVER))
46
+
if (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_D0, STEP_FOREVER))
47
47
intel_de_rmw(display, MTL_CHICKEN_TRANS(hdcp->cpu_transcoder),
48
48
0, HDCP_LINE_REKEY_DISABLE);
49
-
else if (IS_DISPLAY_VER_STEP(display, IP_VER(14, 1), STEP_B0, STEP_FOREVER) ||
50
-
IS_DISPLAY_VER_STEP(display, IP_VER(20, 0), STEP_B0, STEP_FOREVER))
49
+
else if (IS_DISPLAY_VERx100_STEP(display, 1401, STEP_B0, STEP_FOREVER) ||
50
+
IS_DISPLAY_VERx100_STEP(display, 2000, STEP_B0, STEP_FOREVER))
51
51
intel_de_rmw(display,
52
52
TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder),
53
53
0, TRANS_DDI_HDCP_LINE_REKEY_DISABLE);
···
1192
1192
drm_connector_put(&connector->base);
1193
1193
}
1194
1194
1195
-
bool is_hdcp_supported(struct drm_i915_private *i915, enum port port)
1195
+
bool is_hdcp_supported(struct intel_display *display, enum port port)
1196
1196
{
1197
-
return DISPLAY_RUNTIME_INFO(i915)->has_hdcp &&
1198
-
(DISPLAY_VER(i915) >= 12 || port < PORT_E);
1197
+
return DISPLAY_RUNTIME_INFO(display)->has_hdcp &&
1198
+
(DISPLAY_VER(display) >= 12 || port < PORT_E);
1199
1199
}
1200
1200
1201
1201
static int
···
2301
2301
return 0;
2302
2302
}
2303
2303
2304
-
static bool is_hdcp2_supported(struct drm_i915_private *i915)
2304
+
static bool is_hdcp2_supported(struct intel_display *display)
2305
2305
{
2306
-
struct intel_display *display = to_intel_display(&i915->drm);
2306
+
struct drm_i915_private *i915 = to_i915(display->drm);
2307
2307
2308
2308
if (intel_hdcp_gsc_cs_required(display))
2309
2309
return true;
···
2317
2317
IS_COMETLAKE(i915));
2318
2318
}
2319
2319
2320
-
void intel_hdcp_component_init(struct drm_i915_private *i915)
2320
+
void intel_hdcp_component_init(struct intel_display *display)
2321
2321
{
2322
-
struct intel_display *display = to_intel_display(&i915->drm);
2323
2322
int ret;
2324
2323
2325
-
if (!is_hdcp2_supported(i915))
2324
+
if (!is_hdcp2_supported(display))
2326
2325
return;
2327
2326
2328
2327
mutex_lock(&display->hdcp.hdcp_mutex);
···
2366
2367
struct intel_digital_port *dig_port,
2367
2368
const struct intel_hdcp_shim *shim)
2368
2369
{
2369
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
2370
+
struct intel_display *display = to_intel_display(connector);
2370
2371
struct intel_hdcp *hdcp = &connector->hdcp;
2371
2372
int ret;
2372
2373
2373
2374
if (!shim)
2374
2375
return -EINVAL;
2375
2376
2376
-
if (is_hdcp2_supported(i915))
2377
+
if (is_hdcp2_supported(display))
2377
2378
intel_hdcp2_init(connector, dig_port, shim);
2378
2379
2379
-
ret =
2380
-
drm_connector_attach_content_protection_property(&connector->base,
2381
-
hdcp->hdcp2_supported);
2380
+
ret = drm_connector_attach_content_protection_property(&connector->base,
2381
+
hdcp->hdcp2_supported);
2382
2382
if (ret) {
2383
2383
hdcp->hdcp2_supported = false;
2384
2384
kfree(dig_port->hdcp_port_data.streams);
···
2430
2432
hdcp->stream_transcoder = INVALID_TRANSCODER;
2431
2433
}
2432
2434
2433
-
if (DISPLAY_VER(i915) >= 12)
2435
+
if (DISPLAY_VER(display) >= 12)
2434
2436
dig_port->hdcp_port_data.hdcp_transcoder =
2435
2437
intel_get_hdcp_transcoder(hdcp->cpu_transcoder);
2436
2438
···
2581
2583
_intel_hdcp_enable(state, encoder, crtc_state, conn_state);
2582
2584
}
2583
2585
2584
-
void intel_hdcp_component_fini(struct drm_i915_private *i915)
2586
+
void intel_hdcp_component_fini(struct intel_display *display)
2585
2587
{
2586
-
struct intel_display *display = to_intel_display(&i915->drm);
2587
-
2588
2588
mutex_lock(&display->hdcp.hdcp_mutex);
2589
2589
if (!display->hdcp.comp_added) {
2590
2590
mutex_unlock(&display->hdcp.hdcp_mutex);
+5
-5
drivers/gpu/drm/i915/display/intel_hdcp.h
+5
-5
drivers/gpu/drm/i915/display/intel_hdcp.h
···
12
12
13
13
struct drm_connector;
14
14
struct drm_connector_state;
15
-
struct drm_i915_private;
16
15
struct intel_atomic_state;
17
16
struct intel_connector;
18
17
struct intel_crtc_state;
18
+
struct intel_digital_port;
19
+
struct intel_display;
19
20
struct intel_encoder;
20
21
struct intel_hdcp_shim;
21
-
struct intel_digital_port;
22
22
enum port;
23
23
enum transcoder;
24
24
···
37
37
struct intel_encoder *encoder,
38
38
const struct intel_crtc_state *crtc_state,
39
39
const struct drm_connector_state *conn_state);
40
-
bool is_hdcp_supported(struct drm_i915_private *i915, enum port port);
40
+
bool is_hdcp_supported(struct intel_display *display, enum port port);
41
41
bool intel_hdcp_get_capability(struct intel_connector *connector);
42
42
bool intel_hdcp2_get_capability(struct intel_connector *connector);
43
43
void intel_hdcp_get_remote_capability(struct intel_connector *connector,
44
44
bool *hdcp_capable,
45
45
bool *hdcp2_capable);
46
-
void intel_hdcp_component_init(struct drm_i915_private *i915);
47
-
void intel_hdcp_component_fini(struct drm_i915_private *i915);
46
+
void intel_hdcp_component_init(struct intel_display *display);
47
+
void intel_hdcp_component_fini(struct intel_display *display);
48
48
void intel_hdcp_cleanup(struct intel_connector *connector);
49
49
void intel_hdcp_handle_cp_irq(struct intel_connector *connector);
50
50
+29
-7
drivers/gpu/drm/i915/display/intel_hdmi.c
+29
-7
drivers/gpu/drm/i915/display/intel_hdmi.c
···
62
62
#include "intel_hdmi.h"
63
63
#include "intel_lspcon.h"
64
64
#include "intel_panel.h"
65
+
#include "intel_pfit.h"
65
66
#include "intel_snps_phy.h"
66
67
67
68
static void
···
1210
1209
intel_write_infoframe(encoder, crtc_state,
1211
1210
HDMI_INFOFRAME_TYPE_VENDOR,
1212
1211
&crtc_state->infoframes.hdmi);
1212
+
}
1213
+
1214
+
void intel_hdmi_fastset_infoframes(struct intel_encoder *encoder,
1215
+
const struct intel_crtc_state *crtc_state,
1216
+
const struct drm_connector_state *conn_state)
1217
+
{
1218
+
struct intel_display *display = to_intel_display(encoder);
1219
+
i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display,
1220
+
crtc_state->cpu_transcoder);
1221
+
u32 val = intel_de_read(display, reg);
1222
+
1223
+
if ((crtc_state->infoframes.enable &
1224
+
intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) == 0 &&
1225
+
(val & VIDEO_DIP_ENABLE_DRM_GLK) == 0)
1226
+
return;
1227
+
1228
+
val &= ~(VIDEO_DIP_ENABLE_DRM_GLK);
1229
+
1230
+
intel_de_write(display, reg, val);
1231
+
intel_de_posting_read(display, reg);
1232
+
1233
+
intel_write_infoframe(encoder, crtc_state,
1234
+
HDMI_INFOFRAME_TYPE_DRM,
1235
+
&crtc_state->infoframes.drm);
1213
1236
}
1214
1237
1215
1238
static void hsw_set_infoframes(struct intel_encoder *encoder,
···
2942
2917
get_encoder_by_ddc_pin(struct intel_encoder *encoder, u8 ddc_pin)
2943
2918
{
2944
2919
struct intel_display *display = to_intel_display(encoder);
2945
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2946
2920
struct intel_encoder *other;
2947
2921
2948
2922
for_each_intel_encoder(display->drm, other) {
···
2955
2931
2956
2932
connector = enc_to_dig_port(other)->hdmi.attached_connector;
2957
2933
2958
-
if (connector && connector->base.ddc == intel_gmbus_get_adapter(i915, ddc_pin))
2934
+
if (connector && connector->base.ddc == intel_gmbus_get_adapter(display, ddc_pin))
2959
2935
return other;
2960
2936
}
2961
2937
···
2965
2941
static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
2966
2942
{
2967
2943
struct intel_display *display = to_intel_display(encoder);
2968
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2969
2944
struct intel_encoder *other;
2970
2945
const char *source;
2971
2946
u8 ddc_pin;
···
2977
2954
source = "platform default";
2978
2955
}
2979
2956
2980
-
if (!intel_gmbus_is_valid_pin(i915, ddc_pin)) {
2957
+
if (!intel_gmbus_is_valid_pin(display, ddc_pin)) {
2981
2958
drm_dbg_kms(display->drm,
2982
2959
"[ENCODER:%d:%s] Invalid DDC pin %d\n",
2983
2960
encoder->base.base.id, encoder->base.name, ddc_pin);
···
3050
3027
struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3051
3028
struct intel_encoder *intel_encoder = &dig_port->base;
3052
3029
struct drm_device *dev = intel_encoder->base.dev;
3053
-
struct drm_i915_private *dev_priv = to_i915(dev);
3054
3030
enum port port = intel_encoder->port;
3055
3031
struct cec_connector_info conn_info;
3056
3032
u8 ddc_pin;
···
3074
3052
drm_connector_init_with_ddc(dev, connector,
3075
3053
&intel_hdmi_connector_funcs,
3076
3054
DRM_MODE_CONNECTOR_HDMIA,
3077
-
intel_gmbus_get_adapter(dev_priv, ddc_pin));
3055
+
intel_gmbus_get_adapter(display, ddc_pin));
3078
3056
3079
3057
drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
3080
3058
···
3099
3077
intel_connector_attach_encoder(intel_connector, intel_encoder);
3100
3078
intel_hdmi->attached_connector = intel_connector;
3101
3079
3102
-
if (is_hdcp_supported(dev_priv, port)) {
3080
+
if (is_hdcp_supported(display, port)) {
3103
3081
int ret = intel_hdcp_init(intel_connector, dig_port,
3104
3082
&intel_hdmi_hdcp_shim);
3105
3083
if (ret)
+3
drivers/gpu/drm/i915/display/intel_hdmi.h
+3
drivers/gpu/drm/i915/display/intel_hdmi.h
···
42
42
u32 intel_hdmi_infoframe_enable(unsigned int type);
43
43
void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
44
44
struct intel_crtc_state *crtc_state);
45
+
void intel_hdmi_fastset_infoframes(struct intel_encoder *encoder,
46
+
const struct intel_crtc_state *crtc_state,
47
+
const struct drm_connector_state *conn_state);
45
48
void intel_read_infoframe(struct intel_encoder *encoder,
46
49
const struct intel_crtc_state *crtc_state,
47
50
enum hdmi_infoframe_type type,
+4
-2
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+4
-2
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
···
556
556
557
557
void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
558
558
{
559
+
struct intel_display *display = &dev_priv->display;
559
560
u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP;
560
561
u32 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_MASK_ICP;
561
562
u32 pin_mask = 0, long_mask = 0;
···
590
589
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
591
590
592
591
if (pch_iir & SDE_GMBUS_ICP)
593
-
intel_gmbus_irq_handler(dev_priv);
592
+
intel_gmbus_irq_handler(display);
594
593
}
595
594
596
595
void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
597
596
{
597
+
struct intel_display *display = &dev_priv->display;
598
598
u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
599
599
~SDE_PORTE_HOTPLUG_SPT;
600
600
u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
···
627
625
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
628
626
629
627
if (pch_iir & SDE_GMBUS_CPT)
630
-
intel_gmbus_irq_handler(dev_priv);
628
+
intel_gmbus_irq_handler(display);
631
629
}
632
630
633
631
void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger)
+2
-1
drivers/gpu/drm/i915/display/intel_lvds.c
+2
-1
drivers/gpu/drm/i915/display/intel_lvds.c
···
52
52
#include "intel_lvds.h"
53
53
#include "intel_lvds_regs.h"
54
54
#include "intel_panel.h"
55
+
#include "intel_pfit.h"
55
56
#include "intel_pps_regs.h"
56
57
57
58
/* Private structure for the integrated LVDS support */
···
901
900
drm_connector_init_with_ddc(&i915->drm, &connector->base,
902
901
&intel_lvds_connector_funcs,
903
902
DRM_MODE_CONNECTOR_LVDS,
904
-
intel_gmbus_get_adapter(i915, ddc_pin));
903
+
intel_gmbus_get_adapter(display, ddc_pin));
905
904
906
905
drm_encoder_init(&i915->drm, &encoder->base, &intel_lvds_enc_funcs,
907
906
DRM_MODE_ENCODER_LVDS, "LVDS");
+46
-43
drivers/gpu/drm/i915/display/intel_modeset_verify.c
+46
-43
drivers/gpu/drm/i915/display/intel_modeset_verify.c
···
27
27
const struct drm_connector_state *conn_state)
28
28
{
29
29
struct intel_connector *connector = to_intel_connector(conn_state->connector);
30
+
struct intel_display *display = to_intel_display(connector);
30
31
struct drm_i915_private *i915 = to_i915(connector->base.dev);
31
32
32
33
drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
···
36
35
if (connector->get_hw_state(connector)) {
37
36
struct intel_encoder *encoder = intel_attached_encoder(connector);
38
37
39
-
I915_STATE_WARN(i915, !crtc_state,
40
-
"connector enabled without attached crtc\n");
38
+
INTEL_DISPLAY_STATE_WARN(display, !crtc_state,
39
+
"connector enabled without attached crtc\n");
41
40
42
41
if (!crtc_state)
43
42
return;
44
43
45
-
I915_STATE_WARN(i915, !crtc_state->hw.active,
46
-
"connector is active, but attached crtc isn't\n");
44
+
INTEL_DISPLAY_STATE_WARN(display, !crtc_state->hw.active,
45
+
"connector is active, but attached crtc isn't\n");
47
46
48
47
if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
49
48
return;
50
49
51
-
I915_STATE_WARN(i915,
52
-
conn_state->best_encoder != &encoder->base,
53
-
"atomic encoder doesn't match attached encoder\n");
50
+
INTEL_DISPLAY_STATE_WARN(display,
51
+
conn_state->best_encoder != &encoder->base,
52
+
"atomic encoder doesn't match attached encoder\n");
54
53
55
-
I915_STATE_WARN(i915, conn_state->crtc != encoder->base.crtc,
56
-
"attached encoder crtc differs from connector crtc\n");
54
+
INTEL_DISPLAY_STATE_WARN(display, conn_state->crtc != encoder->base.crtc,
55
+
"attached encoder crtc differs from connector crtc\n");
57
56
} else {
58
-
I915_STATE_WARN(i915, crtc_state && crtc_state->hw.active,
59
-
"attached crtc is active, but connector isn't\n");
60
-
I915_STATE_WARN(i915, !crtc_state && conn_state->best_encoder,
61
-
"best encoder set without crtc!\n");
57
+
INTEL_DISPLAY_STATE_WARN(display, crtc_state && crtc_state->hw.active,
58
+
"attached crtc is active, but connector isn't\n");
59
+
INTEL_DISPLAY_STATE_WARN(display, !crtc_state && conn_state->best_encoder,
60
+
"best encoder set without crtc!\n");
62
61
}
63
62
}
64
63
···
66
65
verify_connector_state(struct intel_atomic_state *state,
67
66
struct intel_crtc *crtc)
68
67
{
68
+
struct intel_display *display = to_intel_display(state);
69
69
struct drm_connector *connector;
70
70
const struct drm_connector_state *new_conn_state;
71
71
int i;
···
83
81
84
82
intel_connector_verify_state(crtc_state, new_conn_state);
85
83
86
-
I915_STATE_WARN(to_i915(connector->dev), new_conn_state->best_encoder != encoder,
87
-
"connector's atomic encoder doesn't match legacy encoder\n");
84
+
INTEL_DISPLAY_STATE_WARN(display, new_conn_state->best_encoder != encoder,
85
+
"connector's atomic encoder doesn't match legacy encoder\n");
88
86
}
89
87
}
90
88
···
111
109
static void
112
110
verify_encoder_state(struct intel_atomic_state *state)
113
111
{
112
+
struct intel_display *display = to_intel_display(state);
114
113
struct drm_i915_private *i915 = to_i915(state->base.dev);
115
114
struct intel_encoder *encoder;
116
115
struct drm_connector *connector;
···
137
134
found = true;
138
135
enabled = true;
139
136
140
-
I915_STATE_WARN(i915,
141
-
new_conn_state->crtc != encoder->base.crtc,
142
-
"connector's crtc doesn't match encoder crtc\n");
137
+
INTEL_DISPLAY_STATE_WARN(display,
138
+
new_conn_state->crtc != encoder->base.crtc,
139
+
"connector's crtc doesn't match encoder crtc\n");
143
140
}
144
141
145
142
if (!found)
146
143
continue;
147
144
148
-
I915_STATE_WARN(i915, !!encoder->base.crtc != enabled,
149
-
"encoder's enabled state mismatch (expected %i, found %i)\n",
150
-
!!encoder->base.crtc, enabled);
145
+
INTEL_DISPLAY_STATE_WARN(display, !!encoder->base.crtc != enabled,
146
+
"encoder's enabled state mismatch (expected %i, found %i)\n",
147
+
!!encoder->base.crtc, enabled);
151
148
152
149
if (!encoder->base.crtc) {
153
150
bool active;
154
151
155
152
active = encoder->get_hw_state(encoder, &pipe);
156
-
I915_STATE_WARN(i915, active,
157
-
"encoder detached but still enabled on pipe %c.\n",
158
-
pipe_name(pipe));
153
+
INTEL_DISPLAY_STATE_WARN(display, active,
154
+
"encoder detached but still enabled on pipe %c.\n",
155
+
pipe_name(pipe));
159
156
}
160
157
}
161
158
}
···
164
161
verify_crtc_state(struct intel_atomic_state *state,
165
162
struct intel_crtc *crtc)
166
163
{
167
-
struct drm_device *dev = crtc->base.dev;
168
-
struct drm_i915_private *i915 = to_i915(dev);
164
+
struct intel_display *display = to_intel_display(state);
165
+
struct drm_i915_private *i915 = to_i915(display->drm);
169
166
const struct intel_crtc_state *sw_crtc_state =
170
167
intel_atomic_get_new_crtc_state(state, crtc);
171
168
struct intel_crtc_state *hw_crtc_state;
···
176
173
if (!hw_crtc_state)
177
174
return;
178
175
179
-
drm_dbg_kms(&i915->drm, "[CRTC:%d:%s]\n", crtc->base.base.id,
176
+
drm_dbg_kms(display->drm, "[CRTC:%d:%s]\n", crtc->base.base.id,
180
177
crtc->base.name);
181
178
182
179
hw_crtc_state->hw.enable = sw_crtc_state->hw.enable;
···
187
184
if (IS_I830(i915) && hw_crtc_state->hw.active)
188
185
hw_crtc_state->hw.active = sw_crtc_state->hw.active;
189
186
190
-
I915_STATE_WARN(i915,
191
-
sw_crtc_state->hw.active != hw_crtc_state->hw.active,
192
-
"crtc active state doesn't match with hw state (expected %i, found %i)\n",
193
-
sw_crtc_state->hw.active, hw_crtc_state->hw.active);
187
+
INTEL_DISPLAY_STATE_WARN(display,
188
+
sw_crtc_state->hw.active != hw_crtc_state->hw.active,
189
+
"crtc active state doesn't match with hw state (expected %i, found %i)\n",
190
+
sw_crtc_state->hw.active, hw_crtc_state->hw.active);
194
191
195
-
I915_STATE_WARN(i915, crtc->active != sw_crtc_state->hw.active,
196
-
"transitional active state does not match atomic hw state (expected %i, found %i)\n",
197
-
sw_crtc_state->hw.active, crtc->active);
192
+
INTEL_DISPLAY_STATE_WARN(display, crtc->active != sw_crtc_state->hw.active,
193
+
"transitional active state does not match atomic hw state (expected %i, found %i)\n",
194
+
sw_crtc_state->hw.active, crtc->active);
198
195
199
196
primary_crtc = intel_primary_crtc(sw_crtc_state);
200
197
201
-
for_each_encoder_on_crtc(dev, &primary_crtc->base, encoder) {
198
+
for_each_encoder_on_crtc(display->drm, &primary_crtc->base, encoder) {
202
199
enum pipe pipe;
203
200
bool active;
204
201
205
202
active = encoder->get_hw_state(encoder, &pipe);
206
-
I915_STATE_WARN(i915, active != sw_crtc_state->hw.active,
207
-
"[ENCODER:%i] active %i with crtc active %i\n",
208
-
encoder->base.base.id, active,
209
-
sw_crtc_state->hw.active);
203
+
INTEL_DISPLAY_STATE_WARN(display, active != sw_crtc_state->hw.active,
204
+
"[ENCODER:%i] active %i with crtc active %i\n",
205
+
encoder->base.base.id, active,
206
+
sw_crtc_state->hw.active);
210
207
211
-
I915_STATE_WARN(i915, active && primary_crtc->pipe != pipe,
212
-
"Encoder connected to wrong pipe %c\n",
213
-
pipe_name(pipe));
208
+
INTEL_DISPLAY_STATE_WARN(display, active && primary_crtc->pipe != pipe,
209
+
"Encoder connected to wrong pipe %c\n",
210
+
pipe_name(pipe));
214
211
215
212
if (active)
216
213
intel_encoder_get_config(encoder, hw_crtc_state);
···
223
220
224
221
if (!intel_pipe_config_compare(sw_crtc_state,
225
222
hw_crtc_state, false)) {
226
-
I915_STATE_WARN(i915, 1, "pipe state doesn't match!\n");
223
+
INTEL_DISPLAY_STATE_WARN(display, 1, "pipe state doesn't match!\n");
227
224
intel_crtc_state_dump(hw_crtc_state, NULL, "hw state");
228
225
intel_crtc_state_dump(sw_crtc_state, NULL, "sw state");
229
226
}
+16
-314
drivers/gpu/drm/i915/display/intel_panel.c
+16
-314
drivers/gpu/drm/i915/display/intel_panel.c
···
33
33
34
34
#include <drm/drm_edid.h>
35
35
36
-
#include "i915_reg.h"
36
+
#include "i915_drv.h"
37
37
#include "intel_backlight.h"
38
38
#include "intel_connector.h"
39
-
#include "intel_de.h"
39
+
#include "intel_display_core.h"
40
40
#include "intel_display_driver.h"
41
41
#include "intel_display_types.h"
42
42
#include "intel_drrs.h"
43
-
#include "intel_lvds_regs.h"
44
43
#include "intel_panel.h"
45
44
#include "intel_quirks.h"
46
45
#include "intel_vrr.h"
47
46
48
-
bool intel_panel_use_ssc(struct drm_i915_private *i915)
47
+
bool intel_panel_use_ssc(struct intel_display *display)
49
48
{
50
-
struct intel_display *display = &i915->display;
51
-
52
49
if (display->params.panel_use_ssc >= 0)
53
50
return display->params.panel_use_ssc != 0;
54
51
return display->vbt.lvds_use_ssc &&
···
249
252
250
253
static void intel_panel_add_edid_alt_fixed_modes(struct intel_connector *connector)
251
254
{
252
-
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
255
+
struct intel_display *display = to_intel_display(connector);
253
256
const struct drm_display_mode *preferred_mode =
254
257
intel_panel_preferred_fixed_mode(connector);
255
258
struct drm_display_mode *mode, *next;
···
258
261
if (!is_alt_fixed_mode(mode, preferred_mode))
259
262
continue;
260
263
261
-
drm_dbg_kms(&dev_priv->drm,
264
+
drm_dbg_kms(display->drm,
262
265
"[CONNECTOR:%d:%s] using alternate EDID fixed mode: " DRM_MODE_FMT "\n",
263
266
connector->base.base.id, connector->base.name,
264
267
DRM_MODE_ARG(mode));
···
269
272
270
273
static void intel_panel_add_edid_preferred_mode(struct intel_connector *connector)
271
274
{
272
-
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
275
+
struct intel_display *display = to_intel_display(connector);
273
276
struct drm_display_mode *scan, *fixed_mode = NULL;
274
277
275
278
if (list_empty(&connector->base.probed_modes))
···
287
290
fixed_mode = list_first_entry(&connector->base.probed_modes,
288
291
typeof(*fixed_mode), head);
289
292
290
-
drm_dbg_kms(&dev_priv->drm,
293
+
drm_dbg_kms(display->drm,
291
294
"[CONNECTOR:%d:%s] using %s EDID fixed mode: " DRM_MODE_FMT "\n",
292
295
connector->base.base.id, connector->base.name,
293
296
fixed_mode->type & DRM_MODE_TYPE_PREFERRED ? "preferred" : "first",
···
300
303
301
304
static void intel_panel_destroy_probed_modes(struct intel_connector *connector)
302
305
{
303
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
306
+
struct intel_display *display = to_intel_display(connector);
304
307
struct drm_display_mode *mode, *next;
305
308
306
309
list_for_each_entry_safe(mode, next, &connector->base.probed_modes, head) {
307
-
drm_dbg_kms(&i915->drm,
310
+
drm_dbg_kms(display->drm,
308
311
"[CONNECTOR:%d:%s] not using EDID mode: " DRM_MODE_FMT "\n",
309
312
connector->base.base.id, connector->base.name,
310
313
DRM_MODE_ARG(mode));
311
314
list_del(&mode->head);
312
-
drm_mode_destroy(&i915->drm, mode);
315
+
drm_mode_destroy(display->drm, mode);
313
316
}
314
317
}
315
318
···
326
329
struct drm_display_mode *fixed_mode,
327
330
const char *type)
328
331
{
329
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
332
+
struct intel_display *display = to_intel_display(connector);
330
333
struct drm_display_info *info = &connector->base.display_info;
331
334
332
335
if (!fixed_mode)
···
337
340
info->width_mm = fixed_mode->width_mm;
338
341
info->height_mm = fixed_mode->height_mm;
339
342
340
-
drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] using %s fixed mode: " DRM_MODE_FMT "\n",
343
+
drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] using %s fixed mode: " DRM_MODE_FMT "\n",
341
344
connector->base.base.id, connector->base.name, type,
342
345
DRM_MODE_ARG(fixed_mode));
343
346
···
346
349
347
350
void intel_panel_add_vbt_lfp_fixed_mode(struct intel_connector *connector)
348
351
{
349
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
352
+
struct intel_display *display = to_intel_display(connector);
350
353
const struct drm_display_mode *mode;
351
354
352
355
mode = connector->panel.vbt.lfp_vbt_mode;
···
354
357
return;
355
358
356
359
intel_panel_add_fixed_mode(connector,
357
-
drm_mode_duplicate(&i915->drm, mode),
360
+
drm_mode_duplicate(display->drm, mode),
358
361
"VBT LFP");
359
362
}
360
363
361
364
void intel_panel_add_vbt_sdvo_fixed_mode(struct intel_connector *connector)
362
365
{
363
-
struct drm_i915_private *i915 = to_i915(connector->base.dev);
366
+
struct intel_display *display = to_intel_display(connector);
364
367
const struct drm_display_mode *mode;
365
368
366
369
mode = connector->panel.vbt.sdvo_lvds_vbt_mode;
···
368
371
return;
369
372
370
373
intel_panel_add_fixed_mode(connector,
371
-
drm_mode_duplicate(&i915->drm, mode),
374
+
drm_mode_duplicate(display->drm, mode),
372
375
"VBT SDVO");
373
376
}
374
377
···
378
381
intel_panel_add_fixed_mode(connector,
379
382
intel_encoder_current_mode(encoder),
380
383
"current (BIOS)");
381
-
}
382
-
383
-
/* adjusted_mode has been preset to be the panel's fixed mode */
384
-
static int pch_panel_fitting(struct intel_crtc_state *crtc_state,
385
-
const struct drm_connector_state *conn_state)
386
-
{
387
-
const struct drm_display_mode *adjusted_mode =
388
-
&crtc_state->hw.adjusted_mode;
389
-
int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
390
-
int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
391
-
int x, y, width, height;
392
-
393
-
/* Native modes don't need fitting */
394
-
if (adjusted_mode->crtc_hdisplay == pipe_src_w &&
395
-
adjusted_mode->crtc_vdisplay == pipe_src_h &&
396
-
crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
397
-
return 0;
398
-
399
-
switch (conn_state->scaling_mode) {
400
-
case DRM_MODE_SCALE_CENTER:
401
-
width = pipe_src_w;
402
-
height = pipe_src_h;
403
-
x = (adjusted_mode->crtc_hdisplay - width + 1)/2;
404
-
y = (adjusted_mode->crtc_vdisplay - height + 1)/2;
405
-
break;
406
-
407
-
case DRM_MODE_SCALE_ASPECT:
408
-
/* Scale but preserve the aspect ratio */
409
-
{
410
-
u32 scaled_width = adjusted_mode->crtc_hdisplay * pipe_src_h;
411
-
u32 scaled_height = pipe_src_w * adjusted_mode->crtc_vdisplay;
412
-
if (scaled_width > scaled_height) { /* pillar */
413
-
width = scaled_height / pipe_src_h;
414
-
if (width & 1)
415
-
width++;
416
-
x = (adjusted_mode->crtc_hdisplay - width + 1) / 2;
417
-
y = 0;
418
-
height = adjusted_mode->crtc_vdisplay;
419
-
} else if (scaled_width < scaled_height) { /* letter */
420
-
height = scaled_width / pipe_src_w;
421
-
if (height & 1)
422
-
height++;
423
-
y = (adjusted_mode->crtc_vdisplay - height + 1) / 2;
424
-
x = 0;
425
-
width = adjusted_mode->crtc_hdisplay;
426
-
} else {
427
-
x = y = 0;
428
-
width = adjusted_mode->crtc_hdisplay;
429
-
height = adjusted_mode->crtc_vdisplay;
430
-
}
431
-
}
432
-
break;
433
-
434
-
case DRM_MODE_SCALE_NONE:
435
-
WARN_ON(adjusted_mode->crtc_hdisplay != pipe_src_w);
436
-
WARN_ON(adjusted_mode->crtc_vdisplay != pipe_src_h);
437
-
fallthrough;
438
-
case DRM_MODE_SCALE_FULLSCREEN:
439
-
x = y = 0;
440
-
width = adjusted_mode->crtc_hdisplay;
441
-
height = adjusted_mode->crtc_vdisplay;
442
-
break;
443
-
444
-
default:
445
-
MISSING_CASE(conn_state->scaling_mode);
446
-
return -EINVAL;
447
-
}
448
-
449
-
drm_rect_init(&crtc_state->pch_pfit.dst,
450
-
x, y, width, height);
451
-
crtc_state->pch_pfit.enabled = true;
452
-
453
-
return 0;
454
-
}
455
-
456
-
static void
457
-
centre_horizontally(struct drm_display_mode *adjusted_mode,
458
-
int width)
459
-
{
460
-
u32 border, sync_pos, blank_width, sync_width;
461
-
462
-
/* keep the hsync and hblank widths constant */
463
-
sync_width = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
464
-
blank_width = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start;
465
-
sync_pos = (blank_width - sync_width + 1) / 2;
466
-
467
-
border = (adjusted_mode->crtc_hdisplay - width + 1) / 2;
468
-
border += border & 1; /* make the border even */
469
-
470
-
adjusted_mode->crtc_hdisplay = width;
471
-
adjusted_mode->crtc_hblank_start = width + border;
472
-
adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_start + blank_width;
473
-
474
-
adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hblank_start + sync_pos;
475
-
adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + sync_width;
476
-
}
477
-
478
-
static void
479
-
centre_vertically(struct drm_display_mode *adjusted_mode,
480
-
int height)
481
-
{
482
-
u32 border, sync_pos, blank_width, sync_width;
483
-
484
-
/* keep the vsync and vblank widths constant */
485
-
sync_width = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
486
-
blank_width = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start;
487
-
sync_pos = (blank_width - sync_width + 1) / 2;
488
-
489
-
border = (adjusted_mode->crtc_vdisplay - height + 1) / 2;
490
-
491
-
adjusted_mode->crtc_vdisplay = height;
492
-
adjusted_mode->crtc_vblank_start = height + border;
493
-
adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vblank_start + blank_width;
494
-
495
-
adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vblank_start + sync_pos;
496
-
adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + sync_width;
497
-
}
498
-
499
-
static u32 panel_fitter_scaling(u32 source, u32 target)
500
-
{
501
-
/*
502
-
* Floating point operation is not supported. So the FACTOR
503
-
* is defined, which can avoid the floating point computation
504
-
* when calculating the panel ratio.
505
-
*/
506
-
#define ACCURACY 12
507
-
#define FACTOR (1 << ACCURACY)
508
-
u32 ratio = source * FACTOR / target;
509
-
return (FACTOR * ratio + FACTOR/2) / FACTOR;
510
-
}
511
-
512
-
static void i965_scale_aspect(struct intel_crtc_state *crtc_state,
513
-
u32 *pfit_control)
514
-
{
515
-
const struct drm_display_mode *adjusted_mode =
516
-
&crtc_state->hw.adjusted_mode;
517
-
int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
518
-
int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
519
-
u32 scaled_width = adjusted_mode->crtc_hdisplay * pipe_src_h;
520
-
u32 scaled_height = pipe_src_w * adjusted_mode->crtc_vdisplay;
521
-
522
-
/* 965+ is easy, it does everything in hw */
523
-
if (scaled_width > scaled_height)
524
-
*pfit_control |= PFIT_ENABLE |
525
-
PFIT_SCALING_PILLAR;
526
-
else if (scaled_width < scaled_height)
527
-
*pfit_control |= PFIT_ENABLE |
528
-
PFIT_SCALING_LETTER;
529
-
else if (adjusted_mode->crtc_hdisplay != pipe_src_w)
530
-
*pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
531
-
}
532
-
533
-
static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
534
-
u32 *pfit_control, u32 *pfit_pgm_ratios,
535
-
u32 *border)
536
-
{
537
-
struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
538
-
int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
539
-
int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
540
-
u32 scaled_width = adjusted_mode->crtc_hdisplay * pipe_src_h;
541
-
u32 scaled_height = pipe_src_w * adjusted_mode->crtc_vdisplay;
542
-
u32 bits;
543
-
544
-
/*
545
-
* For earlier chips we have to calculate the scaling
546
-
* ratio by hand and program it into the
547
-
* PFIT_PGM_RATIO register
548
-
*/
549
-
if (scaled_width > scaled_height) { /* pillar */
550
-
centre_horizontally(adjusted_mode,
551
-
scaled_height / pipe_src_h);
552
-
553
-
*border = LVDS_BORDER_ENABLE;
554
-
if (pipe_src_h != adjusted_mode->crtc_vdisplay) {
555
-
bits = panel_fitter_scaling(pipe_src_h,
556
-
adjusted_mode->crtc_vdisplay);
557
-
558
-
*pfit_pgm_ratios |= (PFIT_HORIZ_SCALE(bits) |
559
-
PFIT_VERT_SCALE(bits));
560
-
*pfit_control |= (PFIT_ENABLE |
561
-
PFIT_VERT_INTERP_BILINEAR |
562
-
PFIT_HORIZ_INTERP_BILINEAR);
563
-
}
564
-
} else if (scaled_width < scaled_height) { /* letter */
565
-
centre_vertically(adjusted_mode,
566
-
scaled_width / pipe_src_w);
567
-
568
-
*border = LVDS_BORDER_ENABLE;
569
-
if (pipe_src_w != adjusted_mode->crtc_hdisplay) {
570
-
bits = panel_fitter_scaling(pipe_src_w,
571
-
adjusted_mode->crtc_hdisplay);
572
-
573
-
*pfit_pgm_ratios |= (PFIT_HORIZ_SCALE(bits) |
574
-
PFIT_VERT_SCALE(bits));
575
-
*pfit_control |= (PFIT_ENABLE |
576
-
PFIT_VERT_INTERP_BILINEAR |
577
-
PFIT_HORIZ_INTERP_BILINEAR);
578
-
}
579
-
} else {
580
-
/* Aspects match, Let hw scale both directions */
581
-
*pfit_control |= (PFIT_ENABLE |
582
-
PFIT_VERT_AUTO_SCALE |
583
-
PFIT_HORIZ_AUTO_SCALE |
584
-
PFIT_VERT_INTERP_BILINEAR |
585
-
PFIT_HORIZ_INTERP_BILINEAR);
586
-
}
587
-
}
588
-
589
-
static int gmch_panel_fitting(struct intel_crtc_state *crtc_state,
590
-
const struct drm_connector_state *conn_state)
591
-
{
592
-
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
593
-
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
594
-
u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
595
-
struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
596
-
int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
597
-
int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
598
-
599
-
/* Native modes don't need fitting */
600
-
if (adjusted_mode->crtc_hdisplay == pipe_src_w &&
601
-
adjusted_mode->crtc_vdisplay == pipe_src_h)
602
-
goto out;
603
-
604
-
switch (conn_state->scaling_mode) {
605
-
case DRM_MODE_SCALE_CENTER:
606
-
/*
607
-
* For centered modes, we have to calculate border widths &
608
-
* heights and modify the values programmed into the CRTC.
609
-
*/
610
-
centre_horizontally(adjusted_mode, pipe_src_w);
611
-
centre_vertically(adjusted_mode, pipe_src_h);
612
-
border = LVDS_BORDER_ENABLE;
613
-
break;
614
-
case DRM_MODE_SCALE_ASPECT:
615
-
/* Scale but preserve the aspect ratio */
616
-
if (DISPLAY_VER(dev_priv) >= 4)
617
-
i965_scale_aspect(crtc_state, &pfit_control);
618
-
else
619
-
i9xx_scale_aspect(crtc_state, &pfit_control,
620
-
&pfit_pgm_ratios, &border);
621
-
break;
622
-
case DRM_MODE_SCALE_FULLSCREEN:
623
-
/*
624
-
* Full scaling, even if it changes the aspect ratio.
625
-
* Fortunately this is all done for us in hw.
626
-
*/
627
-
if (pipe_src_h != adjusted_mode->crtc_vdisplay ||
628
-
pipe_src_w != adjusted_mode->crtc_hdisplay) {
629
-
pfit_control |= PFIT_ENABLE;
630
-
if (DISPLAY_VER(dev_priv) >= 4)
631
-
pfit_control |= PFIT_SCALING_AUTO;
632
-
else
633
-
pfit_control |= (PFIT_VERT_AUTO_SCALE |
634
-
PFIT_VERT_INTERP_BILINEAR |
635
-
PFIT_HORIZ_AUTO_SCALE |
636
-
PFIT_HORIZ_INTERP_BILINEAR);
637
-
}
638
-
break;
639
-
default:
640
-
MISSING_CASE(conn_state->scaling_mode);
641
-
return -EINVAL;
642
-
}
643
-
644
-
/* 965+ wants fuzzy fitting */
645
-
/* FIXME: handle multiple panels by failing gracefully */
646
-
if (DISPLAY_VER(dev_priv) >= 4)
647
-
pfit_control |= PFIT_PIPE(crtc->pipe) | PFIT_FILTER_FUZZY;
648
-
649
-
out:
650
-
if ((pfit_control & PFIT_ENABLE) == 0) {
651
-
pfit_control = 0;
652
-
pfit_pgm_ratios = 0;
653
-
}
654
-
655
-
/* Make sure pre-965 set dither correctly for 18bpp panels. */
656
-
if (DISPLAY_VER(dev_priv) < 4 && crtc_state->pipe_bpp == 18)
657
-
pfit_control |= PFIT_PANEL_8TO6_DITHER_ENABLE;
658
-
659
-
crtc_state->gmch_pfit.control = pfit_control;
660
-
crtc_state->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
661
-
crtc_state->gmch_pfit.lvds_border_bits = border;
662
-
663
-
return 0;
664
-
}
665
-
666
-
int intel_panel_fitting(struct intel_crtc_state *crtc_state,
667
-
const struct drm_connector_state *conn_state)
668
-
{
669
-
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
670
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
671
-
672
-
if (HAS_GMCH(i915))
673
-
return gmch_panel_fitting(crtc_state, conn_state);
674
-
else
675
-
return pch_panel_fitting(crtc_state, conn_state);
676
384
}
677
385
678
386
enum drm_connector_status
+2
-4
drivers/gpu/drm/i915/display/intel_panel.h
+2
-4
drivers/gpu/drm/i915/display/intel_panel.h
···
14
14
struct drm_connector_state;
15
15
struct drm_display_mode;
16
16
struct drm_edid;
17
-
struct drm_i915_private;
18
17
struct intel_connector;
19
18
struct intel_crtc_state;
19
+
struct intel_display;
20
20
struct intel_encoder;
21
21
22
22
void intel_panel_init_alloc(struct intel_connector *connector);
···
25
25
void intel_panel_fini(struct intel_connector *connector);
26
26
enum drm_connector_status
27
27
intel_panel_detect(struct drm_connector *connector, bool force);
28
-
bool intel_panel_use_ssc(struct drm_i915_private *i915);
28
+
bool intel_panel_use_ssc(struct intel_display *display);
29
29
const struct drm_display_mode *
30
30
intel_panel_preferred_fixed_mode(struct intel_connector *connector);
31
31
const struct drm_display_mode *
···
42
42
enum drm_mode_status
43
43
intel_panel_mode_valid(struct intel_connector *connector,
44
44
const struct drm_display_mode *mode);
45
-
int intel_panel_fitting(struct intel_crtc_state *crtc_state,
46
-
const struct drm_connector_state *conn_state);
47
45
int intel_panel_compute_config(struct intel_connector *connector,
48
46
struct drm_display_mode *adjusted_mode);
49
47
void intel_panel_add_edid_fixed_modes(struct intel_connector *connector,
+30
-26
drivers/gpu/drm/i915/display/intel_pch_display.c
+30
-26
drivers/gpu/drm/i915/display/intel_pch_display.c
···
39
39
enum pipe pipe, enum port port,
40
40
i915_reg_t dp_reg)
41
41
{
42
+
struct intel_display *display = &dev_priv->display;
42
43
enum pipe port_pipe;
43
44
bool state;
44
45
45
46
state = g4x_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
46
47
47
-
I915_STATE_WARN(dev_priv, state && port_pipe == pipe,
48
-
"PCH DP %c enabled on transcoder %c, should be disabled\n",
49
-
port_name(port), pipe_name(pipe));
48
+
INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe,
49
+
"PCH DP %c enabled on transcoder %c, should be disabled\n",
50
+
port_name(port), pipe_name(pipe));
50
51
51
-
I915_STATE_WARN(dev_priv,
52
-
HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
53
-
"IBX PCH DP %c still using transcoder B\n",
54
-
port_name(port));
52
+
INTEL_DISPLAY_STATE_WARN(display,
53
+
HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
54
+
"IBX PCH DP %c still using transcoder B\n",
55
+
port_name(port));
55
56
}
56
57
57
58
static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
58
59
enum pipe pipe, enum port port,
59
60
i915_reg_t hdmi_reg)
60
61
{
62
+
struct intel_display *display = &dev_priv->display;
61
63
enum pipe port_pipe;
62
64
bool state;
63
65
64
66
state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
65
67
66
-
I915_STATE_WARN(dev_priv, state && port_pipe == pipe,
67
-
"PCH HDMI %c enabled on transcoder %c, should be disabled\n",
68
-
port_name(port), pipe_name(pipe));
68
+
INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe,
69
+
"PCH HDMI %c enabled on transcoder %c, should be disabled\n",
70
+
port_name(port), pipe_name(pipe));
69
71
70
-
I915_STATE_WARN(dev_priv,
71
-
HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
72
-
"IBX PCH HDMI %c still using transcoder B\n",
73
-
port_name(port));
72
+
INTEL_DISPLAY_STATE_WARN(display,
73
+
HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
74
+
"IBX PCH HDMI %c still using transcoder B\n",
75
+
port_name(port));
74
76
}
75
77
76
78
static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
77
79
enum pipe pipe)
78
80
{
81
+
struct intel_display *display = &dev_priv->display;
79
82
enum pipe port_pipe;
80
83
81
84
assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
82
85
assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);
83
86
assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
84
87
85
-
I915_STATE_WARN(dev_priv,
86
-
intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) && port_pipe == pipe,
87
-
"PCH VGA enabled on transcoder %c, should be disabled\n",
88
-
pipe_name(pipe));
88
+
INTEL_DISPLAY_STATE_WARN(display,
89
+
intel_crt_port_enabled(display, PCH_ADPA, &port_pipe) && port_pipe == pipe,
90
+
"PCH VGA enabled on transcoder %c, should be disabled\n",
91
+
pipe_name(pipe));
89
92
90
-
I915_STATE_WARN(dev_priv,
91
-
intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) && port_pipe == pipe,
92
-
"PCH LVDS enabled on transcoder %c, should be disabled\n",
93
-
pipe_name(pipe));
93
+
INTEL_DISPLAY_STATE_WARN(display,
94
+
intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) && port_pipe == pipe,
95
+
"PCH LVDS enabled on transcoder %c, should be disabled\n",
96
+
pipe_name(pipe));
94
97
95
98
/* PCH SDVOB multiplex with HDMIB */
96
99
assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
···
104
101
static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
105
102
enum pipe pipe)
106
103
{
104
+
struct intel_display *display = &dev_priv->display;
107
105
u32 val;
108
106
bool enabled;
109
107
110
-
val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe));
108
+
val = intel_de_read(display, PCH_TRANSCONF(pipe));
111
109
enabled = !!(val & TRANS_ENABLE);
112
-
I915_STATE_WARN(dev_priv, enabled,
113
-
"transcoder assertion failed, should be off on pipe %c but is still active\n",
114
-
pipe_name(pipe));
110
+
INTEL_DISPLAY_STATE_WARN(display, enabled,
111
+
"transcoder assertion failed, should be off on pipe %c but is still active\n",
112
+
pipe_name(pipe));
115
113
}
116
114
117
115
static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
+5
-4
drivers/gpu/drm/i915/display/intel_pch_refclk.c
+5
-4
drivers/gpu/drm/i915/display/intel_pch_refclk.c
···
491
491
492
492
static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
493
493
{
494
+
struct intel_display *display = &dev_priv->display;
494
495
struct intel_encoder *encoder;
495
496
struct intel_shared_dpll *pll;
496
497
int i;
···
573
572
if (has_panel) {
574
573
final |= DREF_SSC_SOURCE_ENABLE;
575
574
576
-
if (intel_panel_use_ssc(dev_priv) && can_ssc)
575
+
if (intel_panel_use_ssc(display) && can_ssc)
577
576
final |= DREF_SSC1_ENABLE;
578
577
579
578
if (has_cpu_edp) {
580
-
if (intel_panel_use_ssc(dev_priv) && can_ssc)
579
+
if (intel_panel_use_ssc(display) && can_ssc)
581
580
final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
582
581
else
583
582
final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
···
605
604
val |= DREF_SSC_SOURCE_ENABLE;
606
605
607
606
/* SSC must be turned on before enabling the CPU output */
608
-
if (intel_panel_use_ssc(dev_priv) && can_ssc) {
607
+
if (intel_panel_use_ssc(display) && can_ssc) {
609
608
drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n");
610
609
val |= DREF_SSC1_ENABLE;
611
610
} else {
···
621
620
622
621
/* Enable CPU source on CPU attached eDP */
623
622
if (has_cpu_edp) {
624
-
if (intel_panel_use_ssc(dev_priv) && can_ssc) {
623
+
if (intel_panel_use_ssc(display) && can_ssc) {
625
624
drm_dbg_kms(&dev_priv->drm,
626
625
"Using SSC on eDP\n");
627
626
val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
+554
drivers/gpu/drm/i915/display/intel_pfit.c
+554
drivers/gpu/drm/i915/display/intel_pfit.c
···
1
+
// SPDX-License-Identifier: MIT
2
+
/*
3
+
* Copyright © 2024 Intel Corporation
4
+
*/
5
+
6
+
#include "i915_drv.h"
7
+
#include "i915_reg.h"
8
+
#include "intel_display_core.h"
9
+
#include "intel_display_driver.h"
10
+
#include "intel_display_types.h"
11
+
#include "intel_lvds_regs.h"
12
+
#include "intel_pfit.h"
13
+
14
+
static int intel_pch_pfit_check_dst_window(const struct intel_crtc_state *crtc_state)
15
+
{
16
+
struct intel_display *display = to_intel_display(crtc_state);
17
+
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
18
+
const struct drm_display_mode *adjusted_mode =
19
+
&crtc_state->hw.adjusted_mode;
20
+
const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
21
+
int width = drm_rect_width(dst);
22
+
int height = drm_rect_height(dst);
23
+
int x = dst->x1;
24
+
int y = dst->y1;
25
+
26
+
if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE &&
27
+
(y & 1 || height & 1)) {
28
+
drm_dbg_kms(display->drm,
29
+
"[CRTC:%d:%s] pfit window (" DRM_RECT_FMT ") misaligned for interlaced output\n",
30
+
crtc->base.base.id, crtc->base.name, DRM_RECT_ARG(dst));
31
+
return -EINVAL;
32
+
}
33
+
34
+
/*
35
+
* "Restriction : When pipe scaling is enabled, the scaled
36
+
* output must equal the pipe active area, so Pipe active
37
+
* size = (2 * PF window position) + PF window size."
38
+
*
39
+
* The vertical direction seems more forgiving than the
40
+
* horizontal direction, but still has some issues so
41
+
* let's follow the same hard rule for both.
42
+
*/
43
+
if (adjusted_mode->crtc_hdisplay != 2 * x + width ||
44
+
adjusted_mode->crtc_vdisplay != 2 * y + height) {
45
+
drm_dbg_kms(display->drm,
46
+
"[CRTC:%d:%s] pfit window (" DRM_RECT_FMT ") not centered\n",
47
+
crtc->base.base.id, crtc->base.name, DRM_RECT_ARG(dst));
48
+
return -EINVAL;
49
+
}
50
+
51
+
/*
52
+
* "Restriction : The X position must not be programmed
53
+
* to be 1 (28:16=0 0000 0000 0001b)."
54
+
*/
55
+
if (x == 1) {
56
+
drm_dbg_kms(display->drm,
57
+
"[CRTC:%d:%s] pfit window (" DRM_RECT_FMT ") badly positioned\n",
58
+
crtc->base.base.id, crtc->base.name, DRM_RECT_ARG(dst));
59
+
return -EINVAL;
60
+
}
61
+
62
+
return 0;
63
+
}
64
+
65
+
static int intel_pch_pfit_check_src_size(const struct intel_crtc_state *crtc_state)
66
+
{
67
+
struct intel_display *display = to_intel_display(crtc_state);
68
+
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
69
+
int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
70
+
int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
71
+
int max_src_w, max_src_h;
72
+
73
+
if (DISPLAY_VER(display) >= 8) {
74
+
max_src_w = 4096;
75
+
max_src_h = 4096;
76
+
} else if (DISPLAY_VER(display) >= 7) {
77
+
/*
78
+
* PF0 7x5 capable
79
+
* PF1 3x3 capable (could be switched to 7x5
80
+
* mode on HSW when PF2 unused)
81
+
* PF2 3x3 capable
82
+
*
83
+
* This assumes we use a 1:1 mapping between pipe and PF.
84
+
*/
85
+
max_src_w = crtc->pipe == PIPE_A ? 4096 : 2048;
86
+
max_src_h = 4096;
87
+
} else {
88
+
max_src_w = 4096;
89
+
max_src_h = 4096;
90
+
}
91
+
92
+
if (pipe_src_w > max_src_w || pipe_src_h > max_src_h) {
93
+
drm_dbg_kms(display->drm,
94
+
"[CRTC:%d:%s] source size (%dx%d) exceeds pfit max (%dx%d)\n",
95
+
crtc->base.base.id, crtc->base.name,
96
+
pipe_src_w, pipe_src_h, max_src_w, max_src_h);
97
+
return -EINVAL;
98
+
}
99
+
100
+
return 0;
101
+
}
102
+
103
+
static int intel_pch_pfit_check_scaling(const struct intel_crtc_state *crtc_state)
104
+
{
105
+
struct intel_display *display = to_intel_display(crtc_state);
106
+
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
107
+
const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
108
+
int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
109
+
int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
110
+
int hscale, vscale, max_scale = 0x12000; /* 1.125 */
111
+
struct drm_rect src;
112
+
113
+
drm_rect_init(&src, 0, 0, pipe_src_w << 16, pipe_src_h << 16);
114
+
115
+
hscale = drm_rect_calc_hscale(&src, dst, 0, max_scale);
116
+
if (hscale < 0) {
117
+
drm_dbg_kms(display->drm,
118
+
"[CRTC:%d:%s] pfit horizontal downscaling (%d->%d) exceeds max (0x%x)\n",
119
+
crtc->base.base.id, crtc->base.name,
120
+
pipe_src_w, drm_rect_width(dst),
121
+
max_scale);
122
+
return hscale;
123
+
}
124
+
125
+
vscale = drm_rect_calc_vscale(&src, dst, 0, max_scale);
126
+
if (vscale < 0) {
127
+
drm_dbg_kms(display->drm,
128
+
"[CRTC:%d:%s] pfit vertical downscaling (%d->%d) exceeds max (0x%x)\n",
129
+
crtc->base.base.id, crtc->base.name,
130
+
pipe_src_h, drm_rect_height(dst),
131
+
max_scale);
132
+
return vscale;
133
+
}
134
+
135
+
return 0;
136
+
}
137
+
138
+
static int intel_pch_pfit_check_timings(const struct intel_crtc_state *crtc_state)
139
+
{
140
+
struct intel_display *display = to_intel_display(crtc_state);
141
+
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
142
+
const struct drm_display_mode *adjusted_mode =
143
+
&crtc_state->hw.adjusted_mode;
144
+
145
+
if (adjusted_mode->crtc_vdisplay < 7) {
146
+
drm_dbg_kms(display->drm,
147
+
"[CRTC:%d:%s] vertical active (%d) below minimum (%d) for pfit\n",
148
+
crtc->base.base.id, crtc->base.name,
149
+
adjusted_mode->crtc_vdisplay, 7);
150
+
return -EINVAL;
151
+
}
152
+
153
+
return 0;
154
+
}
155
+
156
+
static int intel_pch_pfit_check_cloning(const struct intel_crtc_state *crtc_state)
157
+
{
158
+
struct intel_display *display = to_intel_display(crtc_state);
159
+
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
160
+
161
+
/*
162
+
* The panel fitter is in the pipe and thus would affect every
163
+
* cloned output. The relevant properties (scaling mode, TV
164
+
* margins) are per-connector so we'd have to make sure each
165
+
* output sets them up identically. Seems like a very niche use
166
+
* case so let's just reject cloning entirely when pfit is used.
167
+
*/
168
+
if (crtc_state->uapi.encoder_mask &&
169
+
!is_power_of_2(crtc_state->uapi.encoder_mask)) {
170
+
drm_dbg_kms(display->drm,
171
+
"[CRTC:%d:%s] no pfit when cloning\n",
172
+
crtc->base.base.id, crtc->base.name);
173
+
return -EINVAL;
174
+
}
175
+
176
+
return 0;
177
+
}
178
+
179
+
/* adjusted_mode has been preset to be the panel's fixed mode */
180
+
static int pch_panel_fitting(struct intel_crtc_state *crtc_state,
181
+
const struct drm_connector_state *conn_state)
182
+
{
183
+
struct intel_display *display = to_intel_display(crtc_state);
184
+
const struct drm_display_mode *adjusted_mode =
185
+
&crtc_state->hw.adjusted_mode;
186
+
int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
187
+
int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
188
+
int ret, x, y, width, height;
189
+
190
+
/* Native modes don't need fitting */
191
+
if (adjusted_mode->crtc_hdisplay == pipe_src_w &&
192
+
adjusted_mode->crtc_vdisplay == pipe_src_h &&
193
+
crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
194
+
return 0;
195
+
196
+
switch (conn_state->scaling_mode) {
197
+
case DRM_MODE_SCALE_CENTER:
198
+
width = pipe_src_w;
199
+
height = pipe_src_h;
200
+
x = (adjusted_mode->crtc_hdisplay - width + 1)/2;
201
+
y = (adjusted_mode->crtc_vdisplay - height + 1)/2;
202
+
break;
203
+
204
+
case DRM_MODE_SCALE_ASPECT:
205
+
/* Scale but preserve the aspect ratio */
206
+
{
207
+
u32 scaled_width = adjusted_mode->crtc_hdisplay * pipe_src_h;
208
+
u32 scaled_height = pipe_src_w * adjusted_mode->crtc_vdisplay;
209
+
210
+
if (scaled_width > scaled_height) { /* pillar */
211
+
width = scaled_height / pipe_src_h;
212
+
if (width & 1)
213
+
width++;
214
+
x = (adjusted_mode->crtc_hdisplay - width + 1) / 2;
215
+
y = 0;
216
+
height = adjusted_mode->crtc_vdisplay;
217
+
} else if (scaled_width < scaled_height) { /* letter */
218
+
height = scaled_width / pipe_src_w;
219
+
if (height & 1)
220
+
height++;
221
+
y = (adjusted_mode->crtc_vdisplay - height + 1) / 2;
222
+
x = 0;
223
+
width = adjusted_mode->crtc_hdisplay;
224
+
} else {
225
+
x = y = 0;
226
+
width = adjusted_mode->crtc_hdisplay;
227
+
height = adjusted_mode->crtc_vdisplay;
228
+
}
229
+
}
230
+
break;
231
+
232
+
case DRM_MODE_SCALE_NONE:
233
+
WARN_ON(adjusted_mode->crtc_hdisplay != pipe_src_w);
234
+
WARN_ON(adjusted_mode->crtc_vdisplay != pipe_src_h);
235
+
fallthrough;
236
+
case DRM_MODE_SCALE_FULLSCREEN:
237
+
x = y = 0;
238
+
width = adjusted_mode->crtc_hdisplay;
239
+
height = adjusted_mode->crtc_vdisplay;
240
+
break;
241
+
242
+
default:
243
+
MISSING_CASE(conn_state->scaling_mode);
244
+
return -EINVAL;
245
+
}
246
+
247
+
drm_rect_init(&crtc_state->pch_pfit.dst,
248
+
x, y, width, height);
249
+
crtc_state->pch_pfit.enabled = true;
250
+
251
+
/*
252
+
* SKL+ have unified scalers for pipes/planes so the
253
+
* checks are done in a single place for all scalers.
254
+
*/
255
+
if (DISPLAY_VER(display) >= 9)
256
+
return 0;
257
+
258
+
ret = intel_pch_pfit_check_dst_window(crtc_state);
259
+
if (ret)
260
+
return ret;
261
+
262
+
ret = intel_pch_pfit_check_src_size(crtc_state);
263
+
if (ret)
264
+
return ret;
265
+
266
+
ret = intel_pch_pfit_check_scaling(crtc_state);
267
+
if (ret)
268
+
return ret;
269
+
270
+
ret = intel_pch_pfit_check_timings(crtc_state);
271
+
if (ret)
272
+
return ret;
273
+
274
+
ret = intel_pch_pfit_check_cloning(crtc_state);
275
+
if (ret)
276
+
return ret;
277
+
278
+
return 0;
279
+
}
280
+
281
+
static void
282
+
centre_horizontally(struct drm_display_mode *adjusted_mode,
283
+
int width)
284
+
{
285
+
u32 border, sync_pos, blank_width, sync_width;
286
+
287
+
/* keep the hsync and hblank widths constant */
288
+
sync_width = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
289
+
blank_width = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start;
290
+
sync_pos = (blank_width - sync_width + 1) / 2;
291
+
292
+
border = (adjusted_mode->crtc_hdisplay - width + 1) / 2;
293
+
border += border & 1; /* make the border even */
294
+
295
+
adjusted_mode->crtc_hdisplay = width;
296
+
adjusted_mode->crtc_hblank_start = width + border;
297
+
adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_start + blank_width;
298
+
299
+
adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hblank_start + sync_pos;
300
+
adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + sync_width;
301
+
}
302
+
303
+
static void
304
+
centre_vertically(struct drm_display_mode *adjusted_mode,
305
+
int height)
306
+
{
307
+
u32 border, sync_pos, blank_width, sync_width;
308
+
309
+
/* keep the vsync and vblank widths constant */
310
+
sync_width = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
311
+
blank_width = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start;
312
+
sync_pos = (blank_width - sync_width + 1) / 2;
313
+
314
+
border = (adjusted_mode->crtc_vdisplay - height + 1) / 2;
315
+
316
+
adjusted_mode->crtc_vdisplay = height;
317
+
adjusted_mode->crtc_vblank_start = height + border;
318
+
adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vblank_start + blank_width;
319
+
320
+
adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vblank_start + sync_pos;
321
+
adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + sync_width;
322
+
}
323
+
324
+
static u32 panel_fitter_scaling(u32 source, u32 target)
325
+
{
326
+
/*
327
+
* Floating point operation is not supported. So the FACTOR
328
+
* is defined, which can avoid the floating point computation
329
+
* when calculating the panel ratio.
330
+
*/
331
+
#define ACCURACY 12
332
+
#define FACTOR (1 << ACCURACY)
333
+
u32 ratio = source * FACTOR / target;
334
+
return (FACTOR * ratio + FACTOR/2) / FACTOR;
335
+
}
336
+
337
+
static void i965_scale_aspect(struct intel_crtc_state *crtc_state,
338
+
u32 *pfit_control)
339
+
{
340
+
const struct drm_display_mode *adjusted_mode =
341
+
&crtc_state->hw.adjusted_mode;
342
+
int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
343
+
int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
344
+
u32 scaled_width = adjusted_mode->crtc_hdisplay * pipe_src_h;
345
+
u32 scaled_height = pipe_src_w * adjusted_mode->crtc_vdisplay;
346
+
347
+
/* 965+ is easy, it does everything in hw */
348
+
if (scaled_width > scaled_height)
349
+
*pfit_control |= PFIT_ENABLE |
350
+
PFIT_SCALING_PILLAR;
351
+
else if (scaled_width < scaled_height)
352
+
*pfit_control |= PFIT_ENABLE |
353
+
PFIT_SCALING_LETTER;
354
+
else if (adjusted_mode->crtc_hdisplay != pipe_src_w)
355
+
*pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
356
+
}
357
+
358
+
static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
359
+
u32 *pfit_control, u32 *pfit_pgm_ratios,
360
+
u32 *border)
361
+
{
362
+
struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
363
+
int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
364
+
int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
365
+
u32 scaled_width = adjusted_mode->crtc_hdisplay * pipe_src_h;
366
+
u32 scaled_height = pipe_src_w * adjusted_mode->crtc_vdisplay;
367
+
u32 bits;
368
+
369
+
/*
370
+
* For earlier chips we have to calculate the scaling
371
+
* ratio by hand and program it into the
372
+
* PFIT_PGM_RATIO register
373
+
*/
374
+
if (scaled_width > scaled_height) { /* pillar */
375
+
centre_horizontally(adjusted_mode,
376
+
scaled_height / pipe_src_h);
377
+
378
+
*border = LVDS_BORDER_ENABLE;
379
+
if (pipe_src_h != adjusted_mode->crtc_vdisplay) {
380
+
bits = panel_fitter_scaling(pipe_src_h,
381
+
adjusted_mode->crtc_vdisplay);
382
+
383
+
*pfit_pgm_ratios |= (PFIT_HORIZ_SCALE(bits) |
384
+
PFIT_VERT_SCALE(bits));
385
+
*pfit_control |= (PFIT_ENABLE |
386
+
PFIT_VERT_INTERP_BILINEAR |
387
+
PFIT_HORIZ_INTERP_BILINEAR);
388
+
}
389
+
} else if (scaled_width < scaled_height) { /* letter */
390
+
centre_vertically(adjusted_mode,
391
+
scaled_width / pipe_src_w);
392
+
393
+
*border = LVDS_BORDER_ENABLE;
394
+
if (pipe_src_w != adjusted_mode->crtc_hdisplay) {
395
+
bits = panel_fitter_scaling(pipe_src_w,
396
+
adjusted_mode->crtc_hdisplay);
397
+
398
+
*pfit_pgm_ratios |= (PFIT_HORIZ_SCALE(bits) |
399
+
PFIT_VERT_SCALE(bits));
400
+
*pfit_control |= (PFIT_ENABLE |
401
+
PFIT_VERT_INTERP_BILINEAR |
402
+
PFIT_HORIZ_INTERP_BILINEAR);
403
+
}
404
+
} else {
405
+
/* Aspects match, Let hw scale both directions */
406
+
*pfit_control |= (PFIT_ENABLE |
407
+
PFIT_VERT_AUTO_SCALE |
408
+
PFIT_HORIZ_AUTO_SCALE |
409
+
PFIT_VERT_INTERP_BILINEAR |
410
+
PFIT_HORIZ_INTERP_BILINEAR);
411
+
}
412
+
}
413
+
414
+
static int intel_gmch_pfit_check_timings(const struct intel_crtc_state *crtc_state)
415
+
{
416
+
struct intel_display *display = to_intel_display(crtc_state);
417
+
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
418
+
const struct drm_display_mode *adjusted_mode =
419
+
&crtc_state->hw.adjusted_mode;
420
+
int min;
421
+
422
+
if (DISPLAY_VER(display) >= 4)
423
+
min = 3;
424
+
else
425
+
min = 2;
426
+
427
+
if (adjusted_mode->crtc_hdisplay < min) {
428
+
drm_dbg_kms(display->drm,
429
+
"[CRTC:%d:%s] horizontal active (%d) below minimum (%d) for pfit\n",
430
+
crtc->base.base.id, crtc->base.name,
431
+
adjusted_mode->crtc_hdisplay, min);
432
+
return -EINVAL;
433
+
}
434
+
435
+
if (adjusted_mode->crtc_vdisplay < min) {
436
+
drm_dbg_kms(display->drm,
437
+
"[CRTC:%d:%s] vertical active (%d) below minimum (%d) for pfit\n",
438
+
crtc->base.base.id, crtc->base.name,
439
+
adjusted_mode->crtc_vdisplay, min);
440
+
return -EINVAL;
441
+
}
442
+
443
+
return 0;
444
+
}
445
+
446
+
static int gmch_panel_fitting(struct intel_crtc_state *crtc_state,
447
+
const struct drm_connector_state *conn_state)
448
+
{
449
+
struct intel_display *display = to_intel_display(crtc_state);
450
+
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
451
+
u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
452
+
struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
453
+
int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
454
+
int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
455
+
456
+
/* Native modes don't need fitting */
457
+
if (adjusted_mode->crtc_hdisplay == pipe_src_w &&
458
+
adjusted_mode->crtc_vdisplay == pipe_src_h)
459
+
goto out;
460
+
461
+
/*
462
+
* TODO: implement downscaling for i965+. Need to account
463
+
* for downscaling in intel_crtc_compute_pixel_rate().
464
+
*/
465
+
if (adjusted_mode->crtc_hdisplay < pipe_src_w) {
466
+
drm_dbg_kms(display->drm,
467
+
"[CRTC:%d:%s] pfit horizontal downscaling (%d->%d) not supported\n",
468
+
crtc->base.base.id, crtc->base.name,
469
+
pipe_src_w, adjusted_mode->crtc_hdisplay);
470
+
return -EINVAL;
471
+
}
472
+
if (adjusted_mode->crtc_vdisplay < pipe_src_h) {
473
+
drm_dbg_kms(display->drm,
474
+
"[CRTC:%d:%s] pfit vertical downscaling (%d->%d) not supported\n",
475
+
crtc->base.base.id, crtc->base.name,
476
+
pipe_src_h, adjusted_mode->crtc_vdisplay);
477
+
return -EINVAL;
478
+
}
479
+
480
+
switch (conn_state->scaling_mode) {
481
+
case DRM_MODE_SCALE_CENTER:
482
+
/*
483
+
* For centered modes, we have to calculate border widths &
484
+
* heights and modify the values programmed into the CRTC.
485
+
*/
486
+
centre_horizontally(adjusted_mode, pipe_src_w);
487
+
centre_vertically(adjusted_mode, pipe_src_h);
488
+
border = LVDS_BORDER_ENABLE;
489
+
break;
490
+
case DRM_MODE_SCALE_ASPECT:
491
+
/* Scale but preserve the aspect ratio */
492
+
if (DISPLAY_VER(display) >= 4)
493
+
i965_scale_aspect(crtc_state, &pfit_control);
494
+
else
495
+
i9xx_scale_aspect(crtc_state, &pfit_control,
496
+
&pfit_pgm_ratios, &border);
497
+
break;
498
+
case DRM_MODE_SCALE_FULLSCREEN:
499
+
/*
500
+
* Full scaling, even if it changes the aspect ratio.
501
+
* Fortunately this is all done for us in hw.
502
+
*/
503
+
if (pipe_src_h != adjusted_mode->crtc_vdisplay ||
504
+
pipe_src_w != adjusted_mode->crtc_hdisplay) {
505
+
pfit_control |= PFIT_ENABLE;
506
+
if (DISPLAY_VER(display) >= 4)
507
+
pfit_control |= PFIT_SCALING_AUTO;
508
+
else
509
+
pfit_control |= (PFIT_VERT_AUTO_SCALE |
510
+
PFIT_VERT_INTERP_BILINEAR |
511
+
PFIT_HORIZ_AUTO_SCALE |
512
+
PFIT_HORIZ_INTERP_BILINEAR);
513
+
}
514
+
break;
515
+
default:
516
+
MISSING_CASE(conn_state->scaling_mode);
517
+
return -EINVAL;
518
+
}
519
+
520
+
/* 965+ wants fuzzy fitting */
521
+
/* FIXME: handle multiple panels by failing gracefully */
522
+
if (DISPLAY_VER(display) >= 4)
523
+
pfit_control |= PFIT_PIPE(crtc->pipe) | PFIT_FILTER_FUZZY;
524
+
525
+
out:
526
+
if ((pfit_control & PFIT_ENABLE) == 0) {
527
+
pfit_control = 0;
528
+
pfit_pgm_ratios = 0;
529
+
}
530
+
531
+
/* Make sure pre-965 set dither correctly for 18bpp panels. */
532
+
if (DISPLAY_VER(display) < 4 && crtc_state->pipe_bpp == 18)
533
+
pfit_control |= PFIT_PANEL_8TO6_DITHER_ENABLE;
534
+
535
+
crtc_state->gmch_pfit.control = pfit_control;
536
+
crtc_state->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
537
+
crtc_state->gmch_pfit.lvds_border_bits = border;
538
+
539
+
if ((pfit_control & PFIT_ENABLE) == 0)
540
+
return 0;
541
+
542
+
return intel_gmch_pfit_check_timings(crtc_state);
543
+
}
544
+
545
+
int intel_panel_fitting(struct intel_crtc_state *crtc_state,
546
+
const struct drm_connector_state *conn_state)
547
+
{
548
+
struct intel_display *display = to_intel_display(crtc_state);
549
+
550
+
if (HAS_GMCH(display))
551
+
return gmch_panel_fitting(crtc_state, conn_state);
552
+
else
553
+
return pch_panel_fitting(crtc_state, conn_state);
554
+
}
+15
drivers/gpu/drm/i915/display/intel_pfit.h
+15
drivers/gpu/drm/i915/display/intel_pfit.h
···
1
+
/* SPDX-License-Identifier: MIT */
2
+
/*
3
+
* Copyright © 2024 Intel Corporation
4
+
*/
5
+
6
+
#ifndef __INTEL_PFIT_H__
7
+
#define __INTEL_PFIT_H__
8
+
9
+
struct drm_connector_state;
10
+
struct intel_crtc_state;
11
+
12
+
int intel_panel_fitting(struct intel_crtc_state *crtc_state,
13
+
const struct drm_connector_state *conn_state);
14
+
15
+
#endif /* __INTEL_PFIT_H__ */
+49
-22
drivers/gpu/drm/i915/display/intel_pmdemand.c
+49
-22
drivers/gpu/drm/i915/display/intel_pmdemand.c
···
92
92
&pmdemand_state->base,
93
93
&intel_pmdemand_funcs);
94
94
95
-
if (IS_DISPLAY_VER_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0))
95
+
if (IS_DISPLAY_VERx100_STEP(i915, 1400, STEP_A0, STEP_C0))
96
96
/* Wa_14016740474 */
97
97
intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);
98
98
···
258
258
259
259
static bool intel_pmdemand_needs_update(struct intel_atomic_state *state)
260
260
{
261
+
struct intel_display *display = to_intel_display(state);
261
262
const struct intel_bw_state *new_bw_state, *old_bw_state;
262
263
const struct intel_cdclk_state *new_cdclk_state, *old_cdclk_state;
263
264
const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
···
275
274
new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
276
275
old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
277
276
if (new_dbuf_state &&
278
-
(new_dbuf_state->active_pipes !=
279
-
old_dbuf_state->active_pipes ||
280
-
new_dbuf_state->enabled_slices !=
281
-
old_dbuf_state->enabled_slices))
277
+
new_dbuf_state->active_pipes != old_dbuf_state->active_pipes)
282
278
return true;
279
+
280
+
if (DISPLAY_VER(display) < 30) {
281
+
if (new_dbuf_state &&
282
+
new_dbuf_state->enabled_slices !=
283
+
old_dbuf_state->enabled_slices)
284
+
return true;
285
+
}
283
286
284
287
new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
285
288
old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
···
332
327
if (IS_ERR(new_dbuf_state))
333
328
return PTR_ERR(new_dbuf_state);
334
329
335
-
new_pmdemand_state->params.active_pipes =
336
-
min_t(u8, hweight8(new_dbuf_state->active_pipes), 3);
337
-
new_pmdemand_state->params.active_dbufs =
338
-
min_t(u8, hweight8(new_dbuf_state->enabled_slices), 3);
330
+
if (DISPLAY_VER(i915) < 30) {
331
+
new_pmdemand_state->params.active_dbufs =
332
+
min_t(u8, hweight8(new_dbuf_state->enabled_slices), 3);
333
+
new_pmdemand_state->params.active_pipes =
334
+
min_t(u8, hweight8(new_dbuf_state->active_pipes), 3);
335
+
} else {
336
+
new_pmdemand_state->params.active_pipes =
337
+
min_t(u8, hweight8(new_dbuf_state->active_pipes), INTEL_NUM_PIPES(i915));
338
+
}
339
339
340
340
new_cdclk_state = intel_atomic_get_cdclk_state(state);
341
341
if (IS_ERR(new_cdclk_state))
···
405
395
406
396
reg2 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1));
407
397
408
-
/* Set 1*/
409
398
pmdemand_state->params.qclk_gv_bw =
410
399
REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, reg1);
411
400
pmdemand_state->params.voltage_index =
412
401
REG_FIELD_GET(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, reg1);
413
402
pmdemand_state->params.qclk_gv_index =
414
403
REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, reg1);
415
-
pmdemand_state->params.active_pipes =
416
-
REG_FIELD_GET(XELPDP_PMDEMAND_PIPES_MASK, reg1);
417
-
pmdemand_state->params.active_dbufs =
418
-
REG_FIELD_GET(XELPDP_PMDEMAND_DBUFS_MASK, reg1);
419
404
pmdemand_state->params.active_phys =
420
405
REG_FIELD_GET(XELPDP_PMDEMAND_PHYS_MASK, reg1);
421
406
422
-
/* Set 2*/
423
407
pmdemand_state->params.cdclk_freq_mhz =
424
408
REG_FIELD_GET(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, reg2);
425
409
pmdemand_state->params.ddiclk_max =
426
410
REG_FIELD_GET(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, reg2);
427
-
pmdemand_state->params.scalers =
428
-
REG_FIELD_GET(XELPDP_PMDEMAND_SCALERS_MASK, reg2);
411
+
412
+
if (DISPLAY_VER(i915) >= 30) {
413
+
pmdemand_state->params.active_pipes =
414
+
REG_FIELD_GET(XE3_PMDEMAND_PIPES_MASK, reg1);
415
+
} else {
416
+
pmdemand_state->params.active_pipes =
417
+
REG_FIELD_GET(XELPDP_PMDEMAND_PIPES_MASK, reg1);
418
+
pmdemand_state->params.active_dbufs =
419
+
REG_FIELD_GET(XELPDP_PMDEMAND_DBUFS_MASK, reg1);
420
+
421
+
pmdemand_state->params.scalers =
422
+
REG_FIELD_GET(XELPDP_PMDEMAND_SCALERS_MASK, reg2);
423
+
}
429
424
430
425
unlock:
431
426
mutex_unlock(&i915->display.pmdemand.lock);
···
457
442
{
458
443
u32 dbufs = min_t(u32, hweight8(dbuf_slices), 3);
459
444
445
+
/* PM Demand only tracks active dbufs on pre-Xe3 platforms */
446
+
if (DISPLAY_VER(i915) >= 30)
447
+
return;
448
+
460
449
mutex_lock(&i915->display.pmdemand.lock);
461
450
if (drm_WARN_ON(&i915->drm,
462
451
!intel_pmdemand_check_prev_transaction(i915)))
···
479
460
}
480
461
481
462
static void
482
-
intel_pmdemand_update_params(const struct intel_pmdemand_state *new,
463
+
intel_pmdemand_update_params(struct intel_display *display,
464
+
const struct intel_pmdemand_state *new,
483
465
const struct intel_pmdemand_state *old,
484
466
u32 *reg1, u32 *reg2, bool serialized)
485
467
{
···
515
495
update_reg(reg1, qclk_gv_bw, XELPDP_PMDEMAND_QCLK_GV_BW_MASK);
516
496
update_reg(reg1, voltage_index, XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK);
517
497
update_reg(reg1, qclk_gv_index, XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK);
518
-
update_reg(reg1, active_pipes, XELPDP_PMDEMAND_PIPES_MASK);
519
-
update_reg(reg1, active_dbufs, XELPDP_PMDEMAND_DBUFS_MASK);
520
498
update_reg(reg1, active_phys, XELPDP_PMDEMAND_PHYS_MASK);
521
499
522
500
/* Set 2*/
523
501
update_reg(reg2, cdclk_freq_mhz, XELPDP_PMDEMAND_CDCLK_FREQ_MASK);
524
502
update_reg(reg2, ddiclk_max, XELPDP_PMDEMAND_DDICLK_FREQ_MASK);
525
-
update_reg(reg2, scalers, XELPDP_PMDEMAND_SCALERS_MASK);
526
503
update_reg(reg2, plls, XELPDP_PMDEMAND_PLLS_MASK);
504
+
505
+
if (DISPLAY_VER(display) >= 30) {
506
+
update_reg(reg1, active_pipes, XE3_PMDEMAND_PIPES_MASK);
507
+
} else {
508
+
update_reg(reg1, active_pipes, XELPDP_PMDEMAND_PIPES_MASK);
509
+
update_reg(reg1, active_dbufs, XELPDP_PMDEMAND_DBUFS_MASK);
510
+
511
+
update_reg(reg2, scalers, XELPDP_PMDEMAND_SCALERS_MASK);
512
+
}
527
513
528
514
#undef update_reg
529
515
}
···
540
514
const struct intel_pmdemand_state *old,
541
515
bool serialized)
542
516
{
517
+
struct intel_display *display = &i915->display;
543
518
bool changed = false;
544
519
u32 reg1, mod_reg1;
545
520
u32 reg2, mod_reg2;
···
556
529
reg2 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1));
557
530
mod_reg2 = reg2;
558
531
559
-
intel_pmdemand_update_params(new, old, &mod_reg1, &mod_reg2,
532
+
intel_pmdemand_update_params(display, new, old, &mod_reg1, &mod_reg2,
560
533
serialized);
561
534
562
535
if (reg1 != mod_reg1) {
+2
-2
drivers/gpu/drm/i915/display/intel_pmdemand.h
+2
-2
drivers/gpu/drm/i915/display/intel_pmdemand.h
···
20
20
u8 voltage_index;
21
21
u8 qclk_gv_index;
22
22
u8 active_pipes;
23
-
u8 active_dbufs;
23
+
u8 active_dbufs; /* pre-Xe3 only */
24
24
/* Total number of non type C active phys from active_phys_mask */
25
25
u8 active_phys;
26
26
u8 plls;
27
27
u16 cdclk_freq_mhz;
28
28
/* max from ddi_clocks[] */
29
29
u16 ddiclk_max;
30
-
u8 scalers;
30
+
u8 scalers; /* pre-Xe3 only */
31
31
};
32
32
33
33
struct intel_pmdemand_state {
+51
-44
drivers/gpu/drm/i915/display/intel_pps.c
+51
-44
drivers/gpu/drm/i915/display/intel_pps.c
···
29
29
static const char *pps_name(struct intel_dp *intel_dp)
30
30
{
31
31
struct intel_display *display = to_intel_display(intel_dp);
32
-
struct drm_i915_private *i915 = to_i915(display->drm);
33
32
struct intel_pps *pps = &intel_dp->pps;
34
33
35
-
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
34
+
if (display->platform.valleyview || display->platform.cherryview) {
36
35
switch (pps->vlv_pps_pipe) {
37
36
case INVALID_PIPE:
38
37
/*
···
121
122
DP |= DP_PORT_WIDTH(1);
122
123
DP |= DP_LINK_TRAIN_PAT_1;
123
124
124
-
if (IS_CHERRYVIEW(dev_priv))
125
+
if (display->platform.cherryview)
125
126
DP |= DP_PIPE_SEL_CHV(pipe);
126
127
else
127
128
DP |= DP_PIPE_SEL(pipe);
···
133
134
* So enable temporarily it if it's not already enabled.
134
135
*/
135
136
if (!pll_enabled) {
136
-
release_cl_override = IS_CHERRYVIEW(dev_priv) &&
137
+
release_cl_override = display->platform.cherryview &&
137
138
!chv_phy_powergate_ch(dev_priv, phy, ch, true);
138
139
139
140
if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(dev_priv))) {
···
355
356
{
356
357
struct drm_i915_private *i915 = to_i915(display->drm);
357
358
358
-
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
359
+
if (display->platform.valleyview || display->platform.cherryview)
359
360
return 2;
360
361
361
-
if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
362
+
if (display->platform.geminilake || display->platform.broxton)
362
363
return 2;
363
364
364
365
if (INTEL_PCH_TYPE(i915) >= PCH_MTL)
···
405
406
struct intel_display *display = to_intel_display(intel_dp);
406
407
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
407
408
struct intel_connector *connector = intel_dp->attached_connector;
408
-
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
409
409
410
410
lockdep_assert_held(&display->pps.mutex);
411
411
412
-
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
412
+
if (display->platform.valleyview || display->platform.cherryview) {
413
413
vlv_initial_power_sequencer_setup(intel_dp);
414
414
return true;
415
415
}
···
507
509
508
510
memset(regs, 0, sizeof(*regs));
509
511
510
-
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
512
+
if (display->platform.valleyview || display->platform.cherryview)
511
513
pps_idx = vlv_power_sequencer_pipe(intel_dp);
512
-
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
514
+
else if (display->platform.geminilake || display->platform.broxton)
513
515
pps_idx = bxt_power_sequencer_idx(intel_dp);
514
516
else
515
517
pps_idx = intel_dp->pps.pps_idx;
···
520
522
regs->pp_off = PP_OFF_DELAYS(display, pps_idx);
521
523
522
524
/* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
523
-
if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ||
525
+
if (display->platform.geminilake || display->platform.broxton ||
524
526
INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
525
527
regs->pp_div = INVALID_MMIO_REG;
526
528
else
···
550
552
static bool edp_have_panel_power(struct intel_dp *intel_dp)
551
553
{
552
554
struct intel_display *display = to_intel_display(intel_dp);
553
-
struct drm_i915_private *dev_priv = to_i915(display->drm);
554
555
555
556
lockdep_assert_held(&display->pps.mutex);
556
557
557
-
if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
558
+
if ((display->platform.valleyview || display->platform.cherryview) &&
558
559
intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)
559
560
return false;
560
561
···
563
566
static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
564
567
{
565
568
struct intel_display *display = to_intel_display(intel_dp);
566
-
struct drm_i915_private *dev_priv = to_i915(display->drm);
567
569
568
570
lockdep_assert_held(&display->pps.mutex);
569
571
570
-
if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
572
+
if ((display->platform.valleyview || display->platform.cherryview) &&
571
573
intel_dp->pps.vlv_pps_pipe == INVALID_PIPE)
572
574
return false;
573
575
···
797
801
}
798
802
799
803
/*
800
-
* Must be paired with intel_pps_off().
804
+
* Must be paired with intel_pps_vdd_off() or - to disable
805
+
* both VDD and panel power - intel_pps_off().
801
806
* Nested calls to these functions are not allowed since
802
807
* we drop the lock. Caller must use some higher level
803
808
* locking to prevent nested calls from other threads.
···
806
809
void intel_pps_vdd_on(struct intel_dp *intel_dp)
807
810
{
808
811
struct intel_display *display = to_intel_display(intel_dp);
809
-
struct drm_i915_private *i915 = to_i915(display->drm);
810
812
intel_wakeref_t wakeref;
811
813
bool vdd;
812
814
···
815
819
vdd = false;
816
820
with_intel_pps_lock(intel_dp, wakeref)
817
821
vdd = intel_pps_vdd_on_unlocked(intel_dp);
818
-
I915_STATE_WARN(i915, !vdd, "[ENCODER:%d:%s] %s VDD already requested on\n",
819
-
dp_to_dig_port(intel_dp)->base.base.base.id,
820
-
dp_to_dig_port(intel_dp)->base.base.name,
821
-
pps_name(intel_dp));
822
+
INTEL_DISPLAY_STATE_WARN(display, !vdd, "[ENCODER:%d:%s] %s VDD already requested on\n",
823
+
dp_to_dig_port(intel_dp)->base.base.base.id,
824
+
dp_to_dig_port(intel_dp)->base.base.name,
825
+
pps_name(intel_dp));
822
826
}
823
827
824
828
static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
···
857
861
intel_de_read(display, pp_stat_reg),
858
862
intel_de_read(display, pp_ctrl_reg));
859
863
860
-
if ((pp & PANEL_POWER_ON) == 0)
864
+
if ((pp & PANEL_POWER_ON) == 0) {
861
865
intel_dp->pps.panel_power_off_time = ktime_get_boottime();
866
+
intel_dp_invalidate_source_oui(intel_dp);
867
+
}
862
868
863
869
intel_display_power_put(dev_priv,
864
870
intel_aux_power_domain(dig_port),
···
927
929
void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync)
928
930
{
929
931
struct intel_display *display = to_intel_display(intel_dp);
930
-
struct drm_i915_private *dev_priv = to_i915(display->drm);
931
932
932
933
lockdep_assert_held(&display->pps.mutex);
933
934
934
935
if (!intel_dp_is_edp(intel_dp))
935
936
return;
936
937
937
-
I915_STATE_WARN(dev_priv, !intel_dp->pps.want_panel_vdd,
938
-
"[ENCODER:%d:%s] %s VDD not forced on",
939
-
dp_to_dig_port(intel_dp)->base.base.base.id,
940
-
dp_to_dig_port(intel_dp)->base.base.name,
941
-
pps_name(intel_dp));
938
+
INTEL_DISPLAY_STATE_WARN(display, !intel_dp->pps.want_panel_vdd,
939
+
"[ENCODER:%d:%s] %s VDD not forced on",
940
+
dp_to_dig_port(intel_dp)->base.base.base.id,
941
+
dp_to_dig_port(intel_dp)->base.base.name,
942
+
pps_name(intel_dp));
942
943
943
944
intel_dp->pps.want_panel_vdd = false;
944
945
···
947
950
edp_panel_vdd_schedule_off(intel_dp);
948
951
}
949
952
953
+
void intel_pps_vdd_off(struct intel_dp *intel_dp)
954
+
{
955
+
intel_wakeref_t wakeref;
956
+
957
+
if (!intel_dp_is_edp(intel_dp))
958
+
return;
959
+
960
+
with_intel_pps_lock(intel_dp, wakeref)
961
+
intel_pps_vdd_off_unlocked(intel_dp, false);
962
+
}
963
+
950
964
void intel_pps_on_unlocked(struct intel_dp *intel_dp)
951
965
{
952
966
struct intel_display *display = to_intel_display(intel_dp);
953
-
struct drm_i915_private *dev_priv = to_i915(display->drm);
954
967
u32 pp;
955
968
i915_reg_t pp_ctrl_reg;
956
969
···
985
978
986
979
pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
987
980
pp = ilk_get_pp_control(intel_dp);
988
-
if (IS_IRONLAKE(dev_priv)) {
981
+
if (display->platform.ironlake) {
989
982
/* ILK workaround: disable reset around power sequence */
990
983
pp &= ~PANEL_POWER_RESET;
991
984
intel_de_write(display, pp_ctrl_reg, pp);
···
1001
994
0, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
1002
995
1003
996
pp |= PANEL_POWER_ON;
1004
-
if (!IS_IRONLAKE(dev_priv))
997
+
if (!display->platform.ironlake)
1005
998
pp |= PANEL_POWER_RESET;
1006
999
1007
1000
intel_de_write(display, pp_ctrl_reg, pp);
···
1014
1007
intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
1015
1008
PCH_DPLSUNIT_CLOCK_GATE_DISABLE, 0);
1016
1009
1017
-
if (IS_IRONLAKE(dev_priv)) {
1010
+
if (display->platform.ironlake) {
1018
1011
pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1019
1012
intel_de_write(display, pp_ctrl_reg, pp);
1020
1013
intel_de_posting_read(display, pp_ctrl_reg);
···
1069
1062
1070
1063
wait_panel_off(intel_dp);
1071
1064
intel_dp->pps.panel_power_off_time = ktime_get_boottime();
1065
+
1066
+
intel_dp_invalidate_source_oui(intel_dp);
1072
1067
1073
1068
/* We got a reference when we enabled the VDD. */
1074
1069
intel_display_power_put(dev_priv,
···
1157
1148
return;
1158
1149
1159
1150
drm_dbg_kms(display->drm, "panel power control backlight %s\n",
1160
-
enable ? "enable" : "disable");
1151
+
str_enable_disable(enable));
1161
1152
1162
1153
if (enable)
1163
1154
intel_pps_backlight_on(intel_dp);
···
1636
1627
1637
1628
/* Haswell doesn't have any port selection bits for the panel
1638
1629
* power sequencer any more. */
1639
-
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1630
+
if (display->platform.valleyview || display->platform.cherryview) {
1640
1631
port_sel = PANEL_PORT_SELECT_VLV(port);
1641
1632
} else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
1642
1633
switch (port) {
···
1683
1674
void intel_pps_encoder_reset(struct intel_dp *intel_dp)
1684
1675
{
1685
1676
struct intel_display *display = to_intel_display(intel_dp);
1686
-
struct drm_i915_private *i915 = to_i915(display->drm);
1687
1677
intel_wakeref_t wakeref;
1688
1678
1689
1679
if (!intel_dp_is_edp(intel_dp))
···
1693
1685
* Reinit the power sequencer also on the resume path, in case
1694
1686
* BIOS did something nasty with it.
1695
1687
*/
1696
-
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
1688
+
if (display->platform.valleyview || display->platform.cherryview)
1697
1689
vlv_initial_power_sequencer_setup(intel_dp);
1698
1690
1699
1691
pps_init_delays(intel_dp);
···
1729
1721
static void pps_init_late(struct intel_dp *intel_dp)
1730
1722
{
1731
1723
struct intel_display *display = to_intel_display(intel_dp);
1732
-
struct drm_i915_private *i915 = to_i915(display->drm);
1733
1724
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1734
1725
struct intel_connector *connector = intel_dp->attached_connector;
1735
1726
1736
-
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
1727
+
if (display->platform.valleyview || display->platform.cherryview)
1737
1728
return;
1738
1729
1739
1730
if (intel_num_pps(display) < 2)
···
1790
1783
{
1791
1784
struct drm_i915_private *i915 = to_i915(display->drm);
1792
1785
1793
-
if (HAS_PCH_SPLIT(i915) || IS_GEMINILAKE(i915) || IS_BROXTON(i915))
1786
+
if (HAS_PCH_SPLIT(i915) || display->platform.geminilake || display->platform.broxton)
1794
1787
display->pps.mmio_base = PCH_PPS_BASE;
1795
-
else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
1788
+
else if (display->platform.valleyview || display->platform.cherryview)
1796
1789
display->pps.mmio_base = VLV_PPS_BASE;
1797
1790
else
1798
1791
display->pps.mmio_base = PPS_BASE;
···
1864
1857
MISSING_CASE(port_sel);
1865
1858
break;
1866
1859
}
1867
-
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1860
+
} else if (display->platform.valleyview || display->platform.cherryview) {
1868
1861
/* presumably write lock depends on pipe, not port select */
1869
1862
pp_reg = PP_CONTROL(display, pipe);
1870
1863
panel_pipe = pipe;
···
1885
1878
((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1886
1879
locked = false;
1887
1880
1888
-
I915_STATE_WARN(dev_priv, panel_pipe == pipe && locked,
1889
-
"panel assertion failure, pipe %c regs locked\n",
1890
-
pipe_name(pipe));
1881
+
INTEL_DISPLAY_STATE_WARN(display, panel_pipe == pipe && locked,
1882
+
"panel assertion failure, pipe %c regs locked\n",
1883
+
pipe_name(pipe));
1891
1884
}
+1
drivers/gpu/drm/i915/display/intel_pps.h
+1
drivers/gpu/drm/i915/display/intel_pps.h
···
34
34
void intel_pps_check_power_unlocked(struct intel_dp *intel_dp);
35
35
36
36
void intel_pps_vdd_on(struct intel_dp *intel_dp);
37
+
void intel_pps_vdd_off(struct intel_dp *intel_dp);
37
38
void intel_pps_on(struct intel_dp *intel_dp);
38
39
void intel_pps_off(struct intel_dp *intel_dp);
39
40
void intel_pps_vdd_off_sync(struct intel_dp *intel_dp);
+53
-7
drivers/gpu/drm/i915/display/intel_psr.c
+53
-7
drivers/gpu/drm/i915/display/intel_psr.c
···
233
233
switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
234
234
case I915_PSR_DEBUG_DEFAULT:
235
235
if (display->params.enable_psr == -1)
236
-
return connector->panel.vbt.psr.enable;
236
+
return intel_dp_is_edp(intel_dp) ?
237
+
connector->panel.vbt.psr.enable :
238
+
true;
237
239
return display->params.enable_psr;
238
240
case I915_PSR_DEBUG_DISABLE:
239
241
return false;
···
1453
1451
return false;
1454
1452
}
1455
1453
1456
-
if (DISPLAY_VER(display) >= 12) {
1454
+
if (DISPLAY_VER(display) >= 20) {
1455
+
psr_max_h = crtc_hdisplay;
1456
+
psr_max_v = crtc_vdisplay;
1457
+
max_bpp = crtc_state->pipe_bpp;
1458
+
} else if (IS_DISPLAY_VER(display, 12, 14)) {
1457
1459
psr_max_h = 5120;
1458
1460
psr_max_v = 3200;
1459
1461
max_bpp = 30;
1460
-
} else if (DISPLAY_VER(display) >= 10) {
1462
+
} else if (IS_DISPLAY_VER(display, 10, 11)) {
1461
1463
psr_max_h = 4096;
1462
1464
psr_max_v = 2304;
1463
1465
max_bpp = 24;
···
1918
1912
* cause issues if non-supported panels are used.
1919
1913
*/
1920
1914
if (!intel_dp->psr.panel_replay_enabled &&
1921
-
(IS_DISPLAY_VER_STEP(display, IP_VER(14, 0), STEP_A0, STEP_B0) ||
1915
+
(IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) ||
1922
1916
IS_ALDERLAKE_P(dev_priv)))
1923
1917
intel_de_rmw(display, hsw_chicken_trans_reg(dev_priv, cpu_transcoder),
1924
1918
0, ADLP_1_BASED_X_GRANULARITY);
1925
1919
1926
1920
/* Wa_16012604467:adlp,mtl[a0,b0] */
1927
1921
if (!intel_dp->psr.panel_replay_enabled &&
1928
-
IS_DISPLAY_VER_STEP(display, IP_VER(14, 0), STEP_A0, STEP_B0))
1922
+
IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0))
1929
1923
intel_de_rmw(display,
1930
1924
MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder),
1931
1925
0,
···
2012
2006
intel_psr_enable_source(intel_dp, crtc_state);
2013
2007
intel_dp->psr.enabled = true;
2014
2008
intel_dp->psr.paused = false;
2009
+
2010
+
/*
2011
+
* Link_ok is sticky and set here on PSR enable. We can assume link
2012
+
* training is complete as we never continue to PSR enable with
2013
+
* untrained link. Link_ok is kept as set until first short pulse
2014
+
* interrupt. This is targeted to workaround panels stating bad link
2015
+
* after PSR is enabled.
2016
+
*/
2017
+
intel_dp->psr.link_ok = true;
2015
2018
2016
2019
intel_psr_activate(intel_dp);
2017
2020
}
···
2119
2104
if (intel_dp->psr.sel_update_enabled) {
2120
2105
/* Wa_16012604467:adlp,mtl[a0,b0] */
2121
2106
if (!intel_dp->psr.panel_replay_enabled &&
2122
-
IS_DISPLAY_VER_STEP(display, IP_VER(14, 0), STEP_A0, STEP_B0))
2107
+
IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0))
2123
2108
intel_de_rmw(display,
2124
2109
MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder),
2125
2110
MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
···
2180
2165
mutex_lock(&intel_dp->psr.lock);
2181
2166
2182
2167
intel_psr_disable_locked(intel_dp);
2168
+
2169
+
intel_dp->psr.link_ok = false;
2183
2170
2184
2171
mutex_unlock(&intel_dp->psr.lock);
2185
2172
cancel_work_sync(&intel_dp->psr.work);
···
2576
2559
2577
2560
/* Wa_14014971492 */
2578
2561
if (!crtc_state->has_panel_replay &&
2579
-
((IS_DISPLAY_VER_STEP(display, IP_VER(14, 0), STEP_A0, STEP_B0) ||
2562
+
((IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) ||
2580
2563
IS_ALDERLAKE_P(i915) || IS_TIGERLAKE(i915))) &&
2581
2564
crtc_state->splitter.enable)
2582
2565
crtc_state->psr2_su_area.y1 = 0;
···
3473
3456
3474
3457
mutex_lock(&psr->lock);
3475
3458
3459
+
psr->link_ok = false;
3460
+
3476
3461
if (!psr->enabled)
3477
3462
goto exit;
3478
3463
···
3529
3510
3530
3511
mutex_lock(&intel_dp->psr.lock);
3531
3512
ret = intel_dp->psr.enabled;
3513
+
mutex_unlock(&intel_dp->psr.lock);
3514
+
3515
+
return ret;
3516
+
}
3517
+
3518
+
/**
3519
+
* intel_psr_link_ok - return psr->link_ok
3520
+
* @intel_dp: struct intel_dp
3521
+
*
3522
+
* We are seeing unexpected link re-trainings with some panels. This is caused
3523
+
* by panel stating bad link status after PSR is enabled. Code checking link
3524
+
* status can call this to ensure it can ignore bad link status stated by the
3525
+
* panel I.e. if panel is stating bad link and intel_psr_link_ok is stating link
3526
+
* is ok caller should rely on latter.
3527
+
*
3528
+
* Return value of link_ok
3529
+
*/
3530
+
bool intel_psr_link_ok(struct intel_dp *intel_dp)
3531
+
{
3532
+
bool ret;
3533
+
3534
+
if ((!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) ||
3535
+
!intel_dp_is_edp(intel_dp))
3536
+
return false;
3537
+
3538
+
mutex_lock(&intel_dp->psr.lock);
3539
+
ret = intel_dp->psr.link_ok;
3532
3540
mutex_unlock(&intel_dp->psr.lock);
3533
3541
3534
3542
return ret;
+1
drivers/gpu/drm/i915/display/intel_psr.h
+1
drivers/gpu/drm/i915/display/intel_psr.h
···
59
59
void intel_psr_pause(struct intel_dp *intel_dp);
60
60
void intel_psr_resume(struct intel_dp *intel_dp);
61
61
bool intel_psr_needs_block_dc_vblank(const struct intel_crtc_state *crtc_state);
62
+
bool intel_psr_link_ok(struct intel_dp *intel_dp);
62
63
63
64
void intel_psr_lock(const struct intel_crtc_state *crtc_state);
64
65
void intel_psr_unlock(const struct intel_crtc_state *crtc_state);
+1
-1
drivers/gpu/drm/i915/display/intel_psr_regs.h
+1
-1
drivers/gpu/drm/i915/display/intel_psr_regs.h
···
298
298
#define _PORT_ALPM_CTL_B 0x16fc2c
299
299
#define PORT_ALPM_CTL(port) _MMIO_PORT(port, _PORT_ALPM_CTL_A, _PORT_ALPM_CTL_B)
300
300
#define PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE REG_BIT(31)
301
-
#define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK REG_GENMASK(23, 20)
301
+
#define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK REG_GENMASK(25, 20)
302
302
#define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(val) REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK, val)
303
303
#define PORT_ALPM_CTL_MAX_PHY_SWING_HOLD_MASK REG_GENMASK(19, 16)
304
304
#define PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(val) REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_HOLD_MASK, val)
+5
-4
drivers/gpu/drm/i915/display/intel_sdvo.c
+5
-4
drivers/gpu/drm/i915/display/intel_sdvo.c
···
2082
2082
static const struct drm_edid *
2083
2083
intel_sdvo_get_analog_edid(struct drm_connector *connector)
2084
2084
{
2085
-
struct drm_i915_private *i915 = to_i915(connector->dev);
2085
+
struct intel_display *display = to_intel_display(connector->dev);
2086
2086
struct i2c_adapter *ddc;
2087
2087
2088
-
ddc = intel_gmbus_get_adapter(i915, i915->display.vbt.crt_ddc_pin);
2088
+
ddc = intel_gmbus_get_adapter(display, display->vbt.crt_ddc_pin);
2089
2089
if (!ddc)
2090
2090
return NULL;
2091
2091
···
2638
2638
static void
2639
2639
intel_sdvo_select_i2c_bus(struct intel_sdvo *sdvo)
2640
2640
{
2641
+
struct intel_display *display = to_intel_display(&sdvo->base);
2641
2642
struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
2642
2643
const struct sdvo_device_mapping *mapping;
2643
2644
u8 pin;
···
2649
2648
mapping = &dev_priv->display.vbt.sdvo_mappings[1];
2650
2649
2651
2650
if (mapping->initialized &&
2652
-
intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin))
2651
+
intel_gmbus_is_valid_pin(display, mapping->i2c_pin))
2653
2652
pin = mapping->i2c_pin;
2654
2653
else
2655
2654
pin = GMBUS_PIN_DPB;
···
2658
2657
sdvo->base.base.base.id, sdvo->base.base.name,
2659
2658
pin, sdvo->target_addr);
2660
2659
2661
-
sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2660
+
sdvo->i2c = intel_gmbus_get_adapter(display, pin);
2662
2661
2663
2662
/*
2664
2663
* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
+6
-5
drivers/gpu/drm/i915/display/intel_snps_phy.c
+6
-5
drivers/gpu/drm/i915/display/intel_snps_phy.c
···
1997
1997
void intel_mpllb_state_verify(struct intel_atomic_state *state,
1998
1998
struct intel_crtc *crtc)
1999
1999
{
2000
+
struct intel_display *display = to_intel_display(state);
2000
2001
struct drm_i915_private *i915 = to_i915(state->base.dev);
2001
2002
const struct intel_crtc_state *new_crtc_state =
2002
2003
intel_atomic_get_new_crtc_state(state, crtc);
···
2020
2019
intel_mpllb_readout_hw_state(encoder, &mpllb_hw_state);
2021
2020
2022
2021
#define MPLLB_CHECK(__name) \
2023
-
I915_STATE_WARN(i915, mpllb_sw_state->__name != mpllb_hw_state.__name, \
2024
-
"[CRTC:%d:%s] mismatch in MPLLB: %s (expected 0x%08x, found 0x%08x)", \
2025
-
crtc->base.base.id, crtc->base.name, \
2026
-
__stringify(__name), \
2027
-
mpllb_sw_state->__name, mpllb_hw_state.__name)
2022
+
INTEL_DISPLAY_STATE_WARN(display, mpllb_sw_state->__name != mpllb_hw_state.__name, \
2023
+
"[CRTC:%d:%s] mismatch in MPLLB: %s (expected 0x%08x, found 0x%08x)", \
2024
+
crtc->base.base.id, crtc->base.name, \
2025
+
__stringify(__name), \
2026
+
mpllb_sw_state->__name, mpllb_hw_state.__name)
2028
2027
2029
2028
MPLLB_CHECK(mpllb_cp);
2030
2029
MPLLB_CHECK(mpllb_div);
+1
-1
drivers/gpu/drm/i915/display/intel_tc.c
+1
-1
drivers/gpu/drm/i915/display/intel_tc.c
···
1005
1005
if (wait_for(xelpdp_tc_phy_tcss_power_is_enabled(tc) == enabled, 5)) {
1006
1006
drm_dbg_kms(&i915->drm,
1007
1007
"Port %s: timeout waiting for TCSS power to get %s\n",
1008
-
enabled ? "enabled" : "disabled",
1008
+
str_enabled_disabled(enabled),
1009
1009
tc->port_name);
1010
1010
return false;
1011
1011
}
+4
-6
drivers/gpu/drm/i915/display/intel_tv.c
+4
-6
drivers/gpu/drm/i915/display/intel_tv.c
···
1093
1093
struct intel_crtc_state *pipe_config)
1094
1094
{
1095
1095
struct intel_display *display = to_intel_display(encoder);
1096
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1097
1096
struct drm_display_mode *adjusted_mode =
1098
1097
&pipe_config->hw.adjusted_mode;
1099
1098
struct drm_display_mode mode = {};
···
1166
1167
adjusted_mode->crtc_clock /= 2;
1167
1168
1168
1169
/* pixel counter doesn't work on i965gm TV output */
1169
-
if (IS_I965GM(dev_priv))
1170
+
if (display->platform.i965gm)
1170
1171
pipe_config->mode_flags |=
1171
1172
I915_MODE_FLAG_USE_SCANLINE_COUNTER;
1172
1173
}
···
1196
1197
struct intel_atomic_state *state =
1197
1198
to_intel_atomic_state(pipe_config->uapi.state);
1198
1199
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1199
-
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1200
1200
struct intel_tv_connector_state *tv_conn_state =
1201
1201
to_intel_tv_connector_state(conn_state);
1202
1202
const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state);
···
1347
1349
adjusted_mode->name[0] = '\0';
1348
1350
1349
1351
/* pixel counter doesn't work on i965gm TV output */
1350
-
if (IS_I965GM(dev_priv))
1352
+
if (display->platform.i965gm)
1351
1353
pipe_config->mode_flags |=
1352
1354
I915_MODE_FLAG_USE_SCANLINE_COUNTER;
1353
1355
···
1523
1525
tv_mode->dda3_inc << TV_SCDDA3_INC_SHIFT;
1524
1526
1525
1527
/* Enable two fixes for the chips that need them. */
1526
-
if (IS_I915GM(dev_priv))
1528
+
if (display->platform.i915gm)
1527
1529
tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX;
1528
1530
1529
1531
set_tv_mode_timings(display, tv_mode, burst_ena);
···
1625
1627
* The TV sense state should be cleared to zero on cantiga platform. Otherwise
1626
1628
* the TV is misdetected. This is hardware requirement.
1627
1629
*/
1628
-
if (IS_GM45(dev_priv))
1630
+
if (display->platform.gm45)
1629
1631
tv_dac &= ~(TVDAC_STATE_CHG_EN | TVDAC_A_SENSE_CTL |
1630
1632
TVDAC_B_SENSE_CTL | TVDAC_C_SENSE_CTL);
1631
1633
+5
-6
drivers/gpu/drm/i915/display/intel_vblank.c
+5
-6
drivers/gpu/drm/i915/display/intel_vblank.c
···
195
195
int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state)
196
196
{
197
197
struct intel_display *display = to_intel_display(crtc_state);
198
-
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
199
198
200
199
/*
201
200
* The scanline counter increments at the leading edge of hsync.
···
224
225
*/
225
226
if (DISPLAY_VER(display) == 2)
226
227
return -1;
227
-
else if (HAS_DDI(i915) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
228
+
else if (HAS_DDI(display) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
228
229
return 2;
229
230
else
230
231
return 1;
···
326
327
const struct drm_display_mode *mode)
327
328
{
328
329
struct intel_display *display = to_intel_display(_crtc->dev);
329
-
struct drm_i915_private *dev_priv = to_i915(display->drm);
330
330
struct intel_crtc *crtc = to_intel_crtc(_crtc);
331
331
enum pipe pipe = crtc->pipe;
332
332
int position;
333
333
int vbl_start, vbl_end, hsync_start, htotal, vtotal;
334
334
unsigned long irqflags;
335
335
bool use_scanline_counter = DISPLAY_VER(display) >= 5 ||
336
-
IS_G4X(dev_priv) || DISPLAY_VER(display) == 2 ||
336
+
display->platform.g4x || DISPLAY_VER(display) == 2 ||
337
337
crtc->mode_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;
338
338
339
339
if (drm_WARN_ON(display->drm, !mode->crtc_clock)) {
···
601
603
const struct intel_crtc_state *new_crtc_state,
602
604
struct intel_vblank_evade_ctx *evade)
603
605
{
606
+
struct intel_display *display = to_intel_display(new_crtc_state);
604
607
struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
605
-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
606
608
const struct intel_crtc_state *crtc_state;
607
609
const struct drm_display_mode *adjusted_mode;
608
610
609
611
evade->crtc = crtc;
610
612
611
-
evade->need_vlv_dsi_wa = (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) &&
613
+
evade->need_vlv_dsi_wa = (display->platform.valleyview ||
614
+
display->platform.cherryview) &&
612
615
intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
613
616
614
617
/*
+1
-3
drivers/gpu/drm/i915/display/intel_vga.c
+1
-3
drivers/gpu/drm/i915/display/intel_vga.c
···
16
16
17
17
static i915_reg_t intel_vga_cntrl_reg(struct intel_display *display)
18
18
{
19
-
struct drm_i915_private *i915 = to_i915(display->drm);
20
-
21
-
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
19
+
if (display->platform.valleyview || display->platform.cherryview)
22
20
return VLV_VGACNTRL;
23
21
else if (DISPLAY_VER(display) >= 5)
24
22
return CPU_VGACNTRL;
+15
-5
drivers/gpu/drm/i915/display/intel_vrr.c
+15
-5
drivers/gpu/drm/i915/display/intel_vrr.c
···
56
56
vrefresh <= info->monitor_range.max_vfreq;
57
57
}
58
58
59
+
bool intel_vrr_possible(const struct intel_crtc_state *crtc_state)
60
+
{
61
+
return crtc_state->vrr.flipline;
62
+
}
63
+
59
64
void
60
65
intel_vrr_check_modeset(struct intel_atomic_state *state)
61
66
{
···
244
239
(crtc_state->hw.adjusted_mode.crtc_vtotal -
245
240
crtc_state->hw.adjusted_mode.vsync_end);
246
241
}
242
+
}
247
243
248
-
/*
249
-
* For XE_LPD+, we use guardband and pipeline override
250
-
* is deprecated.
251
-
*/
244
+
void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
245
+
{
246
+
struct intel_display *display = to_intel_display(crtc_state);
247
+
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
248
+
249
+
if (!intel_vrr_possible(crtc_state))
250
+
return;
251
+
252
252
if (DISPLAY_VER(display) >= 13) {
253
253
crtc_state->vrr.guardband =
254
254
crtc_state->vrr.vmin + 1 - adjusted_mode->crtc_vblank_start;
···
291
281
intel_de_rmw(display, CHICKEN_TRANS(cpu_transcoder),
292
282
0, PIPE_VBLANK_WITH_DELAY);
293
283
294
-
if (!crtc_state->vrr.flipline) {
284
+
if (!intel_vrr_possible(crtc_state)) {
295
285
intel_de_write(display,
296
286
TRANS_VRR_CTL(display, cpu_transcoder), 0);
297
287
return;
+2
drivers/gpu/drm/i915/display/intel_vrr.h
+2
drivers/gpu/drm/i915/display/intel_vrr.h
···
15
15
16
16
bool intel_vrr_is_capable(struct intel_connector *connector);
17
17
bool intel_vrr_is_in_range(struct intel_connector *connector, int vrefresh);
18
+
bool intel_vrr_possible(const struct intel_crtc_state *crtc_state);
18
19
void intel_vrr_check_modeset(struct intel_atomic_state *state);
19
20
void intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
20
21
struct drm_connector_state *conn_state);
22
+
void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state);
21
23
void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
22
24
void intel_vrr_enable(const struct intel_crtc_state *crtc_state);
23
25
void intel_vrr_send_push(const struct intel_crtc_state *crtc_state);
+10
-67
drivers/gpu/drm/i915/display/skl_scaler.c
+10
-67
drivers/gpu/drm/i915/display/skl_scaler.c
···
272
272
to_intel_plane(plane_state->uapi.plane);
273
273
struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
274
274
struct drm_framebuffer *fb = plane_state->hw.fb;
275
-
int ret;
276
275
bool force_detach = !fb || !plane_state->uapi.visible;
277
276
bool need_scaler = false;
278
277
···
280
281
fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
281
282
need_scaler = true;
282
283
283
-
ret = skl_update_scaler(crtc_state, force_detach,
284
-
drm_plane_index(&intel_plane->base),
285
-
&plane_state->scaler_id,
286
-
drm_rect_width(&plane_state->uapi.src) >> 16,
287
-
drm_rect_height(&plane_state->uapi.src) >> 16,
288
-
drm_rect_width(&plane_state->uapi.dst),
289
-
drm_rect_height(&plane_state->uapi.dst),
290
-
fb ? fb->format : NULL,
291
-
fb ? fb->modifier : 0,
292
-
need_scaler);
293
-
294
-
if (ret || plane_state->scaler_id < 0)
295
-
return ret;
296
-
297
-
/* check colorkey */
298
-
if (plane_state->ckey.flags) {
299
-
drm_dbg_kms(&dev_priv->drm,
300
-
"[PLANE:%d:%s] scaling with color key not allowed",
301
-
intel_plane->base.base.id,
302
-
intel_plane->base.name);
303
-
return -EINVAL;
304
-
}
305
-
306
-
/* Check src format */
307
-
switch (fb->format->format) {
308
-
case DRM_FORMAT_RGB565:
309
-
case DRM_FORMAT_XBGR8888:
310
-
case DRM_FORMAT_XRGB8888:
311
-
case DRM_FORMAT_ABGR8888:
312
-
case DRM_FORMAT_ARGB8888:
313
-
case DRM_FORMAT_XRGB2101010:
314
-
case DRM_FORMAT_XBGR2101010:
315
-
case DRM_FORMAT_ARGB2101010:
316
-
case DRM_FORMAT_ABGR2101010:
317
-
case DRM_FORMAT_YUYV:
318
-
case DRM_FORMAT_YVYU:
319
-
case DRM_FORMAT_UYVY:
320
-
case DRM_FORMAT_VYUY:
321
-
case DRM_FORMAT_NV12:
322
-
case DRM_FORMAT_XYUV8888:
323
-
case DRM_FORMAT_P010:
324
-
case DRM_FORMAT_P012:
325
-
case DRM_FORMAT_P016:
326
-
case DRM_FORMAT_Y210:
327
-
case DRM_FORMAT_Y212:
328
-
case DRM_FORMAT_Y216:
329
-
case DRM_FORMAT_XVYU2101010:
330
-
case DRM_FORMAT_XVYU12_16161616:
331
-
case DRM_FORMAT_XVYU16161616:
332
-
break;
333
-
case DRM_FORMAT_XBGR16161616F:
334
-
case DRM_FORMAT_ABGR16161616F:
335
-
case DRM_FORMAT_XRGB16161616F:
336
-
case DRM_FORMAT_ARGB16161616F:
337
-
if (DISPLAY_VER(dev_priv) >= 11)
338
-
break;
339
-
fallthrough;
340
-
default:
341
-
drm_dbg_kms(&dev_priv->drm,
342
-
"[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
343
-
intel_plane->base.base.id, intel_plane->base.name,
344
-
fb->base.id, fb->format->format);
345
-
return -EINVAL;
346
-
}
347
-
348
-
return 0;
284
+
return skl_update_scaler(crtc_state, force_detach,
285
+
drm_plane_index(&intel_plane->base),
286
+
&plane_state->scaler_id,
287
+
drm_rect_width(&plane_state->uapi.src) >> 16,
288
+
drm_rect_height(&plane_state->uapi.src) >> 16,
289
+
drm_rect_width(&plane_state->uapi.dst),
290
+
drm_rect_height(&plane_state->uapi.dst),
291
+
fb ? fb->format : NULL,
292
+
fb ? fb->modifier : 0,
293
+
need_scaler);
349
294
}
350
295
351
296
static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state,
+24
-5
drivers/gpu/drm/i915/display/skl_universal_plane.c
+24
-5
drivers/gpu/drm/i915/display/skl_universal_plane.c
···
431
431
}
432
432
}
433
433
434
+
static int xe3_plane_max_width(const struct drm_framebuffer *fb,
435
+
int color_plane,
436
+
unsigned int rotation)
437
+
{
438
+
if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
439
+
return 4096;
440
+
else
441
+
return 6144;
442
+
}
443
+
434
444
static int icl_hdr_plane_max_width(const struct drm_framebuffer *fb,
435
445
int color_plane,
436
446
unsigned int rotation)
···
1577
1567
struct intel_display *display = to_intel_display(plane->base.dev);
1578
1568
enum plane_id plane_id = plane->id;
1579
1569
enum pipe pipe = plane->pipe;
1580
-
u32 plane_ctl = plane_state->ctl;
1570
+
u32 plane_ctl = plane_state->ctl, plane_surf;
1581
1571
1582
1572
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
1573
+
plane_surf = skl_plane_surf(plane_state, 0);
1583
1574
1584
-
if (async_flip)
1585
-
plane_ctl |= PLANE_CTL_ASYNC_FLIP;
1575
+
if (async_flip) {
1576
+
if (DISPLAY_VER(display) >= 30)
1577
+
plane_surf |= PLANE_SURF_ASYNC_UPDATE;
1578
+
else
1579
+
plane_ctl |= PLANE_CTL_ASYNC_FLIP;
1580
+
}
1586
1581
1587
1582
intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id),
1588
1583
plane_ctl);
1589
1584
intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id),
1590
-
skl_plane_surf(plane_state, 0));
1585
+
plane_surf);
1591
1586
}
1592
1587
1593
1588
static bool intel_format_is_p01x(u32 format)
···
2599
2584
2600
2585
intel_fbc_add_plane(skl_plane_fbc(dev_priv, pipe, plane_id), plane);
2601
2586
2602
-
if (DISPLAY_VER(dev_priv) >= 11) {
2587
+
if (DISPLAY_VER(dev_priv) >= 30) {
2588
+
plane->max_width = xe3_plane_max_width;
2589
+
plane->max_height = icl_plane_max_height;
2590
+
plane->min_cdclk = icl_plane_min_cdclk;
2591
+
} else if (DISPLAY_VER(dev_priv) >= 11) {
2603
2592
plane->min_width = icl_plane_min_width;
2604
2593
if (icl_is_hdr_plane(dev_priv, plane_id))
2605
2594
plane->max_width = icl_hdr_plane_max_width;
+1
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+1
drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+13
-7
drivers/gpu/drm/i915/display/skl_watermark.c
+13
-7
drivers/gpu/drm/i915/display/skl_watermark.c
···
718
718
int width, const struct drm_format_info *format,
719
719
u64 modifier, unsigned int rotation,
720
720
u32 plane_pixel_rate, struct skl_wm_params *wp,
721
-
int color_plane);
721
+
int color_plane, unsigned int pan_x);
722
722
723
723
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
724
724
struct intel_plane *plane,
···
765
765
drm_format_info(DRM_FORMAT_ARGB8888),
766
766
DRM_FORMAT_MOD_LINEAR,
767
767
DRM_MODE_ROTATE_0,
768
-
crtc_state->pixel_rate, &wp, 0);
768
+
crtc_state->pixel_rate, &wp, 0, 0);
769
769
drm_WARN_ON(&i915->drm, ret);
770
770
771
771
for (level = 0; level < i915->display.wm.num_levels; level++) {
···
1742
1742
int width, const struct drm_format_info *format,
1743
1743
u64 modifier, unsigned int rotation,
1744
1744
u32 plane_pixel_rate, struct skl_wm_params *wp,
1745
-
int color_plane)
1745
+
int color_plane, unsigned int pan_x)
1746
1746
{
1747
1747
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1748
1748
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
···
1803
1803
wp->y_min_scanlines,
1804
1804
wp->dbuf_block_size);
1805
1805
1806
-
if (DISPLAY_VER(i915) >= 10)
1806
+
if (DISPLAY_VER(i915) >= 30)
1807
+
interm_pbpl += (pan_x != 0);
1808
+
else if (DISPLAY_VER(i915) >= 10)
1807
1809
interm_pbpl++;
1808
1810
1809
1811
wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
···
1847
1845
fb->format, fb->modifier,
1848
1846
plane_state->hw.rotation,
1849
1847
intel_plane_pixel_rate(crtc_state, plane_state),
1850
-
wp, color_plane);
1848
+
wp, color_plane,
1849
+
plane_state->uapi.src.x1);
1851
1850
}
1852
1851
1853
1852
static bool skl_wm_has_lines(struct drm_i915_private *i915, int level)
···
1912
1909
}
1913
1910
}
1914
1911
1915
-
blocks = fixed16_to_u32_round_up(selected_result) + 1;
1912
+
blocks = fixed16_to_u32_round_up(selected_result);
1913
+
if (DISPLAY_VER(i915) < 30)
1914
+
blocks++;
1915
+
1916
1916
/*
1917
1917
* Lets have blocks at minimum equivalent to plane_blocks_per_line
1918
1918
* as there will be at minimum one line for lines configuration. This
···
3533
3527
for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, new_dbuf_state->active_pipes) {
3534
3528
u32 pipe_val = val;
3535
3529
3536
-
if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) {
3530
+
if (DISPLAY_VERx100(i915) == 1400) {
3537
3531
if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe,
3538
3532
new_dbuf_state->active_pipes))
3539
3533
pipe_val |= MBUS_DBOX_BW_8CREDITS_MTL;
+1
drivers/gpu/drm/i915/display/vlv_dsi.c
+1
drivers/gpu/drm/i915/display/vlv_dsi.c
+4
-3
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
+4
-3
drivers/gpu/drm/i915/display/vlv_dsi_pll.c
···
592
592
593
593
static void assert_dsi_pll(struct drm_i915_private *i915, bool state)
594
594
{
595
+
struct intel_display *display = &i915->display;
595
596
bool cur_state;
596
597
597
598
vlv_cck_get(i915);
598
599
cur_state = vlv_cck_read(i915, CCK_REG_DSI_PLL_CONTROL) & DSI_PLL_VCO_EN;
599
600
vlv_cck_put(i915);
600
601
601
-
I915_STATE_WARN(i915, cur_state != state,
602
-
"DSI PLL state assertion failure (expected %s, current %s)\n",
603
-
str_on_off(state), str_on_off(cur_state));
602
+
INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
603
+
"DSI PLL state assertion failure (expected %s, current %s)\n",
604
+
str_on_off(state), str_on_off(cur_state));
604
605
}
605
606
606
607
void assert_dsi_pll_enabled(struct drm_i915_private *i915)
+2
-1
drivers/gpu/drm/i915/gt/gen7_renderclear.c
+2
-1
drivers/gpu/drm/i915/gt/gen7_renderclear.c
···
399
399
batch_add(&cmds, MI_LOAD_REGISTER_IMM(2));
400
400
batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0_GEN7));
401
401
batch_add(&cmds, 0xffff0000 |
402
-
((IS_IVB_GT1(i915) || IS_VALLEYVIEW(i915)) ?
402
+
(((IS_IVYBRIDGE(i915) && INTEL_INFO(i915)->gt == 1) ||
403
+
IS_VALLEYVIEW(i915)) ?
403
404
HIZ_RAW_STALL_OPT_DISABLE :
404
405
0));
405
406
batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_1));
+1
-1
drivers/gpu/drm/i915/gt/intel_gt.c
+1
-1
drivers/gpu/drm/i915/gt/intel_gt.c
+12
-12
drivers/gpu/drm/i915/gt/intel_gt_irq.c
+12
-12
drivers/gpu/drm/i915/gt/intel_gt_irq.c
···
452
452
{
453
453
struct intel_uncore *uncore = gt->uncore;
454
454
455
-
gen3_irq_reset(uncore, GEN8_GT_IRQ_REGS(0));
456
-
gen3_irq_reset(uncore, GEN8_GT_IRQ_REGS(1));
457
-
gen3_irq_reset(uncore, GEN8_GT_IRQ_REGS(2));
458
-
gen3_irq_reset(uncore, GEN8_GT_IRQ_REGS(3));
455
+
gen2_irq_reset(uncore, GEN8_GT_IRQ_REGS(0));
456
+
gen2_irq_reset(uncore, GEN8_GT_IRQ_REGS(1));
457
+
gen2_irq_reset(uncore, GEN8_GT_IRQ_REGS(2));
458
+
gen2_irq_reset(uncore, GEN8_GT_IRQ_REGS(3));
459
459
}
460
460
461
461
void gen8_gt_irq_postinstall(struct intel_gt *gt)
···
476
476
477
477
gt->pm_ier = 0x0;
478
478
gt->pm_imr = ~gt->pm_ier;
479
-
gen3_irq_init(uncore, GEN8_GT_IRQ_REGS(0), ~gt_interrupts[0], gt_interrupts[0]);
480
-
gen3_irq_init(uncore, GEN8_GT_IRQ_REGS(1), ~gt_interrupts[1], gt_interrupts[1]);
479
+
gen2_irq_init(uncore, GEN8_GT_IRQ_REGS(0), ~gt_interrupts[0], gt_interrupts[0]);
480
+
gen2_irq_init(uncore, GEN8_GT_IRQ_REGS(1), ~gt_interrupts[1], gt_interrupts[1]);
481
481
/*
482
482
* RPS interrupts will get enabled/disabled on demand when RPS itself
483
483
* is enabled/disabled. Same wil be the case for GuC interrupts.
484
484
*/
485
-
gen3_irq_init(uncore, GEN8_GT_IRQ_REGS(2), gt->pm_imr, gt->pm_ier);
486
-
gen3_irq_init(uncore, GEN8_GT_IRQ_REGS(3), ~gt_interrupts[3], gt_interrupts[3]);
485
+
gen2_irq_init(uncore, GEN8_GT_IRQ_REGS(2), gt->pm_imr, gt->pm_ier);
486
+
gen2_irq_init(uncore, GEN8_GT_IRQ_REGS(3), ~gt_interrupts[3], gt_interrupts[3]);
487
487
}
488
488
489
489
static void gen5_gt_update_irq(struct intel_gt *gt,
···
514
514
{
515
515
struct intel_uncore *uncore = gt->uncore;
516
516
517
-
gen3_irq_reset(uncore, GT_IRQ_REGS);
517
+
gen2_irq_reset(uncore, GT_IRQ_REGS);
518
518
if (GRAPHICS_VER(gt->i915) >= 6)
519
-
gen3_irq_reset(uncore, GEN6_PM_IRQ_REGS);
519
+
gen2_irq_reset(uncore, GEN6_PM_IRQ_REGS);
520
520
}
521
521
522
522
void gen5_gt_irq_postinstall(struct intel_gt *gt)
···
538
538
else
539
539
gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
540
540
541
-
gen3_irq_init(uncore, GT_IRQ_REGS, gt->gt_imr, gt_irqs);
541
+
gen2_irq_init(uncore, GT_IRQ_REGS, gt->gt_imr, gt_irqs);
542
542
543
543
if (GRAPHICS_VER(gt->i915) >= 6) {
544
544
/*
···
551
551
}
552
552
553
553
gt->pm_imr = 0xffffffff;
554
-
gen3_irq_init(uncore, GEN6_PM_IRQ_REGS, gt->pm_imr, pm_irqs);
554
+
gen2_irq_init(uncore, GEN6_PM_IRQ_REGS, gt->pm_imr, pm_irqs);
555
555
}
556
556
}
+5
-2
drivers/gpu/drm/i915/gt/intel_lrc.c
+5
-2
drivers/gpu/drm/i915/gt/intel_lrc.c
···
820
820
bool ctx_is_protected = false;
821
821
822
822
/*
823
-
* On MTL and newer platforms, protected contexts require setting
824
-
* the LRC run-alone bit or else the encryption will not happen.
823
+
* Wa_14019159160 - Case 2.
824
+
* On some platforms, protected contexts require setting
825
+
* the LRC run-alone bit or else the encryption/decryption will not happen.
826
+
* NOTE: Case 2 only applies to PXP use-case of said workaround.
825
827
*/
826
828
if (GRAPHICS_VER_FULL(ce->engine->i915) >= IP_VER(12, 70) &&
827
829
(ce->engine->class == COMPUTE_CLASS || ce->engine->class == RENDER_CLASS)) {
···
852
850
if (GRAPHICS_VER(engine->i915) < 11)
853
851
ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
854
852
CTX_CTRL_RS_CTX_ENABLE);
853
+
/* Wa_14019159160 - Case 2.*/
855
854
if (ctx_needs_runalone(ce))
856
855
ctl |= _MASKED_BIT_ENABLE(GEN12_CTX_CTRL_RUNALONE_MODE);
857
856
regs[CTX_CONTEXT_CONTROL] = ctl;
+2
-2
drivers/gpu/drm/i915/gt/intel_workarounds.c
+2
-2
drivers/gpu/drm/i915/gt/intel_workarounds.c
···
418
418
/* WaForceContextSaveRestoreNonCoherent:bdw */
419
419
HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
420
420
/* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
421
-
(IS_BROADWELL_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
421
+
(INTEL_INFO(i915)->gt == 3 ? HDC_FENCE_DEST_SLM_DISABLE : 0));
422
422
}
423
423
424
424
static void chv_ctx_workarounds_init(struct intel_engine_cs *engine,
···
2546
2546
GEN7_FF_DS_SCHED_HW);
2547
2547
2548
2548
/* WaDisablePSDDualDispatchEnable:ivb */
2549
-
if (IS_IVB_GT1(i915))
2549
+
if (INTEL_INFO(i915)->gt == 1)
2550
2550
wa_masked_en(wal,
2551
2551
GEN7_HALF_SLICE_CHICKEN1,
2552
2552
GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
+3
-1
drivers/gpu/drm/i915/gvt/display.c
+3
-1
drivers/gpu/drm/i915/gvt/display.c
···
32
32
*
33
33
*/
34
34
35
+
#include <drm/display/drm_dp.h>
36
+
35
37
#include "i915_drv.h"
36
38
#include "i915_reg.h"
37
39
#include "gvt.h"
···
570
568
571
569
memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE);
572
570
port->dpcd->data_valid = true;
573
-
port->dpcd->data[DPCD_SINK_COUNT] = 0x1;
571
+
port->dpcd->data[DP_SINK_COUNT] = 0x1;
574
572
port->type = type;
575
573
port->id = resolution;
576
574
port->vrefresh_k = GVT_DEFAULT_REFRESH_RATE * MSEC_PER_SEC;
-42
drivers/gpu/drm/i915/gvt/display.h
-42
drivers/gpu/drm/i915/gvt/display.h
···
59
59
60
60
#define INTEL_GVT_MAX_UEVENT_VARS 3
61
61
62
-
/* DPCD start */
63
-
#define DPCD_SIZE 0x700
64
-
65
-
/* DPCD */
66
-
#define DP_SET_POWER 0x600
67
-
#define DP_SET_POWER_D0 0x1
68
-
#define AUX_NATIVE_WRITE 0x8
69
-
#define AUX_NATIVE_READ 0x9
70
-
71
-
#define AUX_NATIVE_REPLY_MASK (0x3 << 4)
72
-
#define AUX_NATIVE_REPLY_ACK (0x0 << 4)
73
62
#define AUX_NATIVE_REPLY_NAK (0x1 << 4)
74
-
#define AUX_NATIVE_REPLY_DEFER (0x2 << 4)
75
63
76
64
#define AUX_BURST_SIZE 20
77
-
78
-
/* DPCD addresses */
79
-
#define DPCD_REV 0x000
80
-
#define DPCD_MAX_LINK_RATE 0x001
81
-
#define DPCD_MAX_LANE_COUNT 0x002
82
-
83
-
#define DPCD_TRAINING_PATTERN_SET 0x102
84
-
#define DPCD_SINK_COUNT 0x200
85
-
#define DPCD_LANE0_1_STATUS 0x202
86
-
#define DPCD_LANE2_3_STATUS 0x203
87
-
#define DPCD_LANE_ALIGN_STATUS_UPDATED 0x204
88
-
#define DPCD_SINK_STATUS 0x205
89
-
90
-
/* link training */
91
-
#define DPCD_TRAINING_PATTERN_SET_MASK 0x03
92
-
#define DPCD_LINK_TRAINING_DISABLED 0x00
93
-
#define DPCD_TRAINING_PATTERN_1 0x01
94
-
#define DPCD_TRAINING_PATTERN_2 0x02
95
-
96
-
#define DPCD_CP_READY_MASK (1 << 6)
97
-
98
-
/* lane status */
99
-
#define DPCD_LANES_CR_DONE 0x11
100
-
#define DPCD_LANES_EQ_DONE 0x22
101
-
#define DPCD_SYMBOL_LOCKED 0x44
102
-
103
-
#define DPCD_INTERLANE_ALIGN_DONE 0x01
104
-
105
-
#define DPCD_SINK_IN_SYNC 0x03
106
-
/* DPCD end */
107
65
108
66
#define SBI_RESPONSE_MASK 0x3
109
67
#define SBI_RESPONSE_SHIFT 0x1
+7
-5
drivers/gpu/drm/i915/gvt/edid.c
+7
-5
drivers/gpu/drm/i915/gvt/edid.c
···
32
32
*
33
33
*/
34
34
35
+
#include <drm/display/drm_dp.h>
36
+
35
37
#include "display/intel_dp_aux_regs.h"
36
38
#include "display/intel_gmbus_regs.h"
37
39
#include "gvt.h"
···
506
504
}
507
505
508
506
/* Always set the wanted value for vms. */
509
-
ret_msg_size = (((op & 0x1) == GVT_AUX_I2C_READ) ? 2 : 1);
507
+
ret_msg_size = (((op & 0x1) == DP_AUX_I2C_READ) ? 2 : 1);
510
508
vgpu_vreg(vgpu, offset) =
511
509
DP_AUX_CH_CTL_DONE |
512
510
DP_AUX_CH_CTL_MESSAGE_SIZE(ret_msg_size);
513
511
514
512
if (msg_length == 3) {
515
-
if (!(op & GVT_AUX_I2C_MOT)) {
513
+
if (!(op & DP_AUX_I2C_MOT)) {
516
514
/* stop */
517
515
intel_vgpu_init_i2c_edid(vgpu);
518
516
} else {
···
532
530
i2c_edid->edid_available = true;
533
531
}
534
532
}
535
-
} else if ((op & 0x1) == GVT_AUX_I2C_WRITE) {
533
+
} else if ((op & 0x1) == DP_AUX_I2C_WRITE) {
536
534
/* TODO
537
535
* We only support EDID reading from I2C_over_AUX. And
538
536
* we do not expect the index mode to be used. Right now
···
540
538
* support the gfx driver to do EDID access.
541
539
*/
542
540
} else {
543
-
if (drm_WARN_ON(&i915->drm, (op & 0x1) != GVT_AUX_I2C_READ))
541
+
if (drm_WARN_ON(&i915->drm, (op & 0x1) != DP_AUX_I2C_READ))
544
542
return;
545
543
if (drm_WARN_ON(&i915->drm, msg_length != 4))
546
544
return;
···
555
553
* ACK of I2C_WRITE
556
554
* returned byte if it is READ
557
555
*/
558
-
aux_data_for_write |= GVT_AUX_I2C_REPLY_ACK << 24;
556
+
aux_data_for_write |= DP_AUX_I2C_REPLY_ACK << 24;
559
557
vgpu_vreg(vgpu, offset + 4) = aux_data_for_write;
560
558
}
561
559
-8
drivers/gpu/drm/i915/gvt/edid.h
-8
drivers/gpu/drm/i915/gvt/edid.h
···
42
42
#define EDID_SIZE 128
43
43
#define EDID_ADDR 0x50 /* Linux hvm EDID addr */
44
44
45
-
#define GVT_AUX_NATIVE_WRITE 0x8
46
-
#define GVT_AUX_NATIVE_READ 0x9
47
-
#define GVT_AUX_I2C_WRITE 0x0
48
-
#define GVT_AUX_I2C_READ 0x1
49
-
#define GVT_AUX_I2C_STATUS 0x2
50
-
#define GVT_AUX_I2C_MOT 0x4
51
-
#define GVT_AUX_I2C_REPLY_ACK 0x0
52
-
53
45
struct intel_vgpu_edid_data {
54
46
bool data_valid;
55
47
unsigned char edid_block[EDID_SIZE];
+26
-17
drivers/gpu/drm/i915/gvt/handlers.c
+26
-17
drivers/gpu/drm/i915/gvt/handlers.c
···
36
36
37
37
*/
38
38
39
+
#include <drm/display/drm_dp.h>
40
+
39
41
#include "i915_drv.h"
40
42
#include "i915_reg.h"
41
43
#include "gvt.h"
···
1131
1129
static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd,
1132
1130
u8 t)
1133
1131
{
1134
-
if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) {
1132
+
if ((t & DP_TRAINING_PATTERN_MASK) == DP_TRAINING_PATTERN_1) {
1135
1133
/* training pattern 1 for CR */
1136
1134
/* set LANE0_CR_DONE, LANE1_CR_DONE */
1137
-
dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE;
1135
+
dpcd->data[DP_LANE0_1_STATUS] |= DP_LANE_CR_DONE |
1136
+
DP_LANE_CR_DONE << 4;
1138
1137
/* set LANE2_CR_DONE, LANE3_CR_DONE */
1139
-
dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE;
1140
-
} else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
1141
-
DPCD_TRAINING_PATTERN_2) {
1138
+
dpcd->data[DP_LANE2_3_STATUS] |= DP_LANE_CR_DONE |
1139
+
DP_LANE_CR_DONE << 4;
1140
+
} else if ((t & DP_TRAINING_PATTERN_MASK) ==
1141
+
DP_TRAINING_PATTERN_2) {
1142
1142
/* training pattern 2 for EQ */
1143
1143
/* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */
1144
-
dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE;
1145
-
dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED;
1144
+
dpcd->data[DP_LANE0_1_STATUS] |= DP_LANE_CHANNEL_EQ_DONE |
1145
+
DP_LANE_CHANNEL_EQ_DONE << 4;
1146
+
dpcd->data[DP_LANE0_1_STATUS] |= DP_LANE_SYMBOL_LOCKED |
1147
+
DP_LANE_SYMBOL_LOCKED << 4;
1146
1148
/* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */
1147
-
dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE;
1148
-
dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED;
1149
+
dpcd->data[DP_LANE2_3_STATUS] |= DP_LANE_CHANNEL_EQ_DONE |
1150
+
DP_LANE_CHANNEL_EQ_DONE << 4;
1151
+
dpcd->data[DP_LANE2_3_STATUS] |= DP_LANE_SYMBOL_LOCKED |
1152
+
DP_LANE_SYMBOL_LOCKED << 4;
1149
1153
/* set INTERLANE_ALIGN_DONE */
1150
-
dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |=
1151
-
DPCD_INTERLANE_ALIGN_DONE;
1152
-
} else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
1153
-
DPCD_LINK_TRAINING_DISABLED) {
1154
+
dpcd->data[DP_LANE_ALIGN_STATUS_UPDATED] |=
1155
+
DP_INTERLANE_ALIGN_DONE;
1156
+
} else if ((t & DP_TRAINING_PATTERN_MASK) ==
1157
+
DP_TRAINING_PATTERN_DISABLE) {
1154
1158
/* finish link training */
1155
1159
/* set sink status as synchronized */
1156
-
dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC;
1160
+
dpcd->data[DP_SINK_STATUS] = DP_RECEIVE_PORT_0_STATUS |
1161
+
DP_RECEIVE_PORT_1_STATUS;
1157
1162
}
1158
1163
}
1159
1164
···
1215
1206
len = msg & 0xff;
1216
1207
op = ctrl >> 4;
1217
1208
1218
-
if (op == GVT_AUX_NATIVE_WRITE) {
1209
+
if (op == DP_AUX_NATIVE_WRITE) {
1219
1210
int t;
1220
1211
u8 buf[16];
1221
1212
···
1261
1252
1262
1253
dpcd->data[p] = buf[t];
1263
1254
/* check for link training */
1264
-
if (p == DPCD_TRAINING_PATTERN_SET)
1255
+
if (p == DP_TRAINING_PATTERN_SET)
1265
1256
dp_aux_ch_ctl_link_training(dpcd,
1266
1257
buf[t]);
1267
1258
}
···
1274
1265
return 0;
1275
1266
}
1276
1267
1277
-
if (op == GVT_AUX_NATIVE_READ) {
1268
+
if (op == DP_AUX_NATIVE_READ) {
1278
1269
int idx, i, ret = 0;
1279
1270
1280
1271
if ((addr + len + 1) >= DPCD_SIZE) {
+1
-1
drivers/gpu/drm/i915/i915_active.c
+1
-1
drivers/gpu/drm/i915/i915_active.c
+3
-27
drivers/gpu/drm/i915/i915_drv.h
+3
-27
drivers/gpu/drm/i915/i915_drv.h
···
507
507
(IS_PLATFORM(i915, INTEL_IRONLAKE) && IS_MOBILE(i915))
508
508
#define IS_SANDYBRIDGE(i915) IS_PLATFORM(i915, INTEL_SANDYBRIDGE)
509
509
#define IS_IVYBRIDGE(i915) IS_PLATFORM(i915, INTEL_IVYBRIDGE)
510
-
#define IS_IVB_GT1(i915) (IS_IVYBRIDGE(i915) && \
511
-
INTEL_INFO(i915)->gt == 1)
512
510
#define IS_VALLEYVIEW(i915) IS_PLATFORM(i915, INTEL_VALLEYVIEW)
513
511
#define IS_CHERRYVIEW(i915) IS_PLATFORM(i915, INTEL_CHERRYVIEW)
514
512
#define IS_HASWELL(i915) IS_PLATFORM(i915, INTEL_HASWELL)
···
536
538
*/
537
539
#define IS_LUNARLAKE(i915) (0 && i915)
538
540
#define IS_BATTLEMAGE(i915) (0 && i915)
541
+
#define IS_PANTHERLAKE(i915) (0 && i915)
539
542
540
543
#define IS_ARROWLAKE(i915) \
541
544
IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL)
···
560
561
IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
561
562
#define IS_BROADWELL_ULX(i915) \
562
563
IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
563
-
#define IS_BROADWELL_GT3(i915) (IS_BROADWELL(i915) && \
564
-
INTEL_INFO(i915)->gt == 3)
565
564
#define IS_HASWELL_ULT(i915) \
566
565
IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
567
-
#define IS_HASWELL_GT3(i915) (IS_HASWELL(i915) && \
568
-
INTEL_INFO(i915)->gt == 3)
569
-
#define IS_HASWELL_GT1(i915) (IS_HASWELL(i915) && \
570
-
INTEL_INFO(i915)->gt == 1)
571
566
/* ULX machines are also considered ULT. */
572
567
#define IS_HASWELL_ULX(i915) \
573
568
IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
···
573
580
IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
574
581
#define IS_KABYLAKE_ULX(i915) \
575
582
IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
576
-
#define IS_SKYLAKE_GT2(i915) (IS_SKYLAKE(i915) && \
577
-
INTEL_INFO(i915)->gt == 2)
578
-
#define IS_SKYLAKE_GT3(i915) (IS_SKYLAKE(i915) && \
579
-
INTEL_INFO(i915)->gt == 3)
580
-
#define IS_SKYLAKE_GT4(i915) (IS_SKYLAKE(i915) && \
581
-
INTEL_INFO(i915)->gt == 4)
582
-
#define IS_KABYLAKE_GT2(i915) (IS_KABYLAKE(i915) && \
583
-
INTEL_INFO(i915)->gt == 2)
584
-
#define IS_KABYLAKE_GT3(i915) (IS_KABYLAKE(i915) && \
585
-
INTEL_INFO(i915)->gt == 3)
586
583
#define IS_COFFEELAKE_ULT(i915) \
587
584
IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
588
585
#define IS_COFFEELAKE_ULX(i915) \
589
586
IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
590
-
#define IS_COFFEELAKE_GT2(i915) (IS_COFFEELAKE(i915) && \
591
-
INTEL_INFO(i915)->gt == 2)
592
-
#define IS_COFFEELAKE_GT3(i915) (IS_COFFEELAKE(i915) && \
593
-
INTEL_INFO(i915)->gt == 3)
594
-
595
587
#define IS_COMETLAKE_ULT(i915) \
596
588
IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
597
589
#define IS_COMETLAKE_ULX(i915) \
598
590
IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
599
-
#define IS_COMETLAKE_GT2(i915) (IS_COMETLAKE(i915) && \
600
-
INTEL_INFO(i915)->gt == 2)
601
591
602
592
#define IS_ICL_WITH_PORT_F(i915) \
603
593
IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
···
653
677
654
678
/* WaRsDisableCoarsePowerGating:skl,cnl */
655
679
#define NEEDS_WaRsDisableCoarsePowerGating(i915) \
656
-
(IS_SKYLAKE_GT3(i915) || IS_SKYLAKE_GT4(i915))
680
+
(IS_SKYLAKE(i915) && (INTEL_INFO(i915)->gt == 3 || INTEL_INFO(i915)->gt == 4))
657
681
658
682
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
659
683
* rows, which changed the alignment requirements and fence programming.
···
717
741
718
742
/* DPF == dynamic parity feature */
719
743
#define HAS_L3_DPF(i915) (INTEL_INFO(i915)->has_l3_dpf)
720
-
#define NUM_L3_SLICES(i915) (IS_HASWELL_GT3(i915) ? \
744
+
#define NUM_L3_SLICES(i915) (IS_HASWELL(i915) && INTEL_INFO(i915)->gt == 3 ? \
721
745
2 : HAS_L3_DPF(i915))
722
746
723
747
#define HAS_GUC_DEPRIVILEGE(i915) \
+18
-18
drivers/gpu/drm/i915/i915_irq.c
+18
-18
drivers/gpu/drm/i915/i915_irq.c
···
77
77
WRITE_ONCE(i915->pmu.irq_count, i915->pmu.irq_count + 1);
78
78
}
79
79
80
-
void gen3_irq_reset(struct intel_uncore *uncore, struct i915_irq_regs regs)
80
+
void gen2_irq_reset(struct intel_uncore *uncore, struct i915_irq_regs regs)
81
81
{
82
82
intel_uncore_write(uncore, regs.imr, 0xffffffff);
83
83
intel_uncore_posting_read(uncore, regs.imr);
···
94
94
/*
95
95
* We should clear IMR at preinstall/uninstall, and just check at postinstall.
96
96
*/
97
-
void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
97
+
void gen2_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
98
98
{
99
99
u32 val = intel_uncore_read(uncore, reg);
100
100
···
110
110
intel_uncore_posting_read(uncore, reg);
111
111
}
112
112
113
-
void gen3_irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs,
113
+
void gen2_irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs,
114
114
u32 imr_val, u32 ier_val)
115
115
{
116
-
gen3_assert_iir_is_zero(uncore, regs.iir);
116
+
gen2_assert_iir_is_zero(uncore, regs.iir);
117
117
118
118
intel_uncore_write(uncore, regs.ier, ier_val);
119
119
intel_uncore_write(uncore, regs.imr, imr_val);
···
622
622
if (HAS_PCH_NOP(dev_priv))
623
623
return;
624
624
625
-
gen3_irq_reset(uncore, SDE_IRQ_REGS);
625
+
gen2_irq_reset(uncore, SDE_IRQ_REGS);
626
626
627
627
if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
628
628
intel_uncore_write(&dev_priv->uncore, SERR_INT, 0xffffffff);
···
634
634
{
635
635
struct intel_uncore *uncore = &dev_priv->uncore;
636
636
637
-
gen3_irq_reset(uncore, DE_IRQ_REGS);
637
+
gen2_irq_reset(uncore, DE_IRQ_REGS);
638
638
dev_priv->irq_mask = ~0u;
639
639
640
640
if (GRAPHICS_VER(dev_priv) == 7)
···
671
671
672
672
gen8_gt_irq_reset(to_gt(dev_priv));
673
673
gen8_display_irq_reset(dev_priv);
674
-
gen3_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
674
+
gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
675
675
676
676
if (HAS_PCH_SPLIT(dev_priv))
677
677
ibx_irq_reset(dev_priv);
···
688
688
gen11_gt_irq_reset(gt);
689
689
gen11_display_irq_reset(dev_priv);
690
690
691
-
gen3_irq_reset(uncore, GEN11_GU_MISC_IRQ_REGS);
692
-
gen3_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
691
+
gen2_irq_reset(uncore, GEN11_GU_MISC_IRQ_REGS);
692
+
gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
693
693
}
694
694
695
695
static void dg1_irq_reset(struct drm_i915_private *dev_priv)
···
705
705
706
706
gen11_display_irq_reset(dev_priv);
707
707
708
-
gen3_irq_reset(uncore, GEN11_GU_MISC_IRQ_REGS);
709
-
gen3_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
708
+
gen2_irq_reset(uncore, GEN11_GU_MISC_IRQ_REGS);
709
+
gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
710
710
711
711
intel_uncore_write(uncore, GEN11_GFX_MSTR_IRQ, ~0);
712
712
}
···
720
720
721
721
gen8_gt_irq_reset(to_gt(dev_priv));
722
722
723
-
gen3_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
723
+
gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);
724
724
725
725
spin_lock_irq(&dev_priv->irq_lock);
726
726
if (dev_priv->display.irq.display_irqs_enabled)
···
765
765
gen11_gt_irq_postinstall(gt);
766
766
gen11_de_irq_postinstall(dev_priv);
767
767
768
-
gen3_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked);
768
+
gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked);
769
769
770
770
gen11_master_intr_enable(intel_uncore_regs(uncore));
771
771
intel_uncore_posting_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ);
···
781
781
for_each_gt(gt, dev_priv, i)
782
782
gen11_gt_irq_postinstall(gt);
783
783
784
-
gen3_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked);
784
+
gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked);
785
785
786
786
dg1_de_irq_postinstall(dev_priv);
787
787
···
869
869
870
870
i9xx_display_irq_reset(dev_priv);
871
871
872
-
gen3_irq_reset(uncore, GEN2_IRQ_REGS);
872
+
gen2_irq_reset(uncore, GEN2_IRQ_REGS);
873
873
dev_priv->irq_mask = ~0u;
874
874
}
875
875
···
901
901
enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
902
902
}
903
903
904
-
gen3_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->irq_mask, enable_mask);
904
+
gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->irq_mask, enable_mask);
905
905
906
906
/* Interrupt setup is already guaranteed to be single-threaded, this is
907
907
* just to make the assert_spin_locked check happy. */
···
974
974
975
975
i9xx_display_irq_reset(dev_priv);
976
976
977
-
gen3_irq_reset(uncore, GEN2_IRQ_REGS);
977
+
gen2_irq_reset(uncore, GEN2_IRQ_REGS);
978
978
dev_priv->irq_mask = ~0u;
979
979
}
980
980
···
1022
1022
if (IS_G4X(dev_priv))
1023
1023
enable_mask |= I915_BSD_USER_INTERRUPT;
1024
1024
1025
-
gen3_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->irq_mask, enable_mask);
1025
+
gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->irq_mask, enable_mask);
1026
1026
1027
1027
/* Interrupt setup is already guaranteed to be single-threaded, this is
1028
1028
* just to make the assert_spin_locked check happy. */
+3
-3
drivers/gpu/drm/i915/i915_irq.h
+3
-3
drivers/gpu/drm/i915/i915_irq.h
···
40
40
void intel_synchronize_irq(struct drm_i915_private *i915);
41
41
void intel_synchronize_hardirq(struct drm_i915_private *i915);
42
42
43
-
void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg);
43
+
void gen2_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg);
44
44
45
-
void gen3_irq_reset(struct intel_uncore *uncore, struct i915_irq_regs regs);
45
+
void gen2_irq_reset(struct intel_uncore *uncore, struct i915_irq_regs regs);
46
46
47
-
void gen3_irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs,
47
+
void gen2_irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs,
48
48
u32 imr_val, u32 ier_val);
49
49
50
50
#endif /* __I915_IRQ_H__ */
+1
-1
drivers/gpu/drm/i915/i915_pci.c
+1
-1
drivers/gpu/drm/i915/i915_pci.c
+3
-9
drivers/gpu/drm/i915/i915_reg.h
+3
-9
drivers/gpu/drm/i915/i915_reg.h
···
1735
1735
#define PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK REG_GENMASK(2, 0) /* tgl+ */
1736
1736
#define PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id) REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id))
1737
1737
1738
-
#define _ICL_PIPE_A_STATUS 0x70058
1739
-
#define ICL_PIPESTATUS(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _ICL_PIPE_A_STATUS)
1740
-
#define PIPE_STATUS_UNDERRUN REG_BIT(31)
1741
-
#define PIPE_STATUS_SOFT_UNDERRUN_XELPD REG_BIT(28)
1742
-
#define PIPE_STATUS_HARD_UNDERRUN_XELPD REG_BIT(27)
1743
-
#define PIPE_STATUS_PORT_UNDERRUN_XELPD REG_BIT(26)
1744
-
1745
1738
#define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
1746
1739
#define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29)
1747
1740
#define PIPEB_HLINE_INT_EN REG_BIT(28)
···
2505
2512
#define GEN12_PIPEDMC_INTERRUPT REG_BIT(26) /* tgl+ */
2506
2513
#define GEN12_PIPEDMC_FAULT REG_BIT(25) /* tgl+ */
2507
2514
#define MTL_PIPEDMC_ATS_FAULT REG_BIT(24) /* mtl+ */
2508
-
#define XELPD_PIPE_SOFT_UNDERRUN REG_BIT(22) /* adl/dg2+ */
2509
2515
#define GEN11_PIPE_PLANE7_FAULT REG_BIT(22) /* icl/tgl */
2510
-
#define XELPD_PIPE_HARD_UNDERRUN REG_BIT(21) /* adl/dg2+ */
2511
2516
#define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) /* icl/tgl */
2512
2517
#define GEN11_PIPE_PLANE5_FAULT REG_BIT(20) /* icl+ */
2513
2518
#define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) /* tgl+ */
···
2589
2598
#define GEN8_DE_MISC_GSE REG_BIT(27)
2590
2599
#define GEN8_DE_EDP_PSR REG_BIT(19)
2591
2600
#define XELPDP_PMDEMAND_RSP REG_BIT(3)
2601
+
#define XE2LPD_DBUF_OVERLAP_DETECTED REG_BIT(1)
2592
2602
2593
2603
#define GEN8_DE_MISC_IRQ_REGS I915_IRQ_REGS(GEN8_DE_MISC_IMR, \
2594
2604
GEN8_DE_MISC_IER, \
···
2697
2705
#define XELPDP_PMDEMAND_QCLK_GV_BW_MASK REG_GENMASK(31, 16)
2698
2706
#define XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK REG_GENMASK(14, 12)
2699
2707
#define XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK REG_GENMASK(11, 8)
2708
+
#define XE3_PMDEMAND_PIPES_MASK REG_GENMASK(7, 4)
2700
2709
#define XELPDP_PMDEMAND_PIPES_MASK REG_GENMASK(7, 6)
2701
2710
#define XELPDP_PMDEMAND_DBUFS_MASK REG_GENMASK(5, 4)
2702
2711
#define XELPDP_PMDEMAND_PHYS_MASK REG_GENMASK(2, 0)
···
2896
2903
#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
2897
2904
#define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
2898
2905
#define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
2906
+
#define XE2LPD_DFSM_DBUF_OVERLAP_DISABLE (1 << 3)
2899
2907
2900
2908
#define XE2LPD_DE_CAP _MMIO(0x41100)
2901
2909
#define XE2LPD_DE_CAP_3DLUT_MASK REG_GENMASK(31, 30)
+1
-1
drivers/gpu/drm/i915/i915_suspend.c
+1
-1
drivers/gpu/drm/i915/i915_suspend.c
+1
-1
drivers/gpu/drm/i915/intel_clock_gating.c
+1
-1
drivers/gpu/drm/i915/intel_clock_gating.c
+1
-1
drivers/gpu/drm/i915/intel_device_info.c
+1
-1
drivers/gpu/drm/i915/intel_device_info.c
+7
-1
drivers/gpu/drm/i915/intel_runtime_pm.h
+7
-1
drivers/gpu/drm/i915/intel_runtime_pm.h
···
96
96
return wakeref_count >> INTEL_RPM_WAKELOCK_SHIFT;
97
97
}
98
98
99
+
static inline bool
100
+
intel_runtime_pm_suspended(struct intel_runtime_pm *rpm)
101
+
{
102
+
return pm_runtime_suspended(rpm->kdev);
103
+
}
104
+
99
105
static inline void
100
106
assert_rpm_device_not_suspended(struct intel_runtime_pm *rpm)
101
107
{
102
-
WARN_ONCE(pm_runtime_suspended(rpm->kdev),
108
+
WARN_ONCE(intel_runtime_pm_suspended(rpm),
103
109
"Device suspended during HW access\n");
104
110
}
105
111
+1
drivers/gpu/drm/xe/Makefile
+1
drivers/gpu/drm/xe/Makefile
+1
-2
drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
+1
-2
drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
···
67
67
#define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE)
68
68
#define IS_LUNARLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_LUNARLAKE)
69
69
#define IS_BATTLEMAGE(dev_priv) IS_PLATFORM(dev_priv, XE_BATTLEMAGE)
70
+
#define IS_PANTHERLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_PANTHERLAKE)
70
71
71
72
#define IS_HASWELL_ULT(dev_priv) (dev_priv && 0)
72
73
#define IS_BROADWELL_ULT(dev_priv) (dev_priv && 0)
73
74
#define IS_BROADWELL_ULX(dev_priv) (dev_priv && 0)
74
-
75
-
#define IP_VER(ver, rel) ((ver) << 8 | (rel))
76
75
77
76
#define IS_MOBILE(xe) (xe && 0)
78
77
+8
drivers/gpu/drm/xe/compat-i915-headers/intel_runtime_pm.h
+8
drivers/gpu/drm/xe/compat-i915-headers/intel_runtime_pm.h
···
20
20
{
21
21
}
22
22
23
+
static inline bool
24
+
intel_runtime_pm_suspended(struct xe_runtime_pm *pm)
25
+
{
26
+
struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm);
27
+
28
+
return pm_runtime_suspended(xe->drm.dev);
29
+
}
30
+
23
31
static inline intel_wakeref_t intel_runtime_pm_get(struct xe_runtime_pm *pm)
24
32
{
25
33
struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm);
+4
-4
drivers/gpu/drm/xe/display/ext/i915_irq.c
+4
-4
drivers/gpu/drm/xe/display/ext/i915_irq.c
···
7
7
#include "i915_reg.h"
8
8
#include "intel_uncore.h"
9
9
10
-
void gen3_irq_reset(struct intel_uncore *uncore, struct i915_irq_regs regs)
10
+
void gen2_irq_reset(struct intel_uncore *uncore, struct i915_irq_regs regs)
11
11
{
12
12
intel_uncore_write(uncore, regs.imr, 0xffffffff);
13
13
intel_uncore_posting_read(uncore, regs.imr);
···
24
24
/*
25
25
* We should clear IMR at preinstall/uninstall, and just check at postinstall.
26
26
*/
27
-
void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
27
+
void gen2_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
28
28
{
29
29
struct xe_device *xe = container_of(uncore, struct xe_device, uncore);
30
30
u32 val = intel_uncore_read(uncore, reg);
···
41
41
intel_uncore_posting_read(uncore, reg);
42
42
}
43
43
44
-
void gen3_irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs,
44
+
void gen2_irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs,
45
45
u32 imr_val, u32 ier_val)
46
46
{
47
-
gen3_assert_iir_is_zero(uncore, regs.iir);
47
+
gen2_assert_iir_is_zero(uncore, regs.iir);
48
48
49
49
intel_uncore_write(uncore, regs.ier, ier_val);
50
50
intel_uncore_write(uncore, regs.imr, imr_val);
+3
-1
drivers/gpu/drm/xe/display/xe_display.c
+3
-1
drivers/gpu/drm/xe/display/xe_display.c
···
202
202
203
203
void xe_display_fini(struct xe_device *xe)
204
204
{
205
+
struct intel_display *display = &xe->display;
206
+
205
207
if (!xe->info.probe_display)
206
208
return;
207
209
208
210
intel_hpd_poll_fini(xe);
209
211
210
-
intel_hdcp_component_fini(xe);
212
+
intel_hdcp_component_fini(display);
211
213
intel_audio_deinit(xe);
212
214
}
213
215
+1
-1
drivers/gpu/drm/xe/display/xe_hdcp_gsc.c
+1
-1
drivers/gpu/drm/xe/display/xe_hdcp_gsc.c
+23
-30
drivers/gpu/drm/xe/xe_pci.c
+23
-30
drivers/gpu/drm/xe/xe_pci.c
···
13
13
14
14
#include <drm/drm_color_mgmt.h>
15
15
#include <drm/drm_drv.h>
16
-
#include <drm/intel/xe_pciids.h>
16
+
#include <drm/intel/pciids.h>
17
17
18
18
#include "display/xe_display.h"
19
19
#include "regs/xe_gt_regs.h"
···
233
233
.require_force_probe = true,
234
234
};
235
235
236
-
static const u16 adls_rpls_ids[] = { XE_RPLS_IDS(NOP), 0 };
236
+
static const u16 adls_rpls_ids[] = { INTEL_RPLS_IDS(NOP), 0 };
237
237
238
238
static const struct xe_device_desc adl_s_desc = {
239
239
.graphics = &graphics_xelp,
···
248
248
},
249
249
};
250
250
251
-
static const u16 adlp_rplu_ids[] = { XE_RPLU_IDS(NOP), 0 };
251
+
static const u16 adlp_rplu_ids[] = { INTEL_RPLU_IDS(NOP), 0 };
252
252
253
253
static const struct xe_device_desc adl_p_desc = {
254
254
.graphics = &graphics_xelp,
···
285
285
.require_force_probe = true,
286
286
};
287
287
288
-
static const u16 dg2_g10_ids[] = { XE_DG2_G10_IDS(NOP), XE_ATS_M150_IDS(NOP), 0 };
289
-
static const u16 dg2_g11_ids[] = { XE_DG2_G11_IDS(NOP), XE_ATS_M75_IDS(NOP), 0 };
290
-
static const u16 dg2_g12_ids[] = { XE_DG2_G12_IDS(NOP), 0 };
288
+
static const u16 dg2_g10_ids[] = { INTEL_DG2_G10_IDS(NOP), INTEL_ATS_M150_IDS(NOP), 0 };
289
+
static const u16 dg2_g11_ids[] = { INTEL_DG2_G11_IDS(NOP), INTEL_ATS_M75_IDS(NOP), 0 };
290
+
static const u16 dg2_g12_ids[] = { INTEL_DG2_G12_IDS(NOP), 0 };
291
291
292
292
#define DG2_FEATURES \
293
293
DGFX_FEATURES, \
···
348
348
349
349
static const struct xe_device_desc ptl_desc = {
350
350
PLATFORM(PANTHERLAKE),
351
-
.has_display = false,
351
+
.has_display = true,
352
352
.require_force_probe = true,
353
353
};
354
354
···
374
374
{ 3000, &media_xe2 },
375
375
};
376
376
377
-
#define INTEL_VGA_DEVICE(id, info) { \
378
-
PCI_DEVICE(PCI_VENDOR_ID_INTEL, id), \
379
-
PCI_BASE_CLASS_DISPLAY << 16, 0xff << 16, \
380
-
(unsigned long) info }
381
-
382
377
/*
383
378
* Make sure any device matches here are from most specific to most
384
379
* general. For example, since the Quanta match is based on the subsystem
···
381
386
* PCI ID matches, otherwise we'll use the wrong info struct above.
382
387
*/
383
388
static const struct pci_device_id pciidlist[] = {
384
-
XE_TGL_IDS(INTEL_VGA_DEVICE, &tgl_desc),
385
-
XE_RKL_IDS(INTEL_VGA_DEVICE, &rkl_desc),
386
-
XE_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc),
387
-
XE_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
388
-
XE_ADLN_IDS(INTEL_VGA_DEVICE, &adl_n_desc),
389
-
XE_RPLU_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
390
-
XE_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
391
-
XE_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc),
392
-
XE_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc),
393
-
XE_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc),
394
-
XE_ARL_IDS(INTEL_VGA_DEVICE, &mtl_desc),
395
-
XE_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc),
396
-
XE_MTL_IDS(INTEL_VGA_DEVICE, &mtl_desc),
397
-
XE_LNL_IDS(INTEL_VGA_DEVICE, &lnl_desc),
398
-
XE_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc),
399
-
XE_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
389
+
INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_desc),
390
+
INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_desc),
391
+
INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc),
392
+
INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
393
+
INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &adl_n_desc),
394
+
INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
395
+
INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
396
+
INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc),
397
+
INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc),
398
+
INTEL_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc),
399
+
INTEL_ARL_IDS(INTEL_VGA_DEVICE, &mtl_desc),
400
+
INTEL_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc),
401
+
INTEL_MTL_IDS(INTEL_VGA_DEVICE, &mtl_desc),
402
+
INTEL_LNL_IDS(INTEL_VGA_DEVICE, &lnl_desc),
403
+
INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc),
404
+
INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
400
405
{ }
401
406
};
402
407
MODULE_DEVICE_TABLE(pci, pciidlist);
403
-
404
-
#undef INTEL_VGA_DEVICE
405
408
406
409
/* is device_id present in comma separated list of ids */
407
410
static bool device_id_in_list(u16 device_id, const char *devices, bool negative)
+31
-3
include/drm/intel/i915_pciids.h
include/drm/intel/pciids.h
+31
-3
include/drm/intel/i915_pciids.h
include/drm/intel/pciids.h
···
22
22
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23
23
* DEALINGS IN THE SOFTWARE.
24
24
*/
25
-
#ifndef _I915_PCIIDS_H
26
-
#define _I915_PCIIDS_H
25
+
#ifndef __PCIIDS_H__
26
+
#define __PCIIDS_H__
27
27
28
28
#ifdef __KERNEL__
29
29
#define INTEL_VGA_DEVICE(_id, _info) { \
···
780
780
MACRO__(0x7D60, ## __VA_ARGS__), \
781
781
MACRO__(0x7DD5, ## __VA_ARGS__)
782
782
783
+
/* PVC */
784
+
#define INTEL_PVC_IDS(MACRO__, ...) \
785
+
MACRO__(0x0B69, ## __VA_ARGS__), \
786
+
MACRO__(0x0B6E, ## __VA_ARGS__), \
787
+
MACRO__(0x0BD4, ## __VA_ARGS__), \
788
+
MACRO__(0x0BD5, ## __VA_ARGS__), \
789
+
MACRO__(0x0BD6, ## __VA_ARGS__), \
790
+
MACRO__(0x0BD7, ## __VA_ARGS__), \
791
+
MACRO__(0x0BD8, ## __VA_ARGS__), \
792
+
MACRO__(0x0BD9, ## __VA_ARGS__), \
793
+
MACRO__(0x0BDA, ## __VA_ARGS__), \
794
+
MACRO__(0x0BDB, ## __VA_ARGS__), \
795
+
MACRO__(0x0BE0, ## __VA_ARGS__), \
796
+
MACRO__(0x0BE1, ## __VA_ARGS__), \
797
+
MACRO__(0x0BE5, ## __VA_ARGS__)
798
+
783
799
/* LNL */
784
800
#define INTEL_LNL_IDS(MACRO__, ...) \
785
801
MACRO__(0x6420, ## __VA_ARGS__), \
···
810
794
MACRO__(0xE20D, ## __VA_ARGS__), \
811
795
MACRO__(0xE212, ## __VA_ARGS__)
812
796
813
-
#endif /* _I915_PCIIDS_H */
797
+
/* PTL */
798
+
#define INTEL_PTL_IDS(MACRO__, ...) \
799
+
MACRO__(0xB080, ## __VA_ARGS__), \
800
+
MACRO__(0xB081, ## __VA_ARGS__), \
801
+
MACRO__(0xB082, ## __VA_ARGS__), \
802
+
MACRO__(0xB090, ## __VA_ARGS__), \
803
+
MACRO__(0xB091, ## __VA_ARGS__), \
804
+
MACRO__(0xB092, ## __VA_ARGS__), \
805
+
MACRO__(0xB0A0, ## __VA_ARGS__), \
806
+
MACRO__(0xB0A1, ## __VA_ARGS__), \
807
+
MACRO__(0xB0A2, ## __VA_ARGS__)
808
+
809
+
#endif /* __PCIIDS_H__ */
-234
include/drm/intel/xe_pciids.h
-234
include/drm/intel/xe_pciids.h
···
1
-
/* SPDX-License-Identifier: MIT */
2
-
/*
3
-
* Copyright © 2022 Intel Corporation
4
-
*/
5
-
6
-
#ifndef _XE_PCIIDS_H_
7
-
#define _XE_PCIIDS_H_
8
-
9
-
/*
10
-
* Lists below can be turned into initializers for a struct pci_device_id
11
-
* by defining INTEL_VGA_DEVICE:
12
-
*
13
-
* #define INTEL_VGA_DEVICE(id, info) { \
14
-
* 0x8086, id, \
15
-
* ~0, ~0, \
16
-
* 0x030000, 0xff0000, \
17
-
* (unsigned long) info }
18
-
*
19
-
* And then calling like:
20
-
*
21
-
* XE_TGL_12_GT1_IDS(INTEL_VGA_DEVICE, ## __VA_ARGS__)
22
-
*
23
-
* To turn them into something else, just provide a different macro passed as
24
-
* first argument.
25
-
*/
26
-
27
-
/* TGL */
28
-
#define XE_TGL_GT1_IDS(MACRO__, ...) \
29
-
MACRO__(0x9A60, ## __VA_ARGS__), \
30
-
MACRO__(0x9A68, ## __VA_ARGS__), \
31
-
MACRO__(0x9A70, ## __VA_ARGS__)
32
-
33
-
#define XE_TGL_GT2_IDS(MACRO__, ...) \
34
-
MACRO__(0x9A40, ## __VA_ARGS__), \
35
-
MACRO__(0x9A49, ## __VA_ARGS__), \
36
-
MACRO__(0x9A59, ## __VA_ARGS__), \
37
-
MACRO__(0x9A78, ## __VA_ARGS__), \
38
-
MACRO__(0x9AC0, ## __VA_ARGS__), \
39
-
MACRO__(0x9AC9, ## __VA_ARGS__), \
40
-
MACRO__(0x9AD9, ## __VA_ARGS__), \
41
-
MACRO__(0x9AF8, ## __VA_ARGS__)
42
-
43
-
#define XE_TGL_IDS(MACRO__, ...) \
44
-
XE_TGL_GT1_IDS(MACRO__, ## __VA_ARGS__),\
45
-
XE_TGL_GT2_IDS(MACRO__, ## __VA_ARGS__)
46
-
47
-
/* RKL */
48
-
#define XE_RKL_IDS(MACRO__, ...) \
49
-
MACRO__(0x4C80, ## __VA_ARGS__), \
50
-
MACRO__(0x4C8A, ## __VA_ARGS__), \
51
-
MACRO__(0x4C8B, ## __VA_ARGS__), \
52
-
MACRO__(0x4C8C, ## __VA_ARGS__), \
53
-
MACRO__(0x4C90, ## __VA_ARGS__), \
54
-
MACRO__(0x4C9A, ## __VA_ARGS__)
55
-
56
-
/* DG1 */
57
-
#define XE_DG1_IDS(MACRO__, ...) \
58
-
MACRO__(0x4905, ## __VA_ARGS__), \
59
-
MACRO__(0x4906, ## __VA_ARGS__), \
60
-
MACRO__(0x4907, ## __VA_ARGS__), \
61
-
MACRO__(0x4908, ## __VA_ARGS__), \
62
-
MACRO__(0x4909, ## __VA_ARGS__)
63
-
64
-
/* ADL-S */
65
-
#define XE_ADLS_IDS(MACRO__, ...) \
66
-
MACRO__(0x4680, ## __VA_ARGS__), \
67
-
MACRO__(0x4682, ## __VA_ARGS__), \
68
-
MACRO__(0x4688, ## __VA_ARGS__), \
69
-
MACRO__(0x468A, ## __VA_ARGS__), \
70
-
MACRO__(0x468B, ## __VA_ARGS__), \
71
-
MACRO__(0x4690, ## __VA_ARGS__), \
72
-
MACRO__(0x4692, ## __VA_ARGS__), \
73
-
MACRO__(0x4693, ## __VA_ARGS__)
74
-
75
-
/* ADL-P */
76
-
#define XE_ADLP_IDS(MACRO__, ...) \
77
-
MACRO__(0x46A0, ## __VA_ARGS__), \
78
-
MACRO__(0x46A1, ## __VA_ARGS__), \
79
-
MACRO__(0x46A2, ## __VA_ARGS__), \
80
-
MACRO__(0x46A3, ## __VA_ARGS__), \
81
-
MACRO__(0x46A6, ## __VA_ARGS__), \
82
-
MACRO__(0x46A8, ## __VA_ARGS__), \
83
-
MACRO__(0x46AA, ## __VA_ARGS__), \
84
-
MACRO__(0x462A, ## __VA_ARGS__), \
85
-
MACRO__(0x4626, ## __VA_ARGS__), \
86
-
MACRO__(0x4628, ## __VA_ARGS__), \
87
-
MACRO__(0x46B0, ## __VA_ARGS__), \
88
-
MACRO__(0x46B1, ## __VA_ARGS__), \
89
-
MACRO__(0x46B2, ## __VA_ARGS__), \
90
-
MACRO__(0x46B3, ## __VA_ARGS__), \
91
-
MACRO__(0x46C0, ## __VA_ARGS__), \
92
-
MACRO__(0x46C1, ## __VA_ARGS__), \
93
-
MACRO__(0x46C2, ## __VA_ARGS__), \
94
-
MACRO__(0x46C3, ## __VA_ARGS__)
95
-
96
-
/* ADL-N */
97
-
#define XE_ADLN_IDS(MACRO__, ...) \
98
-
MACRO__(0x46D0, ## __VA_ARGS__), \
99
-
MACRO__(0x46D1, ## __VA_ARGS__), \
100
-
MACRO__(0x46D2, ## __VA_ARGS__), \
101
-
MACRO__(0x46D3, ## __VA_ARGS__), \
102
-
MACRO__(0x46D4, ## __VA_ARGS__)
103
-
104
-
/* RPL-S */
105
-
#define XE_RPLS_IDS(MACRO__, ...) \
106
-
MACRO__(0xA780, ## __VA_ARGS__), \
107
-
MACRO__(0xA781, ## __VA_ARGS__), \
108
-
MACRO__(0xA782, ## __VA_ARGS__), \
109
-
MACRO__(0xA783, ## __VA_ARGS__), \
110
-
MACRO__(0xA788, ## __VA_ARGS__), \
111
-
MACRO__(0xA789, ## __VA_ARGS__), \
112
-
MACRO__(0xA78A, ## __VA_ARGS__), \
113
-
MACRO__(0xA78B, ## __VA_ARGS__)
114
-
115
-
/* RPL-U */
116
-
#define XE_RPLU_IDS(MACRO__, ...) \
117
-
MACRO__(0xA721, ## __VA_ARGS__), \
118
-
MACRO__(0xA7A1, ## __VA_ARGS__), \
119
-
MACRO__(0xA7A9, ## __VA_ARGS__), \
120
-
MACRO__(0xA7AC, ## __VA_ARGS__), \
121
-
MACRO__(0xA7AD, ## __VA_ARGS__)
122
-
123
-
/* RPL-P */
124
-
#define XE_RPLP_IDS(MACRO__, ...) \
125
-
MACRO__(0xA720, ## __VA_ARGS__), \
126
-
MACRO__(0xA7A0, ## __VA_ARGS__), \
127
-
MACRO__(0xA7A8, ## __VA_ARGS__), \
128
-
MACRO__(0xA7AA, ## __VA_ARGS__), \
129
-
MACRO__(0xA7AB, ## __VA_ARGS__)
130
-
131
-
/* DG2 */
132
-
#define XE_DG2_G10_IDS(MACRO__, ...) \
133
-
MACRO__(0x5690, ## __VA_ARGS__), \
134
-
MACRO__(0x5691, ## __VA_ARGS__), \
135
-
MACRO__(0x5692, ## __VA_ARGS__), \
136
-
MACRO__(0x56A0, ## __VA_ARGS__), \
137
-
MACRO__(0x56A1, ## __VA_ARGS__), \
138
-
MACRO__(0x56A2, ## __VA_ARGS__), \
139
-
MACRO__(0x56BE, ## __VA_ARGS__), \
140
-
MACRO__(0x56BF, ## __VA_ARGS__)
141
-
142
-
#define XE_DG2_G11_IDS(MACRO__, ...) \
143
-
MACRO__(0x5693, ## __VA_ARGS__), \
144
-
MACRO__(0x5694, ## __VA_ARGS__), \
145
-
MACRO__(0x5695, ## __VA_ARGS__), \
146
-
MACRO__(0x56A5, ## __VA_ARGS__), \
147
-
MACRO__(0x56A6, ## __VA_ARGS__), \
148
-
MACRO__(0x56B0, ## __VA_ARGS__), \
149
-
MACRO__(0x56B1, ## __VA_ARGS__), \
150
-
MACRO__(0x56BA, ## __VA_ARGS__), \
151
-
MACRO__(0x56BB, ## __VA_ARGS__), \
152
-
MACRO__(0x56BC, ## __VA_ARGS__), \
153
-
MACRO__(0x56BD, ## __VA_ARGS__)
154
-
155
-
#define XE_DG2_G12_IDS(MACRO__, ...) \
156
-
MACRO__(0x5696, ## __VA_ARGS__), \
157
-
MACRO__(0x5697, ## __VA_ARGS__), \
158
-
MACRO__(0x56A3, ## __VA_ARGS__), \
159
-
MACRO__(0x56A4, ## __VA_ARGS__), \
160
-
MACRO__(0x56B2, ## __VA_ARGS__), \
161
-
MACRO__(0x56B3, ## __VA_ARGS__)
162
-
163
-
#define XE_DG2_IDS(MACRO__, ...) \
164
-
XE_DG2_G10_IDS(MACRO__, ## __VA_ARGS__),\
165
-
XE_DG2_G11_IDS(MACRO__, ## __VA_ARGS__),\
166
-
XE_DG2_G12_IDS(MACRO__, ## __VA_ARGS__)
167
-
168
-
#define XE_ATS_M150_IDS(MACRO__, ...) \
169
-
MACRO__(0x56C0, ## __VA_ARGS__), \
170
-
MACRO__(0x56C2, ## __VA_ARGS__)
171
-
172
-
#define XE_ATS_M75_IDS(MACRO__, ...) \
173
-
MACRO__(0x56C1, ## __VA_ARGS__)
174
-
175
-
#define XE_ATS_M_IDS(MACRO__, ...) \
176
-
XE_ATS_M150_IDS(MACRO__, ## __VA_ARGS__),\
177
-
XE_ATS_M75_IDS(MACRO__, ## __VA_ARGS__)
178
-
179
-
/* ARL */
180
-
#define XE_ARL_IDS(MACRO__, ...) \
181
-
MACRO__(0x7D41, ## __VA_ARGS__), \
182
-
MACRO__(0x7D51, ## __VA_ARGS__), \
183
-
MACRO__(0x7D67, ## __VA_ARGS__), \
184
-
MACRO__(0x7DD1, ## __VA_ARGS__), \
185
-
MACRO__(0xB640, ## __VA_ARGS__)
186
-
187
-
/* MTL */
188
-
#define XE_MTL_IDS(MACRO__, ...) \
189
-
MACRO__(0x7D40, ## __VA_ARGS__), \
190
-
MACRO__(0x7D45, ## __VA_ARGS__), \
191
-
MACRO__(0x7D55, ## __VA_ARGS__), \
192
-
MACRO__(0x7D60, ## __VA_ARGS__), \
193
-
MACRO__(0x7DD5, ## __VA_ARGS__)
194
-
195
-
/* PVC */
196
-
#define XE_PVC_IDS(MACRO__, ...) \
197
-
MACRO__(0x0B69, ## __VA_ARGS__), \
198
-
MACRO__(0x0B6E, ## __VA_ARGS__), \
199
-
MACRO__(0x0BD4, ## __VA_ARGS__), \
200
-
MACRO__(0x0BD5, ## __VA_ARGS__), \
201
-
MACRO__(0x0BD6, ## __VA_ARGS__), \
202
-
MACRO__(0x0BD7, ## __VA_ARGS__), \
203
-
MACRO__(0x0BD8, ## __VA_ARGS__), \
204
-
MACRO__(0x0BD9, ## __VA_ARGS__), \
205
-
MACRO__(0x0BDA, ## __VA_ARGS__), \
206
-
MACRO__(0x0BDB, ## __VA_ARGS__), \
207
-
MACRO__(0x0BE0, ## __VA_ARGS__), \
208
-
MACRO__(0x0BE1, ## __VA_ARGS__), \
209
-
MACRO__(0x0BE5, ## __VA_ARGS__)
210
-
211
-
#define XE_LNL_IDS(MACRO__, ...) \
212
-
MACRO__(0x6420, ## __VA_ARGS__), \
213
-
MACRO__(0x64A0, ## __VA_ARGS__), \
214
-
MACRO__(0x64B0, ## __VA_ARGS__)
215
-
216
-
#define XE_BMG_IDS(MACRO__, ...) \
217
-
MACRO__(0xE202, ## __VA_ARGS__), \
218
-
MACRO__(0xE20B, ## __VA_ARGS__), \
219
-
MACRO__(0xE20C, ## __VA_ARGS__), \
220
-
MACRO__(0xE20D, ## __VA_ARGS__), \
221
-
MACRO__(0xE212, ## __VA_ARGS__)
222
-
223
-
#define XE_PTL_IDS(MACRO__, ...) \
224
-
MACRO__(0xB080, ## __VA_ARGS__), \
225
-
MACRO__(0xB081, ## __VA_ARGS__), \
226
-
MACRO__(0xB082, ## __VA_ARGS__), \
227
-
MACRO__(0xB090, ## __VA_ARGS__), \
228
-
MACRO__(0xB091, ## __VA_ARGS__), \
229
-
MACRO__(0xB092, ## __VA_ARGS__), \
230
-
MACRO__(0xB0A0, ## __VA_ARGS__), \
231
-
MACRO__(0xB0A1, ## __VA_ARGS__), \
232
-
MACRO__(0xB0A2, ## __VA_ARGS__)
233
-
234
-
#endif