Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: at91: add ACR in all PLL settings
Add the ACR register to all PLL settings and provide the correct
ACR value for each PLL used in different SoCs.
Suggested-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Cristian Birsan <cristian.birsan@microchip.com>
[nicolas.ferre@microchip.com: add sama7d65 and review commit message]
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
authored by
Cristian Birsan
and committed by
Nicolas Ferre
bfa2bddf
94a12741
+14
+1
drivers/clk/at91/pmc.h
+1
drivers/clk/at91/pmc.h
+2
drivers/clk/at91/sam9x60.c
+2
drivers/clk/at91/sam9x60.c
···
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.num_output = ARRAY_SIZE(plla_outputs),
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.output = plla_outputs,
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.core_output = core_outputs,
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+
.acr = UL(0x00020010),
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};
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static const struct clk_range upll_outputs[] = {
···
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.output = upll_outputs,
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.core_output = core_outputs,
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.upll = true,
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.acr = UL(0x12023010), /* fIN = [18 MHz, 32 MHz]*/
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};
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static const struct clk_pll_layout pll_frac_layout = {
+5
drivers/clk/at91/sam9x7.c
+5
drivers/clk/at91/sam9x7.c
···
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.num_output = ARRAY_SIZE(plla_outputs),
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.output = plla_outputs,
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.core_output = plla_core_outputs,
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.acr = UL(0x00020010), /* Old ACR_DEFAULT_PLLA value */
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};
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static const struct clk_pll_characteristics upll_characteristics = {
···
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.output = upll_outputs,
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.core_output = upll_core_outputs,
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.upll = true,
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.acr = UL(0x12023010), /* fIN=[20 MHz, 32 MHz] */
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};
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static const struct clk_pll_characteristics lvdspll_characteristics = {
···
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.num_output = ARRAY_SIZE(lvdspll_outputs),
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.output = lvdspll_outputs,
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.core_output = lvdspll_core_outputs,
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+
.acr = UL(0x12023010), /* fIN=[20 MHz, 32 MHz] */
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};
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static const struct clk_pll_characteristics audiopll_characteristics = {
···
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.num_output = ARRAY_SIZE(audiopll_outputs),
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.output = audiopll_outputs,
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.core_output = audiopll_core_outputs,
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.acr = UL(0x12023010), /* fIN=[20 MHz, 32 MHz] */
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};
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static const struct clk_pll_characteristics plladiv2_characteristics = {
···
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.num_output = ARRAY_SIZE(plladiv2_outputs),
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.output = plladiv2_outputs,
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.core_output = plladiv2_core_outputs,
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+
.acr = UL(0x00020010), /* Old ACR_DEFAULT_PLLA value */
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};
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/* Layout for fractional PLL ID PLLA. */
+4
drivers/clk/at91/sama7d65.c
+4
drivers/clk/at91/sama7d65.c
···
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.num_output = ARRAY_SIZE(cpu_pll_outputs),
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.output = cpu_pll_outputs,
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.core_output = core_outputs,
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.acr = UL(0x00070010),
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};
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/* PLL characteristics. */
···
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.num_output = ARRAY_SIZE(pll_outputs),
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.output = pll_outputs,
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.core_output = core_outputs,
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+
.acr = UL(0x00070010),
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};
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static const struct clk_pll_characteristics lvdspll_characteristics = {
···
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.num_output = ARRAY_SIZE(lvdspll_outputs),
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.output = lvdspll_outputs,
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.core_output = lvdspll_core_outputs,
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.acr = UL(0x00070010),
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};
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static const struct clk_pll_characteristics upll_characteristics = {
···
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.num_output = ARRAY_SIZE(upll_outputs),
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.output = upll_outputs,
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.core_output = upll_core_outputs,
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+
.acr = UL(0x12020010),
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.upll = true,
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};
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+2
drivers/clk/at91/sama7g5.c
+2
drivers/clk/at91/sama7g5.c
···
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.num_output = ARRAY_SIZE(cpu_pll_outputs),
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.output = cpu_pll_outputs,
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.core_output = core_outputs,
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.acr = UL(0x00070010),
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};
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/* PLL characteristics. */
···
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.num_output = ARRAY_SIZE(pll_outputs),
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.output = pll_outputs,
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.core_output = core_outputs,
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+
.acr = UL(0x00070010),
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};
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/*