Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux
Pull clk framework updates from Mike Turquette:
"This is much later than usual due to several last minute bugs that had
to be addressed. As usual the majority of changes are new drivers and
modifications to existing drivers. The core recieved many fixes along
with the groundwork for several large changes coming in the future
which will better parition clock providers from clock consumers"
* tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux: (86 commits)
clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated
ARM: OMAP3: clock: fix boot breakage in legacy mode
ARM: OMAP2+: clock: fix DPLL code to use new determine rate APIs
clk: Really fix deadlock with mmap_sem
clk: mmp: fix sparse non static symbol warning
clk: Change clk_ops->determine_rate to return a clk_hw as the best parent
clk: change clk_debugfs_add_file to take a struct clk_hw
clk: Don't expose __clk_get_accuracy
clk: Don't try to use a struct clk* after it could have been freed
clk: Remove unused function __clk_get_prepare_count
clk: samsung: Fix double add of syscore ops after driver rebind
clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmi
clk: samsung: exynos4415: Fix build with PM_SLEEP disabled
clk: samsung: remove unnecessary inclusion of header files from clk.h
clk: samsung: remove unnecessary CONFIG_OF from clk.c
clk: samsung: Spelling s/bwtween/between/
clk: rockchip: Add support for the mmc clock phases using the framework
clk: rockchip: add bindings for the mmc clocks
clk: rockchip: rk3288 export i2s0_clkout for use in DT
clk: rockchip: use clock ID for DMC (memory controller) on rk3288
...
+6665
-692
+1
-1
Documentation/clk.txt
+1
-1
Documentation/clk.txt
···
74
74
long (*determine_rate)(struct clk_hw *hw,
75
75
unsigned long rate,
76
76
unsigned long *best_parent_rate,
77
-
struct clk **best_parent_clk);
77
+
struct clk_hw **best_parent_clk);
78
78
int (*set_parent)(struct clk_hw *hw, u8 index);
79
79
u8 (*get_parent)(struct clk_hw *hw);
80
80
int (*set_rate)(struct clk_hw *hw,
+38
Documentation/devicetree/bindings/clock/exynos4415-clock.txt
+38
Documentation/devicetree/bindings/clock/exynos4415-clock.txt
···
1
+
* Samsung Exynos4415 Clock Controller
2
+
3
+
The Exynos4415 clock controller generates and supplies clock to various
4
+
consumer devices within the Exynos4415 SoC.
5
+
6
+
Required properties:
7
+
8
+
- compatible: should be one of the following:
9
+
- "samsung,exynos4415-cmu" - for the main system clocks controller
10
+
(CMU_LEFTBUS, CMU_RIGHTBUS, CMU_TOP, CMU_CPU clock domains).
11
+
- "samsung,exynos4415-cmu-dmc" - for the Exynos4415 SoC DRAM Memory
12
+
Controller (DMC) domain clock controller.
13
+
14
+
- reg: physical base address of the controller and length of memory mapped
15
+
region.
16
+
17
+
- #clock-cells: should be 1.
18
+
19
+
Each clock is assigned an identifier and client nodes can use this identifier
20
+
to specify the clock which they consume.
21
+
22
+
All available clocks are defined as preprocessor macros in
23
+
dt-bindings/clock/exynos4415.h header and can be used in device
24
+
tree sources.
25
+
26
+
Example 1: An example of a clock controller node is listed below.
27
+
28
+
cmu: clock-controller@10030000 {
29
+
compatible = "samsung,exynos4415-cmu";
30
+
reg = <0x10030000 0x18000>;
31
+
#clock-cells = <1>;
32
+
};
33
+
34
+
cmu-dmc: clock-controller@105C0000 {
35
+
compatible = "samsung,exynos4415-cmu-dmc";
36
+
reg = <0x105C0000 0x3000>;
37
+
#clock-cells = <1>;
38
+
};
+93
Documentation/devicetree/bindings/clock/exynos7-clock.txt
+93
Documentation/devicetree/bindings/clock/exynos7-clock.txt
···
1
+
* Samsung Exynos7 Clock Controller
2
+
3
+
Exynos7 clock controller has various blocks which are instantiated
4
+
independently from the device-tree. These clock controllers
5
+
generate and supply clocks to various hardware blocks within
6
+
the SoC.
7
+
8
+
Each clock is assigned an identifier and client nodes can use
9
+
this identifier to specify the clock which they consume. All
10
+
available clocks are defined as preprocessor macros in
11
+
dt-bindings/clock/exynos7-clk.h header and can be used in
12
+
device tree sources.
13
+
14
+
External clocks:
15
+
16
+
There are several clocks that are generated outside the SoC. It
17
+
is expected that they are defined using standard clock bindings
18
+
with following clock-output-names:
19
+
20
+
- "fin_pll" - PLL input clock from XXTI
21
+
22
+
Required Properties for Clock Controller:
23
+
24
+
- compatible: clock controllers will use one of the following
25
+
compatible strings to indicate the clock controller
26
+
functionality.
27
+
28
+
- "samsung,exynos7-clock-topc"
29
+
- "samsung,exynos7-clock-top0"
30
+
- "samsung,exynos7-clock-top1"
31
+
- "samsung,exynos7-clock-ccore"
32
+
- "samsung,exynos7-clock-peric0"
33
+
- "samsung,exynos7-clock-peric1"
34
+
- "samsung,exynos7-clock-peris"
35
+
- "samsung,exynos7-clock-fsys0"
36
+
- "samsung,exynos7-clock-fsys1"
37
+
38
+
- reg: physical base address of the controller and the length of
39
+
memory mapped region.
40
+
41
+
- #clock-cells: should be 1.
42
+
43
+
- clocks: list of clock identifiers which are fed as the input to
44
+
the given clock controller. Please refer the next section to
45
+
find the input clocks for a given controller.
46
+
47
+
- clock-names: list of names of clocks which are fed as the input
48
+
to the given clock controller.
49
+
50
+
Input clocks for top0 clock controller:
51
+
- fin_pll
52
+
- dout_sclk_bus0_pll
53
+
- dout_sclk_bus1_pll
54
+
- dout_sclk_cc_pll
55
+
- dout_sclk_mfc_pll
56
+
57
+
Input clocks for top1 clock controller:
58
+
- fin_pll
59
+
- dout_sclk_bus0_pll
60
+
- dout_sclk_bus1_pll
61
+
- dout_sclk_cc_pll
62
+
- dout_sclk_mfc_pll
63
+
64
+
Input clocks for ccore clock controller:
65
+
- fin_pll
66
+
- dout_aclk_ccore_133
67
+
68
+
Input clocks for peric0 clock controller:
69
+
- fin_pll
70
+
- dout_aclk_peric0_66
71
+
- sclk_uart0
72
+
73
+
Input clocks for peric1 clock controller:
74
+
- fin_pll
75
+
- dout_aclk_peric1_66
76
+
- sclk_uart1
77
+
- sclk_uart2
78
+
- sclk_uart3
79
+
80
+
Input clocks for peris clock controller:
81
+
- fin_pll
82
+
- dout_aclk_peris_66
83
+
84
+
Input clocks for fsys0 clock controller:
85
+
- fin_pll
86
+
- dout_aclk_fsys0_200
87
+
- dout_sclk_mmc2
88
+
89
+
Input clocks for fsys1 clock controller:
90
+
- fin_pll
91
+
- dout_aclk_fsys1_200
92
+
- dout_sclk_mmc0
93
+
- dout_sclk_mmc1
+21
Documentation/devicetree/bindings/clock/marvell,mmp2.txt
+21
Documentation/devicetree/bindings/clock/marvell,mmp2.txt
···
1
+
* Marvell MMP2 Clock Controller
2
+
3
+
The MMP2 clock subsystem generates and supplies clock to various
4
+
controllers within the MMP2 SoC.
5
+
6
+
Required Properties:
7
+
8
+
- compatible: should be one of the following.
9
+
- "marvell,mmp2-clock" - controller compatible with MMP2 SoC.
10
+
11
+
- reg: physical base address of the clock subsystem and length of memory mapped
12
+
region. There are 3 places in SOC has clock control logic:
13
+
"mpmu", "apmu", "apbc". So three reg spaces need to be defined.
14
+
15
+
- #clock-cells: should be 1.
16
+
- #reset-cells: should be 1.
17
+
18
+
Each clock is assigned an identifier and client nodes use this identifier
19
+
to specify the clock which they consume.
20
+
21
+
All these identifier could be found in <dt-bindings/clock/marvell-mmp2.h>.
+21
Documentation/devicetree/bindings/clock/marvell,pxa168.txt
+21
Documentation/devicetree/bindings/clock/marvell,pxa168.txt
···
1
+
* Marvell PXA168 Clock Controller
2
+
3
+
The PXA168 clock subsystem generates and supplies clock to various
4
+
controllers within the PXA168 SoC.
5
+
6
+
Required Properties:
7
+
8
+
- compatible: should be one of the following.
9
+
- "marvell,pxa168-clock" - controller compatible with PXA168 SoC.
10
+
11
+
- reg: physical base address of the clock subsystem and length of memory mapped
12
+
region. There are 3 places in SOC has clock control logic:
13
+
"mpmu", "apmu", "apbc". So three reg spaces need to be defined.
14
+
15
+
- #clock-cells: should be 1.
16
+
- #reset-cells: should be 1.
17
+
18
+
Each clock is assigned an identifier and client nodes use this identifier
19
+
to specify the clock which they consume.
20
+
21
+
All these identifier could be found in <dt-bindings/clock/marvell,pxa168.h>.
+21
Documentation/devicetree/bindings/clock/marvell,pxa910.txt
+21
Documentation/devicetree/bindings/clock/marvell,pxa910.txt
···
1
+
* Marvell PXA910 Clock Controller
2
+
3
+
The PXA910 clock subsystem generates and supplies clock to various
4
+
controllers within the PXA910 SoC.
5
+
6
+
Required Properties:
7
+
8
+
- compatible: should be one of the following.
9
+
- "marvell,pxa910-clock" - controller compatible with PXA910 SoC.
10
+
11
+
- reg: physical base address of the clock subsystem and length of memory mapped
12
+
region. There are 4 places in SOC has clock control logic:
13
+
"mpmu", "apmu", "apbc", "apbcp". So four reg spaces need to be defined.
14
+
15
+
- #clock-cells: should be 1.
16
+
- #reset-cells: should be 1.
17
+
18
+
Each clock is assigned an identifier and client nodes use this identifier
19
+
to specify the clock which they consume.
20
+
21
+
All these identifier could be found in <dt-bindings/clock/marvell-pxa910.h>.
+12
-6
Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
+12
-6
Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
···
7
7
Required Properties:
8
8
9
9
- compatible: Must be one of the following
10
+
- "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks
11
+
- "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks
10
12
- "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
11
13
- "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks
14
+
- "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks
12
15
- "renesas,cpg-div6-clock" for generic DIV6 clocks
13
16
- reg: Base address and length of the memory resource used by the DIV6 clock
14
-
- clocks: Reference to the parent clock
17
+
- clocks: Reference to the parent clock(s); either one, four, or eight
18
+
clocks must be specified. For clocks with multiple parents, invalid
19
+
settings must be specified as "<0>".
15
20
- #clock-cells: Must be 0
16
21
- clock-output-names: The name of the clock as a free-form string
17
22
···
24
19
Example
25
20
-------
26
21
27
-
sd2_clk: sd2_clk@e6150078 {
28
-
compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
29
-
reg = <0 0xe6150078 0 4>;
30
-
clocks = <&pll1_div2_clk>;
22
+
sdhi2_clk: sdhi2_clk@e615007c {
23
+
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
24
+
reg = <0 0xe615007c 0 4>;
25
+
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
26
+
<0>, <&extal2_clk>;
31
27
#clock-cells = <0>;
32
-
clock-output-names = "sd2";
28
+
clock-output-names = "sdhi2ck";
33
29
};
+4
-4
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
+4
-4
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
···
26
26
must appear in the same order as the output clocks.
27
27
- #clock-cells: Must be 1
28
28
- clock-output-names: The name of the clocks as free-form strings
29
-
- renesas,clock-indices: Indices of the gate clocks into the group (0 to 31)
29
+
- clock-indices: Indices of the gate clocks into the group (0 to 31)
30
30
31
-
The clocks, clock-output-names and renesas,clock-indices properties contain one
32
-
entry per gate clock. The MSTP groups are sparsely populated. Unimplemented
33
-
gate clocks must not be declared.
31
+
The clocks, clock-output-names and clock-indices properties contain one entry
32
+
per gate clock. The MSTP groups are sparsely populated. Unimplemented gate
33
+
clocks must not be declared.
34
34
35
35
36
36
Example
+27
-4
Documentation/devicetree/bindings/clock/sunxi.txt
+27
-4
Documentation/devicetree/bindings/clock/sunxi.txt
···
10
10
"allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
11
11
"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
12
12
"allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
13
+
"allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80
13
14
"allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
14
15
"allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
15
16
"allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
17
+
"allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80
16
18
"allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
17
19
"allwinner,sun4i-a10-axi-clk" - for the AXI clock
18
20
"allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
19
21
"allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
20
22
"allwinner,sun4i-a10-ahb-clk" - for the AHB clock
23
+
"allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80
21
24
"allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
22
25
"allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
23
26
"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
···
29
26
"allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
30
27
"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
31
28
"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
29
+
"allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
30
+
"allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80
31
+
"allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80
32
32
"allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
33
33
"allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
34
34
"allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23
35
+
"allwinner,sun9i-a80-apb0-clk" - for the APB0 bus clock on A80
35
36
"allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
36
37
"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
37
38
"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
38
39
"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
39
40
"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
40
41
"allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
42
+
"allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
41
43
"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
42
-
"allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
44
+
"allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
43
45
"allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
44
46
"allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
45
47
"allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
46
48
"allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
47
49
"allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
48
50
"allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23
49
-
"allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
51
+
"allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
50
52
"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
51
53
"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
52
54
"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
···
71
63
multiplexed clocks, the list order must match the hardware
72
64
programming order.
73
65
- #clock-cells : from common clock binding; shall be set to 0 except for
74
-
"allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk" and
75
-
"allwinner,sun4i-pll6-clk" where it shall be set to 1
66
+
the following compatibles where it shall be set to 1:
67
+
"allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk",
68
+
"allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk"
76
69
- clock-output-names : shall be the corresponding names of the outputs.
77
70
If the clock module only has one output, the name shall be the
78
71
module name.
···
88
79
"clocks" phandle cell. Consumers that are using a gated clock should
89
80
provide an additional ID in their clock property. This ID is the
90
81
offset of the bit controlling this particular gate in the register.
82
+
For the other clocks with "#clock-cells" = 1, the additional ID shall
83
+
refer to the index of the output.
84
+
85
+
For "allwinner,sun6i-a31-pll6-clk", there are 2 outputs. The first output
86
+
is the normal PLL6 output, or "pll6". The second output is rate doubled
87
+
PLL6, or "pll6x2".
91
88
92
89
For example:
93
90
···
119
104
reg = <0x01c20020 0x4>;
120
105
clocks = <&osc24M>;
121
106
clock-output-names = "pll5_ddr", "pll5_other";
107
+
};
108
+
109
+
pll6: clk@01c20028 {
110
+
#clock-cells = <1>;
111
+
compatible = "allwinner,sun6i-a31-pll6-clk";
112
+
reg = <0x01c20028 0x4>;
113
+
clocks = <&osc24M>;
114
+
clock-output-names = "pll6", "pll6x2";
122
115
};
123
116
124
117
cpu: cpu@01c20054 {
+2
-1
MAINTAINERS
+2
-1
MAINTAINERS
···
2576
2576
2577
2577
COMMON CLK FRAMEWORK
2578
2578
M: Mike Turquette <mturquette@linaro.org>
2579
+
M: Stephen Boyd <sboyd@codeaurora.org>
2579
2580
L: linux-kernel@vger.kernel.org
2580
-
T: git git://git.linaro.org/people/mturquette/linux.git
2581
+
T: git git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
2581
2582
S: Maintained
2582
2583
F: drivers/clk/
2583
2584
X: drivers/clk/clkdev.c
+3
arch/arm/boot/dts/Makefile
+3
arch/arm/boot/dts/Makefile
···
177
177
dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
178
178
dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
179
179
dtb-$(CONFIG_MACH_MESON6) += meson6-atv1200.dtb
180
+
dtb-$(CONFIG_ARCH_MMP) += pxa168-aspenite.dtb \
181
+
pxa910-dkb.dtb \
182
+
mmp2-brownstone.dtb
180
183
dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
181
184
dtb-$(CONFIG_ARCH_MXC) += \
182
185
imx1-ads.dtb \
+1
-1
arch/arm/boot/dts/mmp2-brownstone.dts
+1
-1
arch/arm/boot/dts/mmp2-brownstone.dts
+28
-1
arch/arm/boot/dts/mmp2.dtsi
+28
-1
arch/arm/boot/dts/mmp2.dtsi
···
7
7
* publishhed by the Free Software Foundation.
8
8
*/
9
9
10
-
/include/ "skeleton.dtsi"
10
+
#include "skeleton.dtsi"
11
+
#include <dt-bindings/clock/marvell,mmp2.h>
11
12
12
13
/ {
13
14
aliases {
···
136
135
compatible = "mrvl,mmp-uart";
137
136
reg = <0xd4030000 0x1000>;
138
137
interrupts = <27>;
138
+
clocks = <&soc_clocks MMP2_CLK_UART0>;
139
+
resets = <&soc_clocks MMP2_CLK_UART0>;
139
140
status = "disabled";
140
141
};
141
142
···
145
142
compatible = "mrvl,mmp-uart";
146
143
reg = <0xd4017000 0x1000>;
147
144
interrupts = <28>;
145
+
clocks = <&soc_clocks MMP2_CLK_UART1>;
146
+
resets = <&soc_clocks MMP2_CLK_UART1>;
148
147
status = "disabled";
149
148
};
150
149
···
154
149
compatible = "mrvl,mmp-uart";
155
150
reg = <0xd4018000 0x1000>;
156
151
interrupts = <24>;
152
+
clocks = <&soc_clocks MMP2_CLK_UART2>;
153
+
resets = <&soc_clocks MMP2_CLK_UART2>;
157
154
status = "disabled";
158
155
};
159
156
···
163
156
compatible = "mrvl,mmp-uart";
164
157
reg = <0xd4016000 0x1000>;
165
158
interrupts = <46>;
159
+
clocks = <&soc_clocks MMP2_CLK_UART3>;
160
+
resets = <&soc_clocks MMP2_CLK_UART3>;
166
161
status = "disabled";
167
162
};
168
163
···
177
168
#gpio-cells = <2>;
178
169
interrupts = <49>;
179
170
interrupt-names = "gpio_mux";
171
+
clocks = <&soc_clocks MMP2_CLK_GPIO>;
172
+
resets = <&soc_clocks MMP2_CLK_GPIO>;
180
173
interrupt-controller;
181
174
#interrupt-cells = <1>;
182
175
ranges;
···
212
201
compatible = "mrvl,mmp-twsi";
213
202
reg = <0xd4011000 0x1000>;
214
203
interrupts = <7>;
204
+
clocks = <&soc_clocks MMP2_CLK_TWSI0>;
205
+
resets = <&soc_clocks MMP2_CLK_TWSI0>;
215
206
#address-cells = <1>;
216
207
#size-cells = <0>;
217
208
mrvl,i2c-fast-mode;
···
224
211
compatible = "mrvl,mmp-twsi";
225
212
reg = <0xd4025000 0x1000>;
226
213
interrupts = <58>;
214
+
clocks = <&soc_clocks MMP2_CLK_TWSI1>;
215
+
resets = <&soc_clocks MMP2_CLK_TWSI1>;
227
216
status = "disabled";
228
217
};
229
218
···
235
220
interrupts = <1 0>;
236
221
interrupt-names = "rtc 1Hz", "rtc alarm";
237
222
interrupt-parent = <&intcmux5>;
223
+
clocks = <&soc_clocks MMP2_CLK_RTC>;
224
+
resets = <&soc_clocks MMP2_CLK_RTC>;
238
225
status = "disabled";
239
226
};
227
+
};
228
+
229
+
soc_clocks: clocks{
230
+
compatible = "marvell,mmp2-clock";
231
+
reg = <0xd4050000 0x1000>,
232
+
<0xd4282800 0x400>,
233
+
<0xd4015000 0x1000>;
234
+
reg-names = "mpmu", "apmu", "apbc";
235
+
#clock-cells = <1>;
236
+
#reset-cells = <1>;
240
237
};
241
238
};
242
239
};
+1
-1
arch/arm/boot/dts/pxa168-aspenite.dts
+1
-1
arch/arm/boot/dts/pxa168-aspenite.dts
+26
-1
arch/arm/boot/dts/pxa168.dtsi
+26
-1
arch/arm/boot/dts/pxa168.dtsi
···
7
7
* publishhed by the Free Software Foundation.
8
8
*/
9
9
10
-
/include/ "skeleton.dtsi"
10
+
#include "skeleton.dtsi"
11
+
#include <dt-bindings/clock/marvell,pxa168.h>
11
12
12
13
/ {
13
14
aliases {
···
60
59
compatible = "mrvl,mmp-uart";
61
60
reg = <0xd4017000 0x1000>;
62
61
interrupts = <27>;
62
+
clocks = <&soc_clocks PXA168_CLK_UART0>;
63
+
resets = <&soc_clocks PXA168_CLK_UART0>;
63
64
status = "disabled";
64
65
};
65
66
···
69
66
compatible = "mrvl,mmp-uart";
70
67
reg = <0xd4018000 0x1000>;
71
68
interrupts = <28>;
69
+
clocks = <&soc_clocks PXA168_CLK_UART1>;
70
+
resets = <&soc_clocks PXA168_CLK_UART1>;
72
71
status = "disabled";
73
72
};
74
73
···
78
73
compatible = "mrvl,mmp-uart";
79
74
reg = <0xd4026000 0x1000>;
80
75
interrupts = <29>;
76
+
clocks = <&soc_clocks PXA168_CLK_UART2>;
77
+
resets = <&soc_clocks PXA168_CLK_UART2>;
81
78
status = "disabled";
82
79
};
83
80
···
91
84
gpio-controller;
92
85
#gpio-cells = <2>;
93
86
interrupts = <49>;
87
+
clocks = <&soc_clocks PXA168_CLK_GPIO>;
88
+
resets = <&soc_clocks PXA168_CLK_GPIO>;
94
89
interrupt-names = "gpio_mux";
95
90
interrupt-controller;
96
91
#interrupt-cells = <1>;
···
119
110
compatible = "mrvl,mmp-twsi";
120
111
reg = <0xd4011000 0x1000>;
121
112
interrupts = <7>;
113
+
clocks = <&soc_clocks PXA168_CLK_TWSI0>;
114
+
resets = <&soc_clocks PXA168_CLK_TWSI0>;
122
115
mrvl,i2c-fast-mode;
123
116
status = "disabled";
124
117
};
···
129
118
compatible = "mrvl,mmp-twsi";
130
119
reg = <0xd4025000 0x1000>;
131
120
interrupts = <58>;
121
+
clocks = <&soc_clocks PXA168_CLK_TWSI1>;
122
+
resets = <&soc_clocks PXA168_CLK_TWSI1>;
132
123
status = "disabled";
133
124
};
134
125
···
139
126
reg = <0xd4010000 0x1000>;
140
127
interrupts = <5 6>;
141
128
interrupt-names = "rtc 1Hz", "rtc alarm";
129
+
clocks = <&soc_clocks PXA168_CLK_RTC>;
130
+
resets = <&soc_clocks PXA168_CLK_RTC>;
142
131
status = "disabled";
143
132
};
133
+
};
134
+
135
+
soc_clocks: clocks{
136
+
compatible = "marvell,pxa168-clock";
137
+
reg = <0xd4050000 0x1000>,
138
+
<0xd4282800 0x400>,
139
+
<0xd4015000 0x1000>;
140
+
reg-names = "mpmu", "apmu", "apbc";
141
+
#clock-cells = <1>;
142
+
#reset-cells = <1>;
144
143
};
145
144
};
146
145
};
+1
-1
arch/arm/boot/dts/pxa910-dkb.dts
+1
-1
arch/arm/boot/dts/pxa910-dkb.dts
+27
-1
arch/arm/boot/dts/pxa910.dtsi
+27
-1
arch/arm/boot/dts/pxa910.dtsi
···
7
7
* publishhed by the Free Software Foundation.
8
8
*/
9
9
10
-
/include/ "skeleton.dtsi"
10
+
#include "skeleton.dtsi"
11
+
#include <dt-bindings/clock/marvell,pxa910.h>
11
12
12
13
/ {
13
14
aliases {
···
72
71
compatible = "mrvl,mmp-uart";
73
72
reg = <0xd4017000 0x1000>;
74
73
interrupts = <27>;
74
+
clocks = <&soc_clocks PXA910_CLK_UART0>;
75
+
resets = <&soc_clocks PXA910_CLK_UART0>;
75
76
status = "disabled";
76
77
};
77
78
···
81
78
compatible = "mrvl,mmp-uart";
82
79
reg = <0xd4018000 0x1000>;
83
80
interrupts = <28>;
81
+
clocks = <&soc_clocks PXA910_CLK_UART1>;
82
+
resets = <&soc_clocks PXA910_CLK_UART1>;
84
83
status = "disabled";
85
84
};
86
85
···
90
85
compatible = "mrvl,mmp-uart";
91
86
reg = <0xd4036000 0x1000>;
92
87
interrupts = <59>;
88
+
clocks = <&soc_clocks PXA910_CLK_UART2>;
89
+
resets = <&soc_clocks PXA910_CLK_UART2>;
93
90
status = "disabled";
94
91
};
95
92
···
104
97
#gpio-cells = <2>;
105
98
interrupts = <49>;
106
99
interrupt-names = "gpio_mux";
100
+
clocks = <&soc_clocks PXA910_CLK_GPIO>;
101
+
resets = <&soc_clocks PXA910_CLK_GPIO>;
107
102
interrupt-controller;
108
103
#interrupt-cells = <1>;
109
104
ranges;
···
133
124
#size-cells = <0>;
134
125
reg = <0xd4011000 0x1000>;
135
126
interrupts = <7>;
127
+
clocks = <&soc_clocks PXA910_CLK_TWSI0>;
128
+
resets = <&soc_clocks PXA910_CLK_TWSI0>;
136
129
mrvl,i2c-fast-mode;
137
130
status = "disabled";
138
131
};
···
145
134
#size-cells = <0>;
146
135
reg = <0xd4037000 0x1000>;
147
136
interrupts = <54>;
137
+
clocks = <&soc_clocks PXA910_CLK_TWSI1>;
138
+
resets = <&soc_clocks PXA910_CLK_TWSI1>;
148
139
status = "disabled";
149
140
};
150
141
···
155
142
reg = <0xd4010000 0x1000>;
156
143
interrupts = <5 6>;
157
144
interrupt-names = "rtc 1Hz", "rtc alarm";
145
+
clocks = <&soc_clocks PXA910_CLK_RTC>;
146
+
resets = <&soc_clocks PXA910_CLK_RTC>;
158
147
status = "disabled";
159
148
};
149
+
};
150
+
151
+
soc_clocks: clocks{
152
+
compatible = "marvell,pxa910-clock";
153
+
reg = <0xd4050000 0x1000>,
154
+
<0xd4282800 0x400>,
155
+
<0xd4015000 0x1000>,
156
+
<0xd403b000 0x1000>;
157
+
reg-names = "mpmu", "apmu", "apbc", "apbcp";
158
+
#clock-cells = <1>;
159
+
#reset-cells = <1>;
160
160
};
161
161
};
162
162
};
+2
-10
arch/arm/boot/dts/sun4i-a10.dtsi
+2
-10
arch/arm/boot/dts/sun4i-a10.dtsi
···
188
188
"apb0_ir1", "apb0_keypad";
189
189
};
190
190
191
-
apb1_mux: apb1_mux@01c20058 {
192
-
#clock-cells = <0>;
193
-
compatible = "allwinner,sun4i-a10-apb1-mux-clk";
194
-
reg = <0x01c20058 0x4>;
195
-
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
196
-
clock-output-names = "apb1_mux";
197
-
};
198
-
199
-
apb1: apb1@01c20058 {
191
+
apb1: clk@01c20058 {
200
192
#clock-cells = <0>;
201
193
compatible = "allwinner,sun4i-a10-apb1-clk";
202
194
reg = <0x01c20058 0x4>;
203
-
clocks = <&apb1_mux>;
195
+
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
204
196
clock-output-names = "apb1";
205
197
};
206
198
+2
-10
arch/arm/boot/dts/sun5i-a10s.dtsi
+2
-10
arch/arm/boot/dts/sun5i-a10s.dtsi
···
176
176
"apb0_ir", "apb0_keypad";
177
177
};
178
178
179
-
apb1_mux: apb1_mux@01c20058 {
180
-
#clock-cells = <0>;
181
-
compatible = "allwinner,sun4i-a10-apb1-mux-clk";
182
-
reg = <0x01c20058 0x4>;
183
-
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
184
-
clock-output-names = "apb1_mux";
185
-
};
186
-
187
-
apb1: apb1@01c20058 {
179
+
apb1: clk@01c20058 {
188
180
#clock-cells = <0>;
189
181
compatible = "allwinner,sun4i-a10-apb1-clk";
190
182
reg = <0x01c20058 0x4>;
191
-
clocks = <&apb1_mux>;
183
+
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
192
184
clock-output-names = "apb1";
193
185
};
194
186
+2
-10
arch/arm/boot/dts/sun5i-a13.dtsi
+2
-10
arch/arm/boot/dts/sun5i-a13.dtsi
···
161
161
clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
162
162
};
163
163
164
-
apb1_mux: apb1_mux@01c20058 {
165
-
#clock-cells = <0>;
166
-
compatible = "allwinner,sun4i-a10-apb1-mux-clk";
167
-
reg = <0x01c20058 0x4>;
168
-
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
169
-
clock-output-names = "apb1_mux";
170
-
};
171
-
172
-
apb1: apb1@01c20058 {
164
+
apb1: clk@01c20058 {
173
165
#clock-cells = <0>;
174
166
compatible = "allwinner,sun4i-a10-apb1-clk";
175
167
reg = <0x01c20058 0x4>;
176
-
clocks = <&apb1_mux>;
168
+
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
177
169
clock-output-names = "apb1";
178
170
};
179
171
+2
-10
arch/arm/boot/dts/sun6i-a31.dtsi
+2
-10
arch/arm/boot/dts/sun6i-a31.dtsi
···
229
229
"apb1_daudio1";
230
230
};
231
231
232
-
apb2_mux: apb2_mux@01c20058 {
232
+
apb2: clk@01c20058 {
233
233
#clock-cells = <0>;
234
-
compatible = "allwinner,sun4i-a10-apb1-mux-clk";
234
+
compatible = "allwinner,sun4i-a10-apb1-clk";
235
235
reg = <0x01c20058 0x4>;
236
236
clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
237
-
clock-output-names = "apb2_mux";
238
-
};
239
-
240
-
apb2: apb2@01c20058 {
241
-
#clock-cells = <0>;
242
-
compatible = "allwinner,sun6i-a31-apb2-div-clk";
243
-
reg = <0x01c20058 0x4>;
244
-
clocks = <&apb2_mux>;
245
237
clock-output-names = "apb2";
246
238
};
247
239
+2
-10
arch/arm/boot/dts/sun7i-a20.dtsi
+2
-10
arch/arm/boot/dts/sun7i-a20.dtsi
···
236
236
"apb0_iis2", "apb0_keypad";
237
237
};
238
238
239
-
apb1_mux: apb1_mux@01c20058 {
240
-
#clock-cells = <0>;
241
-
compatible = "allwinner,sun4i-a10-apb1-mux-clk";
242
-
reg = <0x01c20058 0x4>;
243
-
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
244
-
clock-output-names = "apb1_mux";
245
-
};
246
-
247
-
apb1: apb1@01c20058 {
239
+
apb1: clk@01c20058 {
248
240
#clock-cells = <0>;
249
241
compatible = "allwinner,sun4i-a10-apb1-clk";
250
242
reg = <0x01c20058 0x4>;
251
-
clocks = <&apb1_mux>;
243
+
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
252
244
clock-output-names = "apb1";
253
245
};
254
246
+2
-10
arch/arm/boot/dts/sun8i-a23.dtsi
+2
-10
arch/arm/boot/dts/sun8i-a23.dtsi
···
189
189
"apb1_daudio0", "apb1_daudio1";
190
190
};
191
191
192
-
apb2_mux: apb2_mux_clk@01c20058 {
192
+
apb2: clk@01c20058 {
193
193
#clock-cells = <0>;
194
-
compatible = "allwinner,sun4i-a10-apb1-mux-clk";
194
+
compatible = "allwinner,sun4i-a10-apb1-clk";
195
195
reg = <0x01c20058 0x4>;
196
196
clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
197
-
clock-output-names = "apb2_mux";
198
-
};
199
-
200
-
apb2: apb2_clk@01c20058 {
201
-
#clock-cells = <0>;
202
-
compatible = "allwinner,sun6i-a31-apb2-div-clk";
203
-
reg = <0x01c20058 0x4>;
204
-
clocks = <&apb2_mux>;
205
197
clock-output-names = "apb2";
206
198
};
207
199
+6
-6
arch/arm/mach-mmp/Kconfig
+6
-6
arch/arm/mach-mmp/Kconfig
···
86
86
87
87
config MACH_MMP_DT
88
88
bool "Support MMP (ARMv5) platforms from device tree"
89
-
select CPU_PXA168
90
-
select CPU_PXA910
91
89
select USE_OF
92
90
select PINCTRL
93
91
select PINCTRL_SINGLE
92
+
select COMMON_CLK
93
+
select ARCH_HAS_RESET_CONTROLLER
94
+
select CPU_MOHAWK
94
95
help
95
96
Include support for Marvell MMP2 based platforms using
96
97
the device tree. Needn't select any other machine while
···
100
99
config MACH_MMP2_DT
101
100
bool "Support MMP2 (ARMv7) platforms from device tree"
102
101
depends on !CPU_MOHAWK
103
-
select CPU_MMP2
104
102
select USE_OF
105
103
select PINCTRL
106
104
select PINCTRL_SINGLE
105
+
select COMMON_CLK
106
+
select ARCH_HAS_RESET_CONTROLLER
107
+
select CPU_PJ4
107
108
help
108
109
Include support for Marvell MMP2 based platforms using
109
110
the device tree.
···
114
111
115
112
config CPU_PXA168
116
113
bool
117
-
select COMMON_CLK
118
114
select CPU_MOHAWK
119
115
help
120
116
Select code specific to PXA168
121
117
122
118
config CPU_PXA910
123
119
bool
124
-
select COMMON_CLK
125
120
select CPU_MOHAWK
126
121
help
127
122
Select code specific to PXA910
128
123
129
124
config CPU_MMP2
130
125
bool
131
-
select COMMON_CLK
132
126
select CPU_PJ4
133
127
help
134
128
Select code specific to MMP2. MMP2 is ARMv7 compatible.
+20
-41
arch/arm/mach-mmp/mmp-dt.c
+20
-41
arch/arm/mach-mmp/mmp-dt.c
···
11
11
12
12
#include <linux/irqchip.h>
13
13
#include <linux/of_platform.h>
14
+
#include <linux/clk-provider.h>
14
15
#include <asm/mach/arch.h>
15
16
#include <asm/mach/time.h>
17
+
#include <asm/hardware/cache-tauros2.h>
16
18
17
19
#include "common.h"
18
20
19
21
extern void __init mmp_dt_init_timer(void);
20
22
21
-
static const struct of_dev_auxdata pxa168_auxdata_lookup[] __initconst = {
22
-
OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL),
23
-
OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL),
24
-
OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4026000, "pxa2xx-uart.2", NULL),
25
-
OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
26
-
OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4025000, "pxa2xx-i2c.1", NULL),
27
-
OF_DEV_AUXDATA("marvell,mmp-gpio", 0xd4019000, "mmp-gpio", NULL),
28
-
OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
29
-
{}
30
-
};
31
-
32
-
static const struct of_dev_auxdata pxa910_auxdata_lookup[] __initconst = {
33
-
OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL),
34
-
OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL),
35
-
OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4036000, "pxa2xx-uart.2", NULL),
36
-
OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
37
-
OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4037000, "pxa2xx-i2c.1", NULL),
38
-
OF_DEV_AUXDATA("marvell,mmp-gpio", 0xd4019000, "mmp-gpio", NULL),
39
-
OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
40
-
{}
41
-
};
42
-
43
-
static void __init pxa168_dt_init(void)
44
-
{
45
-
of_platform_populate(NULL, of_default_bus_match_table,
46
-
pxa168_auxdata_lookup, NULL);
47
-
}
48
-
49
-
static void __init pxa910_dt_init(void)
50
-
{
51
-
of_platform_populate(NULL, of_default_bus_match_table,
52
-
pxa910_auxdata_lookup, NULL);
53
-
}
54
-
55
-
static const char *mmp_dt_board_compat[] __initdata = {
23
+
static const char *pxa168_dt_board_compat[] __initdata = {
56
24
"mrvl,pxa168-aspenite",
25
+
NULL,
26
+
};
27
+
28
+
static const char *pxa910_dt_board_compat[] __initdata = {
57
29
"mrvl,pxa910-dkb",
58
30
NULL,
59
31
};
60
32
33
+
static void __init mmp_init_time(void)
34
+
{
35
+
#ifdef CONFIG_CACHE_TAUROS2
36
+
tauros2_init(0);
37
+
#endif
38
+
mmp_dt_init_timer();
39
+
of_clk_init(NULL);
40
+
}
41
+
61
42
DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)")
62
43
.map_io = mmp_map_io,
63
-
.init_time = mmp_dt_init_timer,
64
-
.init_machine = pxa168_dt_init,
65
-
.dt_compat = mmp_dt_board_compat,
44
+
.init_time = mmp_init_time,
45
+
.dt_compat = pxa168_dt_board_compat,
66
46
MACHINE_END
67
47
68
48
DT_MACHINE_START(PXA910_DT, "Marvell PXA910 (Device Tree Support)")
69
49
.map_io = mmp_map_io,
70
-
.init_time = mmp_dt_init_timer,
71
-
.init_machine = pxa910_dt_init,
72
-
.dt_compat = mmp_dt_board_compat,
50
+
.init_time = mmp_init_time,
51
+
.dt_compat = pxa910_dt_board_compat,
73
52
MACHINE_END
+9
-17
arch/arm/mach-mmp/mmp2-dt.c
+9
-17
arch/arm/mach-mmp/mmp2-dt.c
···
12
12
#include <linux/io.h>
13
13
#include <linux/irqchip.h>
14
14
#include <linux/of_platform.h>
15
+
#include <linux/clk-provider.h>
15
16
#include <asm/mach/arch.h>
16
17
#include <asm/mach/time.h>
18
+
#include <asm/hardware/cache-tauros2.h>
17
19
18
20
#include "common.h"
19
21
20
22
extern void __init mmp_dt_init_timer(void);
21
23
22
-
static const struct of_dev_auxdata mmp2_auxdata_lookup[] __initconst = {
23
-
OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4030000, "pxa2xx-uart.0", NULL),
24
-
OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.1", NULL),
25
-
OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.2", NULL),
26
-
OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4016000, "pxa2xx-uart.3", NULL),
27
-
OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
28
-
OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4025000, "pxa2xx-i2c.1", NULL),
29
-
OF_DEV_AUXDATA("marvell,mmp-gpio", 0xd4019000, "mmp2-gpio", NULL),
30
-
OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
31
-
{}
32
-
};
33
-
34
-
static void __init mmp2_dt_init(void)
24
+
static void __init mmp_init_time(void)
35
25
{
36
-
of_platform_populate(NULL, of_default_bus_match_table,
37
-
mmp2_auxdata_lookup, NULL);
26
+
#ifdef CONFIG_CACHE_TAUROS2
27
+
tauros2_init(0);
28
+
#endif
29
+
mmp_dt_init_timer();
30
+
of_clk_init(NULL);
38
31
}
39
32
40
33
static const char *mmp2_dt_board_compat[] __initdata = {
···
37
44
38
45
DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)")
39
46
.map_io = mmp_map_io,
40
-
.init_time = mmp_dt_init_timer,
41
-
.init_machine = mmp2_dt_init,
47
+
.init_time = mmp_init_time,
42
48
.dt_compat = mmp2_dt_board_compat,
43
49
MACHINE_END
+14
-9
arch/arm/mach-omap2/cclock3xxx_data.c
+14
-9
arch/arm/mach-omap2/cclock3xxx_data.c
···
111
111
112
112
static const char *dpll3_ck_parent_names[] = {
113
113
"sys_ck",
114
+
"sys_ck",
114
115
};
115
116
116
117
static const struct clk_ops dpll3_ck_ops = {
···
734
733
DEFINE_STRUCT_CLK_HW_OMAP(corex2_fck, NULL);
735
734
DEFINE_STRUCT_CLK(corex2_fck, corex2_fck_parent_names, core_ck_ops);
736
735
736
+
static const char *cpefuse_fck_parent_names[] = {
737
+
"sys_ck",
738
+
};
739
+
737
740
static struct clk cpefuse_fck;
738
741
739
742
static struct clk_hw_omap cpefuse_fck_hw = {
···
749
744
.clkdm_name = "core_l4_clkdm",
750
745
};
751
746
752
-
DEFINE_STRUCT_CLK(cpefuse_fck, dpll3_ck_parent_names, aes2_ick_ops);
747
+
DEFINE_STRUCT_CLK(cpefuse_fck, cpefuse_fck_parent_names, aes2_ick_ops);
753
748
754
749
static struct clk csi2_96m_fck;
755
750
···
780
775
.clkdm_name = "d2d_clkdm",
781
776
};
782
777
783
-
DEFINE_STRUCT_CLK(d2d_26m_fck, dpll3_ck_parent_names, aes2_ick_ops);
778
+
DEFINE_STRUCT_CLK(d2d_26m_fck, cpefuse_fck_parent_names, aes2_ick_ops);
784
779
785
780
static struct clk des1_ick;
786
781
···
1051
1046
.clkdm_name = "dss_clkdm",
1052
1047
};
1053
1048
1054
-
DEFINE_STRUCT_CLK(dss2_alwon_fck, dpll3_ck_parent_names, aes2_ick_ops);
1049
+
DEFINE_STRUCT_CLK(dss2_alwon_fck, cpefuse_fck_parent_names, aes2_ick_ops);
1055
1050
1056
1051
static struct clk dss_96m_fck;
1057
1052
···
1373
1368
static struct clk wkup_l4_ick;
1374
1369
1375
1370
DEFINE_STRUCT_CLK_HW_OMAP(wkup_l4_ick, "wkup_clkdm");
1376
-
DEFINE_STRUCT_CLK(wkup_l4_ick, dpll3_ck_parent_names, core_l4_ick_ops);
1371
+
DEFINE_STRUCT_CLK(wkup_l4_ick, cpefuse_fck_parent_names, core_l4_ick_ops);
1377
1372
1378
1373
static struct clk gpio1_ick;
1379
1374
···
1867
1862
.clkdm_name = "core_l3_clkdm",
1868
1863
};
1869
1864
1870
-
DEFINE_STRUCT_CLK(hecc_ck, dpll3_ck_parent_names, aes2_ick_ops);
1865
+
DEFINE_STRUCT_CLK(hecc_ck, cpefuse_fck_parent_names, aes2_ick_ops);
1871
1866
1872
1867
static struct clk hsotgusb_fck_am35xx;
1873
1868
···
1880
1875
.clkdm_name = "core_l3_clkdm",
1881
1876
};
1882
1877
1883
-
DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx, dpll3_ck_parent_names, aes2_ick_ops);
1878
+
DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx, cpefuse_fck_parent_names, aes2_ick_ops);
1884
1879
1885
1880
static struct clk hsotgusb_ick_3430es1;
1886
1881
···
2416
2411
.clkdm_name = "d2d_clkdm",
2417
2412
};
2418
2413
2419
-
DEFINE_STRUCT_CLK(modem_fck, dpll3_ck_parent_names, aes2_ick_ops);
2414
+
DEFINE_STRUCT_CLK(modem_fck, cpefuse_fck_parent_names, aes2_ick_ops);
2420
2415
2421
2416
static struct clk mspro_fck;
2422
2417
···
2715
2710
.clkdm_name = "wkup_clkdm",
2716
2711
};
2717
2712
2718
-
DEFINE_STRUCT_CLK(sr1_fck, dpll3_ck_parent_names, aes2_ick_ops);
2713
+
DEFINE_STRUCT_CLK(sr1_fck, cpefuse_fck_parent_names, aes2_ick_ops);
2719
2714
2720
2715
static struct clk sr2_fck;
2721
2716
···
2729
2724
.clkdm_name = "wkup_clkdm",
2730
2725
};
2731
2726
2732
-
DEFINE_STRUCT_CLK(sr2_fck, dpll3_ck_parent_names, aes2_ick_ops);
2727
+
DEFINE_STRUCT_CLK(sr2_fck, cpefuse_fck_parent_names, aes2_ick_ops);
2733
2728
2734
2729
static struct clk sr_l4_ick;
2735
2730
+3
-3
arch/arm/mach-omap2/dpll3xxx.c
+3
-3
arch/arm/mach-omap2/dpll3xxx.c
···
474
474
*/
475
475
long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate,
476
476
unsigned long *best_parent_rate,
477
-
struct clk **best_parent_clk)
477
+
struct clk_hw **best_parent_clk)
478
478
{
479
479
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
480
480
struct dpll_data *dd;
···
488
488
489
489
if (__clk_get_rate(dd->clk_bypass) == rate &&
490
490
(dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
491
-
*best_parent_clk = dd->clk_bypass;
491
+
*best_parent_clk = __clk_get_hw(dd->clk_bypass);
492
492
} else {
493
493
rate = omap2_dpll_round_rate(hw, rate, best_parent_rate);
494
-
*best_parent_clk = dd->clk_ref;
494
+
*best_parent_clk = __clk_get_hw(dd->clk_ref);
495
495
}
496
496
497
497
*best_parent_rate = rate;
+3
-3
arch/arm/mach-omap2/dpll44xx.c
+3
-3
arch/arm/mach-omap2/dpll44xx.c
···
223
223
*/
224
224
long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate,
225
225
unsigned long *best_parent_rate,
226
-
struct clk **best_parent_clk)
226
+
struct clk_hw **best_parent_clk)
227
227
{
228
228
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
229
229
struct dpll_data *dd;
···
237
237
238
238
if (__clk_get_rate(dd->clk_bypass) == rate &&
239
239
(dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
240
-
*best_parent_clk = dd->clk_bypass;
240
+
*best_parent_clk = __clk_get_hw(dd->clk_bypass);
241
241
} else {
242
242
rate = omap4_dpll_regm4xen_round_rate(hw, rate,
243
243
best_parent_rate);
244
-
*best_parent_clk = dd->clk_ref;
244
+
*best_parent_clk = __clk_get_hw(dd->clk_ref);
245
245
}
246
246
247
247
*best_parent_rate = rate;
+5
-5
arch/mips/alchemy/common/clock.c
+5
-5
arch/mips/alchemy/common/clock.c
···
374
374
375
375
static long alchemy_clk_fgcs_detr(struct clk_hw *hw, unsigned long rate,
376
376
unsigned long *best_parent_rate,
377
-
struct clk **best_parent_clk,
377
+
struct clk_hw **best_parent_clk,
378
378
int scale, int maxdiv)
379
379
{
380
380
struct clk *pc, *bpc, *free;
···
453
453
}
454
454
455
455
*best_parent_rate = bpr;
456
-
*best_parent_clk = bpc;
456
+
*best_parent_clk = __clk_get_hw(bpc);
457
457
return br;
458
458
}
459
459
···
547
547
548
548
static long alchemy_clk_fgv1_detr(struct clk_hw *hw, unsigned long rate,
549
549
unsigned long *best_parent_rate,
550
-
struct clk **best_parent_clk)
550
+
struct clk_hw **best_parent_clk)
551
551
{
552
552
return alchemy_clk_fgcs_detr(hw, rate, best_parent_rate,
553
553
best_parent_clk, 2, 512);
···
679
679
680
680
static long alchemy_clk_fgv2_detr(struct clk_hw *hw, unsigned long rate,
681
681
unsigned long *best_parent_rate,
682
-
struct clk **best_parent_clk)
682
+
struct clk_hw **best_parent_clk)
683
683
{
684
684
struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
685
685
int scale, maxdiv;
···
898
898
899
899
static long alchemy_clk_csrc_detr(struct clk_hw *hw, unsigned long rate,
900
900
unsigned long *best_parent_rate,
901
-
struct clk **best_parent_clk)
901
+
struct clk_hw **best_parent_clk)
902
902
{
903
903
struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
904
904
int scale = c->dt[2] == 3 ? 1 : 2; /* au1300 check */
+2
-2
drivers/clk/at91/clk-programmable.c
+2
-2
drivers/clk/at91/clk-programmable.c
···
57
57
static long clk_programmable_determine_rate(struct clk_hw *hw,
58
58
unsigned long rate,
59
59
unsigned long *best_parent_rate,
60
-
struct clk **best_parent_clk)
60
+
struct clk_hw **best_parent_hw)
61
61
{
62
62
struct clk *parent = NULL;
63
63
long best_rate = -EINVAL;
···
84
84
if (best_rate < 0 || (rate - tmp_rate) < (rate - best_rate)) {
85
85
best_rate = tmp_rate;
86
86
*best_parent_rate = parent_rate;
87
-
*best_parent_clk = parent;
87
+
*best_parent_hw = __clk_get_hw(parent);
88
88
}
89
89
90
90
if (!best_rate)
+2
-2
drivers/clk/bcm/clk-kona.c
+2
-2
drivers/clk/bcm/clk-kona.c
···
1032
1032
}
1033
1033
1034
1034
static long kona_peri_clk_determine_rate(struct clk_hw *hw, unsigned long rate,
1035
-
unsigned long *best_parent_rate, struct clk **best_parent)
1035
+
unsigned long *best_parent_rate, struct clk_hw **best_parent)
1036
1036
{
1037
1037
struct kona_clk *bcm_clk = to_kona_clk(hw);
1038
1038
struct clk *clk = hw->clk;
···
1075
1075
if (delta < best_delta) {
1076
1076
best_delta = delta;
1077
1077
best_rate = other_rate;
1078
-
*best_parent = parent;
1078
+
*best_parent = __clk_get_hw(parent);
1079
1079
*best_parent_rate = parent_rate;
1080
1080
}
1081
1081
}
+5
-4
drivers/clk/clk-composite.c
+5
-4
drivers/clk/clk-composite.c
···
57
57
58
58
static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate,
59
59
unsigned long *best_parent_rate,
60
-
struct clk **best_parent_p)
60
+
struct clk_hw **best_parent_p)
61
61
{
62
62
struct clk_composite *composite = to_clk_composite(hw);
63
63
const struct clk_ops *rate_ops = composite->rate_ops;
···
80
80
*best_parent_p = NULL;
81
81
82
82
if (__clk_get_flags(hw->clk) & CLK_SET_RATE_NO_REPARENT) {
83
-
*best_parent_p = clk_get_parent(mux_hw->clk);
84
-
*best_parent_rate = __clk_get_rate(*best_parent_p);
83
+
parent = clk_get_parent(mux_hw->clk);
84
+
*best_parent_p = __clk_get_hw(parent);
85
+
*best_parent_rate = __clk_get_rate(parent);
85
86
86
87
return rate_ops->round_rate(rate_hw, rate,
87
88
best_parent_rate);
···
104
103
105
104
if (!rate_diff || !*best_parent_p
106
105
|| best_rate_diff > rate_diff) {
107
-
*best_parent_p = parent;
106
+
*best_parent_p = __clk_get_hw(parent);
108
107
*best_parent_rate = parent_rate;
109
108
best_rate_diff = rate_diff;
110
109
best_rate = tmp_rate;
+1
-1
drivers/clk/clk-mux.c
+1
-1
drivers/clk/clk-mux.c
+1
-1
drivers/clk/clk-s2mps11.c
+1
-1
drivers/clk/clk-s2mps11.c
+23
-19
drivers/clk/clk.c
+23
-19
drivers/clk/clk.c
···
240
240
.release = single_release,
241
241
};
242
242
243
-
/* caller must hold prepare_lock */
244
243
static int clk_debug_create_one(struct clk *clk, struct dentry *pdentry)
245
244
{
246
245
struct dentry *d;
···
353
354
mutex_unlock(&clk_debug_lock);
354
355
}
355
356
356
-
struct dentry *clk_debugfs_add_file(struct clk *clk, char *name, umode_t mode,
357
+
struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode,
357
358
void *data, const struct file_operations *fops)
358
359
{
359
360
struct dentry *d = NULL;
360
361
361
-
if (clk->dentry)
362
-
d = debugfs_create_file(name, mode, clk->dentry, data, fops);
362
+
if (hw->clk->dentry)
363
+
d = debugfs_create_file(name, mode, hw->clk->dentry, data, fops);
363
364
364
365
return d;
365
366
}
···
573
574
return !clk ? 0 : clk->enable_count;
574
575
}
575
576
576
-
unsigned int __clk_get_prepare_count(struct clk *clk)
577
-
{
578
-
return !clk ? 0 : clk->prepare_count;
579
-
}
580
-
581
577
unsigned long __clk_get_rate(struct clk *clk)
582
578
{
583
579
unsigned long ret;
···
595
601
}
596
602
EXPORT_SYMBOL_GPL(__clk_get_rate);
597
603
598
-
unsigned long __clk_get_accuracy(struct clk *clk)
604
+
static unsigned long __clk_get_accuracy(struct clk *clk)
599
605
{
600
606
if (!clk)
601
607
return 0;
···
701
707
*/
702
708
long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
703
709
unsigned long *best_parent_rate,
704
-
struct clk **best_parent_p)
710
+
struct clk_hw **best_parent_p)
705
711
{
706
712
struct clk *clk = hw->clk, *parent, *best_parent = NULL;
707
713
int i, num_parents;
···
737
743
738
744
out:
739
745
if (best_parent)
740
-
*best_parent_p = best_parent;
746
+
*best_parent_p = best_parent->hw;
741
747
*best_parent_rate = best;
742
748
743
749
return best;
···
945
951
{
946
952
unsigned long parent_rate = 0;
947
953
struct clk *parent;
954
+
struct clk_hw *parent_hw;
948
955
949
956
if (!clk)
950
957
return 0;
···
954
959
if (parent)
955
960
parent_rate = parent->rate;
956
961
957
-
if (clk->ops->determine_rate)
962
+
if (clk->ops->determine_rate) {
963
+
parent_hw = parent ? parent->hw : NULL;
958
964
return clk->ops->determine_rate(clk->hw, rate, &parent_rate,
959
-
&parent);
960
-
else if (clk->ops->round_rate)
965
+
&parent_hw);
966
+
} else if (clk->ops->round_rate)
961
967
return clk->ops->round_rate(clk->hw, rate, &parent_rate);
962
968
else if (clk->flags & CLK_SET_RATE_PARENT)
963
969
return __clk_round_rate(clk->parent, rate);
···
1346
1350
{
1347
1351
struct clk *top = clk;
1348
1352
struct clk *old_parent, *parent;
1353
+
struct clk_hw *parent_hw;
1349
1354
unsigned long best_parent_rate = 0;
1350
1355
unsigned long new_rate;
1351
1356
int p_index = 0;
···
1362
1365
1363
1366
/* find the closest rate and parent clk/rate */
1364
1367
if (clk->ops->determine_rate) {
1368
+
parent_hw = parent ? parent->hw : NULL;
1365
1369
new_rate = clk->ops->determine_rate(clk->hw, rate,
1366
1370
&best_parent_rate,
1367
-
&parent);
1371
+
&parent_hw);
1372
+
parent = parent_hw->clk;
1368
1373
} else if (clk->ops->round_rate) {
1369
1374
new_rate = clk->ops->round_rate(clk->hw, rate,
1370
1375
&best_parent_rate);
···
1613
1614
1614
1615
if (clk->num_parents == 1) {
1615
1616
if (IS_ERR_OR_NULL(clk->parent))
1616
-
ret = clk->parent = __clk_lookup(clk->parent_names[0]);
1617
+
clk->parent = __clk_lookup(clk->parent_names[0]);
1617
1618
ret = clk->parent;
1618
1619
goto out;
1619
1620
}
···
1943
1944
else
1944
1945
clk->rate = 0;
1945
1946
1946
-
clk_debug_register(clk);
1947
1947
/*
1948
1948
* walk the list of orphan clocks and reparent any that are children of
1949
1949
* this clock
···
1976
1978
kref_init(&clk->ref);
1977
1979
out:
1978
1980
clk_prepare_unlock();
1981
+
1982
+
if (!ret)
1983
+
clk_debug_register(clk);
1979
1984
1980
1985
return ret;
1981
1986
}
···
2274
2273
2275
2274
void __clk_put(struct clk *clk)
2276
2275
{
2276
+
struct module *owner;
2277
+
2277
2278
if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
2278
2279
return;
2279
2280
2280
2281
clk_prepare_lock();
2282
+
owner = clk->owner;
2281
2283
kref_put(&clk->ref, __clk_release);
2282
2284
clk_prepare_unlock();
2283
2285
2284
-
module_put(clk->owner);
2286
+
module_put(owner);
2285
2287
}
2286
2288
2287
2289
/*** clk rate change notifiers ***/
+36
-36
drivers/clk/hisilicon/clk-hi3620.c
+36
-36
drivers/clk/hisilicon/clk-hi3620.c
···
38
38
#include "clk.h"
39
39
40
40
/* clock parent list */
41
-
static const char *timer0_mux_p[] __initdata = { "osc32k", "timerclk01", };
42
-
static const char *timer1_mux_p[] __initdata = { "osc32k", "timerclk01", };
43
-
static const char *timer2_mux_p[] __initdata = { "osc32k", "timerclk23", };
44
-
static const char *timer3_mux_p[] __initdata = { "osc32k", "timerclk23", };
45
-
static const char *timer4_mux_p[] __initdata = { "osc32k", "timerclk45", };
46
-
static const char *timer5_mux_p[] __initdata = { "osc32k", "timerclk45", };
47
-
static const char *timer6_mux_p[] __initdata = { "osc32k", "timerclk67", };
48
-
static const char *timer7_mux_p[] __initdata = { "osc32k", "timerclk67", };
49
-
static const char *timer8_mux_p[] __initdata = { "osc32k", "timerclk89", };
50
-
static const char *timer9_mux_p[] __initdata = { "osc32k", "timerclk89", };
51
-
static const char *uart0_mux_p[] __initdata = { "osc26m", "pclk", };
52
-
static const char *uart1_mux_p[] __initdata = { "osc26m", "pclk", };
53
-
static const char *uart2_mux_p[] __initdata = { "osc26m", "pclk", };
54
-
static const char *uart3_mux_p[] __initdata = { "osc26m", "pclk", };
55
-
static const char *uart4_mux_p[] __initdata = { "osc26m", "pclk", };
56
-
static const char *spi0_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", };
57
-
static const char *spi1_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", };
58
-
static const char *spi2_mux_p[] __initdata = { "osc26m", "rclk_cfgaxi", };
41
+
static const char *timer0_mux_p[] __initconst = { "osc32k", "timerclk01", };
42
+
static const char *timer1_mux_p[] __initconst = { "osc32k", "timerclk01", };
43
+
static const char *timer2_mux_p[] __initconst = { "osc32k", "timerclk23", };
44
+
static const char *timer3_mux_p[] __initconst = { "osc32k", "timerclk23", };
45
+
static const char *timer4_mux_p[] __initconst = { "osc32k", "timerclk45", };
46
+
static const char *timer5_mux_p[] __initconst = { "osc32k", "timerclk45", };
47
+
static const char *timer6_mux_p[] __initconst = { "osc32k", "timerclk67", };
48
+
static const char *timer7_mux_p[] __initconst = { "osc32k", "timerclk67", };
49
+
static const char *timer8_mux_p[] __initconst = { "osc32k", "timerclk89", };
50
+
static const char *timer9_mux_p[] __initconst = { "osc32k", "timerclk89", };
51
+
static const char *uart0_mux_p[] __initconst = { "osc26m", "pclk", };
52
+
static const char *uart1_mux_p[] __initconst = { "osc26m", "pclk", };
53
+
static const char *uart2_mux_p[] __initconst = { "osc26m", "pclk", };
54
+
static const char *uart3_mux_p[] __initconst = { "osc26m", "pclk", };
55
+
static const char *uart4_mux_p[] __initconst = { "osc26m", "pclk", };
56
+
static const char *spi0_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", };
57
+
static const char *spi1_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", };
58
+
static const char *spi2_mux_p[] __initconst = { "osc26m", "rclk_cfgaxi", };
59
59
/* share axi parent */
60
-
static const char *saxi_mux_p[] __initdata = { "armpll3", "armpll2", };
61
-
static const char *pwm0_mux_p[] __initdata = { "osc32k", "osc26m", };
62
-
static const char *pwm1_mux_p[] __initdata = { "osc32k", "osc26m", };
63
-
static const char *sd_mux_p[] __initdata = { "armpll2", "armpll3", };
64
-
static const char *mmc1_mux_p[] __initdata = { "armpll2", "armpll3", };
65
-
static const char *mmc1_mux2_p[] __initdata = { "osc26m", "mmc1_div", };
66
-
static const char *g2d_mux_p[] __initdata = { "armpll2", "armpll3", };
67
-
static const char *venc_mux_p[] __initdata = { "armpll2", "armpll3", };
68
-
static const char *vdec_mux_p[] __initdata = { "armpll2", "armpll3", };
69
-
static const char *vpp_mux_p[] __initdata = { "armpll2", "armpll3", };
70
-
static const char *edc0_mux_p[] __initdata = { "armpll2", "armpll3", };
71
-
static const char *ldi0_mux_p[] __initdata = { "armpll2", "armpll4",
60
+
static const char *saxi_mux_p[] __initconst = { "armpll3", "armpll2", };
61
+
static const char *pwm0_mux_p[] __initconst = { "osc32k", "osc26m", };
62
+
static const char *pwm1_mux_p[] __initconst = { "osc32k", "osc26m", };
63
+
static const char *sd_mux_p[] __initconst = { "armpll2", "armpll3", };
64
+
static const char *mmc1_mux_p[] __initconst = { "armpll2", "armpll3", };
65
+
static const char *mmc1_mux2_p[] __initconst = { "osc26m", "mmc1_div", };
66
+
static const char *g2d_mux_p[] __initconst = { "armpll2", "armpll3", };
67
+
static const char *venc_mux_p[] __initconst = { "armpll2", "armpll3", };
68
+
static const char *vdec_mux_p[] __initconst = { "armpll2", "armpll3", };
69
+
static const char *vpp_mux_p[] __initconst = { "armpll2", "armpll3", };
70
+
static const char *edc0_mux_p[] __initconst = { "armpll2", "armpll3", };
71
+
static const char *ldi0_mux_p[] __initconst = { "armpll2", "armpll4",
72
72
"armpll3", "armpll5", };
73
-
static const char *edc1_mux_p[] __initdata = { "armpll2", "armpll3", };
74
-
static const char *ldi1_mux_p[] __initdata = { "armpll2", "armpll4",
73
+
static const char *edc1_mux_p[] __initconst = { "armpll2", "armpll3", };
74
+
static const char *ldi1_mux_p[] __initconst = { "armpll2", "armpll4",
75
75
"armpll3", "armpll5", };
76
-
static const char *rclk_hsic_p[] __initdata = { "armpll3", "armpll2", };
77
-
static const char *mmc2_mux_p[] __initdata = { "armpll2", "armpll3", };
78
-
static const char *mmc3_mux_p[] __initdata = { "armpll2", "armpll3", };
76
+
static const char *rclk_hsic_p[] __initconst = { "armpll3", "armpll2", };
77
+
static const char *mmc2_mux_p[] __initconst = { "armpll2", "armpll3", };
78
+
static const char *mmc3_mux_p[] __initconst = { "armpll2", "armpll3", };
79
79
80
80
81
81
/* fixed rate clocks */
···
296
296
297
297
static long mmc_clk_determine_rate(struct clk_hw *hw, unsigned long rate,
298
298
unsigned long *best_parent_rate,
299
-
struct clk **best_parent_p)
299
+
struct clk_hw **best_parent_p)
300
300
{
301
301
struct clk_mmc *mclk = to_mmc(hw);
302
302
unsigned long best = 0;
+6
-1
drivers/clk/mmp/Makefile
+6
-1
drivers/clk/mmp/Makefile
···
2
2
# Makefile for mmp specific clk
3
3
#
4
4
5
-
obj-y += clk-apbc.o clk-apmu.o clk-frac.o
5
+
obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o clk-gate.o clk.o
6
+
7
+
obj-$(CONFIG_RESET_CONTROLLER) += reset.o
8
+
9
+
obj-$(CONFIG_MACH_MMP_DT) += clk-of-pxa168.o clk-of-pxa910.o
10
+
obj-$(CONFIG_MACH_MMP2_DT) += clk-of-mmp2.o
6
11
7
12
obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
8
13
obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
+58
-16
drivers/clk/mmp/clk-frac.c
+58
-16
drivers/clk/mmp/clk-frac.c
···
22
22
* numerator/denominator = Fin / (Fout * factor)
23
23
*/
24
24
25
-
#define to_clk_factor(hw) container_of(hw, struct clk_factor, hw)
26
-
struct clk_factor {
27
-
struct clk_hw hw;
28
-
void __iomem *base;
29
-
struct clk_factor_masks *masks;
30
-
struct clk_factor_tbl *ftbl;
31
-
unsigned int ftbl_cnt;
32
-
};
25
+
#define to_clk_factor(hw) container_of(hw, struct mmp_clk_factor, hw)
33
26
34
27
static long clk_factor_round_rate(struct clk_hw *hw, unsigned long drate,
35
28
unsigned long *prate)
36
29
{
37
-
struct clk_factor *factor = to_clk_factor(hw);
30
+
struct mmp_clk_factor *factor = to_clk_factor(hw);
38
31
unsigned long rate = 0, prev_rate;
39
32
int i;
40
33
···
51
58
static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
52
59
unsigned long parent_rate)
53
60
{
54
-
struct clk_factor *factor = to_clk_factor(hw);
55
-
struct clk_factor_masks *masks = factor->masks;
61
+
struct mmp_clk_factor *factor = to_clk_factor(hw);
62
+
struct mmp_clk_factor_masks *masks = factor->masks;
56
63
unsigned int val, num, den;
57
64
58
65
val = readl_relaxed(factor->base);
···
74
81
static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
75
82
unsigned long prate)
76
83
{
77
-
struct clk_factor *factor = to_clk_factor(hw);
78
-
struct clk_factor_masks *masks = factor->masks;
84
+
struct mmp_clk_factor *factor = to_clk_factor(hw);
85
+
struct mmp_clk_factor_masks *masks = factor->masks;
79
86
int i;
80
87
unsigned long val;
81
88
unsigned long prev_rate, rate = 0;
89
+
unsigned long flags = 0;
82
90
83
91
for (i = 0; i < factor->ftbl_cnt; i++) {
84
92
prev_rate = rate;
···
91
97
if (i > 0)
92
98
i--;
93
99
100
+
if (factor->lock)
101
+
spin_lock_irqsave(factor->lock, flags);
102
+
94
103
val = readl_relaxed(factor->base);
95
104
96
105
val &= ~(masks->num_mask << masks->num_shift);
···
104
107
105
108
writel_relaxed(val, factor->base);
106
109
110
+
if (factor->lock)
111
+
spin_unlock_irqrestore(factor->lock, flags);
112
+
107
113
return 0;
114
+
}
115
+
116
+
static void clk_factor_init(struct clk_hw *hw)
117
+
{
118
+
struct mmp_clk_factor *factor = to_clk_factor(hw);
119
+
struct mmp_clk_factor_masks *masks = factor->masks;
120
+
u32 val, num, den;
121
+
int i;
122
+
unsigned long flags = 0;
123
+
124
+
if (factor->lock)
125
+
spin_lock_irqsave(factor->lock, flags);
126
+
127
+
val = readl(factor->base);
128
+
129
+
/* calculate numerator */
130
+
num = (val >> masks->num_shift) & masks->num_mask;
131
+
132
+
/* calculate denominator */
133
+
den = (val >> masks->den_shift) & masks->den_mask;
134
+
135
+
for (i = 0; i < factor->ftbl_cnt; i++)
136
+
if (den == factor->ftbl[i].den && num == factor->ftbl[i].num)
137
+
break;
138
+
139
+
if (i >= factor->ftbl_cnt) {
140
+
val &= ~(masks->num_mask << masks->num_shift);
141
+
val |= (factor->ftbl[0].num & masks->num_mask) <<
142
+
masks->num_shift;
143
+
144
+
val &= ~(masks->den_mask << masks->den_shift);
145
+
val |= (factor->ftbl[0].den & masks->den_mask) <<
146
+
masks->den_shift;
147
+
148
+
writel(val, factor->base);
149
+
}
150
+
151
+
if (factor->lock)
152
+
spin_unlock_irqrestore(factor->lock, flags);
108
153
}
109
154
110
155
static struct clk_ops clk_factor_ops = {
111
156
.recalc_rate = clk_factor_recalc_rate,
112
157
.round_rate = clk_factor_round_rate,
113
158
.set_rate = clk_factor_set_rate,
159
+
.init = clk_factor_init,
114
160
};
115
161
116
162
struct clk *mmp_clk_register_factor(const char *name, const char *parent_name,
117
163
unsigned long flags, void __iomem *base,
118
-
struct clk_factor_masks *masks, struct clk_factor_tbl *ftbl,
119
-
unsigned int ftbl_cnt)
164
+
struct mmp_clk_factor_masks *masks,
165
+
struct mmp_clk_factor_tbl *ftbl,
166
+
unsigned int ftbl_cnt, spinlock_t *lock)
120
167
{
121
-
struct clk_factor *factor;
168
+
struct mmp_clk_factor *factor;
122
169
struct clk_init_data init;
123
170
struct clk *clk;
124
171
···
183
142
factor->ftbl = ftbl;
184
143
factor->ftbl_cnt = ftbl_cnt;
185
144
factor->hw.init = &init;
145
+
factor->lock = lock;
186
146
187
147
init.name = name;
188
148
init.ops = &clk_factor_ops;
+133
drivers/clk/mmp/clk-gate.c
+133
drivers/clk/mmp/clk-gate.c
···
1
+
/*
2
+
* mmp gate clock operation source file
3
+
*
4
+
* Copyright (C) 2014 Marvell
5
+
* Chao Xie <chao.xie@marvell.com>
6
+
*
7
+
* This file is licensed under the terms of the GNU General Public
8
+
* License version 2. This program is licensed "as is" without any
9
+
* warranty of any kind, whether express or implied.
10
+
*/
11
+
12
+
#include <linux/clk-provider.h>
13
+
#include <linux/slab.h>
14
+
#include <linux/io.h>
15
+
#include <linux/err.h>
16
+
#include <linux/delay.h>
17
+
18
+
#include "clk.h"
19
+
20
+
/*
21
+
* Some clocks will have mutiple bits to enable the clocks, and
22
+
* the bits to disable the clock is not same as enabling bits.
23
+
*/
24
+
25
+
#define to_clk_mmp_gate(hw) container_of(hw, struct mmp_clk_gate, hw)
26
+
27
+
static int mmp_clk_gate_enable(struct clk_hw *hw)
28
+
{
29
+
struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
30
+
struct clk *clk = hw->clk;
31
+
unsigned long flags = 0;
32
+
unsigned long rate;
33
+
u32 tmp;
34
+
35
+
if (gate->lock)
36
+
spin_lock_irqsave(gate->lock, flags);
37
+
38
+
tmp = readl(gate->reg);
39
+
tmp &= ~gate->mask;
40
+
tmp |= gate->val_enable;
41
+
writel(tmp, gate->reg);
42
+
43
+
if (gate->lock)
44
+
spin_unlock_irqrestore(gate->lock, flags);
45
+
46
+
if (gate->flags & MMP_CLK_GATE_NEED_DELAY) {
47
+
rate = __clk_get_rate(clk);
48
+
/* Need delay 2 cycles. */
49
+
udelay(2000000/rate);
50
+
}
51
+
52
+
return 0;
53
+
}
54
+
55
+
static void mmp_clk_gate_disable(struct clk_hw *hw)
56
+
{
57
+
struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
58
+
unsigned long flags = 0;
59
+
u32 tmp;
60
+
61
+
if (gate->lock)
62
+
spin_lock_irqsave(gate->lock, flags);
63
+
64
+
tmp = readl(gate->reg);
65
+
tmp &= ~gate->mask;
66
+
tmp |= gate->val_disable;
67
+
writel(tmp, gate->reg);
68
+
69
+
if (gate->lock)
70
+
spin_unlock_irqrestore(gate->lock, flags);
71
+
}
72
+
73
+
static int mmp_clk_gate_is_enabled(struct clk_hw *hw)
74
+
{
75
+
struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
76
+
unsigned long flags = 0;
77
+
u32 tmp;
78
+
79
+
if (gate->lock)
80
+
spin_lock_irqsave(gate->lock, flags);
81
+
82
+
tmp = readl(gate->reg);
83
+
84
+
if (gate->lock)
85
+
spin_unlock_irqrestore(gate->lock, flags);
86
+
87
+
return (tmp & gate->mask) == gate->val_enable;
88
+
}
89
+
90
+
const struct clk_ops mmp_clk_gate_ops = {
91
+
.enable = mmp_clk_gate_enable,
92
+
.disable = mmp_clk_gate_disable,
93
+
.is_enabled = mmp_clk_gate_is_enabled,
94
+
};
95
+
96
+
struct clk *mmp_clk_register_gate(struct device *dev, const char *name,
97
+
const char *parent_name, unsigned long flags,
98
+
void __iomem *reg, u32 mask, u32 val_enable, u32 val_disable,
99
+
unsigned int gate_flags, spinlock_t *lock)
100
+
{
101
+
struct mmp_clk_gate *gate;
102
+
struct clk *clk;
103
+
struct clk_init_data init;
104
+
105
+
/* allocate the gate */
106
+
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
107
+
if (!gate) {
108
+
pr_err("%s:%s could not allocate gate clk\n", __func__, name);
109
+
return ERR_PTR(-ENOMEM);
110
+
}
111
+
112
+
init.name = name;
113
+
init.ops = &mmp_clk_gate_ops;
114
+
init.flags = flags | CLK_IS_BASIC;
115
+
init.parent_names = (parent_name ? &parent_name : NULL);
116
+
init.num_parents = (parent_name ? 1 : 0);
117
+
118
+
/* struct clk_gate assignments */
119
+
gate->reg = reg;
120
+
gate->mask = mask;
121
+
gate->val_enable = val_enable;
122
+
gate->val_disable = val_disable;
123
+
gate->flags = gate_flags;
124
+
gate->lock = lock;
125
+
gate->hw.init = &init;
126
+
127
+
clk = clk_register(dev, &gate->hw);
128
+
129
+
if (IS_ERR(clk))
130
+
kfree(gate);
131
+
132
+
return clk;
133
+
}
+513
drivers/clk/mmp/clk-mix.c
+513
drivers/clk/mmp/clk-mix.c
···
1
+
/*
2
+
* mmp mix(div and mux) clock operation source file
3
+
*
4
+
* Copyright (C) 2014 Marvell
5
+
* Chao Xie <chao.xie@marvell.com>
6
+
*
7
+
* This file is licensed under the terms of the GNU General Public
8
+
* License version 2. This program is licensed "as is" without any
9
+
* warranty of any kind, whether express or implied.
10
+
*/
11
+
12
+
#include <linux/clk-provider.h>
13
+
#include <linux/slab.h>
14
+
#include <linux/io.h>
15
+
#include <linux/err.h>
16
+
17
+
#include "clk.h"
18
+
19
+
/*
20
+
* The mix clock is a clock combined mux and div type clock.
21
+
* Because the div field and mux field need to be set at same
22
+
* time, we can not divide it into 2 types of clock
23
+
*/
24
+
25
+
#define to_clk_mix(hw) container_of(hw, struct mmp_clk_mix, hw)
26
+
27
+
static unsigned int _get_maxdiv(struct mmp_clk_mix *mix)
28
+
{
29
+
unsigned int div_mask = (1 << mix->reg_info.width_div) - 1;
30
+
unsigned int maxdiv = 0;
31
+
struct clk_div_table *clkt;
32
+
33
+
if (mix->div_flags & CLK_DIVIDER_ONE_BASED)
34
+
return div_mask;
35
+
if (mix->div_flags & CLK_DIVIDER_POWER_OF_TWO)
36
+
return 1 << div_mask;
37
+
if (mix->div_table) {
38
+
for (clkt = mix->div_table; clkt->div; clkt++)
39
+
if (clkt->div > maxdiv)
40
+
maxdiv = clkt->div;
41
+
return maxdiv;
42
+
}
43
+
return div_mask + 1;
44
+
}
45
+
46
+
static unsigned int _get_div(struct mmp_clk_mix *mix, unsigned int val)
47
+
{
48
+
struct clk_div_table *clkt;
49
+
50
+
if (mix->div_flags & CLK_DIVIDER_ONE_BASED)
51
+
return val;
52
+
if (mix->div_flags & CLK_DIVIDER_POWER_OF_TWO)
53
+
return 1 << val;
54
+
if (mix->div_table) {
55
+
for (clkt = mix->div_table; clkt->div; clkt++)
56
+
if (clkt->val == val)
57
+
return clkt->div;
58
+
if (clkt->div == 0)
59
+
return 0;
60
+
}
61
+
return val + 1;
62
+
}
63
+
64
+
static unsigned int _get_mux(struct mmp_clk_mix *mix, unsigned int val)
65
+
{
66
+
int num_parents = __clk_get_num_parents(mix->hw.clk);
67
+
int i;
68
+
69
+
if (mix->mux_flags & CLK_MUX_INDEX_BIT)
70
+
return ffs(val) - 1;
71
+
if (mix->mux_flags & CLK_MUX_INDEX_ONE)
72
+
return val - 1;
73
+
if (mix->mux_table) {
74
+
for (i = 0; i < num_parents; i++)
75
+
if (mix->mux_table[i] == val)
76
+
return i;
77
+
if (i == num_parents)
78
+
return 0;
79
+
}
80
+
81
+
return val;
82
+
}
83
+
static unsigned int _get_div_val(struct mmp_clk_mix *mix, unsigned int div)
84
+
{
85
+
struct clk_div_table *clkt;
86
+
87
+
if (mix->div_flags & CLK_DIVIDER_ONE_BASED)
88
+
return div;
89
+
if (mix->div_flags & CLK_DIVIDER_POWER_OF_TWO)
90
+
return __ffs(div);
91
+
if (mix->div_table) {
92
+
for (clkt = mix->div_table; clkt->div; clkt++)
93
+
if (clkt->div == div)
94
+
return clkt->val;
95
+
if (clkt->div == 0)
96
+
return 0;
97
+
}
98
+
99
+
return div - 1;
100
+
}
101
+
102
+
static unsigned int _get_mux_val(struct mmp_clk_mix *mix, unsigned int mux)
103
+
{
104
+
if (mix->mux_table)
105
+
return mix->mux_table[mux];
106
+
107
+
return mux;
108
+
}
109
+
110
+
static void _filter_clk_table(struct mmp_clk_mix *mix,
111
+
struct mmp_clk_mix_clk_table *table,
112
+
unsigned int table_size)
113
+
{
114
+
int i;
115
+
struct mmp_clk_mix_clk_table *item;
116
+
struct clk *parent, *clk;
117
+
unsigned long parent_rate;
118
+
119
+
clk = mix->hw.clk;
120
+
121
+
for (i = 0; i < table_size; i++) {
122
+
item = &table[i];
123
+
parent = clk_get_parent_by_index(clk, item->parent_index);
124
+
parent_rate = __clk_get_rate(parent);
125
+
if (parent_rate % item->rate) {
126
+
item->valid = 0;
127
+
} else {
128
+
item->divisor = parent_rate / item->rate;
129
+
item->valid = 1;
130
+
}
131
+
}
132
+
}
133
+
134
+
static int _set_rate(struct mmp_clk_mix *mix, u32 mux_val, u32 div_val,
135
+
unsigned int change_mux, unsigned int change_div)
136
+
{
137
+
struct mmp_clk_mix_reg_info *ri = &mix->reg_info;
138
+
u8 width, shift;
139
+
u32 mux_div, fc_req;
140
+
int ret, timeout = 50;
141
+
unsigned long flags = 0;
142
+
143
+
if (!change_mux && !change_div)
144
+
return -EINVAL;
145
+
146
+
if (mix->lock)
147
+
spin_lock_irqsave(mix->lock, flags);
148
+
149
+
if (mix->type == MMP_CLK_MIX_TYPE_V1
150
+
|| mix->type == MMP_CLK_MIX_TYPE_V2)
151
+
mux_div = readl(ri->reg_clk_ctrl);
152
+
else
153
+
mux_div = readl(ri->reg_clk_sel);
154
+
155
+
if (change_div) {
156
+
width = ri->width_div;
157
+
shift = ri->shift_div;
158
+
mux_div &= ~MMP_CLK_BITS_MASK(width, shift);
159
+
mux_div |= MMP_CLK_BITS_SET_VAL(div_val, width, shift);
160
+
}
161
+
162
+
if (change_mux) {
163
+
width = ri->width_mux;
164
+
shift = ri->shift_mux;
165
+
mux_div &= ~MMP_CLK_BITS_MASK(width, shift);
166
+
mux_div |= MMP_CLK_BITS_SET_VAL(mux_val, width, shift);
167
+
}
168
+
169
+
if (mix->type == MMP_CLK_MIX_TYPE_V1) {
170
+
writel(mux_div, ri->reg_clk_ctrl);
171
+
} else if (mix->type == MMP_CLK_MIX_TYPE_V2) {
172
+
mux_div |= (1 << ri->bit_fc);
173
+
writel(mux_div, ri->reg_clk_ctrl);
174
+
175
+
do {
176
+
fc_req = readl(ri->reg_clk_ctrl);
177
+
timeout--;
178
+
if (!(fc_req & (1 << ri->bit_fc)))
179
+
break;
180
+
} while (timeout);
181
+
182
+
if (timeout == 0) {
183
+
pr_err("%s:%s cannot do frequency change\n",
184
+
__func__, __clk_get_name(mix->hw.clk));
185
+
ret = -EBUSY;
186
+
goto error;
187
+
}
188
+
} else {
189
+
fc_req = readl(ri->reg_clk_ctrl);
190
+
fc_req |= 1 << ri->bit_fc;
191
+
writel(fc_req, ri->reg_clk_ctrl);
192
+
writel(mux_div, ri->reg_clk_sel);
193
+
fc_req &= ~(1 << ri->bit_fc);
194
+
}
195
+
196
+
ret = 0;
197
+
error:
198
+
if (mix->lock)
199
+
spin_unlock_irqrestore(mix->lock, flags);
200
+
201
+
return ret;
202
+
}
203
+
204
+
static long mmp_clk_mix_determine_rate(struct clk_hw *hw, unsigned long rate,
205
+
unsigned long *best_parent_rate,
206
+
struct clk_hw **best_parent_clk)
207
+
{
208
+
struct mmp_clk_mix *mix = to_clk_mix(hw);
209
+
struct mmp_clk_mix_clk_table *item;
210
+
struct clk *parent, *parent_best, *mix_clk;
211
+
unsigned long parent_rate, mix_rate, mix_rate_best, parent_rate_best;
212
+
unsigned long gap, gap_best;
213
+
u32 div_val_max;
214
+
unsigned int div;
215
+
int i, j;
216
+
217
+
mix_clk = hw->clk;
218
+
219
+
parent = NULL;
220
+
mix_rate_best = 0;
221
+
parent_rate_best = 0;
222
+
gap_best = rate;
223
+
parent_best = NULL;
224
+
225
+
if (mix->table) {
226
+
for (i = 0; i < mix->table_size; i++) {
227
+
item = &mix->table[i];
228
+
if (item->valid == 0)
229
+
continue;
230
+
parent = clk_get_parent_by_index(mix_clk,
231
+
item->parent_index);
232
+
parent_rate = __clk_get_rate(parent);
233
+
mix_rate = parent_rate / item->divisor;
234
+
gap = abs(mix_rate - rate);
235
+
if (parent_best == NULL || gap < gap_best) {
236
+
parent_best = parent;
237
+
parent_rate_best = parent_rate;
238
+
mix_rate_best = mix_rate;
239
+
gap_best = gap;
240
+
if (gap_best == 0)
241
+
goto found;
242
+
}
243
+
}
244
+
} else {
245
+
for (i = 0; i < __clk_get_num_parents(mix_clk); i++) {
246
+
parent = clk_get_parent_by_index(mix_clk, i);
247
+
parent_rate = __clk_get_rate(parent);
248
+
div_val_max = _get_maxdiv(mix);
249
+
for (j = 0; j < div_val_max; j++) {
250
+
div = _get_div(mix, j);
251
+
mix_rate = parent_rate / div;
252
+
gap = abs(mix_rate - rate);
253
+
if (parent_best == NULL || gap < gap_best) {
254
+
parent_best = parent;
255
+
parent_rate_best = parent_rate;
256
+
mix_rate_best = mix_rate;
257
+
gap_best = gap;
258
+
if (gap_best == 0)
259
+
goto found;
260
+
}
261
+
}
262
+
}
263
+
}
264
+
265
+
found:
266
+
*best_parent_rate = parent_rate_best;
267
+
*best_parent_clk = __clk_get_hw(parent_best);
268
+
269
+
return mix_rate_best;
270
+
}
271
+
272
+
static int mmp_clk_mix_set_rate_and_parent(struct clk_hw *hw,
273
+
unsigned long rate,
274
+
unsigned long parent_rate,
275
+
u8 index)
276
+
{
277
+
struct mmp_clk_mix *mix = to_clk_mix(hw);
278
+
unsigned int div;
279
+
u32 div_val, mux_val;
280
+
281
+
div = parent_rate / rate;
282
+
div_val = _get_div_val(mix, div);
283
+
mux_val = _get_mux_val(mix, index);
284
+
285
+
return _set_rate(mix, mux_val, div_val, 1, 1);
286
+
}
287
+
288
+
static u8 mmp_clk_mix_get_parent(struct clk_hw *hw)
289
+
{
290
+
struct mmp_clk_mix *mix = to_clk_mix(hw);
291
+
struct mmp_clk_mix_reg_info *ri = &mix->reg_info;
292
+
unsigned long flags = 0;
293
+
u32 mux_div = 0;
294
+
u8 width, shift;
295
+
u32 mux_val;
296
+
297
+
if (mix->lock)
298
+
spin_lock_irqsave(mix->lock, flags);
299
+
300
+
if (mix->type == MMP_CLK_MIX_TYPE_V1
301
+
|| mix->type == MMP_CLK_MIX_TYPE_V2)
302
+
mux_div = readl(ri->reg_clk_ctrl);
303
+
else
304
+
mux_div = readl(ri->reg_clk_sel);
305
+
306
+
if (mix->lock)
307
+
spin_unlock_irqrestore(mix->lock, flags);
308
+
309
+
width = mix->reg_info.width_mux;
310
+
shift = mix->reg_info.shift_mux;
311
+
312
+
mux_val = MMP_CLK_BITS_GET_VAL(mux_div, width, shift);
313
+
314
+
return _get_mux(mix, mux_val);
315
+
}
316
+
317
+
static unsigned long mmp_clk_mix_recalc_rate(struct clk_hw *hw,
318
+
unsigned long parent_rate)
319
+
{
320
+
struct mmp_clk_mix *mix = to_clk_mix(hw);
321
+
struct mmp_clk_mix_reg_info *ri = &mix->reg_info;
322
+
unsigned long flags = 0;
323
+
u32 mux_div = 0;
324
+
u8 width, shift;
325
+
unsigned int div;
326
+
327
+
if (mix->lock)
328
+
spin_lock_irqsave(mix->lock, flags);
329
+
330
+
if (mix->type == MMP_CLK_MIX_TYPE_V1
331
+
|| mix->type == MMP_CLK_MIX_TYPE_V2)
332
+
mux_div = readl(ri->reg_clk_ctrl);
333
+
else
334
+
mux_div = readl(ri->reg_clk_sel);
335
+
336
+
if (mix->lock)
337
+
spin_unlock_irqrestore(mix->lock, flags);
338
+
339
+
width = mix->reg_info.width_div;
340
+
shift = mix->reg_info.shift_div;
341
+
342
+
div = _get_div(mix, MMP_CLK_BITS_GET_VAL(mux_div, width, shift));
343
+
344
+
return parent_rate / div;
345
+
}
346
+
347
+
static int mmp_clk_set_parent(struct clk_hw *hw, u8 index)
348
+
{
349
+
struct mmp_clk_mix *mix = to_clk_mix(hw);
350
+
struct mmp_clk_mix_clk_table *item;
351
+
int i;
352
+
u32 div_val, mux_val;
353
+
354
+
if (mix->table) {
355
+
for (i = 0; i < mix->table_size; i++) {
356
+
item = &mix->table[i];
357
+
if (item->valid == 0)
358
+
continue;
359
+
if (item->parent_index == index)
360
+
break;
361
+
}
362
+
if (i < mix->table_size) {
363
+
div_val = _get_div_val(mix, item->divisor);
364
+
mux_val = _get_mux_val(mix, item->parent_index);
365
+
} else
366
+
return -EINVAL;
367
+
} else {
368
+
mux_val = _get_mux_val(mix, index);
369
+
div_val = 0;
370
+
}
371
+
372
+
return _set_rate(mix, mux_val, div_val, 1, div_val ? 1 : 0);
373
+
}
374
+
375
+
static int mmp_clk_set_rate(struct clk_hw *hw, unsigned long rate,
376
+
unsigned long best_parent_rate)
377
+
{
378
+
struct mmp_clk_mix *mix = to_clk_mix(hw);
379
+
struct mmp_clk_mix_clk_table *item;
380
+
unsigned long parent_rate;
381
+
unsigned int best_divisor;
382
+
struct clk *mix_clk, *parent;
383
+
int i;
384
+
385
+
best_divisor = best_parent_rate / rate;
386
+
387
+
mix_clk = hw->clk;
388
+
if (mix->table) {
389
+
for (i = 0; i < mix->table_size; i++) {
390
+
item = &mix->table[i];
391
+
if (item->valid == 0)
392
+
continue;
393
+
parent = clk_get_parent_by_index(mix_clk,
394
+
item->parent_index);
395
+
parent_rate = __clk_get_rate(parent);
396
+
if (parent_rate == best_parent_rate
397
+
&& item->divisor == best_divisor)
398
+
break;
399
+
}
400
+
if (i < mix->table_size)
401
+
return _set_rate(mix,
402
+
_get_mux_val(mix, item->parent_index),
403
+
_get_div_val(mix, item->divisor),
404
+
1, 1);
405
+
else
406
+
return -EINVAL;
407
+
} else {
408
+
for (i = 0; i < __clk_get_num_parents(mix_clk); i++) {
409
+
parent = clk_get_parent_by_index(mix_clk, i);
410
+
parent_rate = __clk_get_rate(parent);
411
+
if (parent_rate == best_parent_rate)
412
+
break;
413
+
}
414
+
if (i < __clk_get_num_parents(mix_clk))
415
+
return _set_rate(mix, _get_mux_val(mix, i),
416
+
_get_div_val(mix, best_divisor), 1, 1);
417
+
else
418
+
return -EINVAL;
419
+
}
420
+
}
421
+
422
+
static void mmp_clk_mix_init(struct clk_hw *hw)
423
+
{
424
+
struct mmp_clk_mix *mix = to_clk_mix(hw);
425
+
426
+
if (mix->table)
427
+
_filter_clk_table(mix, mix->table, mix->table_size);
428
+
}
429
+
430
+
const struct clk_ops mmp_clk_mix_ops = {
431
+
.determine_rate = mmp_clk_mix_determine_rate,
432
+
.set_rate_and_parent = mmp_clk_mix_set_rate_and_parent,
433
+
.set_rate = mmp_clk_set_rate,
434
+
.set_parent = mmp_clk_set_parent,
435
+
.get_parent = mmp_clk_mix_get_parent,
436
+
.recalc_rate = mmp_clk_mix_recalc_rate,
437
+
.init = mmp_clk_mix_init,
438
+
};
439
+
440
+
struct clk *mmp_clk_register_mix(struct device *dev,
441
+
const char *name,
442
+
const char **parent_names,
443
+
u8 num_parents,
444
+
unsigned long flags,
445
+
struct mmp_clk_mix_config *config,
446
+
spinlock_t *lock)
447
+
{
448
+
struct mmp_clk_mix *mix;
449
+
struct clk *clk;
450
+
struct clk_init_data init;
451
+
size_t table_bytes;
452
+
453
+
mix = kzalloc(sizeof(*mix), GFP_KERNEL);
454
+
if (!mix) {
455
+
pr_err("%s:%s: could not allocate mmp mix clk\n",
456
+
__func__, name);
457
+
return ERR_PTR(-ENOMEM);
458
+
}
459
+
460
+
init.name = name;
461
+
init.flags = flags | CLK_GET_RATE_NOCACHE;
462
+
init.parent_names = parent_names;
463
+
init.num_parents = num_parents;
464
+
init.ops = &mmp_clk_mix_ops;
465
+
466
+
memcpy(&mix->reg_info, &config->reg_info, sizeof(config->reg_info));
467
+
if (config->table) {
468
+
table_bytes = sizeof(*config->table) * config->table_size;
469
+
mix->table = kzalloc(table_bytes, GFP_KERNEL);
470
+
if (!mix->table) {
471
+
pr_err("%s:%s: could not allocate mmp mix table\n",
472
+
__func__, name);
473
+
kfree(mix);
474
+
return ERR_PTR(-ENOMEM);
475
+
}
476
+
memcpy(mix->table, config->table, table_bytes);
477
+
mix->table_size = config->table_size;
478
+
}
479
+
480
+
if (config->mux_table) {
481
+
table_bytes = sizeof(u32) * num_parents;
482
+
mix->mux_table = kzalloc(table_bytes, GFP_KERNEL);
483
+
if (!mix->mux_table) {
484
+
pr_err("%s:%s: could not allocate mmp mix mux-table\n",
485
+
__func__, name);
486
+
kfree(mix->table);
487
+
kfree(mix);
488
+
return ERR_PTR(-ENOMEM);
489
+
}
490
+
memcpy(mix->mux_table, config->mux_table, table_bytes);
491
+
}
492
+
493
+
mix->div_flags = config->div_flags;
494
+
mix->mux_flags = config->mux_flags;
495
+
mix->lock = lock;
496
+
mix->hw.init = &init;
497
+
498
+
if (config->reg_info.bit_fc >= 32)
499
+
mix->type = MMP_CLK_MIX_TYPE_V1;
500
+
else if (config->reg_info.reg_clk_sel)
501
+
mix->type = MMP_CLK_MIX_TYPE_V3;
502
+
else
503
+
mix->type = MMP_CLK_MIX_TYPE_V2;
504
+
clk = clk_register(dev, &mix->hw);
505
+
506
+
if (IS_ERR(clk)) {
507
+
kfree(mix->mux_table);
508
+
kfree(mix->table);
509
+
kfree(mix);
510
+
}
511
+
512
+
return clk;
513
+
}
+3
-3
drivers/clk/mmp/clk-mmp2.c
+3
-3
drivers/clk/mmp/clk-mmp2.c
···
54
54
55
55
static DEFINE_SPINLOCK(clk_lock);
56
56
57
-
static struct clk_factor_masks uart_factor_masks = {
57
+
static struct mmp_clk_factor_masks uart_factor_masks = {
58
58
.factor = 2,
59
59
.num_mask = 0x1fff,
60
60
.den_mask = 0x1fff,
···
62
62
.den_shift = 0,
63
63
};
64
64
65
-
static struct clk_factor_tbl uart_factor_tbl[] = {
65
+
static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
66
66
{.num = 14634, .den = 2165}, /*14.745MHZ */
67
67
{.num = 3521, .den = 689}, /*19.23MHZ */
68
68
{.num = 9679, .den = 5728}, /*58.9824MHZ */
···
191
191
clk = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
192
192
mpmu_base + MPMU_UART_PLL,
193
193
&uart_factor_masks, uart_factor_tbl,
194
-
ARRAY_SIZE(uart_factor_tbl));
194
+
ARRAY_SIZE(uart_factor_tbl), &clk_lock);
195
195
clk_set_rate(clk, 14745600);
196
196
clk_register_clkdev(clk, "uart_pll", NULL);
197
197
+334
drivers/clk/mmp/clk-of-mmp2.c
+334
drivers/clk/mmp/clk-of-mmp2.c
···
1
+
/*
2
+
* mmp2 clock framework source file
3
+
*
4
+
* Copyright (C) 2012 Marvell
5
+
* Chao Xie <xiechao.mail@gmail.com>
6
+
*
7
+
* This file is licensed under the terms of the GNU General Public
8
+
* License version 2. This program is licensed "as is" without any
9
+
* warranty of any kind, whether express or implied.
10
+
*/
11
+
12
+
#include <linux/module.h>
13
+
#include <linux/kernel.h>
14
+
#include <linux/spinlock.h>
15
+
#include <linux/io.h>
16
+
#include <linux/delay.h>
17
+
#include <linux/err.h>
18
+
#include <linux/of_address.h>
19
+
20
+
#include <dt-bindings/clock/marvell,mmp2.h>
21
+
22
+
#include "clk.h"
23
+
#include "reset.h"
24
+
25
+
#define APBC_RTC 0x0
26
+
#define APBC_TWSI0 0x4
27
+
#define APBC_TWSI1 0x8
28
+
#define APBC_TWSI2 0xc
29
+
#define APBC_TWSI3 0x10
30
+
#define APBC_TWSI4 0x7c
31
+
#define APBC_TWSI5 0x80
32
+
#define APBC_KPC 0x18
33
+
#define APBC_UART0 0x2c
34
+
#define APBC_UART1 0x30
35
+
#define APBC_UART2 0x34
36
+
#define APBC_UART3 0x88
37
+
#define APBC_GPIO 0x38
38
+
#define APBC_PWM0 0x3c
39
+
#define APBC_PWM1 0x40
40
+
#define APBC_PWM2 0x44
41
+
#define APBC_PWM3 0x48
42
+
#define APBC_SSP0 0x50
43
+
#define APBC_SSP1 0x54
44
+
#define APBC_SSP2 0x58
45
+
#define APBC_SSP3 0x5c
46
+
#define APMU_SDH0 0x54
47
+
#define APMU_SDH1 0x58
48
+
#define APMU_SDH2 0xe8
49
+
#define APMU_SDH3 0xec
50
+
#define APMU_USB 0x5c
51
+
#define APMU_DISP0 0x4c
52
+
#define APMU_DISP1 0x110
53
+
#define APMU_CCIC0 0x50
54
+
#define APMU_CCIC1 0xf4
55
+
#define MPMU_UART_PLL 0x14
56
+
57
+
struct mmp2_clk_unit {
58
+
struct mmp_clk_unit unit;
59
+
void __iomem *mpmu_base;
60
+
void __iomem *apmu_base;
61
+
void __iomem *apbc_base;
62
+
};
63
+
64
+
static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
65
+
{MMP2_CLK_CLK32, "clk32", NULL, CLK_IS_ROOT, 32768},
66
+
{MMP2_CLK_VCTCXO, "vctcxo", NULL, CLK_IS_ROOT, 26000000},
67
+
{MMP2_CLK_PLL1, "pll1", NULL, CLK_IS_ROOT, 800000000},
68
+
{MMP2_CLK_PLL2, "pll2", NULL, CLK_IS_ROOT, 960000000},
69
+
{MMP2_CLK_USB_PLL, "usb_pll", NULL, CLK_IS_ROOT, 480000000},
70
+
};
71
+
72
+
static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
73
+
{MMP2_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
74
+
{MMP2_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
75
+
{MMP2_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0},
76
+
{MMP2_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0},
77
+
{MMP2_CLK_PLL1_20, "pll1_20", "pll1_4", 1, 5, 0},
78
+
{MMP2_CLK_PLL1_3, "pll1_3", "pll1", 1, 3, 0},
79
+
{MMP2_CLK_PLL1_6, "pll1_6", "pll1_3", 1, 2, 0},
80
+
{MMP2_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0},
81
+
{MMP2_CLK_PLL2_2, "pll2_2", "pll2", 1, 2, 0},
82
+
{MMP2_CLK_PLL2_4, "pll2_4", "pll2_2", 1, 2, 0},
83
+
{MMP2_CLK_PLL2_8, "pll2_8", "pll2_4", 1, 2, 0},
84
+
{MMP2_CLK_PLL2_16, "pll2_16", "pll2_8", 1, 2, 0},
85
+
{MMP2_CLK_PLL2_3, "pll2_3", "pll2", 1, 3, 0},
86
+
{MMP2_CLK_PLL2_6, "pll2_6", "pll2_3", 1, 2, 0},
87
+
{MMP2_CLK_PLL2_12, "pll2_12", "pll2_6", 1, 2, 0},
88
+
{MMP2_CLK_VCTCXO_2, "vctcxo_2", "vctcxo", 1, 2, 0},
89
+
{MMP2_CLK_VCTCXO_4, "vctcxo_4", "vctcxo_2", 1, 2, 0},
90
+
};
91
+
92
+
static struct mmp_clk_factor_masks uart_factor_masks = {
93
+
.factor = 2,
94
+
.num_mask = 0x1fff,
95
+
.den_mask = 0x1fff,
96
+
.num_shift = 16,
97
+
.den_shift = 0,
98
+
};
99
+
100
+
static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
101
+
{.num = 14634, .den = 2165}, /*14.745MHZ */
102
+
{.num = 3521, .den = 689}, /*19.23MHZ */
103
+
{.num = 9679, .den = 5728}, /*58.9824MHZ */
104
+
{.num = 15850, .den = 9451}, /*59.429MHZ */
105
+
};
106
+
107
+
static void mmp2_pll_init(struct mmp2_clk_unit *pxa_unit)
108
+
{
109
+
struct clk *clk;
110
+
struct mmp_clk_unit *unit = &pxa_unit->unit;
111
+
112
+
mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
113
+
ARRAY_SIZE(fixed_rate_clks));
114
+
115
+
mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
116
+
ARRAY_SIZE(fixed_factor_clks));
117
+
118
+
clk = mmp_clk_register_factor("uart_pll", "pll1_4",
119
+
CLK_SET_RATE_PARENT,
120
+
pxa_unit->mpmu_base + MPMU_UART_PLL,
121
+
&uart_factor_masks, uart_factor_tbl,
122
+
ARRAY_SIZE(uart_factor_tbl), NULL);
123
+
mmp_clk_add(unit, MMP2_CLK_UART_PLL, clk);
124
+
}
125
+
126
+
static DEFINE_SPINLOCK(uart0_lock);
127
+
static DEFINE_SPINLOCK(uart1_lock);
128
+
static DEFINE_SPINLOCK(uart2_lock);
129
+
static const char *uart_parent_names[] = {"uart_pll", "vctcxo"};
130
+
131
+
static DEFINE_SPINLOCK(ssp0_lock);
132
+
static DEFINE_SPINLOCK(ssp1_lock);
133
+
static DEFINE_SPINLOCK(ssp2_lock);
134
+
static DEFINE_SPINLOCK(ssp3_lock);
135
+
static const char *ssp_parent_names[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
136
+
137
+
static DEFINE_SPINLOCK(reset_lock);
138
+
139
+
static struct mmp_param_mux_clk apbc_mux_clks[] = {
140
+
{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
141
+
{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
142
+
{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2, 4, 3, 0, &uart2_lock},
143
+
{0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART3, 4, 3, 0, &uart2_lock},
144
+
{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
145
+
{0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
146
+
{0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4, 3, 0, &ssp2_lock},
147
+
{0, "ssp3_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP3, 4, 3, 0, &ssp3_lock},
148
+
};
149
+
150
+
static struct mmp_param_gate_clk apbc_gate_clks[] = {
151
+
{MMP2_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x7, 0x3, 0x0, 0, &reset_lock},
152
+
{MMP2_CLK_TWSI1, "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x7, 0x3, 0x0, 0, &reset_lock},
153
+
{MMP2_CLK_TWSI2, "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI2, 0x7, 0x3, 0x0, 0, &reset_lock},
154
+
{MMP2_CLK_TWSI3, "twsi3_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI3, 0x7, 0x3, 0x0, 0, &reset_lock},
155
+
{MMP2_CLK_TWSI4, "twsi4_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI4, 0x7, 0x3, 0x0, 0, &reset_lock},
156
+
{MMP2_CLK_TWSI5, "twsi5_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI5, 0x7, 0x3, 0x0, 0, &reset_lock},
157
+
{MMP2_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x7, 0x3, 0x0, 0, &reset_lock},
158
+
{MMP2_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
159
+
{MMP2_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x87, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
160
+
{MMP2_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x7, 0x3, 0x0, 0, &reset_lock},
161
+
{MMP2_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x7, 0x3, 0x0, 0, &reset_lock},
162
+
{MMP2_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x7, 0x3, 0x0, 0, &reset_lock},
163
+
{MMP2_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x7, 0x3, 0x0, 0, &reset_lock},
164
+
/* The gate clocks has mux parent. */
165
+
{MMP2_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x7, 0x3, 0x0, 0, &uart0_lock},
166
+
{MMP2_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x7, 0x3, 0x0, 0, &uart1_lock},
167
+
{MMP2_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBC_UART2, 0x7, 0x3, 0x0, 0, &uart2_lock},
168
+
{MMP2_CLK_UART3, "uart3_clk", "uart3_mux", CLK_SET_RATE_PARENT, APBC_UART3, 0x7, 0x3, 0x0, 0, &uart2_lock},
169
+
{MMP2_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x7, 0x3, 0x0, 0, &ssp0_lock},
170
+
{MMP2_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x7, 0x3, 0x0, 0, &ssp1_lock},
171
+
{MMP2_CLK_SSP2, "ssp2_clk", "ssp2_mux", CLK_SET_RATE_PARENT, APBC_SSP2, 0x7, 0x3, 0x0, 0, &ssp2_lock},
172
+
{MMP2_CLK_SSP3, "ssp3_clk", "ssp3_mux", CLK_SET_RATE_PARENT, APBC_SSP3, 0x7, 0x3, 0x0, 0, &ssp3_lock},
173
+
};
174
+
175
+
static void mmp2_apb_periph_clk_init(struct mmp2_clk_unit *pxa_unit)
176
+
{
177
+
struct mmp_clk_unit *unit = &pxa_unit->unit;
178
+
179
+
mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
180
+
ARRAY_SIZE(apbc_mux_clks));
181
+
182
+
mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
183
+
ARRAY_SIZE(apbc_gate_clks));
184
+
}
185
+
186
+
static DEFINE_SPINLOCK(sdh_lock);
187
+
static const char *sdh_parent_names[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
188
+
static struct mmp_clk_mix_config sdh_mix_config = {
189
+
.reg_info = DEFINE_MIX_REG_INFO(4, 10, 2, 8, 32),
190
+
};
191
+
192
+
static DEFINE_SPINLOCK(usb_lock);
193
+
194
+
static DEFINE_SPINLOCK(disp0_lock);
195
+
static DEFINE_SPINLOCK(disp1_lock);
196
+
static const char *disp_parent_names[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
197
+
198
+
static DEFINE_SPINLOCK(ccic0_lock);
199
+
static DEFINE_SPINLOCK(ccic1_lock);
200
+
static const char *ccic_parent_names[] = {"pll1_2", "pll1_16", "vctcxo"};
201
+
static struct mmp_clk_mix_config ccic0_mix_config = {
202
+
.reg_info = DEFINE_MIX_REG_INFO(4, 17, 2, 6, 32),
203
+
};
204
+
static struct mmp_clk_mix_config ccic1_mix_config = {
205
+
.reg_info = DEFINE_MIX_REG_INFO(4, 16, 2, 6, 32),
206
+
};
207
+
208
+
static struct mmp_param_mux_clk apmu_mux_clks[] = {
209
+
{MMP2_CLK_DISP0_MUX, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 2, 0, &disp0_lock},
210
+
{MMP2_CLK_DISP1_MUX, "disp1_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP1, 6, 2, 0, &disp1_lock},
211
+
};
212
+
213
+
static struct mmp_param_div_clk apmu_div_clks[] = {
214
+
{0, "disp0_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 8, 4, 0, &disp0_lock},
215
+
{0, "disp0_sphy_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 15, 5, 0, &disp0_lock},
216
+
{0, "disp1_div", "disp1_mux", CLK_SET_RATE_PARENT, APMU_DISP1, 8, 4, 0, &disp1_lock},
217
+
{0, "ccic0_sphy_div", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
218
+
{0, "ccic1_sphy_div", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 10, 5, 0, &ccic1_lock},
219
+
};
220
+
221
+
static struct mmp_param_gate_clk apmu_gate_clks[] = {
222
+
{MMP2_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
223
+
/* The gate clocks has mux parent. */
224
+
{MMP2_CLK_SDH0, "sdh0_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
225
+
{MMP2_CLK_SDH1, "sdh1_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
226
+
{MMP2_CLK_SDH1, "sdh2_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH2, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
227
+
{MMP2_CLK_SDH1, "sdh3_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH3, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
228
+
{MMP2_CLK_DISP0, "disp0_clk", "disp0_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock},
229
+
{MMP2_CLK_DISP0_SPHY, "disp0_sphy_clk", "disp0_sphy_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1024, 0x1024, 0x0, 0, &disp0_lock},
230
+
{MMP2_CLK_DISP1, "disp1_clk", "disp1_div", CLK_SET_RATE_PARENT, APMU_DISP1, 0x1b, 0x1b, 0x0, 0, &disp1_lock},
231
+
{MMP2_CLK_CCIC_ARBITER, "ccic_arbiter", "vctcxo", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1800, 0x1800, 0x0, 0, &ccic0_lock},
232
+
{MMP2_CLK_CCIC0, "ccic0_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
233
+
{MMP2_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
234
+
{MMP2_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock},
235
+
{MMP2_CLK_CCIC1, "ccic1_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x1b, 0x1b, 0x0, 0, &ccic1_lock},
236
+
{MMP2_CLK_CCIC1_PHY, "ccic1_phy_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x24, 0x24, 0x0, 0, &ccic1_lock},
237
+
{MMP2_CLK_CCIC1_SPHY, "ccic1_sphy_clk", "ccic1_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x300, 0x300, 0x0, 0, &ccic1_lock},
238
+
};
239
+
240
+
static void mmp2_axi_periph_clk_init(struct mmp2_clk_unit *pxa_unit)
241
+
{
242
+
struct clk *clk;
243
+
struct mmp_clk_unit *unit = &pxa_unit->unit;
244
+
245
+
sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_SDH0;
246
+
clk = mmp_clk_register_mix(NULL, "sdh_mix_clk", sdh_parent_names,
247
+
ARRAY_SIZE(sdh_parent_names),
248
+
CLK_SET_RATE_PARENT,
249
+
&sdh_mix_config, &sdh_lock);
250
+
251
+
ccic0_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC0;
252
+
clk = mmp_clk_register_mix(NULL, "ccic0_mix_clk", ccic_parent_names,
253
+
ARRAY_SIZE(ccic_parent_names),
254
+
CLK_SET_RATE_PARENT,
255
+
&ccic0_mix_config, &ccic0_lock);
256
+
mmp_clk_add(unit, MMP2_CLK_CCIC0_MIX, clk);
257
+
258
+
ccic1_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC1;
259
+
clk = mmp_clk_register_mix(NULL, "ccic1_mix_clk", ccic_parent_names,
260
+
ARRAY_SIZE(ccic_parent_names),
261
+
CLK_SET_RATE_PARENT,
262
+
&ccic1_mix_config, &ccic1_lock);
263
+
mmp_clk_add(unit, MMP2_CLK_CCIC1_MIX, clk);
264
+
265
+
mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base,
266
+
ARRAY_SIZE(apmu_mux_clks));
267
+
268
+
mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base,
269
+
ARRAY_SIZE(apmu_div_clks));
270
+
271
+
mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
272
+
ARRAY_SIZE(apmu_gate_clks));
273
+
}
274
+
275
+
static void mmp2_clk_reset_init(struct device_node *np,
276
+
struct mmp2_clk_unit *pxa_unit)
277
+
{
278
+
struct mmp_clk_reset_cell *cells;
279
+
int i, nr_resets;
280
+
281
+
nr_resets = ARRAY_SIZE(apbc_gate_clks);
282
+
cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL);
283
+
if (!cells)
284
+
return;
285
+
286
+
for (i = 0; i < nr_resets; i++) {
287
+
cells[i].clk_id = apbc_gate_clks[i].id;
288
+
cells[i].reg = pxa_unit->apbc_base + apbc_gate_clks[i].offset;
289
+
cells[i].flags = 0;
290
+
cells[i].lock = apbc_gate_clks[i].lock;
291
+
cells[i].bits = 0x4;
292
+
}
293
+
294
+
mmp_clk_reset_register(np, cells, nr_resets);
295
+
}
296
+
297
+
static void __init mmp2_clk_init(struct device_node *np)
298
+
{
299
+
struct mmp2_clk_unit *pxa_unit;
300
+
301
+
pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
302
+
if (!pxa_unit)
303
+
return;
304
+
305
+
pxa_unit->mpmu_base = of_iomap(np, 0);
306
+
if (!pxa_unit->mpmu_base) {
307
+
pr_err("failed to map mpmu registers\n");
308
+
return;
309
+
}
310
+
311
+
pxa_unit->apmu_base = of_iomap(np, 1);
312
+
if (!pxa_unit->mpmu_base) {
313
+
pr_err("failed to map apmu registers\n");
314
+
return;
315
+
}
316
+
317
+
pxa_unit->apbc_base = of_iomap(np, 2);
318
+
if (!pxa_unit->apbc_base) {
319
+
pr_err("failed to map apbc registers\n");
320
+
return;
321
+
}
322
+
323
+
mmp_clk_init(np, &pxa_unit->unit, MMP2_NR_CLKS);
324
+
325
+
mmp2_pll_init(pxa_unit);
326
+
327
+
mmp2_apb_periph_clk_init(pxa_unit);
328
+
329
+
mmp2_axi_periph_clk_init(pxa_unit);
330
+
331
+
mmp2_clk_reset_init(np, pxa_unit);
332
+
}
333
+
334
+
CLK_OF_DECLARE(mmp2_clk, "marvell,mmp2-clock", mmp2_clk_init);
+279
drivers/clk/mmp/clk-of-pxa168.c
+279
drivers/clk/mmp/clk-of-pxa168.c
···
1
+
/*
2
+
* pxa168 clock framework source file
3
+
*
4
+
* Copyright (C) 2012 Marvell
5
+
* Chao Xie <xiechao.mail@gmail.com>
6
+
*
7
+
* This file is licensed under the terms of the GNU General Public
8
+
* License version 2. This program is licensed "as is" without any
9
+
* warranty of any kind, whether express or implied.
10
+
*/
11
+
12
+
#include <linux/module.h>
13
+
#include <linux/kernel.h>
14
+
#include <linux/spinlock.h>
15
+
#include <linux/io.h>
16
+
#include <linux/delay.h>
17
+
#include <linux/err.h>
18
+
#include <linux/of_address.h>
19
+
20
+
#include <dt-bindings/clock/marvell,pxa168.h>
21
+
22
+
#include "clk.h"
23
+
#include "reset.h"
24
+
25
+
#define APBC_RTC 0x28
26
+
#define APBC_TWSI0 0x2c
27
+
#define APBC_KPC 0x30
28
+
#define APBC_UART0 0x0
29
+
#define APBC_UART1 0x4
30
+
#define APBC_GPIO 0x8
31
+
#define APBC_PWM0 0xc
32
+
#define APBC_PWM1 0x10
33
+
#define APBC_PWM2 0x14
34
+
#define APBC_PWM3 0x18
35
+
#define APBC_SSP0 0x81c
36
+
#define APBC_SSP1 0x820
37
+
#define APBC_SSP2 0x84c
38
+
#define APBC_SSP3 0x858
39
+
#define APBC_SSP4 0x85c
40
+
#define APBC_TWSI1 0x6c
41
+
#define APBC_UART2 0x70
42
+
#define APMU_SDH0 0x54
43
+
#define APMU_SDH1 0x58
44
+
#define APMU_USB 0x5c
45
+
#define APMU_DISP0 0x4c
46
+
#define APMU_CCIC0 0x50
47
+
#define APMU_DFC 0x60
48
+
#define MPMU_UART_PLL 0x14
49
+
50
+
struct pxa168_clk_unit {
51
+
struct mmp_clk_unit unit;
52
+
void __iomem *mpmu_base;
53
+
void __iomem *apmu_base;
54
+
void __iomem *apbc_base;
55
+
};
56
+
57
+
static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
58
+
{PXA168_CLK_CLK32, "clk32", NULL, CLK_IS_ROOT, 32768},
59
+
{PXA168_CLK_VCTCXO, "vctcxo", NULL, CLK_IS_ROOT, 26000000},
60
+
{PXA168_CLK_PLL1, "pll1", NULL, CLK_IS_ROOT, 624000000},
61
+
};
62
+
63
+
static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
64
+
{PXA168_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
65
+
{PXA168_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
66
+
{PXA168_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0},
67
+
{PXA168_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0},
68
+
{PXA168_CLK_PLL1_6, "pll1_6", "pll1_2", 1, 3, 0},
69
+
{PXA168_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0},
70
+
{PXA168_CLK_PLL1_24, "pll1_24", "pll1_12", 1, 2, 0},
71
+
{PXA168_CLK_PLL1_48, "pll1_48", "pll1_24", 1, 2, 0},
72
+
{PXA168_CLK_PLL1_96, "pll1_96", "pll1_48", 1, 2, 0},
73
+
{PXA168_CLK_PLL1_13, "pll1_13", "pll1", 1, 13, 0},
74
+
{PXA168_CLK_PLL1_13_1_5, "pll1_13_1_5", "pll1_13", 2, 3, 0},
75
+
{PXA168_CLK_PLL1_2_1_5, "pll1_2_1_5", "pll1_2", 2, 3, 0},
76
+
{PXA168_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0},
77
+
};
78
+
79
+
static struct mmp_clk_factor_masks uart_factor_masks = {
80
+
.factor = 2,
81
+
.num_mask = 0x1fff,
82
+
.den_mask = 0x1fff,
83
+
.num_shift = 16,
84
+
.den_shift = 0,
85
+
};
86
+
87
+
static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
88
+
{.num = 8125, .den = 1536}, /*14.745MHZ */
89
+
};
90
+
91
+
static void pxa168_pll_init(struct pxa168_clk_unit *pxa_unit)
92
+
{
93
+
struct clk *clk;
94
+
struct mmp_clk_unit *unit = &pxa_unit->unit;
95
+
96
+
mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
97
+
ARRAY_SIZE(fixed_rate_clks));
98
+
99
+
mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
100
+
ARRAY_SIZE(fixed_factor_clks));
101
+
102
+
clk = mmp_clk_register_factor("uart_pll", "pll1_4",
103
+
CLK_SET_RATE_PARENT,
104
+
pxa_unit->mpmu_base + MPMU_UART_PLL,
105
+
&uart_factor_masks, uart_factor_tbl,
106
+
ARRAY_SIZE(uart_factor_tbl), NULL);
107
+
mmp_clk_add(unit, PXA168_CLK_UART_PLL, clk);
108
+
}
109
+
110
+
static DEFINE_SPINLOCK(uart0_lock);
111
+
static DEFINE_SPINLOCK(uart1_lock);
112
+
static DEFINE_SPINLOCK(uart2_lock);
113
+
static const char *uart_parent_names[] = {"pll1_3_16", "uart_pll"};
114
+
115
+
static DEFINE_SPINLOCK(ssp0_lock);
116
+
static DEFINE_SPINLOCK(ssp1_lock);
117
+
static DEFINE_SPINLOCK(ssp2_lock);
118
+
static DEFINE_SPINLOCK(ssp3_lock);
119
+
static DEFINE_SPINLOCK(ssp4_lock);
120
+
static const char *ssp_parent_names[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
121
+
122
+
static DEFINE_SPINLOCK(reset_lock);
123
+
124
+
static struct mmp_param_mux_clk apbc_mux_clks[] = {
125
+
{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
126
+
{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
127
+
{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2, 4, 3, 0, &uart2_lock},
128
+
{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
129
+
{0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
130
+
{0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4, 3, 0, &ssp2_lock},
131
+
{0, "ssp3_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP3, 4, 3, 0, &ssp3_lock},
132
+
{0, "ssp4_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP4, 4, 3, 0, &ssp4_lock},
133
+
};
134
+
135
+
static struct mmp_param_gate_clk apbc_gate_clks[] = {
136
+
{PXA168_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, &reset_lock},
137
+
{PXA168_CLK_TWSI1, "twsi1_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x3, 0x3, 0x0, 0, &reset_lock},
138
+
{PXA168_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_lock},
139
+
{PXA168_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x3, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
140
+
{PXA168_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x83, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
141
+
{PXA168_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_lock},
142
+
{PXA168_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &reset_lock},
143
+
{PXA168_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x3, 0x3, 0x0, 0, &reset_lock},
144
+
{PXA168_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_lock},
145
+
/* The gate clocks has mux parent. */
146
+
{PXA168_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x3, 0x3, 0x0, 0, &uart0_lock},
147
+
{PXA168_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x3, 0x3, 0x0, 0, &uart1_lock},
148
+
{PXA168_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBC_UART2, 0x3, 0x3, 0x0, 0, &uart2_lock},
149
+
{PXA168_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x3, 0x3, 0x0, 0, &ssp0_lock},
150
+
{PXA168_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x3, 0x3, 0x0, 0, &ssp1_lock},
151
+
{PXA168_CLK_SSP2, "ssp2_clk", "ssp2_mux", CLK_SET_RATE_PARENT, APBC_SSP2, 0x3, 0x3, 0x0, 0, &ssp2_lock},
152
+
{PXA168_CLK_SSP3, "ssp3_clk", "ssp3_mux", CLK_SET_RATE_PARENT, APBC_SSP3, 0x3, 0x3, 0x0, 0, &ssp3_lock},
153
+
{PXA168_CLK_SSP4, "ssp4_clk", "ssp4_mux", CLK_SET_RATE_PARENT, APBC_SSP4, 0x3, 0x3, 0x0, 0, &ssp4_lock},
154
+
};
155
+
156
+
static void pxa168_apb_periph_clk_init(struct pxa168_clk_unit *pxa_unit)
157
+
{
158
+
struct mmp_clk_unit *unit = &pxa_unit->unit;
159
+
160
+
mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
161
+
ARRAY_SIZE(apbc_mux_clks));
162
+
163
+
mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
164
+
ARRAY_SIZE(apbc_gate_clks));
165
+
166
+
}
167
+
168
+
static DEFINE_SPINLOCK(sdh0_lock);
169
+
static DEFINE_SPINLOCK(sdh1_lock);
170
+
static const char *sdh_parent_names[] = {"pll1_12", "pll1_13"};
171
+
172
+
static DEFINE_SPINLOCK(usb_lock);
173
+
174
+
static DEFINE_SPINLOCK(disp0_lock);
175
+
static const char *disp_parent_names[] = {"pll1_2", "pll1_12"};
176
+
177
+
static DEFINE_SPINLOCK(ccic0_lock);
178
+
static const char *ccic_parent_names[] = {"pll1_2", "pll1_12"};
179
+
static const char *ccic_phy_parent_names[] = {"pll1_6", "pll1_12"};
180
+
181
+
static struct mmp_param_mux_clk apmu_mux_clks[] = {
182
+
{0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6, 1, 0, &sdh0_lock},
183
+
{0, "sdh1_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH1, 6, 1, 0, &sdh1_lock},
184
+
{0, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 1, 0, &disp0_lock},
185
+
{0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 6, 1, 0, &ccic0_lock},
186
+
{0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0_lock},
187
+
};
188
+
189
+
static struct mmp_param_div_clk apmu_div_clks[] = {
190
+
{0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
191
+
};
192
+
193
+
static struct mmp_param_gate_clk apmu_gate_clks[] = {
194
+
{PXA168_CLK_DFC, "dfc_clk", "pll1_4", CLK_SET_RATE_PARENT, APMU_DFC, 0x19b, 0x19b, 0x0, 0, NULL},
195
+
{PXA168_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
196
+
{PXA168_CLK_SPH, "sph_clk", "usb_pll", 0, APMU_USB, 0x12, 0x12, 0x0, 0, &usb_lock},
197
+
/* The gate clocks has mux parent. */
198
+
{PXA168_CLK_SDH0, "sdh0_clk", "sdh0_mux", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh0_lock},
199
+
{PXA168_CLK_SDH1, "sdh1_clk", "sdh1_mux", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh1_lock},
200
+
{PXA168_CLK_DISP0, "disp0_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock},
201
+
{PXA168_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
202
+
{PXA168_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
203
+
{PXA168_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock},
204
+
};
205
+
206
+
static void pxa168_axi_periph_clk_init(struct pxa168_clk_unit *pxa_unit)
207
+
{
208
+
struct mmp_clk_unit *unit = &pxa_unit->unit;
209
+
210
+
mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base,
211
+
ARRAY_SIZE(apmu_mux_clks));
212
+
213
+
mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base,
214
+
ARRAY_SIZE(apmu_div_clks));
215
+
216
+
mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
217
+
ARRAY_SIZE(apmu_gate_clks));
218
+
}
219
+
220
+
static void pxa168_clk_reset_init(struct device_node *np,
221
+
struct pxa168_clk_unit *pxa_unit)
222
+
{
223
+
struct mmp_clk_reset_cell *cells;
224
+
int i, nr_resets;
225
+
226
+
nr_resets = ARRAY_SIZE(apbc_gate_clks);
227
+
cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL);
228
+
if (!cells)
229
+
return;
230
+
231
+
for (i = 0; i < nr_resets; i++) {
232
+
cells[i].clk_id = apbc_gate_clks[i].id;
233
+
cells[i].reg = pxa_unit->apbc_base + apbc_gate_clks[i].offset;
234
+
cells[i].flags = 0;
235
+
cells[i].lock = apbc_gate_clks[i].lock;
236
+
cells[i].bits = 0x4;
237
+
}
238
+
239
+
mmp_clk_reset_register(np, cells, nr_resets);
240
+
}
241
+
242
+
static void __init pxa168_clk_init(struct device_node *np)
243
+
{
244
+
struct pxa168_clk_unit *pxa_unit;
245
+
246
+
pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
247
+
if (!pxa_unit)
248
+
return;
249
+
250
+
pxa_unit->mpmu_base = of_iomap(np, 0);
251
+
if (!pxa_unit->mpmu_base) {
252
+
pr_err("failed to map mpmu registers\n");
253
+
return;
254
+
}
255
+
256
+
pxa_unit->apmu_base = of_iomap(np, 1);
257
+
if (!pxa_unit->mpmu_base) {
258
+
pr_err("failed to map apmu registers\n");
259
+
return;
260
+
}
261
+
262
+
pxa_unit->apbc_base = of_iomap(np, 2);
263
+
if (!pxa_unit->apbc_base) {
264
+
pr_err("failed to map apbc registers\n");
265
+
return;
266
+
}
267
+
268
+
mmp_clk_init(np, &pxa_unit->unit, PXA168_NR_CLKS);
269
+
270
+
pxa168_pll_init(pxa_unit);
271
+
272
+
pxa168_apb_periph_clk_init(pxa_unit);
273
+
274
+
pxa168_axi_periph_clk_init(pxa_unit);
275
+
276
+
pxa168_clk_reset_init(np, pxa_unit);
277
+
}
278
+
279
+
CLK_OF_DECLARE(pxa168_clk, "marvell,pxa168-clock", pxa168_clk_init);
+301
drivers/clk/mmp/clk-of-pxa910.c
+301
drivers/clk/mmp/clk-of-pxa910.c
···
1
+
/*
2
+
* pxa910 clock framework source file
3
+
*
4
+
* Copyright (C) 2012 Marvell
5
+
* Chao Xie <xiechao.mail@gmail.com>
6
+
*
7
+
* This file is licensed under the terms of the GNU General Public
8
+
* License version 2. This program is licensed "as is" without any
9
+
* warranty of any kind, whether express or implied.
10
+
*/
11
+
12
+
#include <linux/module.h>
13
+
#include <linux/kernel.h>
14
+
#include <linux/spinlock.h>
15
+
#include <linux/io.h>
16
+
#include <linux/delay.h>
17
+
#include <linux/err.h>
18
+
#include <linux/of_address.h>
19
+
20
+
#include <dt-bindings/clock/marvell,pxa910.h>
21
+
22
+
#include "clk.h"
23
+
#include "reset.h"
24
+
25
+
#define APBC_RTC 0x28
26
+
#define APBC_TWSI0 0x2c
27
+
#define APBC_KPC 0x18
28
+
#define APBC_UART0 0x0
29
+
#define APBC_UART1 0x4
30
+
#define APBC_GPIO 0x8
31
+
#define APBC_PWM0 0xc
32
+
#define APBC_PWM1 0x10
33
+
#define APBC_PWM2 0x14
34
+
#define APBC_PWM3 0x18
35
+
#define APBC_SSP0 0x1c
36
+
#define APBC_SSP1 0x20
37
+
#define APBC_SSP2 0x4c
38
+
#define APBCP_TWSI1 0x28
39
+
#define APBCP_UART2 0x1c
40
+
#define APMU_SDH0 0x54
41
+
#define APMU_SDH1 0x58
42
+
#define APMU_USB 0x5c
43
+
#define APMU_DISP0 0x4c
44
+
#define APMU_CCIC0 0x50
45
+
#define APMU_DFC 0x60
46
+
#define MPMU_UART_PLL 0x14
47
+
48
+
struct pxa910_clk_unit {
49
+
struct mmp_clk_unit unit;
50
+
void __iomem *mpmu_base;
51
+
void __iomem *apmu_base;
52
+
void __iomem *apbc_base;
53
+
void __iomem *apbcp_base;
54
+
};
55
+
56
+
static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
57
+
{PXA910_CLK_CLK32, "clk32", NULL, CLK_IS_ROOT, 32768},
58
+
{PXA910_CLK_VCTCXO, "vctcxo", NULL, CLK_IS_ROOT, 26000000},
59
+
{PXA910_CLK_PLL1, "pll1", NULL, CLK_IS_ROOT, 624000000},
60
+
};
61
+
62
+
static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
63
+
{PXA910_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
64
+
{PXA910_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
65
+
{PXA910_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0},
66
+
{PXA910_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0},
67
+
{PXA910_CLK_PLL1_6, "pll1_6", "pll1_2", 1, 3, 0},
68
+
{PXA910_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0},
69
+
{PXA910_CLK_PLL1_24, "pll1_24", "pll1_12", 1, 2, 0},
70
+
{PXA910_CLK_PLL1_48, "pll1_48", "pll1_24", 1, 2, 0},
71
+
{PXA910_CLK_PLL1_96, "pll1_96", "pll1_48", 1, 2, 0},
72
+
{PXA910_CLK_PLL1_13, "pll1_13", "pll1", 1, 13, 0},
73
+
{PXA910_CLK_PLL1_13_1_5, "pll1_13_1_5", "pll1_13", 2, 3, 0},
74
+
{PXA910_CLK_PLL1_2_1_5, "pll1_2_1_5", "pll1_2", 2, 3, 0},
75
+
{PXA910_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0},
76
+
};
77
+
78
+
static struct mmp_clk_factor_masks uart_factor_masks = {
79
+
.factor = 2,
80
+
.num_mask = 0x1fff,
81
+
.den_mask = 0x1fff,
82
+
.num_shift = 16,
83
+
.den_shift = 0,
84
+
};
85
+
86
+
static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
87
+
{.num = 8125, .den = 1536}, /*14.745MHZ */
88
+
};
89
+
90
+
static void pxa910_pll_init(struct pxa910_clk_unit *pxa_unit)
91
+
{
92
+
struct clk *clk;
93
+
struct mmp_clk_unit *unit = &pxa_unit->unit;
94
+
95
+
mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
96
+
ARRAY_SIZE(fixed_rate_clks));
97
+
98
+
mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
99
+
ARRAY_SIZE(fixed_factor_clks));
100
+
101
+
clk = mmp_clk_register_factor("uart_pll", "pll1_4",
102
+
CLK_SET_RATE_PARENT,
103
+
pxa_unit->mpmu_base + MPMU_UART_PLL,
104
+
&uart_factor_masks, uart_factor_tbl,
105
+
ARRAY_SIZE(uart_factor_tbl), NULL);
106
+
mmp_clk_add(unit, PXA910_CLK_UART_PLL, clk);
107
+
}
108
+
109
+
static DEFINE_SPINLOCK(uart0_lock);
110
+
static DEFINE_SPINLOCK(uart1_lock);
111
+
static DEFINE_SPINLOCK(uart2_lock);
112
+
static const char *uart_parent_names[] = {"pll1_3_16", "uart_pll"};
113
+
114
+
static DEFINE_SPINLOCK(ssp0_lock);
115
+
static DEFINE_SPINLOCK(ssp1_lock);
116
+
static const char *ssp_parent_names[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
117
+
118
+
static DEFINE_SPINLOCK(reset_lock);
119
+
120
+
static struct mmp_param_mux_clk apbc_mux_clks[] = {
121
+
{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
122
+
{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
123
+
{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
124
+
{0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
125
+
};
126
+
127
+
static struct mmp_param_mux_clk apbcp_mux_clks[] = {
128
+
{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBCP_UART2, 4, 3, 0, &uart2_lock},
129
+
};
130
+
131
+
static struct mmp_param_gate_clk apbc_gate_clks[] = {
132
+
{PXA910_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, &reset_lock},
133
+
{PXA910_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_lock},
134
+
{PXA910_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x3, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
135
+
{PXA910_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x83, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
136
+
{PXA910_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_lock},
137
+
{PXA910_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &reset_lock},
138
+
{PXA910_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x3, 0x3, 0x0, 0, &reset_lock},
139
+
{PXA910_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_lock},
140
+
/* The gate clocks has mux parent. */
141
+
{PXA910_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x3, 0x3, 0x0, 0, &uart0_lock},
142
+
{PXA910_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x3, 0x3, 0x0, 0, &uart1_lock},
143
+
{PXA910_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x3, 0x3, 0x0, 0, &ssp0_lock},
144
+
{PXA910_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x3, 0x3, 0x0, 0, &ssp1_lock},
145
+
};
146
+
147
+
static struct mmp_param_gate_clk apbcp_gate_clks[] = {
148
+
{PXA910_CLK_TWSI1, "twsi1_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBCP_TWSI1, 0x3, 0x3, 0x0, 0, &reset_lock},
149
+
/* The gate clocks has mux parent. */
150
+
{PXA910_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBCP_UART2, 0x3, 0x3, 0x0, 0, &uart2_lock},
151
+
};
152
+
153
+
static void pxa910_apb_periph_clk_init(struct pxa910_clk_unit *pxa_unit)
154
+
{
155
+
struct mmp_clk_unit *unit = &pxa_unit->unit;
156
+
157
+
mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
158
+
ARRAY_SIZE(apbc_mux_clks));
159
+
160
+
mmp_register_mux_clks(unit, apbcp_mux_clks, pxa_unit->apbcp_base,
161
+
ARRAY_SIZE(apbcp_mux_clks));
162
+
163
+
mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
164
+
ARRAY_SIZE(apbc_gate_clks));
165
+
166
+
mmp_register_gate_clks(unit, apbcp_gate_clks, pxa_unit->apbcp_base,
167
+
ARRAY_SIZE(apbcp_gate_clks));
168
+
}
169
+
170
+
static DEFINE_SPINLOCK(sdh0_lock);
171
+
static DEFINE_SPINLOCK(sdh1_lock);
172
+
static const char *sdh_parent_names[] = {"pll1_12", "pll1_13"};
173
+
174
+
static DEFINE_SPINLOCK(usb_lock);
175
+
176
+
static DEFINE_SPINLOCK(disp0_lock);
177
+
static const char *disp_parent_names[] = {"pll1_2", "pll1_12"};
178
+
179
+
static DEFINE_SPINLOCK(ccic0_lock);
180
+
static const char *ccic_parent_names[] = {"pll1_2", "pll1_12"};
181
+
static const char *ccic_phy_parent_names[] = {"pll1_6", "pll1_12"};
182
+
183
+
static struct mmp_param_mux_clk apmu_mux_clks[] = {
184
+
{0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6, 1, 0, &sdh0_lock},
185
+
{0, "sdh1_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH1, 6, 1, 0, &sdh1_lock},
186
+
{0, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 1, 0, &disp0_lock},
187
+
{0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 6, 1, 0, &ccic0_lock},
188
+
{0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0_lock},
189
+
};
190
+
191
+
static struct mmp_param_div_clk apmu_div_clks[] = {
192
+
{0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
193
+
};
194
+
195
+
static struct mmp_param_gate_clk apmu_gate_clks[] = {
196
+
{PXA910_CLK_DFC, "dfc_clk", "pll1_4", CLK_SET_RATE_PARENT, APMU_DFC, 0x19b, 0x19b, 0x0, 0, NULL},
197
+
{PXA910_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
198
+
{PXA910_CLK_SPH, "sph_clk", "usb_pll", 0, APMU_USB, 0x12, 0x12, 0x0, 0, &usb_lock},
199
+
/* The gate clocks has mux parent. */
200
+
{PXA910_CLK_SDH0, "sdh0_clk", "sdh0_mux", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh0_lock},
201
+
{PXA910_CLK_SDH1, "sdh1_clk", "sdh1_mux", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh1_lock},
202
+
{PXA910_CLK_DISP0, "disp0_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock},
203
+
{PXA910_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
204
+
{PXA910_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
205
+
{PXA910_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock},
206
+
};
207
+
208
+
static void pxa910_axi_periph_clk_init(struct pxa910_clk_unit *pxa_unit)
209
+
{
210
+
struct mmp_clk_unit *unit = &pxa_unit->unit;
211
+
212
+
mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base,
213
+
ARRAY_SIZE(apmu_mux_clks));
214
+
215
+
mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base,
216
+
ARRAY_SIZE(apmu_div_clks));
217
+
218
+
mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
219
+
ARRAY_SIZE(apmu_gate_clks));
220
+
}
221
+
222
+
static void pxa910_clk_reset_init(struct device_node *np,
223
+
struct pxa910_clk_unit *pxa_unit)
224
+
{
225
+
struct mmp_clk_reset_cell *cells;
226
+
int i, base, nr_resets_apbc, nr_resets_apbcp, nr_resets;
227
+
228
+
nr_resets_apbc = ARRAY_SIZE(apbc_gate_clks);
229
+
nr_resets_apbcp = ARRAY_SIZE(apbcp_gate_clks);
230
+
nr_resets = nr_resets_apbc + nr_resets_apbcp;
231
+
cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL);
232
+
if (!cells)
233
+
return;
234
+
235
+
base = 0;
236
+
for (i = 0; i < nr_resets_apbc; i++) {
237
+
cells[base + i].clk_id = apbc_gate_clks[i].id;
238
+
cells[base + i].reg =
239
+
pxa_unit->apbc_base + apbc_gate_clks[i].offset;
240
+
cells[base + i].flags = 0;
241
+
cells[base + i].lock = apbc_gate_clks[i].lock;
242
+
cells[base + i].bits = 0x4;
243
+
}
244
+
245
+
base = nr_resets_apbc;
246
+
for (i = 0; i < nr_resets_apbcp; i++) {
247
+
cells[base + i].clk_id = apbcp_gate_clks[i].id;
248
+
cells[base + i].reg =
249
+
pxa_unit->apbc_base + apbc_gate_clks[i].offset;
250
+
cells[base + i].flags = 0;
251
+
cells[base + i].lock = apbc_gate_clks[i].lock;
252
+
cells[base + i].bits = 0x4;
253
+
}
254
+
255
+
mmp_clk_reset_register(np, cells, nr_resets);
256
+
}
257
+
258
+
static void __init pxa910_clk_init(struct device_node *np)
259
+
{
260
+
struct pxa910_clk_unit *pxa_unit;
261
+
262
+
pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
263
+
if (!pxa_unit)
264
+
return;
265
+
266
+
pxa_unit->mpmu_base = of_iomap(np, 0);
267
+
if (!pxa_unit->mpmu_base) {
268
+
pr_err("failed to map mpmu registers\n");
269
+
return;
270
+
}
271
+
272
+
pxa_unit->apmu_base = of_iomap(np, 1);
273
+
if (!pxa_unit->mpmu_base) {
274
+
pr_err("failed to map apmu registers\n");
275
+
return;
276
+
}
277
+
278
+
pxa_unit->apbc_base = of_iomap(np, 2);
279
+
if (!pxa_unit->apbc_base) {
280
+
pr_err("failed to map apbc registers\n");
281
+
return;
282
+
}
283
+
284
+
pxa_unit->apbcp_base = of_iomap(np, 3);
285
+
if (!pxa_unit->mpmu_base) {
286
+
pr_err("failed to map apbcp registers\n");
287
+
return;
288
+
}
289
+
290
+
mmp_clk_init(np, &pxa_unit->unit, PXA910_NR_CLKS);
291
+
292
+
pxa910_pll_init(pxa_unit);
293
+
294
+
pxa910_apb_periph_clk_init(pxa_unit);
295
+
296
+
pxa910_axi_periph_clk_init(pxa_unit);
297
+
298
+
pxa910_clk_reset_init(np, pxa_unit);
299
+
}
300
+
301
+
CLK_OF_DECLARE(pxa910_clk, "marvell,pxa910-clock", pxa910_clk_init);
+3
-3
drivers/clk/mmp/clk-pxa168.c
+3
-3
drivers/clk/mmp/clk-pxa168.c
···
47
47
48
48
static DEFINE_SPINLOCK(clk_lock);
49
49
50
-
static struct clk_factor_masks uart_factor_masks = {
50
+
static struct mmp_clk_factor_masks uart_factor_masks = {
51
51
.factor = 2,
52
52
.num_mask = 0x1fff,
53
53
.den_mask = 0x1fff,
···
55
55
.den_shift = 0,
56
56
};
57
57
58
-
static struct clk_factor_tbl uart_factor_tbl[] = {
58
+
static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
59
59
{.num = 8125, .den = 1536}, /*14.745MHZ */
60
60
};
61
61
···
158
158
uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
159
159
mpmu_base + MPMU_UART_PLL,
160
160
&uart_factor_masks, uart_factor_tbl,
161
-
ARRAY_SIZE(uart_factor_tbl));
161
+
ARRAY_SIZE(uart_factor_tbl), &clk_lock);
162
162
clk_set_rate(uart_pll, 14745600);
163
163
clk_register_clkdev(uart_pll, "uart_pll", NULL);
164
164
+3
-3
drivers/clk/mmp/clk-pxa910.c
+3
-3
drivers/clk/mmp/clk-pxa910.c
···
45
45
46
46
static DEFINE_SPINLOCK(clk_lock);
47
47
48
-
static struct clk_factor_masks uart_factor_masks = {
48
+
static struct mmp_clk_factor_masks uart_factor_masks = {
49
49
.factor = 2,
50
50
.num_mask = 0x1fff,
51
51
.den_mask = 0x1fff,
···
53
53
.den_shift = 0,
54
54
};
55
55
56
-
static struct clk_factor_tbl uart_factor_tbl[] = {
56
+
static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
57
57
{.num = 8125, .den = 1536}, /*14.745MHZ */
58
58
};
59
59
···
163
163
uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
164
164
mpmu_base + MPMU_UART_PLL,
165
165
&uart_factor_masks, uart_factor_tbl,
166
-
ARRAY_SIZE(uart_factor_tbl));
166
+
ARRAY_SIZE(uart_factor_tbl), &clk_lock);
167
167
clk_set_rate(uart_pll, 14745600);
168
168
clk_register_clkdev(uart_pll, "uart_pll", NULL);
169
169
+192
drivers/clk/mmp/clk.c
+192
drivers/clk/mmp/clk.c
···
1
+
#include <linux/io.h>
2
+
#include <linux/clk.h>
3
+
#include <linux/clk-provider.h>
4
+
#include <linux/clkdev.h>
5
+
#include <linux/of.h>
6
+
#include <linux/of_address.h>
7
+
8
+
#include "clk.h"
9
+
10
+
void mmp_clk_init(struct device_node *np, struct mmp_clk_unit *unit,
11
+
int nr_clks)
12
+
{
13
+
static struct clk **clk_table;
14
+
15
+
clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
16
+
if (!clk_table)
17
+
return;
18
+
19
+
unit->clk_table = clk_table;
20
+
unit->nr_clks = nr_clks;
21
+
unit->clk_data.clks = clk_table;
22
+
unit->clk_data.clk_num = nr_clks;
23
+
of_clk_add_provider(np, of_clk_src_onecell_get, &unit->clk_data);
24
+
}
25
+
26
+
void mmp_register_fixed_rate_clks(struct mmp_clk_unit *unit,
27
+
struct mmp_param_fixed_rate_clk *clks,
28
+
int size)
29
+
{
30
+
int i;
31
+
struct clk *clk;
32
+
33
+
for (i = 0; i < size; i++) {
34
+
clk = clk_register_fixed_rate(NULL, clks[i].name,
35
+
clks[i].parent_name,
36
+
clks[i].flags,
37
+
clks[i].fixed_rate);
38
+
if (IS_ERR(clk)) {
39
+
pr_err("%s: failed to register clock %s\n",
40
+
__func__, clks[i].name);
41
+
continue;
42
+
}
43
+
if (clks[i].id)
44
+
unit->clk_table[clks[i].id] = clk;
45
+
}
46
+
}
47
+
48
+
void mmp_register_fixed_factor_clks(struct mmp_clk_unit *unit,
49
+
struct mmp_param_fixed_factor_clk *clks,
50
+
int size)
51
+
{
52
+
struct clk *clk;
53
+
int i;
54
+
55
+
for (i = 0; i < size; i++) {
56
+
clk = clk_register_fixed_factor(NULL, clks[i].name,
57
+
clks[i].parent_name,
58
+
clks[i].flags, clks[i].mult,
59
+
clks[i].div);
60
+
if (IS_ERR(clk)) {
61
+
pr_err("%s: failed to register clock %s\n",
62
+
__func__, clks[i].name);
63
+
continue;
64
+
}
65
+
if (clks[i].id)
66
+
unit->clk_table[clks[i].id] = clk;
67
+
}
68
+
}
69
+
70
+
void mmp_register_general_gate_clks(struct mmp_clk_unit *unit,
71
+
struct mmp_param_general_gate_clk *clks,
72
+
void __iomem *base, int size)
73
+
{
74
+
struct clk *clk;
75
+
int i;
76
+
77
+
for (i = 0; i < size; i++) {
78
+
clk = clk_register_gate(NULL, clks[i].name,
79
+
clks[i].parent_name,
80
+
clks[i].flags,
81
+
base + clks[i].offset,
82
+
clks[i].bit_idx,
83
+
clks[i].gate_flags,
84
+
clks[i].lock);
85
+
86
+
if (IS_ERR(clk)) {
87
+
pr_err("%s: failed to register clock %s\n",
88
+
__func__, clks[i].name);
89
+
continue;
90
+
}
91
+
if (clks[i].id)
92
+
unit->clk_table[clks[i].id] = clk;
93
+
}
94
+
}
95
+
96
+
void mmp_register_gate_clks(struct mmp_clk_unit *unit,
97
+
struct mmp_param_gate_clk *clks,
98
+
void __iomem *base, int size)
99
+
{
100
+
struct clk *clk;
101
+
int i;
102
+
103
+
for (i = 0; i < size; i++) {
104
+
clk = mmp_clk_register_gate(NULL, clks[i].name,
105
+
clks[i].parent_name,
106
+
clks[i].flags,
107
+
base + clks[i].offset,
108
+
clks[i].mask,
109
+
clks[i].val_enable,
110
+
clks[i].val_disable,
111
+
clks[i].gate_flags,
112
+
clks[i].lock);
113
+
114
+
if (IS_ERR(clk)) {
115
+
pr_err("%s: failed to register clock %s\n",
116
+
__func__, clks[i].name);
117
+
continue;
118
+
}
119
+
if (clks[i].id)
120
+
unit->clk_table[clks[i].id] = clk;
121
+
}
122
+
}
123
+
124
+
void mmp_register_mux_clks(struct mmp_clk_unit *unit,
125
+
struct mmp_param_mux_clk *clks,
126
+
void __iomem *base, int size)
127
+
{
128
+
struct clk *clk;
129
+
int i;
130
+
131
+
for (i = 0; i < size; i++) {
132
+
clk = clk_register_mux(NULL, clks[i].name,
133
+
clks[i].parent_name,
134
+
clks[i].num_parents,
135
+
clks[i].flags,
136
+
base + clks[i].offset,
137
+
clks[i].shift,
138
+
clks[i].width,
139
+
clks[i].mux_flags,
140
+
clks[i].lock);
141
+
142
+
if (IS_ERR(clk)) {
143
+
pr_err("%s: failed to register clock %s\n",
144
+
__func__, clks[i].name);
145
+
continue;
146
+
}
147
+
if (clks[i].id)
148
+
unit->clk_table[clks[i].id] = clk;
149
+
}
150
+
}
151
+
152
+
void mmp_register_div_clks(struct mmp_clk_unit *unit,
153
+
struct mmp_param_div_clk *clks,
154
+
void __iomem *base, int size)
155
+
{
156
+
struct clk *clk;
157
+
int i;
158
+
159
+
for (i = 0; i < size; i++) {
160
+
clk = clk_register_divider(NULL, clks[i].name,
161
+
clks[i].parent_name,
162
+
clks[i].flags,
163
+
base + clks[i].offset,
164
+
clks[i].shift,
165
+
clks[i].width,
166
+
clks[i].div_flags,
167
+
clks[i].lock);
168
+
169
+
if (IS_ERR(clk)) {
170
+
pr_err("%s: failed to register clock %s\n",
171
+
__func__, clks[i].name);
172
+
continue;
173
+
}
174
+
if (clks[i].id)
175
+
unit->clk_table[clks[i].id] = clk;
176
+
}
177
+
}
178
+
179
+
void mmp_clk_add(struct mmp_clk_unit *unit, unsigned int id,
180
+
struct clk *clk)
181
+
{
182
+
if (IS_ERR_OR_NULL(clk)) {
183
+
pr_err("CLK %d has invalid pointer %p\n", id, clk);
184
+
return;
185
+
}
186
+
if (id > unit->nr_clks) {
187
+
pr_err("CLK %d is invalid\n", id);
188
+
return;
189
+
}
190
+
191
+
unit->clk_table[id] = clk;
192
+
}
+215
-11
drivers/clk/mmp/clk.h
+215
-11
drivers/clk/mmp/clk.h
···
7
7
#define APBC_NO_BUS_CTRL BIT(0)
8
8
#define APBC_POWER_CTRL BIT(1)
9
9
10
-
struct clk_factor_masks {
11
-
unsigned int factor;
12
-
unsigned int num_mask;
13
-
unsigned int den_mask;
14
-
unsigned int num_shift;
15
-
unsigned int den_shift;
10
+
11
+
/* Clock type "factor" */
12
+
struct mmp_clk_factor_masks {
13
+
unsigned int factor;
14
+
unsigned int num_mask;
15
+
unsigned int den_mask;
16
+
unsigned int num_shift;
17
+
unsigned int den_shift;
16
18
};
17
19
18
-
struct clk_factor_tbl {
20
+
struct mmp_clk_factor_tbl {
19
21
unsigned int num;
20
22
unsigned int den;
21
23
};
24
+
25
+
struct mmp_clk_factor {
26
+
struct clk_hw hw;
27
+
void __iomem *base;
28
+
struct mmp_clk_factor_masks *masks;
29
+
struct mmp_clk_factor_tbl *ftbl;
30
+
unsigned int ftbl_cnt;
31
+
spinlock_t *lock;
32
+
};
33
+
34
+
extern struct clk *mmp_clk_register_factor(const char *name,
35
+
const char *parent_name, unsigned long flags,
36
+
void __iomem *base, struct mmp_clk_factor_masks *masks,
37
+
struct mmp_clk_factor_tbl *ftbl, unsigned int ftbl_cnt,
38
+
spinlock_t *lock);
39
+
40
+
/* Clock type "mix" */
41
+
#define MMP_CLK_BITS_MASK(width, shift) \
42
+
(((1 << (width)) - 1) << (shift))
43
+
#define MMP_CLK_BITS_GET_VAL(data, width, shift) \
44
+
((data & MMP_CLK_BITS_MASK(width, shift)) >> (shift))
45
+
#define MMP_CLK_BITS_SET_VAL(val, width, shift) \
46
+
(((val) << (shift)) & MMP_CLK_BITS_MASK(width, shift))
47
+
48
+
enum {
49
+
MMP_CLK_MIX_TYPE_V1,
50
+
MMP_CLK_MIX_TYPE_V2,
51
+
MMP_CLK_MIX_TYPE_V3,
52
+
};
53
+
54
+
/* The register layout */
55
+
struct mmp_clk_mix_reg_info {
56
+
void __iomem *reg_clk_ctrl;
57
+
void __iomem *reg_clk_sel;
58
+
u8 width_div;
59
+
u8 shift_div;
60
+
u8 width_mux;
61
+
u8 shift_mux;
62
+
u8 bit_fc;
63
+
};
64
+
65
+
/* The suggested clock table from user. */
66
+
struct mmp_clk_mix_clk_table {
67
+
unsigned long rate;
68
+
u8 parent_index;
69
+
unsigned int divisor;
70
+
unsigned int valid;
71
+
};
72
+
73
+
struct mmp_clk_mix_config {
74
+
struct mmp_clk_mix_reg_info reg_info;
75
+
struct mmp_clk_mix_clk_table *table;
76
+
unsigned int table_size;
77
+
u32 *mux_table;
78
+
struct clk_div_table *div_table;
79
+
u8 div_flags;
80
+
u8 mux_flags;
81
+
};
82
+
83
+
struct mmp_clk_mix {
84
+
struct clk_hw hw;
85
+
struct mmp_clk_mix_reg_info reg_info;
86
+
struct mmp_clk_mix_clk_table *table;
87
+
u32 *mux_table;
88
+
struct clk_div_table *div_table;
89
+
unsigned int table_size;
90
+
u8 div_flags;
91
+
u8 mux_flags;
92
+
unsigned int type;
93
+
spinlock_t *lock;
94
+
};
95
+
96
+
extern const struct clk_ops mmp_clk_mix_ops;
97
+
extern struct clk *mmp_clk_register_mix(struct device *dev,
98
+
const char *name,
99
+
const char **parent_names,
100
+
u8 num_parents,
101
+
unsigned long flags,
102
+
struct mmp_clk_mix_config *config,
103
+
spinlock_t *lock);
104
+
105
+
106
+
/* Clock type "gate". MMP private gate */
107
+
#define MMP_CLK_GATE_NEED_DELAY BIT(0)
108
+
109
+
struct mmp_clk_gate {
110
+
struct clk_hw hw;
111
+
void __iomem *reg;
112
+
u32 mask;
113
+
u32 val_enable;
114
+
u32 val_disable;
115
+
unsigned int flags;
116
+
spinlock_t *lock;
117
+
};
118
+
119
+
extern const struct clk_ops mmp_clk_gate_ops;
120
+
extern struct clk *mmp_clk_register_gate(struct device *dev, const char *name,
121
+
const char *parent_name, unsigned long flags,
122
+
void __iomem *reg, u32 mask, u32 val_enable,
123
+
u32 val_disable, unsigned int gate_flags,
124
+
spinlock_t *lock);
125
+
22
126
23
127
extern struct clk *mmp_clk_register_pll2(const char *name,
24
128
const char *parent_name, unsigned long flags);
···
132
28
extern struct clk *mmp_clk_register_apmu(const char *name,
133
29
const char *parent_name, void __iomem *base, u32 enable_mask,
134
30
spinlock_t *lock);
135
-
extern struct clk *mmp_clk_register_factor(const char *name,
136
-
const char *parent_name, unsigned long flags,
137
-
void __iomem *base, struct clk_factor_masks *masks,
138
-
struct clk_factor_tbl *ftbl, unsigned int ftbl_cnt);
31
+
32
+
struct mmp_clk_unit {
33
+
unsigned int nr_clks;
34
+
struct clk **clk_table;
35
+
struct clk_onecell_data clk_data;
36
+
};
37
+
38
+
struct mmp_param_fixed_rate_clk {
39
+
unsigned int id;
40
+
char *name;
41
+
const char *parent_name;
42
+
unsigned long flags;
43
+
unsigned long fixed_rate;
44
+
};
45
+
void mmp_register_fixed_rate_clks(struct mmp_clk_unit *unit,
46
+
struct mmp_param_fixed_rate_clk *clks,
47
+
int size);
48
+
49
+
struct mmp_param_fixed_factor_clk {
50
+
unsigned int id;
51
+
char *name;
52
+
const char *parent_name;
53
+
unsigned long mult;
54
+
unsigned long div;
55
+
unsigned long flags;
56
+
};
57
+
void mmp_register_fixed_factor_clks(struct mmp_clk_unit *unit,
58
+
struct mmp_param_fixed_factor_clk *clks,
59
+
int size);
60
+
61
+
struct mmp_param_general_gate_clk {
62
+
unsigned int id;
63
+
const char *name;
64
+
const char *parent_name;
65
+
unsigned long flags;
66
+
unsigned long offset;
67
+
u8 bit_idx;
68
+
u8 gate_flags;
69
+
spinlock_t *lock;
70
+
};
71
+
void mmp_register_general_gate_clks(struct mmp_clk_unit *unit,
72
+
struct mmp_param_general_gate_clk *clks,
73
+
void __iomem *base, int size);
74
+
75
+
struct mmp_param_gate_clk {
76
+
unsigned int id;
77
+
char *name;
78
+
const char *parent_name;
79
+
unsigned long flags;
80
+
unsigned long offset;
81
+
u32 mask;
82
+
u32 val_enable;
83
+
u32 val_disable;
84
+
unsigned int gate_flags;
85
+
spinlock_t *lock;
86
+
};
87
+
void mmp_register_gate_clks(struct mmp_clk_unit *unit,
88
+
struct mmp_param_gate_clk *clks,
89
+
void __iomem *base, int size);
90
+
91
+
struct mmp_param_mux_clk {
92
+
unsigned int id;
93
+
char *name;
94
+
const char **parent_name;
95
+
u8 num_parents;
96
+
unsigned long flags;
97
+
unsigned long offset;
98
+
u8 shift;
99
+
u8 width;
100
+
u8 mux_flags;
101
+
spinlock_t *lock;
102
+
};
103
+
void mmp_register_mux_clks(struct mmp_clk_unit *unit,
104
+
struct mmp_param_mux_clk *clks,
105
+
void __iomem *base, int size);
106
+
107
+
struct mmp_param_div_clk {
108
+
unsigned int id;
109
+
char *name;
110
+
const char *parent_name;
111
+
unsigned long flags;
112
+
unsigned long offset;
113
+
u8 shift;
114
+
u8 width;
115
+
u8 div_flags;
116
+
spinlock_t *lock;
117
+
};
118
+
void mmp_register_div_clks(struct mmp_clk_unit *unit,
119
+
struct mmp_param_div_clk *clks,
120
+
void __iomem *base, int size);
121
+
122
+
#define DEFINE_MIX_REG_INFO(w_d, s_d, w_m, s_m, fc) \
123
+
{ \
124
+
.width_div = (w_d), \
125
+
.shift_div = (s_d), \
126
+
.width_mux = (w_m), \
127
+
.shift_mux = (s_m), \
128
+
.bit_fc = (fc), \
129
+
}
130
+
131
+
void mmp_clk_init(struct device_node *np, struct mmp_clk_unit *unit,
132
+
int nr_clks);
133
+
void mmp_clk_add(struct mmp_clk_unit *unit, unsigned int id,
134
+
struct clk *clk);
139
135
#endif
+99
drivers/clk/mmp/reset.c
+99
drivers/clk/mmp/reset.c
···
1
+
#include <linux/slab.h>
2
+
#include <linux/io.h>
3
+
#include <linux/of.h>
4
+
#include <linux/of_address.h>
5
+
#include <linux/reset-controller.h>
6
+
7
+
#include "reset.h"
8
+
9
+
#define rcdev_to_unit(rcdev) container_of(rcdev, struct mmp_clk_reset_unit, rcdev)
10
+
11
+
static int mmp_of_reset_xlate(struct reset_controller_dev *rcdev,
12
+
const struct of_phandle_args *reset_spec)
13
+
{
14
+
struct mmp_clk_reset_unit *unit = rcdev_to_unit(rcdev);
15
+
struct mmp_clk_reset_cell *cell;
16
+
int i;
17
+
18
+
if (WARN_ON(reset_spec->args_count != rcdev->of_reset_n_cells))
19
+
return -EINVAL;
20
+
21
+
for (i = 0; i < rcdev->nr_resets; i++) {
22
+
cell = &unit->cells[i];
23
+
if (cell->clk_id == reset_spec->args[0])
24
+
break;
25
+
}
26
+
27
+
if (i == rcdev->nr_resets)
28
+
return -EINVAL;
29
+
30
+
return i;
31
+
}
32
+
33
+
static int mmp_clk_reset_assert(struct reset_controller_dev *rcdev,
34
+
unsigned long id)
35
+
{
36
+
struct mmp_clk_reset_unit *unit = rcdev_to_unit(rcdev);
37
+
struct mmp_clk_reset_cell *cell;
38
+
unsigned long flags = 0;
39
+
u32 val;
40
+
41
+
cell = &unit->cells[id];
42
+
if (cell->lock)
43
+
spin_lock_irqsave(cell->lock, flags);
44
+
45
+
val = readl(cell->reg);
46
+
val |= cell->bits;
47
+
writel(val, cell->reg);
48
+
49
+
if (cell->lock)
50
+
spin_unlock_irqrestore(cell->lock, flags);
51
+
52
+
return 0;
53
+
}
54
+
55
+
static int mmp_clk_reset_deassert(struct reset_controller_dev *rcdev,
56
+
unsigned long id)
57
+
{
58
+
struct mmp_clk_reset_unit *unit = rcdev_to_unit(rcdev);
59
+
struct mmp_clk_reset_cell *cell;
60
+
unsigned long flags = 0;
61
+
u32 val;
62
+
63
+
cell = &unit->cells[id];
64
+
if (cell->lock)
65
+
spin_lock_irqsave(cell->lock, flags);
66
+
67
+
val = readl(cell->reg);
68
+
val &= ~cell->bits;
69
+
writel(val, cell->reg);
70
+
71
+
if (cell->lock)
72
+
spin_unlock_irqrestore(cell->lock, flags);
73
+
74
+
return 0;
75
+
}
76
+
77
+
static struct reset_control_ops mmp_clk_reset_ops = {
78
+
.assert = mmp_clk_reset_assert,
79
+
.deassert = mmp_clk_reset_deassert,
80
+
};
81
+
82
+
void mmp_clk_reset_register(struct device_node *np,
83
+
struct mmp_clk_reset_cell *cells, int nr_resets)
84
+
{
85
+
struct mmp_clk_reset_unit *unit;
86
+
87
+
unit = kzalloc(sizeof(*unit), GFP_KERNEL);
88
+
if (!unit)
89
+
return;
90
+
91
+
unit->cells = cells;
92
+
unit->rcdev.of_reset_n_cells = 1;
93
+
unit->rcdev.nr_resets = nr_resets;
94
+
unit->rcdev.ops = &mmp_clk_reset_ops;
95
+
unit->rcdev.of_node = np;
96
+
unit->rcdev.of_xlate = mmp_of_reset_xlate;
97
+
98
+
reset_controller_register(&unit->rcdev);
99
+
}
+31
drivers/clk/mmp/reset.h
+31
drivers/clk/mmp/reset.h
···
1
+
#ifndef __MACH_MMP_CLK_RESET_H
2
+
#define __MACH_MMP_CLK_RESET_H
3
+
4
+
#include <linux/reset-controller.h>
5
+
6
+
#define MMP_RESET_INVERT 1
7
+
8
+
struct mmp_clk_reset_cell {
9
+
unsigned int clk_id;
10
+
void __iomem *reg;
11
+
u32 bits;
12
+
unsigned int flags;
13
+
spinlock_t *lock;
14
+
};
15
+
16
+
struct mmp_clk_reset_unit {
17
+
struct reset_controller_dev rcdev;
18
+
struct mmp_clk_reset_cell *cells;
19
+
};
20
+
21
+
#ifdef CONFIG_RESET_CONTROLLER
22
+
void mmp_clk_reset_register(struct device_node *np,
23
+
struct mmp_clk_reset_cell *cells, int nr_resets);
24
+
#else
25
+
static inline void mmp_clk_reset_register(struct device_node *np,
26
+
struct mmp_clk_reset_cell *cells, int nr_resets)
27
+
{
28
+
}
29
+
#endif
30
+
31
+
#endif
+1
drivers/clk/pxa/Makefile
+1
drivers/clk/pxa/Makefile
+28
-17
drivers/clk/pxa/clk-pxa.c
+28
-17
drivers/clk/pxa/clk-pxa.c
···
26
26
.clk_num = CLK_MAX,
27
27
};
28
28
29
-
#define to_pxa_clk(_hw) container_of(_hw, struct pxa_clk_cken, hw)
29
+
struct pxa_clk {
30
+
struct clk_hw hw;
31
+
struct clk_fixed_factor lp;
32
+
struct clk_fixed_factor hp;
33
+
struct clk_gate gate;
34
+
bool (*is_in_low_power)(void);
35
+
};
36
+
37
+
#define to_pxa_clk(_hw) container_of(_hw, struct pxa_clk, hw)
30
38
31
39
static unsigned long cken_recalc_rate(struct clk_hw *hw,
32
40
unsigned long parent_rate)
33
41
{
34
-
struct pxa_clk_cken *pclk = to_pxa_clk(hw);
42
+
struct pxa_clk *pclk = to_pxa_clk(hw);
35
43
struct clk_fixed_factor *fix;
36
44
37
45
if (!pclk->is_in_low_power || pclk->is_in_low_power())
···
56
48
57
49
static u8 cken_get_parent(struct clk_hw *hw)
58
50
{
59
-
struct pxa_clk_cken *pclk = to_pxa_clk(hw);
51
+
struct pxa_clk *pclk = to_pxa_clk(hw);
60
52
61
53
if (!pclk->is_in_low_power)
62
54
return 0;
···
77
69
clk_register_clkdev(clk, con_id, dev_id);
78
70
}
79
71
80
-
int __init clk_pxa_cken_init(struct pxa_clk_cken *clks, int nb_clks)
72
+
int __init clk_pxa_cken_init(const struct desc_clk_cken *clks, int nb_clks)
81
73
{
82
74
int i;
83
-
struct pxa_clk_cken *pclk;
75
+
struct pxa_clk *pxa_clk;
84
76
struct clk *clk;
85
77
86
78
for (i = 0; i < nb_clks; i++) {
87
-
pclk = clks + i;
88
-
pclk->gate.lock = &lock;
89
-
clk = clk_register_composite(NULL, pclk->name,
90
-
pclk->parent_names, 2,
91
-
&pclk->hw, &cken_mux_ops,
92
-
&pclk->hw, &cken_rate_ops,
93
-
&pclk->gate.hw, &clk_gate_ops,
94
-
pclk->flags);
95
-
clkdev_pxa_register(pclk->ckid, pclk->con_id, pclk->dev_id,
96
-
clk);
79
+
pxa_clk = kzalloc(sizeof(*pxa_clk), GFP_KERNEL);
80
+
pxa_clk->is_in_low_power = clks[i].is_in_low_power;
81
+
pxa_clk->lp = clks[i].lp;
82
+
pxa_clk->hp = clks[i].hp;
83
+
pxa_clk->gate = clks[i].gate;
84
+
pxa_clk->gate.lock = &lock;
85
+
clk = clk_register_composite(NULL, clks[i].name,
86
+
clks[i].parent_names, 2,
87
+
&pxa_clk->hw, &cken_mux_ops,
88
+
&pxa_clk->hw, &cken_rate_ops,
89
+
&pxa_clk->gate.hw, &clk_gate_ops,
90
+
clks[i].flags);
91
+
clkdev_pxa_register(clks[i].ckid, clks[i].con_id,
92
+
clks[i].dev_id, clk);
97
93
}
98
94
return 0;
99
95
}
100
96
101
-
static void __init pxa_dt_clocks_init(struct device_node *np)
97
+
void __init clk_pxa_dt_common_init(struct device_node *np)
102
98
{
103
99
of_clk_add_provider(np, of_clk_src_onecell_get, &onecell_data);
104
100
}
105
-
CLK_OF_DECLARE(pxa_clks, "marvell,pxa-clocks", pxa_dt_clocks_init);
+5
-4
drivers/clk/pxa/clk-pxa.h
+5
-4
drivers/clk/pxa/clk-pxa.h
···
25
25
static struct clk_ops name ## _rate_ops = { \
26
26
.recalc_rate = name ## _get_rate, \
27
27
}; \
28
-
static struct clk *clk_register_ ## name(void) \
28
+
static struct clk * __init clk_register_ ## name(void) \
29
29
{ \
30
30
return clk_register_composite(NULL, clk_name, \
31
31
name ## _parents, \
···
40
40
static struct clk_ops name ## _rate_ops = { \
41
41
.recalc_rate = name ## _get_rate, \
42
42
}; \
43
-
static struct clk *clk_register_ ## name(void) \
43
+
static struct clk * __init clk_register_ ## name(void) \
44
44
{ \
45
45
return clk_register_composite(NULL, clk_name, \
46
46
name ## _parents, \
···
66
66
* | Clock | --- | / div_hp |
67
67
* +------------+ +-----------+
68
68
*/
69
-
struct pxa_clk_cken {
69
+
struct desc_clk_cken {
70
70
struct clk_hw hw;
71
71
int ckid;
72
72
const char *name;
···
102
102
103
103
extern void clkdev_pxa_register(int ckid, const char *con_id,
104
104
const char *dev_id, struct clk *clk);
105
-
extern int clk_pxa_cken_init(struct pxa_clk_cken *clks, int nb_clks);
105
+
extern int clk_pxa_cken_init(const struct desc_clk_cken *clks, int nb_clks);
106
+
void clk_pxa_dt_common_init(struct device_node *np);
106
107
107
108
#endif
+273
drivers/clk/pxa/clk-pxa25x.c
+273
drivers/clk/pxa/clk-pxa25x.c
···
1
+
/*
2
+
* Marvell PXA25x family clocks
3
+
*
4
+
* Copyright (C) 2014 Robert Jarzmik
5
+
*
6
+
* Heavily inspired from former arch/arm/mach-pxa/pxa25x.c.
7
+
*
8
+
* This program is free software; you can redistribute it and/or modify
9
+
* it under the terms of the GNU General Public License as published by
10
+
* the Free Software Foundation; version 2 of the License.
11
+
*
12
+
* For non-devicetree platforms. Once pxa is fully converted to devicetree, this
13
+
* should go away.
14
+
*/
15
+
#include <linux/clk-provider.h>
16
+
#include <linux/clk.h>
17
+
#include <linux/clkdev.h>
18
+
#include <linux/io.h>
19
+
#include <linux/of.h>
20
+
#include <mach/pxa25x.h>
21
+
#include <mach/pxa2xx-regs.h>
22
+
23
+
#include <dt-bindings/clock/pxa-clock.h>
24
+
#include "clk-pxa.h"
25
+
26
+
#define KHz 1000
27
+
#define MHz (1000 * 1000)
28
+
29
+
enum {
30
+
PXA_CORE_RUN = 0,
31
+
PXA_CORE_TURBO,
32
+
};
33
+
34
+
/*
35
+
* Various clock factors driven by the CCCR register.
36
+
*/
37
+
38
+
/* Crystal Frequency to Memory Frequency Multiplier (L) */
39
+
static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
40
+
41
+
/* Memory Frequency to Run Mode Frequency Multiplier (M) */
42
+
static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
43
+
44
+
/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
45
+
/* Note: we store the value N * 2 here. */
46
+
static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
47
+
48
+
static const char * const get_freq_khz[] = {
49
+
"core", "run", "cpll", "memory"
50
+
};
51
+
52
+
/*
53
+
* Get the clock frequency as reflected by CCCR and the turbo flag.
54
+
* We assume these values have been applied via a fcs.
55
+
* If info is not 0 we also display the current settings.
56
+
*/
57
+
unsigned int pxa25x_get_clk_frequency_khz(int info)
58
+
{
59
+
struct clk *clk;
60
+
unsigned long clks[5];
61
+
int i;
62
+
63
+
for (i = 0; i < ARRAY_SIZE(get_freq_khz); i++) {
64
+
clk = clk_get(NULL, get_freq_khz[i]);
65
+
if (IS_ERR(clk)) {
66
+
clks[i] = 0;
67
+
} else {
68
+
clks[i] = clk_get_rate(clk);
69
+
clk_put(clk);
70
+
}
71
+
}
72
+
73
+
if (info) {
74
+
pr_info("Run Mode clock: %ld.%02ldMHz\n",
75
+
clks[1] / 1000000, (clks[1] % 1000000) / 10000);
76
+
pr_info("Turbo Mode clock: %ld.%02ldMHz\n",
77
+
clks[2] / 1000000, (clks[2] % 1000000) / 10000);
78
+
pr_info("Memory clock: %ld.%02ldMHz\n",
79
+
clks[3] / 1000000, (clks[3] % 1000000) / 10000);
80
+
}
81
+
82
+
return (unsigned int)clks[0];
83
+
}
84
+
85
+
static unsigned long clk_pxa25x_memory_get_rate(struct clk_hw *hw,
86
+
unsigned long parent_rate)
87
+
{
88
+
unsigned long cccr = CCCR;
89
+
unsigned int m = M_clk_mult[(cccr >> 5) & 0x03];
90
+
91
+
return parent_rate / m;
92
+
}
93
+
PARENTS(clk_pxa25x_memory) = { "run" };
94
+
RATE_RO_OPS(clk_pxa25x_memory, "memory");
95
+
96
+
PARENTS(pxa25x_pbus95) = { "ppll_95_85mhz", "ppll_95_85mhz" };
97
+
PARENTS(pxa25x_pbus147) = { "ppll_147_46mhz", "ppll_147_46mhz" };
98
+
PARENTS(pxa25x_osc3) = { "osc_3_6864mhz", "osc_3_6864mhz" };
99
+
100
+
#define PXA25X_CKEN(dev_id, con_id, parents, mult, div, \
101
+
bit, is_lp, flags) \
102
+
PXA_CKEN(dev_id, con_id, bit, parents, mult, div, mult, div, \
103
+
is_lp, &CKEN, CKEN_ ## bit, flags)
104
+
#define PXA25X_PBUS95_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \
105
+
PXA25X_CKEN(dev_id, con_id, pxa25x_pbus95_parents, mult_hp, \
106
+
div_hp, bit, NULL, 0)
107
+
#define PXA25X_PBUS147_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay)\
108
+
PXA25X_CKEN(dev_id, con_id, pxa25x_pbus147_parents, mult_hp, \
109
+
div_hp, bit, NULL, 0)
110
+
#define PXA25X_OSC3_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \
111
+
PXA25X_CKEN(dev_id, con_id, pxa25x_osc3_parents, mult_hp, \
112
+
div_hp, bit, NULL, 0)
113
+
114
+
#define PXA25X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \
115
+
PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
116
+
&CKEN, CKEN_ ## bit, 0)
117
+
#define PXA25X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \
118
+
PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
119
+
&CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)
120
+
121
+
static struct desc_clk_cken pxa25x_clocks[] __initdata = {
122
+
PXA25X_PBUS95_CKEN("pxa2xx-mci.0", NULL, MMC, 1, 5, 0),
123
+
PXA25X_PBUS95_CKEN("pxa2xx-i2c.0", NULL, I2C, 1, 3, 0),
124
+
PXA25X_PBUS95_CKEN("pxa2xx-ir", "FICPCLK", FICP, 1, 2, 0),
125
+
PXA25X_PBUS95_CKEN("pxa25x-udc", NULL, USB, 1, 2, 5),
126
+
PXA25X_PBUS147_CKEN("pxa2xx-uart.0", NULL, FFUART, 1, 10, 1),
127
+
PXA25X_PBUS147_CKEN("pxa2xx-uart.1", NULL, BTUART, 1, 10, 1),
128
+
PXA25X_PBUS147_CKEN("pxa2xx-uart.2", NULL, STUART, 1, 10, 1),
129
+
PXA25X_PBUS147_CKEN("pxa2xx-uart.3", NULL, HWUART, 1, 10, 1),
130
+
PXA25X_PBUS147_CKEN("pxa2xx-i2s", NULL, I2S, 1, 10, 0),
131
+
PXA25X_PBUS147_CKEN(NULL, "AC97CLK", AC97, 1, 12, 0),
132
+
PXA25X_OSC3_CKEN("pxa25x-ssp.0", NULL, SSP, 1, 1, 0),
133
+
PXA25X_OSC3_CKEN("pxa25x-nssp.1", NULL, NSSP, 1, 1, 0),
134
+
PXA25X_OSC3_CKEN("pxa25x-nssp.2", NULL, ASSP, 1, 1, 0),
135
+
PXA25X_OSC3_CKEN("pxa25x-pwm.0", NULL, PWM0, 1, 1, 0),
136
+
PXA25X_OSC3_CKEN("pxa25x-pwm.1", NULL, PWM1, 1, 1, 0),
137
+
138
+
PXA25X_CKEN_1RATE("pxa2xx-fb", NULL, LCD, clk_pxa25x_memory_parents, 0),
139
+
PXA25X_CKEN_1RATE_AO("pxa2xx-pcmcia", NULL, MEMC,
140
+
clk_pxa25x_memory_parents, 0),
141
+
};
142
+
143
+
static u8 clk_pxa25x_core_get_parent(struct clk_hw *hw)
144
+
{
145
+
unsigned long clkcfg;
146
+
unsigned int t;
147
+
148
+
asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
149
+
t = clkcfg & (1 << 0);
150
+
if (t)
151
+
return PXA_CORE_TURBO;
152
+
return PXA_CORE_RUN;
153
+
}
154
+
155
+
static unsigned long clk_pxa25x_core_get_rate(struct clk_hw *hw,
156
+
unsigned long parent_rate)
157
+
{
158
+
return parent_rate;
159
+
}
160
+
PARENTS(clk_pxa25x_core) = { "run", "cpll" };
161
+
MUX_RO_RATE_RO_OPS(clk_pxa25x_core, "core");
162
+
163
+
static unsigned long clk_pxa25x_run_get_rate(struct clk_hw *hw,
164
+
unsigned long parent_rate)
165
+
{
166
+
unsigned long cccr = CCCR;
167
+
unsigned int n2 = N2_clk_mult[(cccr >> 7) & 0x07];
168
+
169
+
return (parent_rate / n2) * 2;
170
+
}
171
+
PARENTS(clk_pxa25x_run) = { "cpll" };
172
+
RATE_RO_OPS(clk_pxa25x_run, "run");
173
+
174
+
static unsigned long clk_pxa25x_cpll_get_rate(struct clk_hw *hw,
175
+
unsigned long parent_rate)
176
+
{
177
+
unsigned long clkcfg, cccr = CCCR;
178
+
unsigned int l, m, n2, t;
179
+
180
+
asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
181
+
t = clkcfg & (1 << 0);
182
+
l = L_clk_mult[(cccr >> 0) & 0x1f];
183
+
m = M_clk_mult[(cccr >> 5) & 0x03];
184
+
n2 = N2_clk_mult[(cccr >> 7) & 0x07];
185
+
186
+
if (t)
187
+
return m * l * n2 * parent_rate / 2;
188
+
return m * l * parent_rate;
189
+
}
190
+
PARENTS(clk_pxa25x_cpll) = { "osc_3_6864mhz" };
191
+
RATE_RO_OPS(clk_pxa25x_cpll, "cpll");
192
+
193
+
static void __init pxa25x_register_core(void)
194
+
{
195
+
clk_register_clk_pxa25x_cpll();
196
+
clk_register_clk_pxa25x_run();
197
+
clkdev_pxa_register(CLK_CORE, "core", NULL,
198
+
clk_register_clk_pxa25x_core());
199
+
}
200
+
201
+
static void __init pxa25x_register_plls(void)
202
+
{
203
+
clk_register_fixed_rate(NULL, "osc_3_6864mhz", NULL,
204
+
CLK_GET_RATE_NOCACHE | CLK_IS_ROOT,
205
+
3686400);
206
+
clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
207
+
CLK_GET_RATE_NOCACHE | CLK_IS_ROOT,
208
+
32768);
209
+
clk_register_fixed_rate(NULL, "clk_dummy", NULL, CLK_IS_ROOT, 0);
210
+
clk_register_fixed_factor(NULL, "ppll_95_85mhz", "osc_3_6864mhz",
211
+
0, 26, 1);
212
+
clk_register_fixed_factor(NULL, "ppll_147_46mhz", "osc_3_6864mhz",
213
+
0, 40, 1);
214
+
}
215
+
216
+
static void __init pxa25x_base_clocks_init(void)
217
+
{
218
+
pxa25x_register_plls();
219
+
pxa25x_register_core();
220
+
clk_register_clk_pxa25x_memory();
221
+
}
222
+
223
+
#define DUMMY_CLK(_con_id, _dev_id, _parent) \
224
+
{ .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
225
+
struct dummy_clk {
226
+
const char *con_id;
227
+
const char *dev_id;
228
+
const char *parent;
229
+
};
230
+
static struct dummy_clk dummy_clks[] __initdata = {
231
+
DUMMY_CLK(NULL, "pxa25x-gpio", "osc_32_768khz"),
232
+
DUMMY_CLK(NULL, "pxa26x-gpio", "osc_32_768khz"),
233
+
DUMMY_CLK("GPIO11_CLK", NULL, "osc_3_6864mhz"),
234
+
DUMMY_CLK("GPIO12_CLK", NULL, "osc_32_768khz"),
235
+
DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
236
+
DUMMY_CLK("OSTIMER0", NULL, "osc_32_768khz"),
237
+
DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
238
+
};
239
+
240
+
static void __init pxa25x_dummy_clocks_init(void)
241
+
{
242
+
struct clk *clk;
243
+
struct dummy_clk *d;
244
+
const char *name;
245
+
int i;
246
+
247
+
/*
248
+
* All pinctrl logic has been wiped out of the clock driver, especially
249
+
* for gpio11 and gpio12 outputs. Machine code should ensure proper pin
250
+
* control (ie. pxa2xx_mfp_config() invocation).
251
+
*/
252
+
for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) {
253
+
d = &dummy_clks[i];
254
+
name = d->dev_id ? d->dev_id : d->con_id;
255
+
clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
256
+
clk_register_clkdev(clk, d->con_id, d->dev_id);
257
+
}
258
+
}
259
+
260
+
int __init pxa25x_clocks_init(void)
261
+
{
262
+
pxa25x_base_clocks_init();
263
+
pxa25x_dummy_clocks_init();
264
+
return clk_pxa_cken_init(pxa25x_clocks, ARRAY_SIZE(pxa25x_clocks));
265
+
}
266
+
267
+
static void __init pxa25x_dt_clocks_init(struct device_node *np)
268
+
{
269
+
pxa25x_clocks_init();
270
+
clk_pxa_dt_common_init(np);
271
+
}
272
+
CLK_OF_DECLARE(pxa25x_clks, "marvell,pxa250-core-clocks",
273
+
pxa25x_dt_clocks_init);
+8
-1
drivers/clk/pxa/clk-pxa27x.c
+8
-1
drivers/clk/pxa/clk-pxa27x.c
···
111
111
PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
112
112
&CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)
113
113
114
-
static struct pxa_clk_cken pxa27x_clocks[] = {
114
+
static struct desc_clk_cken pxa27x_clocks[] __initdata = {
115
115
PXA27X_PBUS_CKEN("pxa2xx-uart.0", NULL, FFUART, 2, 42, 1),
116
116
PXA27X_PBUS_CKEN("pxa2xx-uart.1", NULL, BTUART, 2, 42, 1),
117
117
PXA27X_PBUS_CKEN("pxa2xx-uart.2", NULL, STUART, 2, 42, 1),
···
368
368
return clk_pxa_cken_init(pxa27x_clocks, ARRAY_SIZE(pxa27x_clocks));
369
369
}
370
370
postcore_initcall(pxa27x_clocks_init);
371
+
372
+
static void __init pxa27x_dt_clocks_init(struct device_node *np)
373
+
{
374
+
pxa27x_clocks_init();
375
+
clk_pxa_dt_common_init(np);
376
+
}
377
+
CLK_OF_DECLARE(pxa_clks, "marvell,pxa270-clocks", pxa27x_dt_clocks_init);
+1
-1
drivers/clk/qcom/clk-pll.c
+1
-1
drivers/clk/qcom/clk-pll.c
+12
-8
drivers/clk/qcom/clk-rcg.c
+12
-8
drivers/clk/qcom/clk-rcg.c
···
368
368
369
369
static long _freq_tbl_determine_rate(struct clk_hw *hw,
370
370
const struct freq_tbl *f, unsigned long rate,
371
-
unsigned long *p_rate, struct clk **p)
371
+
unsigned long *p_rate, struct clk_hw **p_hw)
372
372
{
373
373
unsigned long clk_flags;
374
+
struct clk *p;
374
375
375
376
f = qcom_find_freq(f, rate);
376
377
if (!f)
377
378
return -EINVAL;
378
379
379
380
clk_flags = __clk_get_flags(hw->clk);
380
-
*p = clk_get_parent_by_index(hw->clk, f->src);
381
+
p = clk_get_parent_by_index(hw->clk, f->src);
381
382
if (clk_flags & CLK_SET_RATE_PARENT) {
382
383
rate = rate * f->pre_div;
383
384
if (f->n) {
···
388
387
rate = tmp;
389
388
}
390
389
} else {
391
-
rate = __clk_get_rate(*p);
390
+
rate = __clk_get_rate(p);
392
391
}
392
+
*p_hw = __clk_get_hw(p);
393
393
*p_rate = rate;
394
394
395
395
return f->freq;
396
396
}
397
397
398
398
static long clk_rcg_determine_rate(struct clk_hw *hw, unsigned long rate,
399
-
unsigned long *p_rate, struct clk **p)
399
+
unsigned long *p_rate, struct clk_hw **p)
400
400
{
401
401
struct clk_rcg *rcg = to_clk_rcg(hw);
402
402
···
405
403
}
406
404
407
405
static long clk_dyn_rcg_determine_rate(struct clk_hw *hw, unsigned long rate,
408
-
unsigned long *p_rate, struct clk **p)
406
+
unsigned long *p_rate, struct clk_hw **p)
409
407
{
410
408
struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
411
409
···
413
411
}
414
412
415
413
static long clk_rcg_bypass_determine_rate(struct clk_hw *hw, unsigned long rate,
416
-
unsigned long *p_rate, struct clk **p)
414
+
unsigned long *p_rate, struct clk_hw **p_hw)
417
415
{
418
416
struct clk_rcg *rcg = to_clk_rcg(hw);
419
417
const struct freq_tbl *f = rcg->freq_tbl;
418
+
struct clk *p;
420
419
421
-
*p = clk_get_parent_by_index(hw->clk, f->src);
422
-
*p_rate = __clk_round_rate(*p, rate);
420
+
p = clk_get_parent_by_index(hw->clk, f->src);
421
+
*p_hw = __clk_get_hw(p);
422
+
*p_rate = __clk_round_rate(p, rate);
423
423
424
424
return *p_rate;
425
425
}
+17
-11
drivers/clk/qcom/clk-rcg2.c
+17
-11
drivers/clk/qcom/clk-rcg2.c
···
175
175
176
176
static long _freq_tbl_determine_rate(struct clk_hw *hw,
177
177
const struct freq_tbl *f, unsigned long rate,
178
-
unsigned long *p_rate, struct clk **p)
178
+
unsigned long *p_rate, struct clk_hw **p_hw)
179
179
{
180
180
unsigned long clk_flags;
181
+
struct clk *p;
181
182
182
183
f = qcom_find_freq(f, rate);
183
184
if (!f)
184
185
return -EINVAL;
185
186
186
187
clk_flags = __clk_get_flags(hw->clk);
187
-
*p = clk_get_parent_by_index(hw->clk, f->src);
188
+
p = clk_get_parent_by_index(hw->clk, f->src);
188
189
if (clk_flags & CLK_SET_RATE_PARENT) {
189
190
if (f->pre_div) {
190
191
rate /= 2;
···
199
198
rate = tmp;
200
199
}
201
200
} else {
202
-
rate = __clk_get_rate(*p);
201
+
rate = __clk_get_rate(p);
203
202
}
203
+
*p_hw = __clk_get_hw(p);
204
204
*p_rate = rate;
205
205
206
206
return f->freq;
207
207
}
208
208
209
209
static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate,
210
-
unsigned long *p_rate, struct clk **p)
210
+
unsigned long *p_rate, struct clk_hw **p)
211
211
{
212
212
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
213
213
···
361
359
}
362
360
363
361
static long clk_edp_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
364
-
unsigned long *p_rate, struct clk **p)
362
+
unsigned long *p_rate, struct clk_hw **p)
365
363
{
366
364
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
367
365
const struct freq_tbl *f = rcg->freq_tbl;
···
373
371
u32 hid_div;
374
372
375
373
/* Force the correct parent */
376
-
*p = clk_get_parent_by_index(hw->clk, f->src);
374
+
*p = __clk_get_hw(clk_get_parent_by_index(hw->clk, f->src));
377
375
378
376
if (src_rate == 810000000)
379
377
frac = frac_table_810m;
···
412
410
EXPORT_SYMBOL_GPL(clk_edp_pixel_ops);
413
411
414
412
static long clk_byte_determine_rate(struct clk_hw *hw, unsigned long rate,
415
-
unsigned long *p_rate, struct clk **p)
413
+
unsigned long *p_rate, struct clk_hw **p_hw)
416
414
{
417
415
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
418
416
const struct freq_tbl *f = rcg->freq_tbl;
419
417
unsigned long parent_rate, div;
420
418
u32 mask = BIT(rcg->hid_width) - 1;
419
+
struct clk *p;
421
420
422
421
if (rate == 0)
423
422
return -EINVAL;
424
423
425
-
*p = clk_get_parent_by_index(hw->clk, f->src);
426
-
*p_rate = parent_rate = __clk_round_rate(*p, rate);
424
+
p = clk_get_parent_by_index(hw->clk, f->src);
425
+
*p_hw = __clk_get_hw(p);
426
+
*p_rate = parent_rate = __clk_round_rate(p, rate);
427
427
428
428
div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
429
429
div = min_t(u32, div, mask);
···
476
472
};
477
473
478
474
static long clk_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
479
-
unsigned long *p_rate, struct clk **p)
475
+
unsigned long *p_rate, struct clk_hw **p)
480
476
{
481
477
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
482
478
unsigned long request, src_rate;
483
479
int delta = 100000;
484
480
const struct freq_tbl *f = rcg->freq_tbl;
485
481
const struct frac_entry *frac = frac_table_pixel;
486
-
struct clk *parent = *p = clk_get_parent_by_index(hw->clk, f->src);
482
+
struct clk *parent = clk_get_parent_by_index(hw->clk, f->src);
483
+
484
+
*p = __clk_get_hw(parent);
487
485
488
486
for (; frac->num; frac++) {
489
487
request = (rate * frac->den) / frac->num;
+1
drivers/clk/rockchip/Makefile
+1
drivers/clk/rockchip/Makefile
+154
drivers/clk/rockchip/clk-mmc-phase.c
+154
drivers/clk/rockchip/clk-mmc-phase.c
···
1
+
/*
2
+
* Copyright 2014 Google, Inc
3
+
* Author: Alexandru M Stan <amstan@chromium.org>
4
+
*
5
+
* This program is free software; you can redistribute it and/or modify
6
+
* it under the terms of the GNU General Public License as published by
7
+
* the Free Software Foundation; either version 2 of the License, or
8
+
* (at your option) any later version.
9
+
*
10
+
* This program is distributed in the hope that it will be useful,
11
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
12
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13
+
* GNU General Public License for more details.
14
+
*/
15
+
16
+
#include <linux/slab.h>
17
+
#include <linux/clk-provider.h>
18
+
#include "clk.h"
19
+
20
+
struct rockchip_mmc_clock {
21
+
struct clk_hw hw;
22
+
void __iomem *reg;
23
+
int id;
24
+
int shift;
25
+
};
26
+
27
+
#define to_mmc_clock(_hw) container_of(_hw, struct rockchip_mmc_clock, hw)
28
+
29
+
#define RK3288_MMC_CLKGEN_DIV 2
30
+
31
+
static unsigned long rockchip_mmc_recalc(struct clk_hw *hw,
32
+
unsigned long parent_rate)
33
+
{
34
+
return parent_rate / RK3288_MMC_CLKGEN_DIV;
35
+
}
36
+
37
+
#define ROCKCHIP_MMC_DELAY_SEL BIT(10)
38
+
#define ROCKCHIP_MMC_DEGREE_MASK 0x3
39
+
#define ROCKCHIP_MMC_DELAYNUM_OFFSET 2
40
+
#define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET)
41
+
42
+
#define PSECS_PER_SEC 1000000000000LL
43
+
44
+
/*
45
+
* Each fine delay is between 40ps-80ps. Assume each fine delay is 60ps to
46
+
* simplify calculations. So 45degs could be anywhere between 33deg and 66deg.
47
+
*/
48
+
#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60
49
+
50
+
static int rockchip_mmc_get_phase(struct clk_hw *hw)
51
+
{
52
+
struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
53
+
unsigned long rate = clk_get_rate(hw->clk);
54
+
u32 raw_value;
55
+
u16 degrees;
56
+
u32 delay_num = 0;
57
+
58
+
raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);
59
+
60
+
degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;
61
+
62
+
if (raw_value & ROCKCHIP_MMC_DELAY_SEL) {
63
+
/* degrees/delaynum * 10000 */
64
+
unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) *
65
+
36 * (rate / 1000000);
66
+
67
+
delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK);
68
+
delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET;
69
+
degrees += delay_num * factor / 10000;
70
+
}
71
+
72
+
return degrees % 360;
73
+
}
74
+
75
+
static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees)
76
+
{
77
+
struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
78
+
unsigned long rate = clk_get_rate(hw->clk);
79
+
u8 nineties, remainder;
80
+
u8 delay_num;
81
+
u32 raw_value;
82
+
u64 delay;
83
+
84
+
/* allow 22 to be 22.5 */
85
+
degrees++;
86
+
/* floor to 22.5 increment */
87
+
degrees -= ((degrees) * 10 % 225) / 10;
88
+
89
+
nineties = degrees / 90;
90
+
/* 22.5 multiples */
91
+
remainder = (degrees % 90) / 22;
92
+
93
+
delay = PSECS_PER_SEC;
94
+
do_div(delay, rate);
95
+
/* / 360 / 22.5 */
96
+
do_div(delay, 16);
97
+
do_div(delay, ROCKCHIP_MMC_DELAY_ELEMENT_PSEC);
98
+
99
+
delay *= remainder;
100
+
delay_num = (u8) min(delay, 255ULL);
101
+
102
+
raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;
103
+
raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET;
104
+
raw_value |= nineties;
105
+
writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift), mmc_clock->reg);
106
+
107
+
pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n",
108
+
__clk_get_name(hw->clk), degrees, delay_num,
109
+
mmc_clock->reg, raw_value>>(mmc_clock->shift),
110
+
rockchip_mmc_get_phase(hw)
111
+
);
112
+
113
+
return 0;
114
+
}
115
+
116
+
static const struct clk_ops rockchip_mmc_clk_ops = {
117
+
.recalc_rate = rockchip_mmc_recalc,
118
+
.get_phase = rockchip_mmc_get_phase,
119
+
.set_phase = rockchip_mmc_set_phase,
120
+
};
121
+
122
+
struct clk *rockchip_clk_register_mmc(const char *name,
123
+
const char **parent_names, u8 num_parents,
124
+
void __iomem *reg, int shift)
125
+
{
126
+
struct clk_init_data init;
127
+
struct rockchip_mmc_clock *mmc_clock;
128
+
struct clk *clk;
129
+
130
+
mmc_clock = kmalloc(sizeof(*mmc_clock), GFP_KERNEL);
131
+
if (!mmc_clock)
132
+
return NULL;
133
+
134
+
init.num_parents = num_parents;
135
+
init.parent_names = parent_names;
136
+
init.ops = &rockchip_mmc_clk_ops;
137
+
138
+
mmc_clock->hw.init = &init;
139
+
mmc_clock->reg = reg;
140
+
mmc_clock->shift = shift;
141
+
142
+
if (name)
143
+
init.name = name;
144
+
145
+
clk = clk_register(NULL, &mmc_clock->hw);
146
+
if (IS_ERR(clk))
147
+
goto err_free;
148
+
149
+
return clk;
150
+
151
+
err_free:
152
+
kfree(mmc_clock);
153
+
return NULL;
154
+
}
+66
-15
drivers/clk/rockchip/clk-pll.c
+66
-15
drivers/clk/rockchip/clk-pll.c
···
39
39
int lock_offset;
40
40
unsigned int lock_shift;
41
41
enum rockchip_pll_type type;
42
+
u8 flags;
42
43
const struct rockchip_pll_rate_table *rate_table;
43
44
unsigned int rate_count;
44
45
spinlock_t *lock;
···
258
257
return !(pllcon & RK3066_PLLCON3_PWRDOWN);
259
258
}
260
259
260
+
static void rockchip_rk3066_pll_init(struct clk_hw *hw)
261
+
{
262
+
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
263
+
const struct rockchip_pll_rate_table *rate;
264
+
unsigned int nf, nr, no, bwadj;
265
+
unsigned long drate;
266
+
u32 pllcon;
267
+
268
+
if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
269
+
return;
270
+
271
+
drate = __clk_get_rate(hw->clk);
272
+
rate = rockchip_get_pll_settings(pll, drate);
273
+
274
+
/* when no rate setting for the current rate, rely on clk_set_rate */
275
+
if (!rate)
276
+
return;
277
+
278
+
pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));
279
+
nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT) & RK3066_PLLCON0_NR_MASK) + 1;
280
+
no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT) & RK3066_PLLCON0_OD_MASK) + 1;
281
+
282
+
pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));
283
+
nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT) & RK3066_PLLCON1_NF_MASK) + 1;
284
+
285
+
pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2));
286
+
bwadj = (pllcon >> RK3066_PLLCON2_BWADJ_SHIFT) & RK3066_PLLCON2_BWADJ_MASK;
287
+
288
+
pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), bwadj(%d:%d)\n",
289
+
__func__, __clk_get_name(hw->clk), drate, rate->nr, nr,
290
+
rate->no, no, rate->nf, nf, rate->bwadj, bwadj);
291
+
if (rate->nr != nr || rate->no != no || rate->nf != nf
292
+
|| rate->bwadj != bwadj) {
293
+
struct clk *parent = __clk_get_parent(hw->clk);
294
+
unsigned long prate;
295
+
296
+
if (!parent) {
297
+
pr_warn("%s: parent of %s not available\n",
298
+
__func__, __clk_get_name(hw->clk));
299
+
return;
300
+
}
301
+
302
+
pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
303
+
__func__, __clk_get_name(hw->clk));
304
+
prate = __clk_get_rate(parent);
305
+
rockchip_rk3066_pll_set_rate(hw, drate, prate);
306
+
}
307
+
}
308
+
261
309
static const struct clk_ops rockchip_rk3066_pll_clk_norate_ops = {
262
310
.recalc_rate = rockchip_rk3066_pll_recalc_rate,
263
311
.enable = rockchip_rk3066_pll_enable,
···
321
271
.enable = rockchip_rk3066_pll_enable,
322
272
.disable = rockchip_rk3066_pll_disable,
323
273
.is_enabled = rockchip_rk3066_pll_is_enabled,
274
+
.init = rockchip_rk3066_pll_init,
324
275
};
325
276
326
277
/*
···
333
282
void __iomem *base, int con_offset, int grf_lock_offset,
334
283
int lock_shift, int mode_offset, int mode_shift,
335
284
struct rockchip_pll_rate_table *rate_table,
336
-
spinlock_t *lock)
285
+
u8 clk_pll_flags, spinlock_t *lock)
337
286
{
338
287
const char *pll_parents[3];
339
288
struct clk_init_data init;
···
396
345
pll->reg_base = base + con_offset;
397
346
pll->lock_offset = grf_lock_offset;
398
347
pll->lock_shift = lock_shift;
348
+
pll->flags = clk_pll_flags;
399
349
pll->lock = lock;
350
+
351
+
/* create the mux on top of the real pll */
352
+
pll->pll_mux_ops = &clk_mux_ops;
353
+
pll_mux = &pll->pll_mux;
354
+
pll_mux->reg = base + mode_offset;
355
+
pll_mux->shift = mode_shift;
356
+
pll_mux->mask = PLL_MODE_MASK;
357
+
pll_mux->flags = 0;
358
+
pll_mux->lock = lock;
359
+
pll_mux->hw.init = &init;
360
+
361
+
if (pll_type == pll_rk3066)
362
+
pll_mux->flags |= CLK_MUX_HIWORD_MASK;
400
363
401
364
pll_clk = clk_register(NULL, &pll->hw);
402
365
if (IS_ERR(pll_clk)) {
···
419
354
mux_clk = pll_clk;
420
355
goto err_pll;
421
356
}
422
-
423
-
/* create the mux on top of the real pll */
424
-
pll->pll_mux_ops = &clk_mux_ops;
425
-
pll_mux = &pll->pll_mux;
426
357
427
358
/* the actual muxing is xin24m, pll-output, xin32k */
428
359
pll_parents[0] = parent_names[0];
···
430
369
init.ops = pll->pll_mux_ops;
431
370
init.parent_names = pll_parents;
432
371
init.num_parents = ARRAY_SIZE(pll_parents);
433
-
434
-
pll_mux->reg = base + mode_offset;
435
-
pll_mux->shift = mode_shift;
436
-
pll_mux->mask = PLL_MODE_MASK;
437
-
pll_mux->flags = 0;
438
-
pll_mux->lock = lock;
439
-
pll_mux->hw.init = &init;
440
-
441
-
if (pll_type == pll_rk3066)
442
-
pll_mux->flags |= CLK_MUX_HIWORD_MASK;
443
372
444
373
mux_clk = clk_register(NULL, &pll_mux->hw);
445
374
if (IS_ERR(mux_clk))
+36
-43
drivers/clk/rockchip/clk-rk3188.c
+36
-43
drivers/clk/rockchip/clk-rk3188.c
···
212
212
213
213
static struct rockchip_pll_clock rk3188_pll_clks[] __initdata = {
214
214
[apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
215
-
RK2928_MODE_CON, 0, 6, rk3188_pll_rates),
215
+
RK2928_MODE_CON, 0, 6, 0, rk3188_pll_rates),
216
216
[dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
217
-
RK2928_MODE_CON, 4, 5, NULL),
217
+
RK2928_MODE_CON, 4, 5, 0, NULL),
218
218
[cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
219
-
RK2928_MODE_CON, 8, 7, rk3188_pll_rates),
219
+
RK2928_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
220
220
[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
221
-
RK2928_MODE_CON, 12, 8, rk3188_pll_rates),
221
+
RK2928_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
222
222
};
223
223
224
224
#define MFLAGS CLK_MUX_HIWORD_MASK
···
257
257
GATE(0, "hclk_vdpu", "aclk_vdpu", 0,
258
258
RK2928_CLKGATE_CON(3), 12, GFLAGS),
259
259
260
-
GATE(0, "gpll_ddr", "gpll", 0,
260
+
GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
261
261
RK2928_CLKGATE_CON(1), 7, GFLAGS),
262
-
COMPOSITE(0, "ddrphy", mux_ddrphy_p, 0,
262
+
COMPOSITE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
263
263
RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
264
264
RK2928_CLKGATE_CON(0), 2, GFLAGS),
265
265
···
270
270
RK2928_CLKGATE_CON(0), 6, GFLAGS),
271
271
GATE(0, "pclk_cpu", "pclk_cpu_pre", 0,
272
272
RK2928_CLKGATE_CON(0), 5, GFLAGS),
273
-
GATE(0, "hclk_cpu", "hclk_cpu_pre", 0,
273
+
GATE(0, "hclk_cpu", "hclk_cpu_pre", CLK_IGNORE_UNUSED,
274
274
RK2928_CLKGATE_CON(0), 4, GFLAGS),
275
275
276
-
COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, 0,
276
+
COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
277
277
RK2928_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 5, DFLAGS,
278
278
RK2928_CLKGATE_CON(3), 0, GFLAGS),
279
279
COMPOSITE(0, "aclk_lcdc1_pre", mux_pll_src_cpll_gpll_p, 0,
···
304
304
* the 480m are generated inside the usb block from these clocks,
305
305
* but they are also a source for the hsicphy clock.
306
306
*/
307
-
GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", 0,
307
+
GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", CLK_IGNORE_UNUSED,
308
308
RK2928_CLKGATE_CON(1), 5, GFLAGS),
309
-
GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", 0,
309
+
GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", CLK_IGNORE_UNUSED,
310
310
RK2928_CLKGATE_CON(1), 6, GFLAGS),
311
311
312
312
COMPOSITE(0, "mac_src", mux_mac_p, 0,
···
320
320
COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0,
321
321
RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
322
322
RK2928_CLKGATE_CON(2), 6, GFLAGS),
323
-
COMPOSITE_FRAC(0, "hsadc_frac", "hsadc_src",
323
+
COMPOSITE_FRAC(0, "hsadc_frac", "hsadc_src", 0,
324
324
RK2928_CLKSEL_CON(23), 0,
325
-
RK2928_CLKGATE_CON(2), 7, 0, GFLAGS),
325
+
RK2928_CLKGATE_CON(2), 7, GFLAGS),
326
326
MUX(SCLK_HSADC, "sclk_hsadc", mux_sclk_hsadc_p, 0,
327
327
RK2928_CLKSEL_CON(22), 4, 2, MFLAGS),
328
328
329
329
COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
330
330
RK2928_CLKSEL_CON(24), 8, 8, DFLAGS,
331
331
RK2928_CLKGATE_CON(2), 8, GFLAGS),
332
+
333
+
COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0,
334
+
RK2928_CLKSEL_CON(5), 0, 7, DFLAGS,
335
+
RK2928_CLKGATE_CON(0), 13, GFLAGS),
336
+
COMPOSITE_FRAC(0, "spdif_frac", "spdif_pll", 0,
337
+
RK2928_CLKSEL_CON(9), 0,
338
+
RK2928_CLKGATE_CON(0), 14, GFLAGS),
339
+
MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0,
340
+
RK2928_CLKSEL_CON(5), 8, 2, MFLAGS),
332
341
333
342
/*
334
343
* Clock-Architecture Diagram 4
···
408
399
409
400
/* aclk_cpu gates */
410
401
GATE(ACLK_DMA1, "aclk_dma1", "aclk_cpu", 0, RK2928_CLKGATE_CON(5), 0, GFLAGS),
411
-
GATE(0, "aclk_intmem", "aclk_cpu", 0, RK2928_CLKGATE_CON(4), 12, GFLAGS),
412
-
GATE(0, "aclk_strc_sys", "aclk_cpu", 0, RK2928_CLKGATE_CON(4), 10, GFLAGS),
402
+
GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS),
403
+
GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS),
413
404
414
405
/* hclk_cpu gates */
415
406
GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, GFLAGS),
···
419
410
/* hclk_ahb2apb is part of a clk branch */
420
411
GATE(0, "hclk_vio_bus", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 12, GFLAGS),
421
412
GATE(HCLK_LCDC0, "hclk_lcdc0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 1, GFLAGS),
422
-
GATE(HCLK_LCDC1, "hclk_lcdc1", "aclk_cpu", 0, RK2928_CLKGATE_CON(6), 2, GFLAGS),
413
+
GATE(HCLK_LCDC1, "hclk_lcdc1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 2, GFLAGS),
423
414
GATE(HCLK_CIF0, "hclk_cif0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 4, GFLAGS),
424
415
GATE(HCLK_IPP, "hclk_ipp", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 9, GFLAGS),
425
416
GATE(HCLK_RGA, "hclk_rga", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 10, GFLAGS),
426
417
427
418
/* hclk_peri gates */
428
-
GATE(0, "hclk_peri_axi_matrix", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 0, GFLAGS),
429
-
GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 6, GFLAGS),
419
+
GATE(0, "hclk_peri_axi_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS),
420
+
GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 6, GFLAGS),
430
421
GATE(0, "hclk_emem_peri", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 7, GFLAGS),
431
422
GATE(HCLK_EMAC, "hclk_emac", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS),
432
423
GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
···
466
457
GATE(0, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS),
467
458
GATE(0, "pclk_ddrpubl", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
468
459
GATE(0, "pclk_dbg", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
469
-
GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 4, GFLAGS),
470
-
GATE(PCLK_PMU, "pclk_pmu", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 5, GFLAGS),
460
+
GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
461
+
GATE(PCLK_PMU, "pclk_pmu", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 5, GFLAGS),
471
462
472
463
/* aclk_peri */
473
464
GATE(ACLK_DMA2, "aclk_dma2", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS),
474
465
GATE(ACLK_SMC, "aclk_smc", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 8, GFLAGS),
475
-
GATE(0, "aclk_peri_niu", "aclk_peri", 0, RK2928_CLKGATE_CON(4), 4, GFLAGS),
476
-
GATE(0, "aclk_cpu_peri", "aclk_peri", 0, RK2928_CLKGATE_CON(4), 2, GFLAGS),
477
-
GATE(0, "aclk_peri_axi_matrix", "aclk_peri", 0, RK2928_CLKGATE_CON(4), 3, GFLAGS),
466
+
GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 4, GFLAGS),
467
+
GATE(0, "aclk_cpu_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS),
468
+
GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS),
478
469
479
470
/* pclk_peri gates */
480
-
GATE(0, "pclk_peri_axi_matrix", "pclk_peri", 0, RK2928_CLKGATE_CON(4), 1, GFLAGS),
471
+
GATE(0, "pclk_peri_axi_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS),
481
472
GATE(PCLK_PWM23, "pclk_pwm23", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 11, GFLAGS),
482
473
GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
483
474
GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS),
···
520
511
| CLK_DIVIDER_READ_ONLY,
521
512
RK2928_CLKGATE_CON(4), 9, GFLAGS),
522
513
523
-
GATE(CORE_L2C, "core_l2c", "aclk_cpu", 0,
514
+
GATE(CORE_L2C, "core_l2c", "aclk_cpu", CLK_IGNORE_UNUSED,
524
515
RK2928_CLKGATE_CON(9), 4, GFLAGS),
525
516
526
517
COMPOSITE(0, "aclk_peri_pre", mux_pll_src_gpll_cpll_p, 0,
···
586
577
RK2928_CLKGATE_CON(0), 12, GFLAGS),
587
578
MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, 0,
588
579
RK2928_CLKSEL_CON(4), 8, 2, MFLAGS),
589
-
COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0,
590
-
RK2928_CLKSEL_CON(5), 0, 7, DFLAGS,
591
-
RK2928_CLKGATE_CON(0), 13, GFLAGS),
592
-
COMPOSITE_FRAC(0, "spdif_frac", "spdif_pll", 0,
593
-
RK2928_CLKSEL_CON(9), 0,
594
-
RK2928_CLKGATE_CON(0), 14, GFLAGS),
595
-
MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0,
596
-
RK2928_CLKSEL_CON(5), 8, 2, MFLAGS),
597
580
598
581
GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
599
582
GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
···
619
618
"gpll", "cpll" };
620
619
621
620
static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
622
-
COMPOSITE_NOMUX_DIVTBL(0, "aclk_core", "armclk", 0,
621
+
COMPOSITE_NOMUX_DIVTBL(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
623
622
RK2928_CLKSEL_CON(1), 3, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
624
623
div_rk3188_aclk_core_t, RK2928_CLKGATE_CON(0), 7, GFLAGS),
625
624
···
634
633
RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
635
634
RK2928_CLKGATE_CON(4), 9, GFLAGS),
636
635
637
-
GATE(CORE_L2C, "core_l2c", "armclk", 0,
636
+
GATE(CORE_L2C, "core_l2c", "armclk", CLK_IGNORE_UNUSED,
638
637
RK2928_CLKGATE_CON(9), 4, GFLAGS),
639
638
640
639
COMPOSITE(0, "aclk_peri_pre", mux_pll_src_cpll_gpll_p, 0,
···
664
663
RK2928_CLKSEL_CON(30), 0, 2, DFLAGS,
665
664
RK2928_CLKGATE_CON(3), 6, GFLAGS),
666
665
DIV(0, "sclk_hsicphy_12m", "sclk_hsicphy_480m", 0,
667
-
RK2928_CLKGATE_CON(11), 8, 6, DFLAGS),
666
+
RK2928_CLKSEL_CON(11), 8, 6, DFLAGS),
668
667
669
668
MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,
670
669
RK2928_CLKSEL_CON(2), 15, 1, MFLAGS),
···
676
675
RK2928_CLKGATE_CON(0), 10, GFLAGS),
677
676
MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
678
677
RK2928_CLKSEL_CON(3), 8, 2, MFLAGS),
679
-
COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0,
680
-
RK2928_CLKSEL_CON(5), 0, 7, DFLAGS,
681
-
RK2928_CLKGATE_CON(13), 13, GFLAGS),
682
-
COMPOSITE_FRAC(0, "spdif_frac", "spdif_pll", 0,
683
-
RK2928_CLKSEL_CON(9), 0,
684
-
RK2928_CLKGATE_CON(0), 14, GFLAGS),
685
-
MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0,
686
-
RK2928_CLKSEL_CON(5), 8, 2, MFLAGS),
687
678
688
679
GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
689
680
GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS),
+160
-86
drivers/clk/rockchip/clk-rk3288.c
+160
-86
drivers/clk/rockchip/clk-rk3288.c
···
16
16
#include <linux/clk-provider.h>
17
17
#include <linux/of.h>
18
18
#include <linux/of_address.h>
19
+
#include <linux/syscore_ops.h>
19
20
#include <dt-bindings/clock/rk3288-cru.h>
20
21
#include "clk.h"
21
22
···
84
83
RK3066_PLL_RATE( 742500000, 8, 495, 2),
85
84
RK3066_PLL_RATE( 696000000, 1, 58, 2),
86
85
RK3066_PLL_RATE( 600000000, 1, 50, 2),
87
-
RK3066_PLL_RATE( 594000000, 2, 198, 4),
86
+
RK3066_PLL_RATE_BWADJ(594000000, 1, 198, 8, 1),
88
87
RK3066_PLL_RATE( 552000000, 1, 46, 2),
89
88
RK3066_PLL_RATE( 504000000, 1, 84, 4),
89
+
RK3066_PLL_RATE( 500000000, 3, 125, 2),
90
90
RK3066_PLL_RATE( 456000000, 1, 76, 4),
91
91
RK3066_PLL_RATE( 408000000, 1, 68, 4),
92
+
RK3066_PLL_RATE( 400000000, 3, 100, 2),
92
93
RK3066_PLL_RATE( 384000000, 2, 128, 4),
93
94
RK3066_PLL_RATE( 360000000, 1, 60, 4),
94
95
RK3066_PLL_RATE( 312000000, 1, 52, 4),
···
176
173
PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
177
174
PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
178
175
PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
179
-
PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usb480m" };
176
+
PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usbphy480m_src" };
177
+
PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "usbphy480m_src", "npll" };
180
178
181
179
PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "xin24m" };
182
180
PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
183
181
PNAME(mux_i2s_clkout_p) = { "i2s_pre", "xin12m" };
184
182
PNAME(mux_spdif_p) = { "spdif_pre", "spdif_frac", "xin12m" };
185
183
PNAME(mux_spdif_8ch_p) = { "spdif_8ch_pre", "spdif_8ch_frac", "xin12m" };
186
-
PNAME(mux_uart0_pll_p) = { "cpll", "gpll", "usbphy_480m_src", "npll" };
187
184
PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
188
185
PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
189
186
PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
···
195
192
PNAME(mux_edp_24m_p) = { "ext_edp_24m", "xin24m" };
196
193
PNAME(mux_tspout_p) = { "cpll", "gpll", "npll", "xin27m" };
197
194
198
-
PNAME(mux_usbphy480m_p) = { "sclk_otgphy0", "sclk_otgphy1",
199
-
"sclk_otgphy2" };
195
+
PNAME(mux_usbphy480m_p) = { "sclk_otgphy1", "sclk_otgphy2",
196
+
"sclk_otgphy0" };
200
197
PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy480m_src" };
201
198
PNAME(mux_hsicphy12m_p) = { "hsicphy12m_xin12m", "hsicphy12m_usbphy" };
202
199
203
200
static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
204
201
[apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK3288_PLL_CON(0),
205
-
RK3288_MODE_CON, 0, 6, rk3288_pll_rates),
202
+
RK3288_MODE_CON, 0, 6, 0, rk3288_pll_rates),
206
203
[dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3288_PLL_CON(4),
207
-
RK3288_MODE_CON, 4, 5, NULL),
204
+
RK3288_MODE_CON, 4, 5, 0, NULL),
208
205
[cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),
209
-
RK3288_MODE_CON, 8, 7, rk3288_pll_rates),
206
+
RK3288_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
210
207
[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
211
-
RK3288_MODE_CON, 12, 8, rk3288_pll_rates),
208
+
RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
212
209
[npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16),
213
-
RK3288_MODE_CON, 14, 9, rk3288_pll_rates),
210
+
RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
214
211
};
215
212
216
213
static struct clk_div_table div_hclk_cpu_t[] = {
···
229
226
* Clock-Architecture Diagram 1
230
227
*/
231
228
232
-
GATE(0, "apll_core", "apll", 0,
229
+
GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
233
230
RK3288_CLKGATE_CON(0), 1, GFLAGS),
234
-
GATE(0, "gpll_core", "gpll", 0,
231
+
GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
235
232
RK3288_CLKGATE_CON(0), 2, GFLAGS),
236
233
237
-
COMPOSITE_NOMUX(0, "armcore0", "armclk", 0,
234
+
COMPOSITE_NOMUX(0, "armcore0", "armclk", CLK_IGNORE_UNUSED,
238
235
RK3288_CLKSEL_CON(36), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
239
236
RK3288_CLKGATE_CON(12), 0, GFLAGS),
240
-
COMPOSITE_NOMUX(0, "armcore1", "armclk", 0,
237
+
COMPOSITE_NOMUX(0, "armcore1", "armclk", CLK_IGNORE_UNUSED,
241
238
RK3288_CLKSEL_CON(36), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
242
239
RK3288_CLKGATE_CON(12), 1, GFLAGS),
243
-
COMPOSITE_NOMUX(0, "armcore2", "armclk", 0,
240
+
COMPOSITE_NOMUX(0, "armcore2", "armclk", CLK_IGNORE_UNUSED,
244
241
RK3288_CLKSEL_CON(36), 8, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
245
242
RK3288_CLKGATE_CON(12), 2, GFLAGS),
246
-
COMPOSITE_NOMUX(0, "armcore3", "armclk", 0,
243
+
COMPOSITE_NOMUX(0, "armcore3", "armclk", CLK_IGNORE_UNUSED,
247
244
RK3288_CLKSEL_CON(36), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
248
245
RK3288_CLKGATE_CON(12), 3, GFLAGS),
249
-
COMPOSITE_NOMUX(0, "l2ram", "armclk", 0,
246
+
COMPOSITE_NOMUX(0, "l2ram", "armclk", CLK_IGNORE_UNUSED,
250
247
RK3288_CLKSEL_CON(37), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
251
248
RK3288_CLKGATE_CON(12), 4, GFLAGS),
252
-
COMPOSITE_NOMUX(0, "aclk_core_m0", "armclk", 0,
249
+
COMPOSITE_NOMUX(0, "aclk_core_m0", "armclk", CLK_IGNORE_UNUSED,
253
250
RK3288_CLKSEL_CON(0), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
254
251
RK3288_CLKGATE_CON(12), 5, GFLAGS),
255
-
COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", 0,
252
+
COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", CLK_IGNORE_UNUSED,
256
253
RK3288_CLKSEL_CON(0), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
257
254
RK3288_CLKGATE_CON(12), 6, GFLAGS),
258
255
COMPOSITE_NOMUX(0, "atclk", "armclk", 0,
259
256
RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
260
257
RK3288_CLKGATE_CON(12), 7, GFLAGS),
261
-
COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", 0,
258
+
COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", CLK_IGNORE_UNUSED,
262
259
RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
263
260
RK3288_CLKGATE_CON(12), 8, GFLAGS),
264
261
GATE(0, "pclk_dbg", "pclk_dbg_pre", 0,
265
262
RK3288_CLKGATE_CON(12), 9, GFLAGS),
266
-
GATE(0, "cs_dbg", "pclk_dbg_pre", 0,
263
+
GATE(0, "cs_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
267
264
RK3288_CLKGATE_CON(12), 10, GFLAGS),
268
265
GATE(0, "pclk_core_niu", "pclk_dbg_pre", 0,
269
266
RK3288_CLKGATE_CON(12), 11, GFLAGS),
270
267
271
-
GATE(0, "dpll_ddr", "dpll", 0,
268
+
GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
272
269
RK3288_CLKGATE_CON(0), 8, GFLAGS),
273
270
GATE(0, "gpll_ddr", "gpll", 0,
274
271
RK3288_CLKGATE_CON(0), 9, GFLAGS),
275
-
COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, 0,
272
+
COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
276
273
RK3288_CLKSEL_CON(26), 2, 1, MFLAGS, 0, 2,
277
274
DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
278
275
279
-
GATE(0, "gpll_aclk_cpu", "gpll", 0,
276
+
GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED,
280
277
RK3288_CLKGATE_CON(0), 10, GFLAGS),
281
-
GATE(0, "cpll_aclk_cpu", "cpll", 0,
278
+
GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED,
282
279
RK3288_CLKGATE_CON(0), 11, GFLAGS),
283
-
COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,
280
+
COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, CLK_IGNORE_UNUSED,
284
281
RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS),
285
-
DIV(0, "aclk_cpu_pre", "aclk_cpu_src", 0,
282
+
DIV(0, "aclk_cpu_pre", "aclk_cpu_src", CLK_SET_RATE_PARENT,
286
283
RK3288_CLKSEL_CON(1), 0, 3, DFLAGS),
287
-
GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0,
284
+
GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
288
285
RK3288_CLKGATE_CON(0), 3, GFLAGS),
289
-
COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", 0,
286
+
COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
290
287
RK3288_CLKSEL_CON(1), 12, 3, DFLAGS,
291
288
RK3288_CLKGATE_CON(0), 5, GFLAGS),
292
-
COMPOSITE_NOMUX_DIVTBL(HCLK_CPU, "hclk_cpu", "aclk_cpu_pre", 0,
289
+
COMPOSITE_NOMUX_DIVTBL(HCLK_CPU, "hclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
293
290
RK3288_CLKSEL_CON(1), 8, 2, DFLAGS, div_hclk_cpu_t,
294
291
RK3288_CLKGATE_CON(0), 4, GFLAGS),
295
292
GATE(0, "c2c_host", "aclk_cpu_src", 0,
···
297
294
COMPOSITE_NOMUX(0, "crypto", "aclk_cpu_pre", 0,
298
295
RK3288_CLKSEL_CON(26), 6, 2, DFLAGS,
299
296
RK3288_CLKGATE_CON(5), 4, GFLAGS),
300
-
GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", 0,
297
+
GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
301
298
RK3288_CLKGATE_CON(0), 7, GFLAGS),
302
299
303
300
COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0,
···
308
305
RK3288_CLKGATE_CON(4), 2, GFLAGS),
309
306
MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
310
307
RK3288_CLKSEL_CON(4), 8, 2, MFLAGS),
311
-
COMPOSITE_NODIV(0, "i2s0_clkout", mux_i2s_clkout_p, CLK_SET_RATE_PARENT,
308
+
COMPOSITE_NODIV(SCLK_I2S0_OUT, "i2s0_clkout", mux_i2s_clkout_p, 0,
312
309
RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,
313
310
RK3288_CLKGATE_CON(4), 0, GFLAGS),
314
311
GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT,
···
328
325
COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", 0,
329
326
RK3288_CLKSEL_CON(40), 0, 7, DFLAGS,
330
327
RK3288_CLKGATE_CON(4), 7, GFLAGS),
331
-
COMPOSITE_FRAC(0, "spdif_8ch_frac", "spdif_8ch_src", 0,
328
+
COMPOSITE_FRAC(0, "spdif_8ch_frac", "spdif_8ch_pre", 0,
332
329
RK3288_CLKSEL_CON(41), 0,
333
330
RK3288_CLKGATE_CON(4), 8, GFLAGS),
334
331
COMPOSITE_NODIV(SCLK_SPDIF8CH, "sclk_spdif_8ch", mux_spdif_8ch_p, 0,
···
376
373
GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
377
374
RK3288_CLKGATE_CON(9), 1, GFLAGS),
378
375
379
-
COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, 0,
376
+
COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
380
377
RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
381
378
RK3288_CLKGATE_CON(3), 0, GFLAGS),
382
379
DIV(0, "hclk_vio", "aclk_vio0", 0,
383
380
RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
384
-
COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, 0,
381
+
COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
385
382
RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
386
383
RK3288_CLKGATE_CON(3), 2, GFLAGS),
387
384
···
439
436
440
437
DIV(0, "pclk_pd_alive", "gpll", 0,
441
438
RK3288_CLKSEL_CON(33), 8, 5, DFLAGS),
442
-
COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", 0,
439
+
COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", CLK_IGNORE_UNUSED,
443
440
RK3288_CLKSEL_CON(33), 0, 5, DFLAGS,
444
441
RK3288_CLKGATE_CON(5), 8, GFLAGS),
445
442
446
-
COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_cpll_gpll_usb480m_p, 0,
443
+
COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_cpll_gll_usb_npll_p, 0,
447
444
RK3288_CLKSEL_CON(34), 6, 2, MFLAGS, 0, 5, DFLAGS,
448
445
RK3288_CLKGATE_CON(5), 7, GFLAGS),
449
446
450
-
COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, 0,
447
+
COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
451
448
RK3288_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
452
449
RK3288_CLKGATE_CON(2), 0, GFLAGS),
453
450
COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
454
451
RK3288_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
455
452
RK3288_CLKGATE_CON(2), 3, GFLAGS),
456
-
COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0,
453
+
COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
457
454
RK3288_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
458
455
RK3288_CLKGATE_CON(2), 2, GFLAGS),
459
-
GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
456
+
GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
460
457
RK3288_CLKGATE_CON(2), 1, GFLAGS),
461
458
462
459
/*
···
486
483
RK3288_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 6, DFLAGS,
487
484
RK3288_CLKGATE_CON(13), 3, GFLAGS),
488
485
486
+
MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3288_SDMMC_CON0, 1),
487
+
MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3288_SDMMC_CON1, 0),
488
+
489
+
MMC(SCLK_SDIO0_DRV, "sdio0_drv", "sclk_sdio0", RK3288_SDIO0_CON0, 1),
490
+
MMC(SCLK_SDIO0_SAMPLE, "sdio0_sample", "sclk_sdio0", RK3288_SDIO0_CON1, 0),
491
+
492
+
MMC(SCLK_SDIO1_DRV, "sdio1_drv", "sclk_sdio1", RK3288_SDIO1_CON0, 1),
493
+
MMC(SCLK_SDIO1_SAMPLE, "sdio1_sample", "sclk_sdio1", RK3288_SDIO1_CON1, 0),
494
+
495
+
MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3288_EMMC_CON0, 1),
496
+
MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3288_EMMC_CON1, 0),
497
+
489
498
COMPOSITE(0, "sclk_tspout", mux_tspout_p, 0,
490
499
RK3288_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS,
491
500
RK3288_CLKGATE_CON(4), 11, GFLAGS),
···
505
490
RK3288_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
506
491
RK3288_CLKGATE_CON(4), 10, GFLAGS),
507
492
508
-
GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", 0,
493
+
GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", CLK_IGNORE_UNUSED,
509
494
RK3288_CLKGATE_CON(13), 4, GFLAGS),
510
-
GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", 0,
495
+
GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", CLK_IGNORE_UNUSED,
511
496
RK3288_CLKGATE_CON(13), 5, GFLAGS),
512
-
GATE(SCLK_OTGPHY2, "sclk_otgphy2", "usb480m", 0,
497
+
GATE(SCLK_OTGPHY2, "sclk_otgphy2", "usb480m", CLK_IGNORE_UNUSED,
513
498
RK3288_CLKGATE_CON(13), 6, GFLAGS),
514
-
GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", 0,
499
+
GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", CLK_IGNORE_UNUSED,
515
500
RK3288_CLKGATE_CON(13), 7, GFLAGS),
516
501
517
502
COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin32k", 0,
···
532
517
RK3288_CLKSEL_CON(38), 15, 1, MFLAGS, 8, 5, DFLAGS,
533
518
RK3288_CLKGATE_CON(5), 6, GFLAGS),
534
519
535
-
COMPOSITE(0, "uart0_src", mux_uart0_pll_p, 0,
520
+
COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gll_usb_npll_p, 0,
536
521
RK3288_CLKSEL_CON(13), 13, 2, MFLAGS, 0, 7, DFLAGS,
537
522
RK3288_CLKGATE_CON(1), 8, GFLAGS),
538
523
COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", 0,
···
600
585
601
586
COMPOSITE_NODIV(0, "usbphy480m_src", mux_usbphy480m_p, 0,
602
587
RK3288_CLKSEL_CON(13), 11, 2, MFLAGS,
603
-
RK3288_CLKGATE_CON(5), 15, GFLAGS),
588
+
RK3288_CLKGATE_CON(5), 14, GFLAGS),
604
589
COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
605
590
RK3288_CLKSEL_CON(29), 0, 2, MFLAGS,
606
591
RK3288_CLKGATE_CON(3), 6, GFLAGS),
···
616
601
*/
617
602
618
603
/* aclk_cpu gates */
619
-
GATE(0, "sclk_intmem0", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 5, GFLAGS),
620
-
GATE(0, "sclk_intmem1", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 6, GFLAGS),
621
-
GATE(0, "sclk_intmem2", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 7, GFLAGS),
604
+
GATE(0, "sclk_intmem0", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 5, GFLAGS),
605
+
GATE(0, "sclk_intmem1", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 6, GFLAGS),
606
+
GATE(0, "sclk_intmem2", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 7, GFLAGS),
622
607
GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 12, GFLAGS),
623
-
GATE(0, "aclk_strc_sys", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 13, GFLAGS),
624
-
GATE(0, "aclk_intmem", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 4, GFLAGS),
608
+
GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 13, GFLAGS),
609
+
GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 4, GFLAGS),
625
610
GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 6, GFLAGS),
626
611
GATE(0, "aclk_ccp", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 8, GFLAGS),
627
612
628
613
/* hclk_cpu gates */
629
614
GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 0, RK3288_CLKGATE_CON(11), 7, GFLAGS),
630
615
GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 8, GFLAGS),
631
-
GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 9, GFLAGS),
616
+
GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 9, GFLAGS),
632
617
GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 10, GFLAGS),
633
618
GATE(HCLK_SPDIF8CH, "hclk_spdif_8ch", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 11, GFLAGS),
634
619
···
637
622
GATE(PCLK_TIMER, "pclk_timer", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 1, GFLAGS),
638
623
GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 2, GFLAGS),
639
624
GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 3, GFLAGS),
640
-
GATE(0, "pclk_ddrupctl0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 14, GFLAGS),
641
-
GATE(0, "pclk_publ0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 15, GFLAGS),
642
-
GATE(0, "pclk_ddrupctl1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 0, GFLAGS),
643
-
GATE(0, "pclk_publ1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 1, GFLAGS),
625
+
GATE(PCLK_DDRUPCTL0, "pclk_ddrupctl0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 14, GFLAGS),
626
+
GATE(PCLK_PUBL0, "pclk_publ0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 15, GFLAGS),
627
+
GATE(PCLK_DDRUPCTL1, "pclk_ddrupctl1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 0, GFLAGS),
628
+
GATE(PCLK_PUBL1, "pclk_publ1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 1, GFLAGS),
644
629
GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 2, GFLAGS),
645
630
GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS),
646
631
GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS),
647
632
GATE(0, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),
648
-
GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 11, GFLAGS),
633
+
GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 11, GFLAGS),
649
634
650
635
/* ddrctrl [DDR Controller PHY clock] gates */
651
-
GATE(0, "nclk_ddrupctl0", "ddrphy", 0, RK3288_CLKGATE_CON(11), 4, GFLAGS),
652
-
GATE(0, "nclk_ddrupctl1", "ddrphy", 0, RK3288_CLKGATE_CON(11), 5, GFLAGS),
636
+
GATE(0, "nclk_ddrupctl0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 4, GFLAGS),
637
+
GATE(0, "nclk_ddrupctl1", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 5, GFLAGS),
653
638
654
639
/* ddrphy gates */
655
-
GATE(0, "sclk_ddrphy0", "ddrphy", 0, RK3288_CLKGATE_CON(4), 12, GFLAGS),
656
-
GATE(0, "sclk_ddrphy1", "ddrphy", 0, RK3288_CLKGATE_CON(4), 13, GFLAGS),
640
+
GATE(0, "sclk_ddrphy0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(4), 12, GFLAGS),
641
+
GATE(0, "sclk_ddrphy1", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(4), 13, GFLAGS),
657
642
658
643
/* aclk_peri gates */
659
-
GATE(0, "aclk_peri_axi_matrix", "aclk_peri", 0, RK3288_CLKGATE_CON(6), 2, GFLAGS),
644
+
GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 2, GFLAGS),
660
645
GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK3288_CLKGATE_CON(6), 3, GFLAGS),
661
-
GATE(0, "aclk_peri_niu", "aclk_peri", 0, RK3288_CLKGATE_CON(7), 11, GFLAGS),
662
-
GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 12, GFLAGS),
646
+
GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 11, GFLAGS),
647
+
GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(8), 12, GFLAGS),
663
648
GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 0, GFLAGS),
664
649
GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 2, GFLAGS),
665
650
666
651
/* hclk_peri gates */
667
-
GATE(0, "hclk_peri_matrix", "hclk_peri", 0, RK3288_CLKGATE_CON(6), 0, GFLAGS),
668
-
GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 4, GFLAGS),
652
+
GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 0, GFLAGS),
653
+
GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 4, GFLAGS),
669
654
GATE(HCLK_USBHOST0, "hclk_host0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 6, GFLAGS),
670
-
GATE(HCLK_USBHOST1, "hclk_host1", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 7, GFLAGS),
655
+
GATE(HCLK_USBHOST1, "hclk_host1", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 7, GFLAGS),
671
656
GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 8, GFLAGS),
672
-
GATE(0, "hclk_usb_peri", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 9, GFLAGS),
673
-
GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 10, GFLAGS),
674
-
GATE(0, "hclk_emem", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 12, GFLAGS),
675
-
GATE(0, "hclk_mem", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 13, GFLAGS),
657
+
GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 9, GFLAGS),
658
+
GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 10, GFLAGS),
659
+
GATE(0, "hclk_emem", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 12, GFLAGS),
660
+
GATE(0, "hclk_mem", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 13, GFLAGS),
676
661
GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 14, GFLAGS),
677
662
GATE(HCLK_NANDC1, "hclk_nandc1", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 15, GFLAGS),
678
663
GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 8, GFLAGS),
···
684
669
GATE(0, "pmu_hclk_otg0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 5, GFLAGS),
685
670
686
671
/* pclk_peri gates */
687
-
GATE(0, "pclk_peri_matrix", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 1, GFLAGS),
672
+
GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 1, GFLAGS),
688
673
GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 4, GFLAGS),
689
674
GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 5, GFLAGS),
690
675
GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 6, GFLAGS),
···
720
705
GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 4, GFLAGS),
721
706
GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 5, GFLAGS),
722
707
GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 6, GFLAGS),
723
-
GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 11, GFLAGS),
724
-
GATE(0, "pclk_alive_niu", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 12, GFLAGS),
708
+
GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 11, GFLAGS),
709
+
GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 12, GFLAGS),
725
710
726
711
/* pclk_pd_pmu gates */
727
-
GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 0, GFLAGS),
728
-
GATE(0, "pclk_intmem1", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 1, GFLAGS),
729
-
GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 2, GFLAGS),
730
-
GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 3, GFLAGS),
712
+
GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 0, GFLAGS),
713
+
GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 1, GFLAGS),
714
+
GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 2, GFLAGS),
715
+
GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 3, GFLAGS),
731
716
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 4, GFLAGS),
732
717
733
718
/* hclk_vio gates */
734
719
GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 1, GFLAGS),
735
720
GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 6, GFLAGS),
736
721
GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 8, GFLAGS),
737
-
GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 9, GFLAGS),
738
-
GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10, GFLAGS),
722
+
GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 9, GFLAGS),
723
+
GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 10, GFLAGS),
739
724
GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS),
740
725
GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 3, GFLAGS),
741
726
GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 1, GFLAGS),
742
-
GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 10, GFLAGS),
727
+
GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 10, GFLAGS),
743
728
GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS),
744
729
GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS),
745
730
GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS),
746
731
GATE(PCLK_LVDS_PHY, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS),
747
-
GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 8, GFLAGS),
732
+
GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 8, GFLAGS),
748
733
GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS),
749
-
GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 11, GFLAGS),
734
+
GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 11, GFLAGS),
750
735
751
736
/* aclk_vio0 gates */
752
737
GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5, GFLAGS),
753
738
GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS),
754
-
GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 11, GFLAGS),
739
+
GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 11, GFLAGS),
755
740
GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS),
756
741
757
742
/* aclk_vio1 gates */
758
743
GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 7, GFLAGS),
759
744
GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS),
760
-
GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 12, GFLAGS),
745
+
GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 12, GFLAGS),
761
746
762
747
/* aclk_rga_pre gates */
763
748
GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 0, GFLAGS),
764
-
GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 13, GFLAGS),
749
+
GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 13, GFLAGS),
765
750
766
751
/*
767
752
* Other ungrouped clocks.
···
776
761
"aclk_peri",
777
762
"hclk_peri",
778
763
};
764
+
765
+
#ifdef CONFIG_PM_SLEEP
766
+
static void __iomem *rk3288_cru_base;
767
+
768
+
/* Some CRU registers will be reset in maskrom when the system
769
+
* wakes up from fastboot.
770
+
* So save them before suspend, restore them after resume.
771
+
*/
772
+
static const int rk3288_saved_cru_reg_ids[] = {
773
+
RK3288_MODE_CON,
774
+
RK3288_CLKSEL_CON(0),
775
+
RK3288_CLKSEL_CON(1),
776
+
RK3288_CLKSEL_CON(10),
777
+
RK3288_CLKSEL_CON(33),
778
+
RK3288_CLKSEL_CON(37),
779
+
};
780
+
781
+
static u32 rk3288_saved_cru_regs[ARRAY_SIZE(rk3288_saved_cru_reg_ids)];
782
+
783
+
static int rk3288_clk_suspend(void)
784
+
{
785
+
int i, reg_id;
786
+
787
+
for (i = 0; i < ARRAY_SIZE(rk3288_saved_cru_reg_ids); i++) {
788
+
reg_id = rk3288_saved_cru_reg_ids[i];
789
+
790
+
rk3288_saved_cru_regs[i] =
791
+
readl_relaxed(rk3288_cru_base + reg_id);
792
+
}
793
+
return 0;
794
+
}
795
+
796
+
static void rk3288_clk_resume(void)
797
+
{
798
+
int i, reg_id;
799
+
800
+
for (i = ARRAY_SIZE(rk3288_saved_cru_reg_ids) - 1; i >= 0; i--) {
801
+
reg_id = rk3288_saved_cru_reg_ids[i];
802
+
803
+
writel_relaxed(rk3288_saved_cru_regs[i] | 0xffff0000,
804
+
rk3288_cru_base + reg_id);
805
+
}
806
+
}
807
+
808
+
static struct syscore_ops rk3288_clk_syscore_ops = {
809
+
.suspend = rk3288_clk_suspend,
810
+
.resume = rk3288_clk_resume,
811
+
};
812
+
813
+
static void rk3288_clk_sleep_init(void __iomem *reg_base)
814
+
{
815
+
rk3288_cru_base = reg_base;
816
+
register_syscore_ops(&rk3288_clk_syscore_ops);
817
+
}
818
+
819
+
#else /* CONFIG_PM_SLEEP */
820
+
static void rk3288_clk_sleep_init(void __iomem *reg_base) {}
821
+
#endif
779
822
780
823
static void __init rk3288_clk_init(struct device_node *np)
781
824
{
···
883
810
ROCKCHIP_SOFTRST_HIWORD_MASK);
884
811
885
812
rockchip_register_restart_notifier(RK3288_GLB_SRST_FST);
813
+
rk3288_clk_sleep_init(reg_base);
886
814
}
887
815
CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);
+10
-10
drivers/clk/rockchip/clk.c
+10
-10
drivers/clk/rockchip/clk.c
···
197
197
list->parent_names, list->num_parents,
198
198
reg_base, list->con_offset, grf_lock_offset,
199
199
list->lock_shift, list->mode_offset,
200
-
list->mode_shift, list->rate_table, &clk_lock);
200
+
list->mode_shift, list->rate_table,
201
+
list->pll_flags, &clk_lock);
201
202
if (IS_ERR(clk)) {
202
203
pr_err("%s: failed to register clock %s\n", __func__,
203
204
list->name);
···
245
244
list->div_flags, &clk_lock);
246
245
break;
247
246
case branch_fraction_divider:
248
-
/* keep all gates untouched for now */
249
-
flags |= CLK_IGNORE_UNUSED;
250
-
251
247
clk = rockchip_clk_register_frac_branch(list->name,
252
248
list->parent_names, list->num_parents,
253
249
reg_base, list->muxdiv_offset, list->div_flags,
···
254
256
case branch_gate:
255
257
flags |= CLK_SET_RATE_PARENT;
256
258
257
-
/* keep all gates untouched for now */
258
-
flags |= CLK_IGNORE_UNUSED;
259
-
260
259
clk = clk_register_gate(NULL, list->name,
261
260
list->parent_names[0], flags,
262
261
reg_base + list->gate_offset,
263
262
list->gate_shift, list->gate_flags, &clk_lock);
264
263
break;
265
264
case branch_composite:
266
-
/* keep all gates untouched for now */
267
-
flags |= CLK_IGNORE_UNUSED;
268
-
269
265
clk = rockchip_clk_register_branch(list->name,
270
266
list->parent_names, list->num_parents,
271
267
reg_base, list->muxdiv_offset, list->mux_shift,
···
268
276
list->div_flags, list->div_table,
269
277
list->gate_offset, list->gate_shift,
270
278
list->gate_flags, flags, &clk_lock);
279
+
break;
280
+
case branch_mmc:
281
+
clk = rockchip_clk_register_mmc(
282
+
list->name,
283
+
list->parent_names, list->num_parents,
284
+
reg_base + list->muxdiv_offset,
285
+
list->div_shift
286
+
);
271
287
break;
272
288
}
273
289
+43
-2
drivers/clk/rockchip/clk.h
+43
-2
drivers/clk/rockchip/clk.h
···
48
48
#define RK3288_GLB_SRST_SND 0x1b4
49
49
#define RK3288_SOFTRST_CON(x) (x * 0x4 + 0x1b8)
50
50
#define RK3288_MISC_CON 0x1e8
51
+
#define RK3288_SDMMC_CON0 0x200
52
+
#define RK3288_SDMMC_CON1 0x204
53
+
#define RK3288_SDIO0_CON0 0x208
54
+
#define RK3288_SDIO0_CON1 0x20c
55
+
#define RK3288_SDIO1_CON0 0x210
56
+
#define RK3288_SDIO1_CON1 0x214
57
+
#define RK3288_EMMC_CON0 0x218
58
+
#define RK3288_EMMC_CON1 0x21c
51
59
52
60
enum rockchip_pll_type {
53
61
pll_rk3066,
···
68
60
.nf = _nf, \
69
61
.no = _no, \
70
62
.bwadj = (_nf >> 1), \
63
+
}
64
+
65
+
#define RK3066_PLL_RATE_BWADJ(_rate, _nr, _nf, _no, _bw) \
66
+
{ \
67
+
.rate = _rate##U, \
68
+
.nr = _nr, \
69
+
.nf = _nf, \
70
+
.no = _no, \
71
+
.bwadj = _bw, \
71
72
}
72
73
73
74
struct rockchip_pll_rate_table {
···
98
81
* @mode_shift: offset inside the mode-register for the mode of this pll.
99
82
* @lock_shift: offset inside the lock register for the lock status.
100
83
* @type: Type of PLL to be registered.
84
+
* @pll_flags: hardware-specific flags
101
85
* @rate_table: Table of usable pll rates
86
+
*
87
+
* Flags:
88
+
* ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
89
+
* rate_table parameters and ajust them if necessary.
102
90
*/
103
91
struct rockchip_pll_clock {
104
92
unsigned int id;
···
116
94
int mode_shift;
117
95
int lock_shift;
118
96
enum rockchip_pll_type type;
97
+
u8 pll_flags;
119
98
struct rockchip_pll_rate_table *rate_table;
120
99
};
121
100
101
+
#define ROCKCHIP_PLL_SYNC_RATE BIT(0)
102
+
122
103
#define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
123
-
_lshift, _rtable) \
104
+
_lshift, _pflags, _rtable) \
124
105
{ \
125
106
.id = _id, \
126
107
.type = _type, \
···
135
110
.mode_offset = _mode, \
136
111
.mode_shift = _mshift, \
137
112
.lock_shift = _lshift, \
113
+
.pll_flags = _pflags, \
138
114
.rate_table = _rtable, \
139
115
}
140
116
···
144
118
void __iomem *base, int con_offset, int grf_lock_offset,
145
119
int lock_shift, int reg_mode, int mode_shift,
146
120
struct rockchip_pll_rate_table *rate_table,
147
-
spinlock_t *lock);
121
+
u8 clk_pll_flags, spinlock_t *lock);
148
122
149
123
struct rockchip_cpuclk_clksel {
150
124
int reg;
···
178
152
const struct rockchip_cpuclk_rate_table *rates,
179
153
int nrates, void __iomem *reg_base, spinlock_t *lock);
180
154
155
+
struct clk *rockchip_clk_register_mmc(const char *name,
156
+
const char **parent_names, u8 num_parents,
157
+
void __iomem *reg, int shift);
158
+
181
159
#define PNAME(x) static const char *x[] __initconst
182
160
183
161
enum rockchip_clk_branch_type {
···
190
160
branch_divider,
191
161
branch_fraction_divider,
192
162
branch_gate,
163
+
branch_mmc,
193
164
};
194
165
195
166
struct rockchip_clk_branch {
···
383
352
.gate_flags = gf, \
384
353
}
385
354
355
+
#define MMC(_id, cname, pname, offset, shift) \
356
+
{ \
357
+
.id = _id, \
358
+
.branch_type = branch_mmc, \
359
+
.name = cname, \
360
+
.parent_names = (const char *[]){ pname }, \
361
+
.num_parents = 1, \
362
+
.muxdiv_offset = offset, \
363
+
.div_shift = shift, \
364
+
}
386
365
387
366
void rockchip_clk_init(struct device_node *np, void __iomem *base,
388
367
unsigned long nr_clks);
+2
drivers/clk/samsung/Makefile
+2
drivers/clk/samsung/Makefile
···
5
5
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
6
6
obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o
7
7
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
8
+
obj-$(CONFIG_SOC_EXYNOS4415) += clk-exynos4415.o
8
9
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
9
10
obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o
10
11
obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
···
13
12
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
14
13
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
15
14
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o
15
+
obj-$(CONFIG_ARCH_EXYNOS7) += clk-exynos7.o
16
16
obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
17
17
obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
18
18
obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
+32
-1
drivers/clk/samsung/clk-exynos-audss.c
+32
-1
drivers/clk/samsung/clk-exynos-audss.c
···
29
29
static struct clk **clk_table;
30
30
static void __iomem *reg_base;
31
31
static struct clk_onecell_data clk_data;
32
+
/*
33
+
* On Exynos5420 this will be a clock which has to be enabled before any
34
+
* access to audss registers. Typically a child of EPLL.
35
+
*
36
+
* On other platforms this will be -ENODEV.
37
+
*/
38
+
static struct clk *epll;
32
39
33
40
#define ASS_CLK_SRC 0x0
34
41
#define ASS_CLK_DIV 0x4
···
105
98
dev_err(&pdev->dev, "failed to map audss registers\n");
106
99
return PTR_ERR(reg_base);
107
100
}
101
+
/* EPLL don't have to be enabled for boards other than Exynos5420 */
102
+
epll = ERR_PTR(-ENODEV);
108
103
109
104
clk_table = devm_kzalloc(&pdev->dev,
110
105
sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
···
124
115
pll_in = devm_clk_get(&pdev->dev, "pll_in");
125
116
if (!IS_ERR(pll_ref))
126
117
mout_audss_p[0] = __clk_get_name(pll_ref);
127
-
if (!IS_ERR(pll_in))
118
+
if (!IS_ERR(pll_in)) {
128
119
mout_audss_p[1] = __clk_get_name(pll_in);
120
+
121
+
if (variant == TYPE_EXYNOS5420) {
122
+
epll = pll_in;
123
+
124
+
ret = clk_prepare_enable(epll);
125
+
if (ret) {
126
+
dev_err(&pdev->dev,
127
+
"failed to prepare the epll clock\n");
128
+
return ret;
129
+
}
130
+
}
131
+
}
129
132
clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
130
133
mout_audss_p, ARRAY_SIZE(mout_audss_p),
131
134
CLK_SET_RATE_NO_REPARENT,
···
224
203
clk_unregister(clk_table[i]);
225
204
}
226
205
206
+
if (!IS_ERR(epll))
207
+
clk_disable_unprepare(epll);
208
+
227
209
return ret;
228
210
}
229
211
···
234
210
{
235
211
int i;
236
212
213
+
#ifdef CONFIG_PM_SLEEP
214
+
unregister_syscore_ops(&exynos_audss_clk_syscore_ops);
215
+
#endif
216
+
237
217
of_clk_del_provider(pdev->dev.of_node);
238
218
239
219
for (i = 0; i < clk_data.clk_num; i++) {
240
220
if (!IS_ERR(clk_table[i]))
241
221
clk_unregister(clk_table[i]);
242
222
}
223
+
224
+
if (!IS_ERR(epll))
225
+
clk_disable_unprepare(epll);
243
226
244
227
return 0;
245
228
}
+1
-1
drivers/clk/samsung/clk-exynos4.c
+1
-1
drivers/clk/samsung/clk-exynos4.c
···
505
505
/* fixed rate clocks generated inside the soc */
506
506
static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
507
507
FRATE(0, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
508
-
FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
508
+
FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", "hdmi", 0, 27000000),
509
509
FRATE(0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
510
510
};
511
511
+1144
drivers/clk/samsung/clk-exynos4415.c
+1144
drivers/clk/samsung/clk-exynos4415.c
···
1
+
/*
2
+
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
3
+
* Author: Chanwoo Choi <cw00.choi@samsung.com>
4
+
*
5
+
* This program is free software; you can redistribute it and/or modify
6
+
* it under the terms of the GNU General Public License version 2 as
7
+
* published by the Free Software Foundation.
8
+
*
9
+
* Common Clock Framework support for Exynos4415 SoC.
10
+
*/
11
+
12
+
#include <linux/clk.h>
13
+
#include <linux/clkdev.h>
14
+
#include <linux/clk-provider.h>
15
+
#include <linux/of.h>
16
+
#include <linux/of_address.h>
17
+
#include <linux/platform_device.h>
18
+
#include <linux/syscore_ops.h>
19
+
20
+
#include <dt-bindings/clock/exynos4415.h>
21
+
22
+
#include "clk.h"
23
+
#include "clk-pll.h"
24
+
25
+
#define SRC_LEFTBUS 0x4200
26
+
#define DIV_LEFTBUS 0x4500
27
+
#define GATE_IP_LEFTBUS 0x4800
28
+
#define GATE_IP_IMAGE 0x4930
29
+
#define SRC_RIGHTBUS 0x8200
30
+
#define DIV_RIGHTBUS 0x8500
31
+
#define GATE_IP_RIGHTBUS 0x8800
32
+
#define GATE_IP_PERIR 0x8960
33
+
#define EPLL_LOCK 0xc010
34
+
#define G3D_PLL_LOCK 0xc020
35
+
#define DISP_PLL_LOCK 0xc030
36
+
#define ISP_PLL_LOCK 0xc040
37
+
#define EPLL_CON0 0xc110
38
+
#define EPLL_CON1 0xc114
39
+
#define EPLL_CON2 0xc118
40
+
#define G3D_PLL_CON0 0xc120
41
+
#define G3D_PLL_CON1 0xc124
42
+
#define G3D_PLL_CON2 0xc128
43
+
#define ISP_PLL_CON0 0xc130
44
+
#define ISP_PLL_CON1 0xc134
45
+
#define ISP_PLL_CON2 0xc138
46
+
#define DISP_PLL_CON0 0xc140
47
+
#define DISP_PLL_CON1 0xc144
48
+
#define DISP_PLL_CON2 0xc148
49
+
#define SRC_TOP0 0xc210
50
+
#define SRC_TOP1 0xc214
51
+
#define SRC_CAM 0xc220
52
+
#define SRC_TV 0xc224
53
+
#define SRC_MFC 0xc228
54
+
#define SRC_G3D 0xc22c
55
+
#define SRC_LCD 0xc234
56
+
#define SRC_ISP 0xc238
57
+
#define SRC_MAUDIO 0xc23c
58
+
#define SRC_FSYS 0xc240
59
+
#define SRC_PERIL0 0xc250
60
+
#define SRC_PERIL1 0xc254
61
+
#define SRC_CAM1 0xc258
62
+
#define SRC_TOP_ISP0 0xc25c
63
+
#define SRC_TOP_ISP1 0xc260
64
+
#define SRC_MASK_TOP 0xc310
65
+
#define SRC_MASK_CAM 0xc320
66
+
#define SRC_MASK_TV 0xc324
67
+
#define SRC_MASK_LCD 0xc334
68
+
#define SRC_MASK_ISP 0xc338
69
+
#define SRC_MASK_MAUDIO 0xc33c
70
+
#define SRC_MASK_FSYS 0xc340
71
+
#define SRC_MASK_PERIL0 0xc350
72
+
#define SRC_MASK_PERIL1 0xc354
73
+
#define DIV_TOP 0xc510
74
+
#define DIV_CAM 0xc520
75
+
#define DIV_TV 0xc524
76
+
#define DIV_MFC 0xc528
77
+
#define DIV_G3D 0xc52c
78
+
#define DIV_LCD 0xc534
79
+
#define DIV_ISP 0xc538
80
+
#define DIV_MAUDIO 0xc53c
81
+
#define DIV_FSYS0 0xc540
82
+
#define DIV_FSYS1 0xc544
83
+
#define DIV_FSYS2 0xc548
84
+
#define DIV_PERIL0 0xc550
85
+
#define DIV_PERIL1 0xc554
86
+
#define DIV_PERIL2 0xc558
87
+
#define DIV_PERIL3 0xc55c
88
+
#define DIV_PERIL4 0xc560
89
+
#define DIV_PERIL5 0xc564
90
+
#define DIV_CAM1 0xc568
91
+
#define DIV_TOP_ISP1 0xc56c
92
+
#define DIV_TOP_ISP0 0xc570
93
+
#define CLKDIV2_RATIO 0xc580
94
+
#define GATE_SCLK_CAM 0xc820
95
+
#define GATE_SCLK_TV 0xc824
96
+
#define GATE_SCLK_MFC 0xc828
97
+
#define GATE_SCLK_G3D 0xc82c
98
+
#define GATE_SCLK_LCD 0xc834
99
+
#define GATE_SCLK_MAUDIO 0xc83c
100
+
#define GATE_SCLK_FSYS 0xc840
101
+
#define GATE_SCLK_PERIL 0xc850
102
+
#define GATE_IP_CAM 0xc920
103
+
#define GATE_IP_TV 0xc924
104
+
#define GATE_IP_MFC 0xc928
105
+
#define GATE_IP_G3D 0xc92c
106
+
#define GATE_IP_LCD 0xc934
107
+
#define GATE_IP_FSYS 0xc940
108
+
#define GATE_IP_PERIL 0xc950
109
+
#define GATE_BLOCK 0xc970
110
+
#define APLL_LOCK 0x14000
111
+
#define APLL_CON0 0x14100
112
+
#define SRC_CPU 0x14200
113
+
#define DIV_CPU0 0x14500
114
+
#define DIV_CPU1 0x14504
115
+
116
+
enum exynos4415_plls {
117
+
apll, epll, g3d_pll, isp_pll, disp_pll,
118
+
nr_plls,
119
+
};
120
+
121
+
static struct samsung_clk_provider *exynos4415_ctx;
122
+
123
+
/*
124
+
* Support for CMU save/restore across system suspends
125
+
*/
126
+
#ifdef CONFIG_PM_SLEEP
127
+
static struct samsung_clk_reg_dump *exynos4415_clk_regs;
128
+
129
+
static unsigned long exynos4415_cmu_clk_regs[] __initdata = {
130
+
SRC_LEFTBUS,
131
+
DIV_LEFTBUS,
132
+
GATE_IP_LEFTBUS,
133
+
GATE_IP_IMAGE,
134
+
SRC_RIGHTBUS,
135
+
DIV_RIGHTBUS,
136
+
GATE_IP_RIGHTBUS,
137
+
GATE_IP_PERIR,
138
+
EPLL_LOCK,
139
+
G3D_PLL_LOCK,
140
+
DISP_PLL_LOCK,
141
+
ISP_PLL_LOCK,
142
+
EPLL_CON0,
143
+
EPLL_CON1,
144
+
EPLL_CON2,
145
+
G3D_PLL_CON0,
146
+
G3D_PLL_CON1,
147
+
G3D_PLL_CON2,
148
+
ISP_PLL_CON0,
149
+
ISP_PLL_CON1,
150
+
ISP_PLL_CON2,
151
+
DISP_PLL_CON0,
152
+
DISP_PLL_CON1,
153
+
DISP_PLL_CON2,
154
+
SRC_TOP0,
155
+
SRC_TOP1,
156
+
SRC_CAM,
157
+
SRC_TV,
158
+
SRC_MFC,
159
+
SRC_G3D,
160
+
SRC_LCD,
161
+
SRC_ISP,
162
+
SRC_MAUDIO,
163
+
SRC_FSYS,
164
+
SRC_PERIL0,
165
+
SRC_PERIL1,
166
+
SRC_CAM1,
167
+
SRC_TOP_ISP0,
168
+
SRC_TOP_ISP1,
169
+
SRC_MASK_TOP,
170
+
SRC_MASK_CAM,
171
+
SRC_MASK_TV,
172
+
SRC_MASK_LCD,
173
+
SRC_MASK_ISP,
174
+
SRC_MASK_MAUDIO,
175
+
SRC_MASK_FSYS,
176
+
SRC_MASK_PERIL0,
177
+
SRC_MASK_PERIL1,
178
+
DIV_TOP,
179
+
DIV_CAM,
180
+
DIV_TV,
181
+
DIV_MFC,
182
+
DIV_G3D,
183
+
DIV_LCD,
184
+
DIV_ISP,
185
+
DIV_MAUDIO,
186
+
DIV_FSYS0,
187
+
DIV_FSYS1,
188
+
DIV_FSYS2,
189
+
DIV_PERIL0,
190
+
DIV_PERIL1,
191
+
DIV_PERIL2,
192
+
DIV_PERIL3,
193
+
DIV_PERIL4,
194
+
DIV_PERIL5,
195
+
DIV_CAM1,
196
+
DIV_TOP_ISP1,
197
+
DIV_TOP_ISP0,
198
+
CLKDIV2_RATIO,
199
+
GATE_SCLK_CAM,
200
+
GATE_SCLK_TV,
201
+
GATE_SCLK_MFC,
202
+
GATE_SCLK_G3D,
203
+
GATE_SCLK_LCD,
204
+
GATE_SCLK_MAUDIO,
205
+
GATE_SCLK_FSYS,
206
+
GATE_SCLK_PERIL,
207
+
GATE_IP_CAM,
208
+
GATE_IP_TV,
209
+
GATE_IP_MFC,
210
+
GATE_IP_G3D,
211
+
GATE_IP_LCD,
212
+
GATE_IP_FSYS,
213
+
GATE_IP_PERIL,
214
+
GATE_BLOCK,
215
+
APLL_LOCK,
216
+
APLL_CON0,
217
+
SRC_CPU,
218
+
DIV_CPU0,
219
+
DIV_CPU1,
220
+
};
221
+
222
+
static int exynos4415_clk_suspend(void)
223
+
{
224
+
samsung_clk_save(exynos4415_ctx->reg_base, exynos4415_clk_regs,
225
+
ARRAY_SIZE(exynos4415_cmu_clk_regs));
226
+
227
+
return 0;
228
+
}
229
+
230
+
static void exynos4415_clk_resume(void)
231
+
{
232
+
samsung_clk_restore(exynos4415_ctx->reg_base, exynos4415_clk_regs,
233
+
ARRAY_SIZE(exynos4415_cmu_clk_regs));
234
+
}
235
+
236
+
static struct syscore_ops exynos4415_clk_syscore_ops = {
237
+
.suspend = exynos4415_clk_suspend,
238
+
.resume = exynos4415_clk_resume,
239
+
};
240
+
241
+
static void exynos4415_clk_sleep_init(void)
242
+
{
243
+
exynos4415_clk_regs =
244
+
samsung_clk_alloc_reg_dump(exynos4415_cmu_clk_regs,
245
+
ARRAY_SIZE(exynos4415_cmu_clk_regs));
246
+
if (!exynos4415_clk_regs) {
247
+
pr_warn("%s: Failed to allocate sleep save data\n", __func__);
248
+
return;
249
+
}
250
+
251
+
register_syscore_ops(&exynos4415_clk_syscore_ops);
252
+
}
253
+
#else
254
+
static inline void exynos4415_clk_sleep_init(void) { }
255
+
#endif
256
+
257
+
/* list of all parent clock list */
258
+
PNAME(mout_g3d_pllsrc_p) = { "fin_pll", };
259
+
260
+
PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
261
+
PNAME(mout_g3d_pll_p) = { "fin_pll", "fout_g3d_pll", };
262
+
PNAME(mout_isp_pll_p) = { "fin_pll", "fout_isp_pll", };
263
+
PNAME(mout_disp_pll_p) = { "fin_pll", "fout_disp_pll", };
264
+
265
+
PNAME(mout_mpll_user_p) = { "fin_pll", "div_mpll_pre", };
266
+
PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
267
+
PNAME(mout_core_p) = { "mout_apll", "mout_mpll_user_c", };
268
+
PNAME(mout_hpm_p) = { "mout_apll", "mout_mpll_user_c", };
269
+
270
+
PNAME(mout_ebi_p) = { "div_aclk_200", "div_aclk_160", };
271
+
PNAME(mout_ebi_1_p) = { "mout_ebi", "mout_g3d_pll", };
272
+
273
+
PNAME(mout_gdl_p) = { "mout_mpll_user_l", };
274
+
PNAME(mout_gdr_p) = { "mout_mpll_user_r", };
275
+
276
+
PNAME(mout_aclk_266_p) = { "mout_mpll_user_t", "mout_g3d_pll", };
277
+
278
+
PNAME(group_epll_g3dpll_p) = { "mout_epll", "mout_g3d_pll" };
279
+
PNAME(group_sclk_p) = { "xxti", "xusbxti",
280
+
"none", "mout_isp_pll",
281
+
"none", "none", "div_mpll_pre",
282
+
"mout_epll", "mout_g3d_pll", };
283
+
PNAME(group_spdif_p) = { "mout_audio0", "mout_audio1",
284
+
"mout_audio2", "spdif_extclk", };
285
+
PNAME(group_sclk_audio2_p) = { "audiocdclk2", "none",
286
+
"none", "mout_isp_pll",
287
+
"mout_disp_pll", "xusbxti",
288
+
"div_mpll_pre", "mout_epll",
289
+
"mout_g3d_pll", };
290
+
PNAME(group_sclk_audio1_p) = { "audiocdclk1", "none",
291
+
"none", "mout_isp_pll",
292
+
"mout_disp_pll", "xusbxti",
293
+
"div_mpll_pre", "mout_epll",
294
+
"mout_g3d_pll", };
295
+
PNAME(group_sclk_audio0_p) = { "audiocdclk0", "none",
296
+
"none", "mout_isp_pll",
297
+
"mout_disp_pll", "xusbxti",
298
+
"div_mpll_pre", "mout_epll",
299
+
"mout_g3d_pll", };
300
+
PNAME(group_fimc_lclk_p) = { "xxti", "xusbxti",
301
+
"none", "mout_isp_pll",
302
+
"none", "mout_disp_pll",
303
+
"mout_mpll_user_t", "mout_epll",
304
+
"mout_g3d_pll", };
305
+
PNAME(group_sclk_fimd0_p) = { "xxti", "xusbxti",
306
+
"m_bitclkhsdiv4_4l", "mout_isp_pll",
307
+
"mout_disp_pll", "sclk_hdmiphy",
308
+
"div_mpll_pre", "mout_epll",
309
+
"mout_g3d_pll", };
310
+
PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy" };
311
+
PNAME(mout_mfc_p) = { "mout_mfc_0", "mout_mfc_1" };
312
+
PNAME(mout_g3d_p) = { "mout_g3d_0", "mout_g3d_1" };
313
+
PNAME(mout_jpeg_p) = { "mout_jpeg_0", "mout_jpeg_1" };
314
+
PNAME(mout_jpeg1_p) = { "mout_epll", "mout_g3d_pll" };
315
+
PNAME(group_aclk_isp0_300_p) = { "mout_isp_pll", "div_mpll_pre" };
316
+
PNAME(group_aclk_isp0_400_user_p) = { "fin_pll", "div_aclk_400_mcuisp" };
317
+
PNAME(group_aclk_isp0_300_user_p) = { "fin_pll", "mout_aclk_isp0_300" };
318
+
PNAME(group_aclk_isp1_300_user_p) = { "fin_pll", "mout_aclk_isp1_300" };
319
+
PNAME(group_mout_mpll_user_t_p) = { "mout_mpll_user_t" };
320
+
321
+
static struct samsung_fixed_factor_clock exynos4415_fixed_factor_clks[] __initdata = {
322
+
/* HACK: fin_pll hardcoded to xusbxti until detection is implemented. */
323
+
FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),
324
+
};
325
+
326
+
static struct samsung_fixed_rate_clock exynos4415_fixed_rate_clks[] __initdata = {
327
+
FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
328
+
};
329
+
330
+
static struct samsung_mux_clock exynos4415_mux_clks[] __initdata = {
331
+
/*
332
+
* NOTE: Following table is sorted by register address in ascending
333
+
* order and then bitfield shift in descending order, as it is done
334
+
* in the User's Manual. When adding new entries, please make sure
335
+
* that the order is preserved, to avoid merge conflicts and make
336
+
* further work with defined data easier.
337
+
*/
338
+
339
+
/* SRC_LEFTBUS */
340
+
MUX(CLK_MOUT_MPLL_USER_L, "mout_mpll_user_l", mout_mpll_user_p,
341
+
SRC_LEFTBUS, 4, 1),
342
+
MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1),
343
+
344
+
/* SRC_RIGHTBUS */
345
+
MUX(CLK_MOUT_MPLL_USER_R, "mout_mpll_user_r", mout_mpll_user_p,
346
+
SRC_RIGHTBUS, 4, 1),
347
+
MUX(CLK_MOUT_GDR, "mout_gdr", mout_gdr_p, SRC_RIGHTBUS, 0, 1),
348
+
349
+
/* SRC_TOP0 */
350
+
MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1),
351
+
MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_mout_mpll_user_t_p,
352
+
SRC_TOP0, 24, 1),
353
+
MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_mout_mpll_user_t_p,
354
+
SRC_TOP0, 20, 1),
355
+
MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_mout_mpll_user_t_p,
356
+
SRC_TOP0, 16, 1),
357
+
MUX(CLK_MOUT_ACLK_266, "mout_aclk_266", mout_aclk_266_p,
358
+
SRC_TOP0, 12, 1),
359
+
MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
360
+
SRC_TOP0, 8, 1),
361
+
MUX(CLK_MOUT_EPLL, "mout_epll", mout_epll_p, SRC_TOP0, 4, 1),
362
+
MUX(CLK_MOUT_EBI_1, "mout_ebi_1", mout_ebi_1_p, SRC_TOP0, 0, 1),
363
+
364
+
/* SRC_TOP1 */
365
+
MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p,
366
+
SRC_TOP1, 28, 1),
367
+
MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p,
368
+
SRC_TOP1, 16, 1),
369
+
MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p,
370
+
SRC_TOP1, 12, 1),
371
+
MUX(CLK_MOUT_ACLK_400_MCUISP, "mout_aclk_400_mcuisp",
372
+
group_mout_mpll_user_t_p, SRC_TOP1, 8, 1),
373
+
MUX(CLK_MOUT_G3D_PLLSRC, "mout_g3d_pllsrc", mout_g3d_pllsrc_p,
374
+
SRC_TOP1, 0, 1),
375
+
376
+
/* SRC_CAM */
377
+
MUX(CLK_MOUT_CSIS1, "mout_csis1", group_fimc_lclk_p, SRC_CAM, 28, 4),
378
+
MUX(CLK_MOUT_CSIS0, "mout_csis0", group_fimc_lclk_p, SRC_CAM, 24, 4),
379
+
MUX(CLK_MOUT_CAM1, "mout_cam1", group_fimc_lclk_p, SRC_CAM, 20, 4),
380
+
MUX(CLK_MOUT_FIMC3_LCLK, "mout_fimc3_lclk", group_fimc_lclk_p, SRC_CAM,
381
+
12, 4),
382
+
MUX(CLK_MOUT_FIMC2_LCLK, "mout_fimc2_lclk", group_fimc_lclk_p, SRC_CAM,
383
+
8, 4),
384
+
MUX(CLK_MOUT_FIMC1_LCLK, "mout_fimc1_lclk", group_fimc_lclk_p, SRC_CAM,
385
+
4, 4),
386
+
MUX(CLK_MOUT_FIMC0_LCLK, "mout_fimc0_lclk", group_fimc_lclk_p, SRC_CAM,
387
+
0, 4),
388
+
389
+
/* SRC_TV */
390
+
MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
391
+
392
+
/* SRC_MFC */
393
+
MUX(CLK_MOUT_MFC, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
394
+
MUX(CLK_MOUT_MFC_1, "mout_mfc_1", group_epll_g3dpll_p, SRC_MFC, 4, 1),
395
+
MUX(CLK_MOUT_MFC_0, "mout_mfc_0", group_mout_mpll_user_t_p, SRC_MFC, 0,
396
+
1),
397
+
398
+
/* SRC_G3D */
399
+
MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
400
+
MUX(CLK_MOUT_G3D_1, "mout_g3d_1", group_epll_g3dpll_p, SRC_G3D, 4, 1),
401
+
MUX(CLK_MOUT_G3D_0, "mout_g3d_0", group_mout_mpll_user_t_p, SRC_G3D, 0,
402
+
1),
403
+
404
+
/* SRC_LCD */
405
+
MUX(CLK_MOUT_MIPI0, "mout_mipi0", group_fimc_lclk_p, SRC_LCD, 12, 4),
406
+
MUX(CLK_MOUT_FIMD0, "mout_fimd0", group_sclk_fimd0_p, SRC_LCD, 0, 4),
407
+
408
+
/* SRC_ISP */
409
+
MUX(CLK_MOUT_TSADC_ISP, "mout_tsadc_isp", group_fimc_lclk_p, SRC_ISP,
410
+
16, 4),
411
+
MUX(CLK_MOUT_UART_ISP, "mout_uart_isp", group_fimc_lclk_p, SRC_ISP,
412
+
12, 4),
413
+
MUX(CLK_MOUT_SPI1_ISP, "mout_spi1_isp", group_fimc_lclk_p, SRC_ISP,
414
+
8, 4),
415
+
MUX(CLK_MOUT_SPI0_ISP, "mout_spi0_isp", group_fimc_lclk_p, SRC_ISP,
416
+
4, 4),
417
+
MUX(CLK_MOUT_PWM_ISP, "mout_pwm_isp", group_fimc_lclk_p, SRC_ISP,
418
+
0, 4),
419
+
420
+
/* SRC_MAUDIO */
421
+
MUX(CLK_MOUT_AUDIO0, "mout_audio0", group_sclk_audio0_p, SRC_MAUDIO,
422
+
0, 4),
423
+
424
+
/* SRC_FSYS */
425
+
MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
426
+
MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4),
427
+
MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),
428
+
MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
429
+
430
+
/* SRC_PERIL0 */
431
+
MUX(CLK_MOUT_UART3, "mout_uart3", group_sclk_p, SRC_PERIL0, 12, 4),
432
+
MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
433
+
MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
434
+
MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
435
+
436
+
/* SRC_PERIL1 */
437
+
MUX(CLK_MOUT_SPI2, "mout_spi2", group_sclk_p, SRC_PERIL1, 24, 4),
438
+
MUX(CLK_MOUT_SPI1, "mout_spi1", group_sclk_p, SRC_PERIL1, 20, 4),
439
+
MUX(CLK_MOUT_SPI0, "mout_spi0", group_sclk_p, SRC_PERIL1, 16, 4),
440
+
MUX(CLK_MOUT_SPDIF, "mout_spdif", group_spdif_p, SRC_PERIL1, 8, 4),
441
+
MUX(CLK_MOUT_AUDIO2, "mout_audio2", group_sclk_audio2_p, SRC_PERIL1,
442
+
4, 4),
443
+
MUX(CLK_MOUT_AUDIO1, "mout_audio1", group_sclk_audio1_p, SRC_PERIL1,
444
+
0, 4),
445
+
446
+
/* SRC_CPU */
447
+
MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p,
448
+
SRC_CPU, 24, 1),
449
+
MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),
450
+
MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1, 0,
451
+
CLK_MUX_READ_ONLY),
452
+
MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
453
+
CLK_SET_RATE_PARENT, 0),
454
+
455
+
/* SRC_CAM1 */
456
+
MUX(CLK_MOUT_PXLASYNC_CSIS1_FIMC, "mout_pxlasync_csis1",
457
+
group_fimc_lclk_p, SRC_CAM1, 20, 1),
458
+
MUX(CLK_MOUT_PXLASYNC_CSIS0_FIMC, "mout_pxlasync_csis0",
459
+
group_fimc_lclk_p, SRC_CAM1, 16, 1),
460
+
MUX(CLK_MOUT_JPEG, "mout_jpeg", mout_jpeg_p, SRC_CAM1, 8, 1),
461
+
MUX(CLK_MOUT_JPEG1, "mout_jpeg_1", mout_jpeg1_p, SRC_CAM1, 4, 1),
462
+
MUX(CLK_MOUT_JPEG0, "mout_jpeg_0", group_mout_mpll_user_t_p, SRC_CAM1,
463
+
0, 1),
464
+
465
+
/* SRC_TOP_ISP0 */
466
+
MUX(CLK_MOUT_ACLK_ISP0_300, "mout_aclk_isp0_300",
467
+
group_aclk_isp0_300_p, SRC_TOP_ISP0, 8, 1),
468
+
MUX(CLK_MOUT_ACLK_ISP0_400, "mout_aclk_isp0_400_user",
469
+
group_aclk_isp0_400_user_p, SRC_TOP_ISP0, 4, 1),
470
+
MUX(CLK_MOUT_ACLK_ISP0_300_USER, "mout_aclk_isp0_300_user",
471
+
group_aclk_isp0_300_user_p, SRC_TOP_ISP0, 0, 1),
472
+
473
+
/* SRC_TOP_ISP1 */
474
+
MUX(CLK_MOUT_ACLK_ISP1_300, "mout_aclk_isp1_300",
475
+
group_aclk_isp0_300_p, SRC_TOP_ISP1, 4, 1),
476
+
MUX(CLK_MOUT_ACLK_ISP1_300_USER, "mout_aclk_isp1_300_user",
477
+
group_aclk_isp1_300_user_p, SRC_TOP_ISP1, 0, 1),
478
+
};
479
+
480
+
static struct samsung_div_clock exynos4415_div_clks[] __initdata = {
481
+
/*
482
+
* NOTE: Following table is sorted by register address in ascending
483
+
* order and then bitfield shift in descending order, as it is done
484
+
* in the User's Manual. When adding new entries, please make sure
485
+
* that the order is preserved, to avoid merge conflicts and make
486
+
* further work with defined data easier.
487
+
*/
488
+
489
+
/* DIV_LEFTBUS */
490
+
DIV(CLK_DIV_GPL, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
491
+
DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 4),
492
+
493
+
/* DIV_RIGHTBUS */
494
+
DIV(CLK_DIV_GPR, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
495
+
DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 4),
496
+
497
+
/* DIV_TOP */
498
+
DIV(CLK_DIV_ACLK_400_MCUISP, "div_aclk_400_mcuisp",
499
+
"mout_aclk_400_mcuisp", DIV_TOP, 24, 3),
500
+
DIV(CLK_DIV_EBI, "div_ebi", "mout_ebi_1", DIV_TOP, 16, 3),
501
+
DIV(CLK_DIV_ACLK_200, "div_aclk_200", "mout_aclk_200", DIV_TOP, 12, 3),
502
+
DIV(CLK_DIV_ACLK_160, "div_aclk_160", "mout_aclk_160", DIV_TOP, 8, 3),
503
+
DIV(CLK_DIV_ACLK_100, "div_aclk_100", "mout_aclk_100", DIV_TOP, 4, 4),
504
+
DIV(CLK_DIV_ACLK_266, "div_aclk_266", "mout_aclk_266", DIV_TOP, 0, 3),
505
+
506
+
/* DIV_CAM */
507
+
DIV(CLK_DIV_CSIS1, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
508
+
DIV(CLK_DIV_CSIS0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
509
+
DIV(CLK_DIV_CAM1, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
510
+
DIV(CLK_DIV_FIMC3_LCLK, "div_fimc3_lclk", "mout_fimc3_lclk", DIV_CAM,
511
+
12, 4),
512
+
DIV(CLK_DIV_FIMC2_LCLK, "div_fimc2_lclk", "mout_fimc2_lclk", DIV_CAM,
513
+
8, 4),
514
+
DIV(CLK_DIV_FIMC1_LCLK, "div_fimc1_lclk", "mout_fimc1_lclk", DIV_CAM,
515
+
4, 4),
516
+
DIV(CLK_DIV_FIMC0_LCLK, "div_fimc0_lclk", "mout_fimc0_lclk", DIV_CAM,
517
+
0, 4),
518
+
519
+
/* DIV_TV */
520
+
DIV(CLK_DIV_TV_BLK, "div_tv_blk", "mout_g3d_pll", DIV_TV, 0, 4),
521
+
522
+
/* DIV_MFC */
523
+
DIV(CLK_DIV_MFC, "div_mfc", "mout_mfc", DIV_MFC, 0, 4),
524
+
525
+
/* DIV_G3D */
526
+
DIV(CLK_DIV_G3D, "div_g3d", "mout_g3d", DIV_G3D, 0, 4),
527
+
528
+
/* DIV_LCD */
529
+
DIV_F(CLK_DIV_MIPI0_PRE, "div_mipi0_pre", "div_mipi0", DIV_LCD, 20, 4,
530
+
CLK_SET_RATE_PARENT, 0),
531
+
DIV(CLK_DIV_MIPI0, "div_mipi0", "mout_mipi0", DIV_LCD, 16, 4),
532
+
DIV(CLK_DIV_FIMD0, "div_fimd0", "mout_fimd0", DIV_LCD, 0, 4),
533
+
534
+
/* DIV_ISP */
535
+
DIV(CLK_DIV_UART_ISP, "div_uart_isp", "mout_uart_isp", DIV_ISP, 28, 4),
536
+
DIV_F(CLK_DIV_SPI1_ISP_PRE, "div_spi1_isp_pre", "div_spi1_isp",
537
+
DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),
538
+
DIV(CLK_DIV_SPI1_ISP, "div_spi1_isp", "mout_spi1_isp", DIV_ISP, 16, 4),
539
+
DIV_F(CLK_DIV_SPI0_ISP_PRE, "div_spi0_isp_pre", "div_spi0_isp",
540
+
DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
541
+
DIV(CLK_DIV_SPI0_ISP, "div_spi0_isp", "mout_spi0_isp", DIV_ISP, 4, 4),
542
+
DIV(CLK_DIV_PWM_ISP, "div_pwm_isp", "mout_pwm_isp", DIV_ISP, 0, 4),
543
+
544
+
/* DIV_MAUDIO */
545
+
DIV(CLK_DIV_PCM0, "div_pcm0", "div_audio0", DIV_MAUDIO, 4, 8),
546
+
DIV(CLK_DIV_AUDIO0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
547
+
548
+
/* DIV_FSYS0 */
549
+
DIV_F(CLK_DIV_TSADC_PRE, "div_tsadc_pre", "div_tsadc", DIV_FSYS0, 8, 8,
550
+
CLK_SET_RATE_PARENT, 0),
551
+
DIV(CLK_DIV_TSADC, "div_tsadc", "mout_tsadc", DIV_FSYS0, 0, 4),
552
+
553
+
/* DIV_FSYS1 */
554
+
DIV_F(CLK_DIV_MMC1_PRE, "div_mmc1_pre", "div_mmc1", DIV_FSYS1, 24, 8,
555
+
CLK_SET_RATE_PARENT, 0),
556
+
DIV(CLK_DIV_MMC1, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
557
+
DIV_F(CLK_DIV_MMC0_PRE, "div_mmc0_pre", "div_mmc0", DIV_FSYS1, 8, 8,
558
+
CLK_SET_RATE_PARENT, 0),
559
+
DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
560
+
561
+
/* DIV_FSYS2 */
562
+
DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8,
563
+
CLK_SET_RATE_PARENT, 0),
564
+
DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4,
565
+
CLK_SET_RATE_PARENT, 0),
566
+
567
+
/* DIV_PERIL0 */
568
+
DIV(CLK_DIV_UART3, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
569
+
DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
570
+
DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
571
+
DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
572
+
573
+
/* DIV_PERIL1 */
574
+
DIV_F(CLK_DIV_SPI1_PRE, "div_spi1_pre", "div_spi1", DIV_PERIL1, 24, 8,
575
+
CLK_SET_RATE_PARENT, 0),
576
+
DIV(CLK_DIV_SPI1, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
577
+
DIV_F(CLK_DIV_SPI0_PRE, "div_spi0_pre", "div_spi0", DIV_PERIL1, 8, 8,
578
+
CLK_SET_RATE_PARENT, 0),
579
+
DIV(CLK_DIV_SPI0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
580
+
581
+
/* DIV_PERIL2 */
582
+
DIV_F(CLK_DIV_SPI2_PRE, "div_spi2_pre", "div_spi2", DIV_PERIL2, 8, 8,
583
+
CLK_SET_RATE_PARENT, 0),
584
+
DIV(CLK_DIV_SPI2, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
585
+
586
+
/* DIV_PERIL4 */
587
+
DIV(CLK_DIV_PCM2, "div_pcm2", "div_audio2", DIV_PERIL4, 20, 8),
588
+
DIV(CLK_DIV_AUDIO2, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
589
+
DIV(CLK_DIV_PCM1, "div_pcm1", "div_audio1", DIV_PERIL4, 20, 8),
590
+
DIV(CLK_DIV_AUDIO1, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
591
+
592
+
/* DIV_PERIL5 */
593
+
DIV(CLK_DIV_I2S1, "div_i2s1", "div_audio1", DIV_PERIL5, 0, 6),
594
+
595
+
/* DIV_CAM1 */
596
+
DIV(CLK_DIV_PXLASYNC_CSIS1_FIMC, "div_pxlasync_csis1_fimc",
597
+
"mout_pxlasync_csis1", DIV_CAM1, 24, 4),
598
+
DIV(CLK_DIV_PXLASYNC_CSIS0_FIMC, "div_pxlasync_csis0_fimc",
599
+
"mout_pxlasync_csis0", DIV_CAM1, 20, 4),
600
+
DIV(CLK_DIV_JPEG, "div_jpeg", "mout_jpeg", DIV_CAM1, 0, 4),
601
+
602
+
/* DIV_CPU0 */
603
+
DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
604
+
DIV_F(CLK_DIV_APLL, "div_apll", "mout_apll", DIV_CPU0, 24, 3,
605
+
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
606
+
DIV(CLK_DIV_PCLK_DBG, "div_pclk_dbg", "div_core2", DIV_CPU0, 20, 3),
607
+
DIV(CLK_DIV_ATB, "div_atb", "div_core2", DIV_CPU0, 16, 3),
608
+
DIV(CLK_DIV_PERIPH, "div_periph", "div_core2", DIV_CPU0, 12, 3),
609
+
DIV(CLK_DIV_COREM1, "div_corem1", "div_core2", DIV_CPU0, 8, 3),
610
+
DIV(CLK_DIV_COREM0, "div_corem0", "div_core2", DIV_CPU0, 4, 3),
611
+
DIV_F(CLK_DIV_CORE, "div_core", "mout_core", DIV_CPU0, 0, 3,
612
+
CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
613
+
614
+
/* DIV_CPU1 */
615
+
DIV(CLK_DIV_HPM, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
616
+
DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
617
+
};
618
+
619
+
static struct samsung_gate_clock exynos4415_gate_clks[] __initdata = {
620
+
/*
621
+
* NOTE: Following table is sorted by register address in ascending
622
+
* order and then bitfield shift in descending order, as it is done
623
+
* in the User's Manual. When adding new entries, please make sure
624
+
* that the order is preserved, to avoid merge conflicts and make
625
+
* further work with defined data easier.
626
+
*/
627
+
628
+
/* GATE_IP_LEFTBUS */
629
+
GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6,
630
+
CLK_IGNORE_UNUSED, 0),
631
+
GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4,
632
+
CLK_IGNORE_UNUSED, 0),
633
+
GATE(CLK_ASYNC_TVX, "async_tvx", "div_aclk_100", GATE_IP_LEFTBUS, 3,
634
+
CLK_IGNORE_UNUSED, 0),
635
+
GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,
636
+
CLK_IGNORE_UNUSED, 0),
637
+
GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0,
638
+
CLK_IGNORE_UNUSED, 0),
639
+
640
+
/* GATE_IP_IMAGE */
641
+
GATE(CLK_PPMUIMAGE, "ppmuimage", "div_aclk_100", GATE_IP_IMAGE,
642
+
9, 0, 0),
643
+
GATE(CLK_QEMDMA2, "qe_mdma2", "div_aclk_100", GATE_IP_IMAGE,
644
+
8, 0, 0),
645
+
GATE(CLK_QEROTATOR, "qe_rotator", "div_aclk_100", GATE_IP_IMAGE,
646
+
7, 0, 0),
647
+
GATE(CLK_SMMUMDMA2, "smmu_mdam2", "div_aclk_100", GATE_IP_IMAGE,
648
+
5, 0, 0),
649
+
GATE(CLK_SMMUROTATOR, "smmu_rotator", "div_aclk_100", GATE_IP_IMAGE,
650
+
4, 0, 0),
651
+
GATE(CLK_MDMA2, "mdma2", "div_aclk_100", GATE_IP_IMAGE, 2, 0, 0),
652
+
GATE(CLK_ROTATOR, "rotator", "div_aclk_100", GATE_IP_IMAGE, 1, 0, 0),
653
+
654
+
/* GATE_IP_RIGHTBUS */
655
+
GATE(CLK_ASYNC_ISPMX, "async_ispmx", "div_aclk_100",
656
+
GATE_IP_RIGHTBUS, 9, CLK_IGNORE_UNUSED, 0),
657
+
GATE(CLK_ASYNC_MAUDIOX, "async_maudiox", "div_aclk_100",
658
+
GATE_IP_RIGHTBUS, 7, CLK_IGNORE_UNUSED, 0),
659
+
GATE(CLK_ASYNC_MFCR, "async_mfcr", "div_aclk_100",
660
+
GATE_IP_RIGHTBUS, 6, CLK_IGNORE_UNUSED, 0),
661
+
GATE(CLK_ASYNC_FSYSD, "async_fsysd", "div_aclk_100",
662
+
GATE_IP_RIGHTBUS, 5, CLK_IGNORE_UNUSED, 0),
663
+
GATE(CLK_ASYNC_LCD0X, "async_lcd0x", "div_aclk_100",
664
+
GATE_IP_RIGHTBUS, 3, CLK_IGNORE_UNUSED, 0),
665
+
GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100",
666
+
GATE_IP_RIGHTBUS, 2, CLK_IGNORE_UNUSED, 0),
667
+
GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100",
668
+
GATE_IP_RIGHTBUS, 1, CLK_IGNORE_UNUSED, 0),
669
+
GATE(CLK_GPIO_RIGHT, "gpio_right", "div_aclk_100",
670
+
GATE_IP_RIGHTBUS, 0, CLK_IGNORE_UNUSED, 0),
671
+
672
+
/* GATE_IP_PERIR */
673
+
GATE(CLK_ANTIRBK_APBIF, "antirbk_apbif", "div_aclk_100",
674
+
GATE_IP_PERIR, 24, CLK_IGNORE_UNUSED, 0),
675
+
GATE(CLK_EFUSE_WRITER_APBIF, "efuse_writer_apbif", "div_aclk_100",
676
+
GATE_IP_PERIR, 23, CLK_IGNORE_UNUSED, 0),
677
+
GATE(CLK_MONOCNT, "monocnt", "div_aclk_100", GATE_IP_PERIR, 22,
678
+
CLK_IGNORE_UNUSED, 0),
679
+
GATE(CLK_TZPC6, "tzpc6", "div_aclk_100", GATE_IP_PERIR, 21,
680
+
CLK_IGNORE_UNUSED, 0),
681
+
GATE(CLK_PROVISIONKEY1, "provisionkey1", "div_aclk_100",
682
+
GATE_IP_PERIR, 20, CLK_IGNORE_UNUSED, 0),
683
+
GATE(CLK_PROVISIONKEY0, "provisionkey0", "div_aclk_100",
684
+
GATE_IP_PERIR, 19, CLK_IGNORE_UNUSED, 0),
685
+
GATE(CLK_CMU_ISPPART, "cmu_isppart", "div_aclk_100", GATE_IP_PERIR, 18,
686
+
CLK_IGNORE_UNUSED, 0),
687
+
GATE(CLK_TMU_APBIF, "tmu_apbif", "div_aclk_100",
688
+
GATE_IP_PERIR, 17, 0, 0),
689
+
GATE(CLK_KEYIF, "keyif", "div_aclk_100", GATE_IP_PERIR, 16, 0, 0),
690
+
GATE(CLK_RTC, "rtc", "div_aclk_100", GATE_IP_PERIR, 15, 0, 0),
691
+
GATE(CLK_WDT, "wdt", "div_aclk_100", GATE_IP_PERIR, 14, 0, 0),
692
+
GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0),
693
+
GATE(CLK_SECKEY, "seckey", "div_aclk_100", GATE_IP_PERIR, 12,
694
+
CLK_IGNORE_UNUSED, 0),
695
+
GATE(CLK_HDMI_CEC, "hdmi_cec", "div_aclk_100", GATE_IP_PERIR, 11,
696
+
CLK_IGNORE_UNUSED, 0),
697
+
GATE(CLK_TZPC5, "tzpc5", "div_aclk_100", GATE_IP_PERIR, 10,
698
+
CLK_IGNORE_UNUSED, 0),
699
+
GATE(CLK_TZPC4, "tzpc4", "div_aclk_100", GATE_IP_PERIR, 9,
700
+
CLK_IGNORE_UNUSED, 0),
701
+
GATE(CLK_TZPC3, "tzpc3", "div_aclk_100", GATE_IP_PERIR, 8,
702
+
CLK_IGNORE_UNUSED, 0),
703
+
GATE(CLK_TZPC2, "tzpc2", "div_aclk_100", GATE_IP_PERIR, 7,
704
+
CLK_IGNORE_UNUSED, 0),
705
+
GATE(CLK_TZPC1, "tzpc1", "div_aclk_100", GATE_IP_PERIR, 6,
706
+
CLK_IGNORE_UNUSED, 0),
707
+
GATE(CLK_TZPC0, "tzpc0", "div_aclk_100", GATE_IP_PERIR, 5,
708
+
CLK_IGNORE_UNUSED, 0),
709
+
GATE(CLK_CMU_COREPART, "cmu_corepart", "div_aclk_100", GATE_IP_PERIR, 4,
710
+
CLK_IGNORE_UNUSED, 0),
711
+
GATE(CLK_CMU_TOPPART, "cmu_toppart", "div_aclk_100", GATE_IP_PERIR, 3,
712
+
CLK_IGNORE_UNUSED, 0),
713
+
GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2,
714
+
CLK_IGNORE_UNUSED, 0),
715
+
GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1,
716
+
CLK_IGNORE_UNUSED, 0),
717
+
GATE(CLK_CHIP_ID, "chip_id", "div_aclk_100", GATE_IP_PERIR, 0,
718
+
CLK_IGNORE_UNUSED, 0),
719
+
720
+
/* GATE_SCLK_CAM - non-completed */
721
+
GATE(CLK_SCLK_PXLAYSNC_CSIS1_FIMC, "sclk_pxlasync_csis1_fimc",
722
+
"div_pxlasync_csis1_fimc", GATE_SCLK_CAM, 11,
723
+
CLK_SET_RATE_PARENT, 0),
724
+
GATE(CLK_SCLK_PXLAYSNC_CSIS0_FIMC, "sclk_pxlasync_csis0_fimc",
725
+
"div_pxlasync_csis0_fimc", GATE_SCLK_CAM,
726
+
10, CLK_SET_RATE_PARENT, 0),
727
+
GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_jpeg",
728
+
GATE_SCLK_CAM, 8, CLK_SET_RATE_PARENT, 0),
729
+
GATE(CLK_SCLK_CSIS1, "sclk_csis1", "div_csis1",
730
+
GATE_SCLK_CAM, 7, CLK_SET_RATE_PARENT, 0),
731
+
GATE(CLK_SCLK_CSIS0, "sclk_csis0", "div_csis0",
732
+
GATE_SCLK_CAM, 6, CLK_SET_RATE_PARENT, 0),
733
+
GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
734
+
GATE_SCLK_CAM, 5, CLK_SET_RATE_PARENT, 0),
735
+
GATE(CLK_SCLK_FIMC3_LCLK, "sclk_fimc3_lclk", "div_fimc3_lclk",
736
+
GATE_SCLK_CAM, 3, CLK_SET_RATE_PARENT, 0),
737
+
GATE(CLK_SCLK_FIMC2_LCLK, "sclk_fimc2_lclk", "div_fimc2_lclk",
738
+
GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),
739
+
GATE(CLK_SCLK_FIMC1_LCLK, "sclk_fimc1_lclk", "div_fimc1_lclk",
740
+
GATE_SCLK_CAM, 1, CLK_SET_RATE_PARENT, 0),
741
+
GATE(CLK_SCLK_FIMC0_LCLK, "sclk_fimc0_lclk", "div_fimc0_lclk",
742
+
GATE_SCLK_CAM, 0, CLK_SET_RATE_PARENT, 0),
743
+
744
+
/* GATE_SCLK_TV */
745
+
GATE(CLK_SCLK_PIXEL, "sclk_pixel", "div_tv_blk",
746
+
GATE_SCLK_TV, 3, CLK_SET_RATE_PARENT, 0),
747
+
GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
748
+
GATE_SCLK_TV, 2, CLK_SET_RATE_PARENT, 0),
749
+
GATE(CLK_SCLK_MIXER, "sclk_mixer", "div_tv_blk",
750
+
GATE_SCLK_TV, 0, CLK_SET_RATE_PARENT, 0),
751
+
752
+
/* GATE_SCLK_MFC */
753
+
GATE(CLK_SCLK_MFC, "sclk_mfc", "div_mfc",
754
+
GATE_SCLK_MFC, 0, CLK_SET_RATE_PARENT, 0),
755
+
756
+
/* GATE_SCLK_G3D */
757
+
GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d",
758
+
GATE_SCLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
759
+
760
+
/* GATE_SCLK_LCD */
761
+
GATE(CLK_SCLK_MIPIDPHY4L, "sclk_mipidphy4l", "div_mipi0",
762
+
GATE_SCLK_LCD, 4, CLK_SET_RATE_PARENT, 0),
763
+
GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi0_pre",
764
+
GATE_SCLK_LCD, 3, CLK_SET_RATE_PARENT, 0),
765
+
GATE(CLK_SCLK_MDNIE0, "sclk_mdnie0", "div_fimd0",
766
+
GATE_SCLK_LCD, 1, CLK_SET_RATE_PARENT, 0),
767
+
GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0",
768
+
GATE_SCLK_LCD, 0, CLK_SET_RATE_PARENT, 0),
769
+
770
+
/* GATE_SCLK_MAUDIO */
771
+
GATE(CLK_SCLK_PCM0, "sclk_pcm0", "div_pcm0",
772
+
GATE_SCLK_MAUDIO, 1, CLK_SET_RATE_PARENT, 0),
773
+
GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0",
774
+
GATE_SCLK_MAUDIO, 0, CLK_SET_RATE_PARENT, 0),
775
+
776
+
/* GATE_SCLK_FSYS */
777
+
GATE(CLK_SCLK_TSADC, "sclk_tsadc", "div_tsadc_pre",
778
+
GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
779
+
GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
780
+
GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
781
+
GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre",
782
+
GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
783
+
GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
784
+
GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
785
+
GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
786
+
GATE_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
787
+
788
+
/* GATE_SCLK_PERIL */
789
+
GATE(CLK_SCLK_I2S, "sclk_i2s1", "div_i2s1",
790
+
GATE_SCLK_PERIL, 18, CLK_SET_RATE_PARENT, 0),
791
+
GATE(CLK_SCLK_PCM2, "sclk_pcm2", "div_pcm2",
792
+
GATE_SCLK_PERIL, 16, CLK_SET_RATE_PARENT, 0),
793
+
GATE(CLK_SCLK_PCM1, "sclk_pcm1", "div_pcm1",
794
+
GATE_SCLK_PERIL, 15, CLK_SET_RATE_PARENT, 0),
795
+
GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2",
796
+
GATE_SCLK_PERIL, 14, CLK_SET_RATE_PARENT, 0),
797
+
GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1",
798
+
GATE_SCLK_PERIL, 13, CLK_SET_RATE_PARENT, 0),
799
+
GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
800
+
GATE_SCLK_PERIL, 10, CLK_SET_RATE_PARENT, 0),
801
+
GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi2_pre",
802
+
GATE_SCLK_PERIL, 8, CLK_SET_RATE_PARENT, 0),
803
+
GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi1_pre",
804
+
GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
805
+
GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
806
+
GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
807
+
GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
808
+
GATE_SCLK_PERIL, 3, CLK_SET_RATE_PARENT, 0),
809
+
GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
810
+
GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
811
+
GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
812
+
GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
813
+
GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
814
+
GATE_SCLK_PERIL, 0, CLK_SET_RATE_PARENT, 0),
815
+
816
+
/* GATE_IP_CAM */
817
+
GATE(CLK_SMMUFIMC_LITE2, "smmufimc_lite2", "div_aclk_160", GATE_IP_CAM,
818
+
22, CLK_IGNORE_UNUSED, 0),
819
+
GATE(CLK_FIMC_LITE2, "fimc_lite2", "div_aclk_160", GATE_IP_CAM,
820
+
20, CLK_IGNORE_UNUSED, 0),
821
+
GATE(CLK_PIXELASYNCM1, "pixelasyncm1", "div_aclk_160", GATE_IP_CAM,
822
+
18, CLK_IGNORE_UNUSED, 0),
823
+
GATE(CLK_PIXELASYNCM0, "pixelasyncm0", "div_aclk_160", GATE_IP_CAM,
824
+
17, CLK_IGNORE_UNUSED, 0),
825
+
GATE(CLK_PPMUCAMIF, "ppmucamif", "div_aclk_160", GATE_IP_CAM,
826
+
16, CLK_IGNORE_UNUSED, 0),
827
+
GATE(CLK_SMMUJPEG, "smmujpeg", "div_aclk_160", GATE_IP_CAM, 11, 0, 0),
828
+
GATE(CLK_SMMUFIMC3, "smmufimc3", "div_aclk_160", GATE_IP_CAM, 10, 0, 0),
829
+
GATE(CLK_SMMUFIMC2, "smmufimc2", "div_aclk_160", GATE_IP_CAM, 9, 0, 0),
830
+
GATE(CLK_SMMUFIMC1, "smmufimc1", "div_aclk_160", GATE_IP_CAM, 8, 0, 0),
831
+
GATE(CLK_SMMUFIMC0, "smmufimc0", "div_aclk_160", GATE_IP_CAM, 7, 0, 0),
832
+
GATE(CLK_JPEG, "jpeg", "div_aclk_160", GATE_IP_CAM, 6, 0, 0),
833
+
GATE(CLK_CSIS1, "csis1", "div_aclk_160", GATE_IP_CAM, 5, 0, 0),
834
+
GATE(CLK_CSIS0, "csis0", "div_aclk_160", GATE_IP_CAM, 4, 0, 0),
835
+
GATE(CLK_FIMC3, "fimc3", "div_aclk_160", GATE_IP_CAM, 3, 0, 0),
836
+
GATE(CLK_FIMC2, "fimc2", "div_aclk_160", GATE_IP_CAM, 2, 0, 0),
837
+
GATE(CLK_FIMC1, "fimc1", "div_aclk_160", GATE_IP_CAM, 1, 0, 0),
838
+
GATE(CLK_FIMC0, "fimc0", "div_aclk_160", GATE_IP_CAM, 0, 0, 0),
839
+
840
+
/* GATE_IP_TV */
841
+
GATE(CLK_PPMUTV, "ppmutv", "div_aclk_100", GATE_IP_TV, 5, 0, 0),
842
+
GATE(CLK_SMMUTV, "smmutv", "div_aclk_100", GATE_IP_TV, 4, 0, 0),
843
+
GATE(CLK_HDMI, "hdmi", "div_aclk_100", GATE_IP_TV, 3, 0, 0),
844
+
GATE(CLK_MIXER, "mixer", "div_aclk_100", GATE_IP_TV, 1, 0, 0),
845
+
GATE(CLK_VP, "vp", "div_aclk_100", GATE_IP_TV, 0, 0, 0),
846
+
847
+
/* GATE_IP_MFC */
848
+
GATE(CLK_PPMUMFC_R, "ppmumfc_r", "div_aclk_200", GATE_IP_MFC, 4,
849
+
CLK_IGNORE_UNUSED, 0),
850
+
GATE(CLK_PPMUMFC_L, "ppmumfc_l", "div_aclk_200", GATE_IP_MFC, 3,
851
+
CLK_IGNORE_UNUSED, 0),
852
+
GATE(CLK_SMMUMFC_R, "smmumfc_r", "div_aclk_200", GATE_IP_MFC, 2, 0, 0),
853
+
GATE(CLK_SMMUMFC_L, "smmumfc_l", "div_aclk_200", GATE_IP_MFC, 1, 0, 0),
854
+
GATE(CLK_MFC, "mfc", "div_aclk_200", GATE_IP_MFC, 0, 0, 0),
855
+
856
+
/* GATE_IP_G3D */
857
+
GATE(CLK_PPMUG3D, "ppmug3d", "div_aclk_200", GATE_IP_G3D, 1,
858
+
CLK_IGNORE_UNUSED, 0),
859
+
GATE(CLK_G3D, "g3d", "div_aclk_200", GATE_IP_G3D, 0, 0, 0),
860
+
861
+
/* GATE_IP_LCD */
862
+
GATE(CLK_PPMULCD0, "ppmulcd0", "div_aclk_160", GATE_IP_LCD, 5,
863
+
CLK_IGNORE_UNUSED, 0),
864
+
GATE(CLK_SMMUFIMD0, "smmufimd0", "div_aclk_160", GATE_IP_LCD, 4, 0, 0),
865
+
GATE(CLK_DSIM0, "dsim0", "div_aclk_160", GATE_IP_LCD, 3, 0, 0),
866
+
GATE(CLK_SMIES, "smies", "div_aclk_160", GATE_IP_LCD, 2, 0, 0),
867
+
GATE(CLK_MIE0, "mie0", "div_aclk_160", GATE_IP_LCD, 1, 0, 0),
868
+
GATE(CLK_FIMD0, "fimd0", "div_aclk_160", GATE_IP_LCD, 0, 0, 0),
869
+
870
+
/* GATE_IP_FSYS */
871
+
GATE(CLK_TSADC, "tsadc", "div_aclk_200", GATE_IP_FSYS, 20, 0, 0),
872
+
GATE(CLK_PPMUFILE, "ppmufile", "div_aclk_200", GATE_IP_FSYS, 17,
873
+
CLK_IGNORE_UNUSED, 0),
874
+
GATE(CLK_NFCON, "nfcon", "div_aclk_200", GATE_IP_FSYS, 16, 0, 0),
875
+
GATE(CLK_USBDEVICE, "usbdevice", "div_aclk_200", GATE_IP_FSYS, 13,
876
+
0, 0),
877
+
GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
878
+
GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
879
+
GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
880
+
GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
881
+
GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
882
+
GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
883
+
GATE(CLK_PDMA0, "pdma0", "div_aclk_200", GATE_IP_FSYS, 0, 0, 0),
884
+
885
+
/* GATE_IP_PERIL */
886
+
GATE(CLK_SPDIF, "spdif", "div_aclk_100", GATE_IP_PERIL, 26, 0, 0),
887
+
GATE(CLK_PWM, "pwm", "div_aclk_100", GATE_IP_PERIL, 24, 0, 0),
888
+
GATE(CLK_PCM2, "pcm2", "div_aclk_100", GATE_IP_PERIL, 23, 0, 0),
889
+
GATE(CLK_PCM1, "pcm1", "div_aclk_100", GATE_IP_PERIL, 22, 0, 0),
890
+
GATE(CLK_I2S1, "i2s1", "div_aclk_100", GATE_IP_PERIL, 20, 0, 0),
891
+
GATE(CLK_SPI2, "spi2", "div_aclk_100", GATE_IP_PERIL, 18, 0, 0),
892
+
GATE(CLK_SPI1, "spi1", "div_aclk_100", GATE_IP_PERIL, 17, 0, 0),
893
+
GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0),
894
+
GATE(CLK_I2CHDMI, "i2chdmi", "div_aclk_100", GATE_IP_PERIL, 14, 0, 0),
895
+
GATE(CLK_I2C7, "i2c7", "div_aclk_100", GATE_IP_PERIL, 13, 0, 0),
896
+
GATE(CLK_I2C6, "i2c6", "div_aclk_100", GATE_IP_PERIL, 12, 0, 0),
897
+
GATE(CLK_I2C5, "i2c5", "div_aclk_100", GATE_IP_PERIL, 11, 0, 0),
898
+
GATE(CLK_I2C4, "i2c4", "div_aclk_100", GATE_IP_PERIL, 10, 0, 0),
899
+
GATE(CLK_I2C3, "i2c3", "div_aclk_100", GATE_IP_PERIL, 9, 0, 0),
900
+
GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
901
+
GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
902
+
GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
903
+
GATE(CLK_UART3, "uart3", "div_aclk_100", GATE_IP_PERIL, 3, 0, 0),
904
+
GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
905
+
GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
906
+
GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
907
+
};
908
+
909
+
/*
910
+
* APLL & MPLL & BPLL & ISP_PLL & DISP_PLL & G3D_PLL
911
+
*/
912
+
static struct samsung_pll_rate_table exynos4415_pll_rates[] = {
913
+
PLL_35XX_RATE(1600000000, 400, 3, 1),
914
+
PLL_35XX_RATE(1500000000, 250, 2, 1),
915
+
PLL_35XX_RATE(1400000000, 175, 3, 0),
916
+
PLL_35XX_RATE(1300000000, 325, 3, 1),
917
+
PLL_35XX_RATE(1200000000, 400, 4, 1),
918
+
PLL_35XX_RATE(1100000000, 275, 3, 1),
919
+
PLL_35XX_RATE(1066000000, 533, 6, 1),
920
+
PLL_35XX_RATE(1000000000, 250, 3, 1),
921
+
PLL_35XX_RATE(960000000, 320, 4, 1),
922
+
PLL_35XX_RATE(900000000, 300, 4, 1),
923
+
PLL_35XX_RATE(850000000, 425, 6, 1),
924
+
PLL_35XX_RATE(800000000, 200, 3, 1),
925
+
PLL_35XX_RATE(700000000, 175, 3, 1),
926
+
PLL_35XX_RATE(667000000, 667, 12, 1),
927
+
PLL_35XX_RATE(600000000, 400, 4, 2),
928
+
PLL_35XX_RATE(550000000, 275, 3, 2),
929
+
PLL_35XX_RATE(533000000, 533, 6, 2),
930
+
PLL_35XX_RATE(520000000, 260, 3, 2),
931
+
PLL_35XX_RATE(500000000, 250, 3, 2),
932
+
PLL_35XX_RATE(440000000, 220, 3, 2),
933
+
PLL_35XX_RATE(400000000, 200, 3, 2),
934
+
PLL_35XX_RATE(350000000, 175, 3, 2),
935
+
PLL_35XX_RATE(300000000, 300, 3, 3),
936
+
PLL_35XX_RATE(266000000, 266, 3, 3),
937
+
PLL_35XX_RATE(200000000, 200, 3, 3),
938
+
PLL_35XX_RATE(160000000, 160, 3, 3),
939
+
PLL_35XX_RATE(100000000, 200, 3, 4),
940
+
{ /* sentinel */ }
941
+
};
942
+
943
+
/* EPLL */
944
+
static struct samsung_pll_rate_table exynos4415_epll_rates[] = {
945
+
PLL_36XX_RATE(800000000, 200, 3, 1, 0),
946
+
PLL_36XX_RATE(288000000, 96, 2, 2, 0),
947
+
PLL_36XX_RATE(192000000, 128, 2, 3, 0),
948
+
PLL_36XX_RATE(144000000, 96, 2, 3, 0),
949
+
PLL_36XX_RATE(96000000, 128, 2, 4, 0),
950
+
PLL_36XX_RATE(84000000, 112, 2, 4, 0),
951
+
PLL_36XX_RATE(80750011, 107, 2, 4, 43691),
952
+
PLL_36XX_RATE(73728004, 98, 2, 4, 19923),
953
+
PLL_36XX_RATE(67987602, 271, 3, 5, 62285),
954
+
PLL_36XX_RATE(65911004, 175, 2, 5, 49982),
955
+
PLL_36XX_RATE(50000000, 200, 3, 5, 0),
956
+
PLL_36XX_RATE(49152003, 131, 2, 5, 4719),
957
+
PLL_36XX_RATE(48000000, 128, 2, 5, 0),
958
+
PLL_36XX_RATE(45250000, 181, 3, 5, 0),
959
+
{ /* sentinel */ }
960
+
};
961
+
962
+
static struct samsung_pll_clock exynos4415_plls[nr_plls] __initdata = {
963
+
[apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
964
+
APLL_LOCK, APLL_CON0, NULL),
965
+
[epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
966
+
EPLL_LOCK, EPLL_CON0, NULL),
967
+
[g3d_pll] = PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll",
968
+
"mout_g3d_pllsrc", G3D_PLL_LOCK, G3D_PLL_CON0, NULL),
969
+
[isp_pll] = PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "fin_pll",
970
+
ISP_PLL_LOCK, ISP_PLL_CON0, NULL),
971
+
[disp_pll] = PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll",
972
+
"fin_pll", DISP_PLL_LOCK, DISP_PLL_CON0, NULL),
973
+
};
974
+
975
+
static void __init exynos4415_cmu_init(struct device_node *np)
976
+
{
977
+
void __iomem *reg_base;
978
+
979
+
reg_base = of_iomap(np, 0);
980
+
if (!reg_base)
981
+
panic("%s: failed to map registers\n", __func__);
982
+
983
+
exynos4415_ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
984
+
if (!exynos4415_ctx)
985
+
panic("%s: unable to allocate context.\n", __func__);
986
+
987
+
exynos4415_plls[apll].rate_table = exynos4415_pll_rates;
988
+
exynos4415_plls[epll].rate_table = exynos4415_epll_rates;
989
+
exynos4415_plls[g3d_pll].rate_table = exynos4415_pll_rates;
990
+
exynos4415_plls[isp_pll].rate_table = exynos4415_pll_rates;
991
+
exynos4415_plls[disp_pll].rate_table = exynos4415_pll_rates;
992
+
993
+
samsung_clk_register_fixed_factor(exynos4415_ctx,
994
+
exynos4415_fixed_factor_clks,
995
+
ARRAY_SIZE(exynos4415_fixed_factor_clks));
996
+
samsung_clk_register_fixed_rate(exynos4415_ctx,
997
+
exynos4415_fixed_rate_clks,
998
+
ARRAY_SIZE(exynos4415_fixed_rate_clks));
999
+
1000
+
samsung_clk_register_pll(exynos4415_ctx, exynos4415_plls,
1001
+
ARRAY_SIZE(exynos4415_plls), reg_base);
1002
+
samsung_clk_register_mux(exynos4415_ctx, exynos4415_mux_clks,
1003
+
ARRAY_SIZE(exynos4415_mux_clks));
1004
+
samsung_clk_register_div(exynos4415_ctx, exynos4415_div_clks,
1005
+
ARRAY_SIZE(exynos4415_div_clks));
1006
+
samsung_clk_register_gate(exynos4415_ctx, exynos4415_gate_clks,
1007
+
ARRAY_SIZE(exynos4415_gate_clks));
1008
+
1009
+
exynos4415_clk_sleep_init();
1010
+
1011
+
samsung_clk_of_add_provider(np, exynos4415_ctx);
1012
+
}
1013
+
CLK_OF_DECLARE(exynos4415_cmu, "samsung,exynos4415-cmu", exynos4415_cmu_init);
1014
+
1015
+
/*
1016
+
* CMU DMC
1017
+
*/
1018
+
1019
+
#define MPLL_LOCK 0x008
1020
+
#define MPLL_CON0 0x108
1021
+
#define MPLL_CON1 0x10c
1022
+
#define MPLL_CON2 0x110
1023
+
#define BPLL_LOCK 0x118
1024
+
#define BPLL_CON0 0x218
1025
+
#define BPLL_CON1 0x21c
1026
+
#define BPLL_CON2 0x220
1027
+
#define SRC_DMC 0x300
1028
+
#define DIV_DMC1 0x504
1029
+
1030
+
enum exynos4415_dmc_plls {
1031
+
mpll, bpll,
1032
+
nr_dmc_plls,
1033
+
};
1034
+
1035
+
static struct samsung_clk_provider *exynos4415_dmc_ctx;
1036
+
1037
+
#ifdef CONFIG_PM_SLEEP
1038
+
static struct samsung_clk_reg_dump *exynos4415_dmc_clk_regs;
1039
+
1040
+
static unsigned long exynos4415_cmu_dmc_clk_regs[] __initdata = {
1041
+
MPLL_LOCK,
1042
+
MPLL_CON0,
1043
+
MPLL_CON1,
1044
+
MPLL_CON2,
1045
+
BPLL_LOCK,
1046
+
BPLL_CON0,
1047
+
BPLL_CON1,
1048
+
BPLL_CON2,
1049
+
SRC_DMC,
1050
+
DIV_DMC1,
1051
+
};
1052
+
1053
+
static int exynos4415_dmc_clk_suspend(void)
1054
+
{
1055
+
samsung_clk_save(exynos4415_dmc_ctx->reg_base,
1056
+
exynos4415_dmc_clk_regs,
1057
+
ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs));
1058
+
return 0;
1059
+
}
1060
+
1061
+
static void exynos4415_dmc_clk_resume(void)
1062
+
{
1063
+
samsung_clk_restore(exynos4415_dmc_ctx->reg_base,
1064
+
exynos4415_dmc_clk_regs,
1065
+
ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs));
1066
+
}
1067
+
1068
+
static struct syscore_ops exynos4415_dmc_clk_syscore_ops = {
1069
+
.suspend = exynos4415_dmc_clk_suspend,
1070
+
.resume = exynos4415_dmc_clk_resume,
1071
+
};
1072
+
1073
+
static void exynos4415_dmc_clk_sleep_init(void)
1074
+
{
1075
+
exynos4415_dmc_clk_regs =
1076
+
samsung_clk_alloc_reg_dump(exynos4415_cmu_dmc_clk_regs,
1077
+
ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs));
1078
+
if (!exynos4415_dmc_clk_regs) {
1079
+
pr_warn("%s: Failed to allocate sleep save data\n", __func__);
1080
+
return;
1081
+
}
1082
+
1083
+
register_syscore_ops(&exynos4415_dmc_clk_syscore_ops);
1084
+
}
1085
+
#else
1086
+
static inline void exynos4415_dmc_clk_sleep_init(void) { }
1087
+
#endif /* CONFIG_PM_SLEEP */
1088
+
1089
+
PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
1090
+
PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", };
1091
+
PNAME(mbpll_p) = { "mout_mpll", "mout_bpll", };
1092
+
1093
+
static struct samsung_mux_clock exynos4415_dmc_mux_clks[] __initdata = {
1094
+
MUX(CLK_DMC_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_DMC, 12, 1),
1095
+
MUX(CLK_DMC_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_DMC, 10, 1),
1096
+
MUX(CLK_DMC_MOUT_DPHY, "mout_dphy", mbpll_p, SRC_DMC, 8, 1),
1097
+
MUX(CLK_DMC_MOUT_DMC_BUS, "mout_dmc_bus", mbpll_p, SRC_DMC, 4, 1),
1098
+
};
1099
+
1100
+
static struct samsung_div_clock exynos4415_dmc_div_clks[] __initdata = {
1101
+
DIV(CLK_DMC_DIV_DMC, "div_dmc", "div_dmc_pre", DIV_DMC1, 27, 3),
1102
+
DIV(CLK_DMC_DIV_DPHY, "div_dphy", "mout_dphy", DIV_DMC1, 23, 3),
1103
+
DIV(CLK_DMC_DIV_DMC_PRE, "div_dmc_pre", "mout_dmc_bus",
1104
+
DIV_DMC1, 19, 2),
1105
+
DIV(CLK_DMC_DIV_DMCP, "div_dmcp", "div_dmcd", DIV_DMC1, 15, 3),
1106
+
DIV(CLK_DMC_DIV_DMCD, "div_dmcd", "div_dmc", DIV_DMC1, 11, 3),
1107
+
DIV(CLK_DMC_DIV_MPLL_PRE, "div_mpll_pre", "mout_mpll", DIV_DMC1, 8, 2),
1108
+
};
1109
+
1110
+
static struct samsung_pll_clock exynos4415_dmc_plls[nr_dmc_plls] __initdata = {
1111
+
[mpll] = PLL(pll_35xx, CLK_DMC_FOUT_MPLL, "fout_mpll", "fin_pll",
1112
+
MPLL_LOCK, MPLL_CON0, NULL),
1113
+
[bpll] = PLL(pll_35xx, CLK_DMC_FOUT_BPLL, "fout_bpll", "fin_pll",
1114
+
BPLL_LOCK, BPLL_CON0, NULL),
1115
+
};
1116
+
1117
+
static void __init exynos4415_cmu_dmc_init(struct device_node *np)
1118
+
{
1119
+
void __iomem *reg_base;
1120
+
1121
+
reg_base = of_iomap(np, 0);
1122
+
if (!reg_base)
1123
+
panic("%s: failed to map registers\n", __func__);
1124
+
1125
+
exynos4415_dmc_ctx = samsung_clk_init(np, reg_base, NR_CLKS_DMC);
1126
+
if (!exynos4415_dmc_ctx)
1127
+
panic("%s: unable to allocate context.\n", __func__);
1128
+
1129
+
exynos4415_dmc_plls[mpll].rate_table = exynos4415_pll_rates;
1130
+
exynos4415_dmc_plls[bpll].rate_table = exynos4415_pll_rates;
1131
+
1132
+
samsung_clk_register_pll(exynos4415_dmc_ctx, exynos4415_dmc_plls,
1133
+
ARRAY_SIZE(exynos4415_dmc_plls), reg_base);
1134
+
samsung_clk_register_mux(exynos4415_dmc_ctx, exynos4415_dmc_mux_clks,
1135
+
ARRAY_SIZE(exynos4415_dmc_mux_clks));
1136
+
samsung_clk_register_div(exynos4415_dmc_ctx, exynos4415_dmc_div_clks,
1137
+
ARRAY_SIZE(exynos4415_dmc_div_clks));
1138
+
1139
+
exynos4415_dmc_clk_sleep_init();
1140
+
1141
+
samsung_clk_of_add_provider(np, exynos4415_dmc_ctx);
1142
+
}
1143
+
CLK_OF_DECLARE(exynos4415_cmu_dmc, "samsung,exynos4415-cmu-dmc",
1144
+
exynos4415_cmu_dmc_init);
+26
-159
drivers/clk/samsung/clk-exynos5260.c
+26
-159
drivers/clk/samsung/clk-exynos5260.c
···
11
11
12
12
#include <linux/clk.h>
13
13
#include <linux/clkdev.h>
14
-
#include <linux/clk-provider.h>
15
14
#include <linux/of.h>
16
15
#include <linux/of_address.h>
17
-
#include <linux/syscore_ops.h>
18
16
19
17
#include "clk-exynos5260.h"
20
18
#include "clk.h"
21
19
#include "clk-pll.h"
22
20
23
21
#include <dt-bindings/clock/exynos5260-clk.h>
24
-
25
-
static LIST_HEAD(clock_reg_cache_list);
26
-
27
-
struct exynos5260_clock_reg_cache {
28
-
struct list_head node;
29
-
void __iomem *reg_base;
30
-
struct samsung_clk_reg_dump *rdump;
31
-
unsigned int rd_num;
32
-
};
33
-
34
-
struct exynos5260_cmu_info {
35
-
/* list of pll clocks and respective count */
36
-
struct samsung_pll_clock *pll_clks;
37
-
unsigned int nr_pll_clks;
38
-
/* list of mux clocks and respective count */
39
-
struct samsung_mux_clock *mux_clks;
40
-
unsigned int nr_mux_clks;
41
-
/* list of div clocks and respective count */
42
-
struct samsung_div_clock *div_clks;
43
-
unsigned int nr_div_clks;
44
-
/* list of gate clocks and respective count */
45
-
struct samsung_gate_clock *gate_clks;
46
-
unsigned int nr_gate_clks;
47
-
/* list of fixed clocks and respective count */
48
-
struct samsung_fixed_rate_clock *fixed_clks;
49
-
unsigned int nr_fixed_clks;
50
-
/* total number of clocks with IDs assigned*/
51
-
unsigned int nr_clk_ids;
52
-
53
-
/* list and number of clocks registers */
54
-
unsigned long *clk_regs;
55
-
unsigned int nr_clk_regs;
56
-
};
57
22
58
23
/*
59
24
* Applicable for all 2550 Type PLLS for Exynos5260, listed below
···
78
113
PLL_36XX_RATE(66000000, 176, 2, 5, 0),
79
114
};
80
115
81
-
#ifdef CONFIG_PM_SLEEP
82
-
83
-
static int exynos5260_clk_suspend(void)
84
-
{
85
-
struct exynos5260_clock_reg_cache *cache;
86
-
87
-
list_for_each_entry(cache, &clock_reg_cache_list, node)
88
-
samsung_clk_save(cache->reg_base, cache->rdump,
89
-
cache->rd_num);
90
-
91
-
return 0;
92
-
}
93
-
94
-
static void exynos5260_clk_resume(void)
95
-
{
96
-
struct exynos5260_clock_reg_cache *cache;
97
-
98
-
list_for_each_entry(cache, &clock_reg_cache_list, node)
99
-
samsung_clk_restore(cache->reg_base, cache->rdump,
100
-
cache->rd_num);
101
-
}
102
-
103
-
static struct syscore_ops exynos5260_clk_syscore_ops = {
104
-
.suspend = exynos5260_clk_suspend,
105
-
.resume = exynos5260_clk_resume,
106
-
};
107
-
108
-
static void exynos5260_clk_sleep_init(void __iomem *reg_base,
109
-
unsigned long *rdump,
110
-
unsigned long nr_rdump)
111
-
{
112
-
struct exynos5260_clock_reg_cache *reg_cache;
113
-
114
-
reg_cache = kzalloc(sizeof(struct exynos5260_clock_reg_cache),
115
-
GFP_KERNEL);
116
-
if (!reg_cache)
117
-
panic("could not allocate register cache.\n");
118
-
119
-
reg_cache->rdump = samsung_clk_alloc_reg_dump(rdump, nr_rdump);
120
-
121
-
if (!reg_cache->rdump)
122
-
panic("could not allocate register dump storage.\n");
123
-
124
-
if (list_empty(&clock_reg_cache_list))
125
-
register_syscore_ops(&exynos5260_clk_syscore_ops);
126
-
127
-
reg_cache->rd_num = nr_rdump;
128
-
reg_cache->reg_base = reg_base;
129
-
list_add_tail(®_cache->node, &clock_reg_cache_list);
130
-
}
131
-
132
-
#else
133
-
static void exynos5260_clk_sleep_init(void __iomem *reg_base,
134
-
unsigned long *rdump,
135
-
unsigned long nr_rdump){}
136
-
#endif
137
-
138
-
/*
139
-
* Common function which registers plls, muxes, dividers and gates
140
-
* for each CMU. It also add CMU register list to register cache.
141
-
*/
142
-
143
-
void __init exynos5260_cmu_register_one(struct device_node *np,
144
-
struct exynos5260_cmu_info *cmu)
145
-
{
146
-
void __iomem *reg_base;
147
-
struct samsung_clk_provider *ctx;
148
-
149
-
reg_base = of_iomap(np, 0);
150
-
if (!reg_base)
151
-
panic("%s: failed to map registers\n", __func__);
152
-
153
-
ctx = samsung_clk_init(np, reg_base, cmu->nr_clk_ids);
154
-
if (!ctx)
155
-
panic("%s: unable to alllocate ctx\n", __func__);
156
-
157
-
if (cmu->pll_clks)
158
-
samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks,
159
-
reg_base);
160
-
if (cmu->mux_clks)
161
-
samsung_clk_register_mux(ctx, cmu->mux_clks,
162
-
cmu->nr_mux_clks);
163
-
if (cmu->div_clks)
164
-
samsung_clk_register_div(ctx, cmu->div_clks, cmu->nr_div_clks);
165
-
if (cmu->gate_clks)
166
-
samsung_clk_register_gate(ctx, cmu->gate_clks,
167
-
cmu->nr_gate_clks);
168
-
if (cmu->fixed_clks)
169
-
samsung_clk_register_fixed_rate(ctx, cmu->fixed_clks,
170
-
cmu->nr_fixed_clks);
171
-
if (cmu->clk_regs)
172
-
exynos5260_clk_sleep_init(reg_base, cmu->clk_regs,
173
-
cmu->nr_clk_regs);
174
-
175
-
samsung_clk_of_add_provider(np, ctx);
176
-
}
177
-
178
-
179
116
/* CMU_AUD */
180
117
181
118
static unsigned long aud_clk_regs[] __initdata = {
···
135
268
136
269
static void __init exynos5260_clk_aud_init(struct device_node *np)
137
270
{
138
-
struct exynos5260_cmu_info cmu = {0};
271
+
struct samsung_cmu_info cmu = {0};
139
272
140
273
cmu.mux_clks = aud_mux_clks;
141
274
cmu.nr_mux_clks = ARRAY_SIZE(aud_mux_clks);
···
147
280
cmu.clk_regs = aud_clk_regs;
148
281
cmu.nr_clk_regs = ARRAY_SIZE(aud_clk_regs);
149
282
150
-
exynos5260_cmu_register_one(np, &cmu);
283
+
samsung_cmu_register_one(np, &cmu);
151
284
}
152
285
153
286
CLK_OF_DECLARE(exynos5260_clk_aud, "samsung,exynos5260-clock-aud",
···
325
458
326
459
static void __init exynos5260_clk_disp_init(struct device_node *np)
327
460
{
328
-
struct exynos5260_cmu_info cmu = {0};
461
+
struct samsung_cmu_info cmu = {0};
329
462
330
463
cmu.mux_clks = disp_mux_clks;
331
464
cmu.nr_mux_clks = ARRAY_SIZE(disp_mux_clks);
···
337
470
cmu.clk_regs = disp_clk_regs;
338
471
cmu.nr_clk_regs = ARRAY_SIZE(disp_clk_regs);
339
472
340
-
exynos5260_cmu_register_one(np, &cmu);
473
+
samsung_cmu_register_one(np, &cmu);
341
474
}
342
475
343
476
CLK_OF_DECLARE(exynos5260_clk_disp, "samsung,exynos5260-clock-disp",
···
389
522
390
523
static void __init exynos5260_clk_egl_init(struct device_node *np)
391
524
{
392
-
struct exynos5260_cmu_info cmu = {0};
525
+
struct samsung_cmu_info cmu = {0};
393
526
394
527
cmu.pll_clks = egl_pll_clks;
395
528
cmu.nr_pll_clks = ARRAY_SIZE(egl_pll_clks);
···
401
534
cmu.clk_regs = egl_clk_regs;
402
535
cmu.nr_clk_regs = ARRAY_SIZE(egl_clk_regs);
403
536
404
-
exynos5260_cmu_register_one(np, &cmu);
537
+
samsung_cmu_register_one(np, &cmu);
405
538
}
406
539
407
540
CLK_OF_DECLARE(exynos5260_clk_egl, "samsung,exynos5260-clock-egl",
···
491
624
492
625
static void __init exynos5260_clk_fsys_init(struct device_node *np)
493
626
{
494
-
struct exynos5260_cmu_info cmu = {0};
627
+
struct samsung_cmu_info cmu = {0};
495
628
496
629
cmu.mux_clks = fsys_mux_clks;
497
630
cmu.nr_mux_clks = ARRAY_SIZE(fsys_mux_clks);
···
501
634
cmu.clk_regs = fsys_clk_regs;
502
635
cmu.nr_clk_regs = ARRAY_SIZE(fsys_clk_regs);
503
636
504
-
exynos5260_cmu_register_one(np, &cmu);
637
+
samsung_cmu_register_one(np, &cmu);
505
638
}
506
639
507
640
CLK_OF_DECLARE(exynos5260_clk_fsys, "samsung,exynos5260-clock-fsys",
···
580
713
581
714
static void __init exynos5260_clk_g2d_init(struct device_node *np)
582
715
{
583
-
struct exynos5260_cmu_info cmu = {0};
716
+
struct samsung_cmu_info cmu = {0};
584
717
585
718
cmu.mux_clks = g2d_mux_clks;
586
719
cmu.nr_mux_clks = ARRAY_SIZE(g2d_mux_clks);
···
592
725
cmu.clk_regs = g2d_clk_regs;
593
726
cmu.nr_clk_regs = ARRAY_SIZE(g2d_clk_regs);
594
727
595
-
exynos5260_cmu_register_one(np, &cmu);
728
+
samsung_cmu_register_one(np, &cmu);
596
729
}
597
730
598
731
CLK_OF_DECLARE(exynos5260_clk_g2d, "samsung,exynos5260-clock-g2d",
···
641
774
642
775
static void __init exynos5260_clk_g3d_init(struct device_node *np)
643
776
{
644
-
struct exynos5260_cmu_info cmu = {0};
777
+
struct samsung_cmu_info cmu = {0};
645
778
646
779
cmu.pll_clks = g3d_pll_clks;
647
780
cmu.nr_pll_clks = ARRAY_SIZE(g3d_pll_clks);
···
655
788
cmu.clk_regs = g3d_clk_regs;
656
789
cmu.nr_clk_regs = ARRAY_SIZE(g3d_clk_regs);
657
790
658
-
exynos5260_cmu_register_one(np, &cmu);
791
+
samsung_cmu_register_one(np, &cmu);
659
792
}
660
793
661
794
CLK_OF_DECLARE(exynos5260_clk_g3d, "samsung,exynos5260-clock-g3d",
···
776
909
777
910
static void __init exynos5260_clk_gscl_init(struct device_node *np)
778
911
{
779
-
struct exynos5260_cmu_info cmu = {0};
912
+
struct samsung_cmu_info cmu = {0};
780
913
781
914
cmu.mux_clks = gscl_mux_clks;
782
915
cmu.nr_mux_clks = ARRAY_SIZE(gscl_mux_clks);
···
788
921
cmu.clk_regs = gscl_clk_regs;
789
922
cmu.nr_clk_regs = ARRAY_SIZE(gscl_clk_regs);
790
923
791
-
exynos5260_cmu_register_one(np, &cmu);
924
+
samsung_cmu_register_one(np, &cmu);
792
925
}
793
926
794
927
CLK_OF_DECLARE(exynos5260_clk_gscl, "samsung,exynos5260-clock-gscl",
···
895
1028
896
1029
static void __init exynos5260_clk_isp_init(struct device_node *np)
897
1030
{
898
-
struct exynos5260_cmu_info cmu = {0};
1031
+
struct samsung_cmu_info cmu = {0};
899
1032
900
1033
cmu.mux_clks = isp_mux_clks;
901
1034
cmu.nr_mux_clks = ARRAY_SIZE(isp_mux_clks);
···
907
1040
cmu.clk_regs = isp_clk_regs;
908
1041
cmu.nr_clk_regs = ARRAY_SIZE(isp_clk_regs);
909
1042
910
-
exynos5260_cmu_register_one(np, &cmu);
1043
+
samsung_cmu_register_one(np, &cmu);
911
1044
}
912
1045
913
1046
CLK_OF_DECLARE(exynos5260_clk_isp, "samsung,exynos5260-clock-isp",
···
959
1092
960
1093
static void __init exynos5260_clk_kfc_init(struct device_node *np)
961
1094
{
962
-
struct exynos5260_cmu_info cmu = {0};
1095
+
struct samsung_cmu_info cmu = {0};
963
1096
964
1097
cmu.pll_clks = kfc_pll_clks;
965
1098
cmu.nr_pll_clks = ARRAY_SIZE(kfc_pll_clks);
···
971
1104
cmu.clk_regs = kfc_clk_regs;
972
1105
cmu.nr_clk_regs = ARRAY_SIZE(kfc_clk_regs);
973
1106
974
-
exynos5260_cmu_register_one(np, &cmu);
1107
+
samsung_cmu_register_one(np, &cmu);
975
1108
}
976
1109
977
1110
CLK_OF_DECLARE(exynos5260_clk_kfc, "samsung,exynos5260-clock-kfc",
···
1015
1148
1016
1149
static void __init exynos5260_clk_mfc_init(struct device_node *np)
1017
1150
{
1018
-
struct exynos5260_cmu_info cmu = {0};
1151
+
struct samsung_cmu_info cmu = {0};
1019
1152
1020
1153
cmu.mux_clks = mfc_mux_clks;
1021
1154
cmu.nr_mux_clks = ARRAY_SIZE(mfc_mux_clks);
···
1027
1160
cmu.clk_regs = mfc_clk_regs;
1028
1161
cmu.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs);
1029
1162
1030
-
exynos5260_cmu_register_one(np, &cmu);
1163
+
samsung_cmu_register_one(np, &cmu);
1031
1164
}
1032
1165
1033
1166
CLK_OF_DECLARE(exynos5260_clk_mfc, "samsung,exynos5260-clock-mfc",
···
1162
1295
1163
1296
static void __init exynos5260_clk_mif_init(struct device_node *np)
1164
1297
{
1165
-
struct exynos5260_cmu_info cmu = {0};
1298
+
struct samsung_cmu_info cmu = {0};
1166
1299
1167
1300
cmu.pll_clks = mif_pll_clks;
1168
1301
cmu.nr_pll_clks = ARRAY_SIZE(mif_pll_clks);
···
1176
1309
cmu.clk_regs = mif_clk_regs;
1177
1310
cmu.nr_clk_regs = ARRAY_SIZE(mif_clk_regs);
1178
1311
1179
-
exynos5260_cmu_register_one(np, &cmu);
1312
+
samsung_cmu_register_one(np, &cmu);
1180
1313
}
1181
1314
1182
1315
CLK_OF_DECLARE(exynos5260_clk_mif, "samsung,exynos5260-clock-mif",
···
1370
1503
1371
1504
static void __init exynos5260_clk_peri_init(struct device_node *np)
1372
1505
{
1373
-
struct exynos5260_cmu_info cmu = {0};
1506
+
struct samsung_cmu_info cmu = {0};
1374
1507
1375
1508
cmu.mux_clks = peri_mux_clks;
1376
1509
cmu.nr_mux_clks = ARRAY_SIZE(peri_mux_clks);
···
1382
1515
cmu.clk_regs = peri_clk_regs;
1383
1516
cmu.nr_clk_regs = ARRAY_SIZE(peri_clk_regs);
1384
1517
1385
-
exynos5260_cmu_register_one(np, &cmu);
1518
+
samsung_cmu_register_one(np, &cmu);
1386
1519
}
1387
1520
1388
1521
CLK_OF_DECLARE(exynos5260_clk_peri, "samsung,exynos5260-clock-peri",
···
1826
1959
1827
1960
static void __init exynos5260_clk_top_init(struct device_node *np)
1828
1961
{
1829
-
struct exynos5260_cmu_info cmu = {0};
1962
+
struct samsung_cmu_info cmu = {0};
1830
1963
1831
1964
cmu.pll_clks = top_pll_clks;
1832
1965
cmu.nr_pll_clks = ARRAY_SIZE(top_pll_clks);
···
1842
1975
cmu.clk_regs = top_clk_regs;
1843
1976
cmu.nr_clk_regs = ARRAY_SIZE(top_clk_regs);
1844
1977
1845
-
exynos5260_cmu_register_one(np, &cmu);
1978
+
samsung_cmu_register_one(np, &cmu);
1846
1979
}
1847
1980
1848
1981
CLK_OF_DECLARE(exynos5260_clk_top, "samsung,exynos5260-clock-top",
+743
drivers/clk/samsung/clk-exynos7.c
+743
drivers/clk/samsung/clk-exynos7.c
···
1
+
/*
2
+
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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* Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include "clk.h"
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#include <dt-bindings/clock/exynos7-clk.h>
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/* Register Offset definitions for CMU_TOPC (0x10570000) */
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#define CC_PLL_LOCK 0x0000
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#define BUS0_PLL_LOCK 0x0004
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#define BUS1_DPLL_LOCK 0x0008
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#define MFC_PLL_LOCK 0x000C
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#define AUD_PLL_LOCK 0x0010
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#define CC_PLL_CON0 0x0100
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#define BUS0_PLL_CON0 0x0110
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#define BUS1_DPLL_CON0 0x0120
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#define MFC_PLL_CON0 0x0130
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#define AUD_PLL_CON0 0x0140
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#define MUX_SEL_TOPC0 0x0200
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#define MUX_SEL_TOPC1 0x0204
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#define MUX_SEL_TOPC2 0x0208
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#define MUX_SEL_TOPC3 0x020C
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#define DIV_TOPC0 0x0600
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#define DIV_TOPC1 0x0604
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#define DIV_TOPC3 0x060C
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static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = {
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FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_bus0_pll_ctrl", 1, 2, 0),
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FFACTOR(0, "ffac_topc_bus0_pll_div4",
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"ffac_topc_bus0_pll_div2", 1, 2, 0),
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FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_bus1_pll_ctrl", 1, 2, 0),
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FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_cc_pll_ctrl", 1, 2, 0),
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FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_mfc_pll_ctrl", 1, 2, 0),
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};
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/* List of parent clocks for Muxes in CMU_TOPC */
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PNAME(mout_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" };
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PNAME(mout_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" };
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PNAME(mout_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" };
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PNAME(mout_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" };
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PNAME(mout_topc_group2) = { "mout_sclk_bus0_pll_cmuc",
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"mout_sclk_bus1_pll_cmuc", "mout_sclk_cc_pll_cmuc",
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"mout_sclk_mfc_pll_cmuc" };
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PNAME(mout_sclk_bus0_pll_cmuc_p) = { "mout_bus0_pll_ctrl",
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"ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"};
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PNAME(mout_sclk_bus1_pll_cmuc_p) = { "mout_bus1_pll_ctrl",
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"ffac_topc_bus1_pll_div2"};
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PNAME(mout_sclk_cc_pll_cmuc_p) = { "mout_cc_pll_ctrl",
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"ffac_topc_cc_pll_div2"};
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PNAME(mout_sclk_mfc_pll_cmuc_p) = { "mout_mfc_pll_ctrl",
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"ffac_topc_mfc_pll_div2"};
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PNAME(mout_sclk_bus0_pll_out_p) = {"mout_bus0_pll_ctrl",
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"ffac_topc_bus0_pll_div2"};
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static unsigned long topc_clk_regs[] __initdata = {
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CC_PLL_LOCK,
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BUS0_PLL_LOCK,
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BUS1_DPLL_LOCK,
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MFC_PLL_LOCK,
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AUD_PLL_LOCK,
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CC_PLL_CON0,
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BUS0_PLL_CON0,
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BUS1_DPLL_CON0,
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MFC_PLL_CON0,
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AUD_PLL_CON0,
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MUX_SEL_TOPC0,
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MUX_SEL_TOPC1,
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MUX_SEL_TOPC2,
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MUX_SEL_TOPC3,
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DIV_TOPC0,
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DIV_TOPC1,
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DIV_TOPC3,
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};
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static struct samsung_mux_clock topc_mux_clks[] __initdata = {
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MUX(0, "mout_bus0_pll_ctrl", mout_bus0_pll_ctrl_p, MUX_SEL_TOPC0, 0, 1),
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MUX(0, "mout_bus1_pll_ctrl", mout_bus1_pll_ctrl_p, MUX_SEL_TOPC0, 4, 1),
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MUX(0, "mout_cc_pll_ctrl", mout_cc_pll_ctrl_p, MUX_SEL_TOPC0, 8, 1),
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MUX(0, "mout_mfc_pll_ctrl", mout_mfc_pll_ctrl_p, MUX_SEL_TOPC0, 12, 1),
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MUX(0, "mout_sclk_bus0_pll_cmuc", mout_sclk_bus0_pll_cmuc_p,
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MUX_SEL_TOPC0, 16, 2),
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MUX(0, "mout_sclk_bus1_pll_cmuc", mout_sclk_bus1_pll_cmuc_p,
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MUX_SEL_TOPC0, 20, 1),
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MUX(0, "mout_sclk_cc_pll_cmuc", mout_sclk_cc_pll_cmuc_p,
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MUX_SEL_TOPC0, 24, 1),
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MUX(0, "mout_sclk_mfc_pll_cmuc", mout_sclk_mfc_pll_cmuc_p,
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MUX_SEL_TOPC0, 28, 1),
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MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p,
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MUX_SEL_TOPC1, 16, 1),
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MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
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MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
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};
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static struct samsung_div_clock topc_div_clks[] __initdata = {
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DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133",
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DIV_TOPC0, 4, 4),
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DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66",
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DIV_TOPC1, 24, 4),
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DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_sclk_bus0_pll_out",
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DIV_TOPC3, 0, 3),
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DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_bus1_pll_ctrl",
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DIV_TOPC3, 8, 3),
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DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_cc_pll_ctrl",
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DIV_TOPC3, 12, 3),
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DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl",
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DIV_TOPC3, 16, 3),
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};
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static struct samsung_pll_clock topc_pll_clks[] __initdata = {
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PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK,
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BUS0_PLL_CON0, NULL),
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PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK,
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CC_PLL_CON0, NULL),
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PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK,
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BUS1_DPLL_CON0, NULL),
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PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK,
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MFC_PLL_CON0, NULL),
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PLL(pll_1460x, 0, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK,
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AUD_PLL_CON0, NULL),
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};
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static struct samsung_cmu_info topc_cmu_info __initdata = {
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.pll_clks = topc_pll_clks,
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.nr_pll_clks = ARRAY_SIZE(topc_pll_clks),
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.mux_clks = topc_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(topc_mux_clks),
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.div_clks = topc_div_clks,
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.nr_div_clks = ARRAY_SIZE(topc_div_clks),
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.fixed_factor_clks = topc_fixed_factor_clks,
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.nr_fixed_factor_clks = ARRAY_SIZE(topc_fixed_factor_clks),
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.nr_clk_ids = TOPC_NR_CLK,
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.clk_regs = topc_clk_regs,
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.nr_clk_regs = ARRAY_SIZE(topc_clk_regs),
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};
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static void __init exynos7_clk_topc_init(struct device_node *np)
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{
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samsung_cmu_register_one(np, &topc_cmu_info);
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}
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CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc",
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exynos7_clk_topc_init);
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/* Register Offset definitions for CMU_TOP0 (0x105D0000) */
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#define MUX_SEL_TOP00 0x0200
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#define MUX_SEL_TOP01 0x0204
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#define MUX_SEL_TOP03 0x020C
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#define MUX_SEL_TOP0_PERIC3 0x023C
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#define DIV_TOP03 0x060C
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#define DIV_TOP0_PERIC3 0x063C
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#define ENABLE_SCLK_TOP0_PERIC3 0x0A3C
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/* List of parent clocks for Muxes in CMU_TOP0 */
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PNAME(mout_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" };
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PNAME(mout_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll" };
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PNAME(mout_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll" };
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PNAME(mout_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll" };
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PNAME(mout_top0_half_bus0_pll_p) = {"mout_top0_bus0_pll",
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"ffac_top0_bus0_pll_div2"};
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PNAME(mout_top0_half_bus1_pll_p) = {"mout_top0_bus1_pll",
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"ffac_top0_bus1_pll_div2"};
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PNAME(mout_top0_half_cc_pll_p) = {"mout_top0_cc_pll",
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"ffac_top0_cc_pll_div2"};
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PNAME(mout_top0_half_mfc_pll_p) = {"mout_top0_mfc_pll",
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"ffac_top0_mfc_pll_div2"};
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PNAME(mout_top0_group1) = {"mout_top0_half_bus0_pll",
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"mout_top0_half_bus1_pll", "mout_top0_half_cc_pll",
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"mout_top0_half_mfc_pll"};
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static unsigned long top0_clk_regs[] __initdata = {
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MUX_SEL_TOP00,
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MUX_SEL_TOP01,
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MUX_SEL_TOP03,
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MUX_SEL_TOP0_PERIC3,
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DIV_TOP03,
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DIV_TOP0_PERIC3,
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ENABLE_SCLK_TOP0_PERIC3,
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};
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static struct samsung_mux_clock top0_mux_clks[] __initdata = {
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MUX(0, "mout_top0_mfc_pll", mout_mfc_pll_p, MUX_SEL_TOP00, 4, 1),
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MUX(0, "mout_top0_cc_pll", mout_cc_pll_p, MUX_SEL_TOP00, 8, 1),
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MUX(0, "mout_top0_bus1_pll", mout_bus1_pll_p, MUX_SEL_TOP00, 12, 1),
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MUX(0, "mout_top0_bus0_pll", mout_bus0_pll_p, MUX_SEL_TOP00, 16, 1),
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MUX(0, "mout_top0_half_mfc_pll", mout_top0_half_mfc_pll_p,
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MUX_SEL_TOP01, 4, 1),
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MUX(0, "mout_top0_half_cc_pll", mout_top0_half_cc_pll_p,
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MUX_SEL_TOP01, 8, 1),
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MUX(0, "mout_top0_half_bus1_pll", mout_top0_half_bus1_pll_p,
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MUX_SEL_TOP01, 12, 1),
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MUX(0, "mout_top0_half_bus0_pll", mout_top0_half_bus0_pll_p,
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MUX_SEL_TOP01, 16, 1),
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MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2),
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MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2),
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MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2),
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MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2),
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MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2),
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MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2),
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};
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static struct samsung_div_clock top0_div_clks[] __initdata = {
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DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66",
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DIV_TOP03, 12, 6),
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DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66",
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DIV_TOP03, 20, 6),
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DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4),
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DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4),
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DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4),
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DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4),
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};
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static struct samsung_gate_clock top0_gate_clks[] __initdata = {
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GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3",
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ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
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GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2",
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ENABLE_SCLK_TOP0_PERIC3, 8, 0, 0),
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GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1",
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ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0),
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GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0",
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ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0),
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};
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static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = {
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FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll", 1, 2, 0),
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FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll", 1, 2, 0),
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FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll", 1, 2, 0),
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FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll", 1, 2, 0),
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};
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static struct samsung_cmu_info top0_cmu_info __initdata = {
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.mux_clks = top0_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(top0_mux_clks),
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.div_clks = top0_div_clks,
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.nr_div_clks = ARRAY_SIZE(top0_div_clks),
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.gate_clks = top0_gate_clks,
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.nr_gate_clks = ARRAY_SIZE(top0_gate_clks),
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.fixed_factor_clks = top0_fixed_factor_clks,
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.nr_fixed_factor_clks = ARRAY_SIZE(top0_fixed_factor_clks),
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.nr_clk_ids = TOP0_NR_CLK,
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.clk_regs = top0_clk_regs,
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.nr_clk_regs = ARRAY_SIZE(top0_clk_regs),
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};
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static void __init exynos7_clk_top0_init(struct device_node *np)
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{
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samsung_cmu_register_one(np, &top0_cmu_info);
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}
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+
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CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
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exynos7_clk_top0_init);
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+
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/* Register Offset definitions for CMU_TOP1 (0x105E0000) */
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#define MUX_SEL_TOP10 0x0200
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#define MUX_SEL_TOP11 0x0204
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#define MUX_SEL_TOP13 0x020C
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#define MUX_SEL_TOP1_FSYS0 0x0224
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#define MUX_SEL_TOP1_FSYS1 0x0228
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#define DIV_TOP13 0x060C
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#define DIV_TOP1_FSYS0 0x0624
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#define DIV_TOP1_FSYS1 0x0628
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#define ENABLE_ACLK_TOP13 0x080C
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#define ENABLE_SCLK_TOP1_FSYS0 0x0A24
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#define ENABLE_SCLK_TOP1_FSYS1 0x0A28
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+
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/* List of parent clocks for Muxes in CMU_TOP1 */
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PNAME(mout_top1_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" };
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PNAME(mout_top1_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll_b" };
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PNAME(mout_top1_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll_b" };
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PNAME(mout_top1_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll_b" };
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+
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PNAME(mout_top1_half_bus0_pll_p) = {"mout_top1_bus0_pll",
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"ffac_top1_bus0_pll_div2"};
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PNAME(mout_top1_half_bus1_pll_p) = {"mout_top1_bus1_pll",
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"ffac_top1_bus1_pll_div2"};
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PNAME(mout_top1_half_cc_pll_p) = {"mout_top1_cc_pll",
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"ffac_top1_cc_pll_div2"};
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PNAME(mout_top1_half_mfc_pll_p) = {"mout_top1_mfc_pll",
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"ffac_top1_mfc_pll_div2"};
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+
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PNAME(mout_top1_group1) = {"mout_top1_half_bus0_pll",
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"mout_top1_half_bus1_pll", "mout_top1_half_cc_pll",
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"mout_top1_half_mfc_pll"};
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+
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+
static unsigned long top1_clk_regs[] __initdata = {
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+
MUX_SEL_TOP10,
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+
MUX_SEL_TOP11,
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+
MUX_SEL_TOP13,
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+
MUX_SEL_TOP1_FSYS0,
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MUX_SEL_TOP1_FSYS1,
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+
DIV_TOP13,
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DIV_TOP1_FSYS0,
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DIV_TOP1_FSYS1,
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ENABLE_ACLK_TOP13,
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ENABLE_SCLK_TOP1_FSYS0,
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ENABLE_SCLK_TOP1_FSYS1,
323
+
};
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+
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+
static struct samsung_mux_clock top1_mux_clks[] __initdata = {
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+
MUX(0, "mout_top1_mfc_pll", mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1),
327
+
MUX(0, "mout_top1_cc_pll", mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1),
328
+
MUX(0, "mout_top1_bus1_pll", mout_top1_bus1_pll_p,
329
+
MUX_SEL_TOP10, 12, 1),
330
+
MUX(0, "mout_top1_bus0_pll", mout_top1_bus0_pll_p,
331
+
MUX_SEL_TOP10, 16, 1),
332
+
333
+
MUX(0, "mout_top1_half_mfc_pll", mout_top1_half_mfc_pll_p,
334
+
MUX_SEL_TOP11, 4, 1),
335
+
MUX(0, "mout_top1_half_cc_pll", mout_top1_half_cc_pll_p,
336
+
MUX_SEL_TOP11, 8, 1),
337
+
MUX(0, "mout_top1_half_bus1_pll", mout_top1_half_bus1_pll_p,
338
+
MUX_SEL_TOP11, 12, 1),
339
+
MUX(0, "mout_top1_half_bus0_pll", mout_top1_half_bus0_pll_p,
340
+
MUX_SEL_TOP11, 16, 1),
341
+
342
+
MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
343
+
MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
344
+
345
+
MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2),
346
+
347
+
MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2),
348
+
MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2),
349
+
};
350
+
351
+
static struct samsung_div_clock top1_div_clks[] __initdata = {
352
+
DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200",
353
+
DIV_TOP13, 24, 4),
354
+
DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200",
355
+
DIV_TOP13, 28, 4),
356
+
357
+
DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
358
+
DIV_TOP1_FSYS0, 24, 4),
359
+
360
+
DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",
361
+
DIV_TOP1_FSYS1, 24, 4),
362
+
DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",
363
+
DIV_TOP1_FSYS1, 28, 4),
364
+
};
365
+
366
+
static struct samsung_gate_clock top1_gate_clks[] __initdata = {
367
+
GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
368
+
ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0),
369
+
370
+
GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
371
+
ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0),
372
+
GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
373
+
ENABLE_SCLK_TOP1_FSYS1, 28, CLK_SET_RATE_PARENT, 0),
374
+
};
375
+
376
+
static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
377
+
FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll", 1, 2, 0),
378
+
FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll", 1, 2, 0),
379
+
FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll", 1, 2, 0),
380
+
FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll", 1, 2, 0),
381
+
};
382
+
383
+
static struct samsung_cmu_info top1_cmu_info __initdata = {
384
+
.mux_clks = top1_mux_clks,
385
+
.nr_mux_clks = ARRAY_SIZE(top1_mux_clks),
386
+
.div_clks = top1_div_clks,
387
+
.nr_div_clks = ARRAY_SIZE(top1_div_clks),
388
+
.gate_clks = top1_gate_clks,
389
+
.nr_gate_clks = ARRAY_SIZE(top1_gate_clks),
390
+
.fixed_factor_clks = top1_fixed_factor_clks,
391
+
.nr_fixed_factor_clks = ARRAY_SIZE(top1_fixed_factor_clks),
392
+
.nr_clk_ids = TOP1_NR_CLK,
393
+
.clk_regs = top1_clk_regs,
394
+
.nr_clk_regs = ARRAY_SIZE(top1_clk_regs),
395
+
};
396
+
397
+
static void __init exynos7_clk_top1_init(struct device_node *np)
398
+
{
399
+
samsung_cmu_register_one(np, &top1_cmu_info);
400
+
}
401
+
402
+
CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
403
+
exynos7_clk_top1_init);
404
+
405
+
/* Register Offset definitions for CMU_CCORE (0x105B0000) */
406
+
#define MUX_SEL_CCORE 0x0200
407
+
#define DIV_CCORE 0x0600
408
+
#define ENABLE_ACLK_CCORE0 0x0800
409
+
#define ENABLE_ACLK_CCORE1 0x0804
410
+
#define ENABLE_PCLK_CCORE 0x0900
411
+
412
+
/*
413
+
* List of parent clocks for Muxes in CMU_CCORE
414
+
*/
415
+
PNAME(mout_aclk_ccore_133_p) = { "fin_pll", "dout_aclk_ccore_133" };
416
+
417
+
static unsigned long ccore_clk_regs[] __initdata = {
418
+
MUX_SEL_CCORE,
419
+
ENABLE_PCLK_CCORE,
420
+
};
421
+
422
+
static struct samsung_mux_clock ccore_mux_clks[] __initdata = {
423
+
MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_p,
424
+
MUX_SEL_CCORE, 1, 1),
425
+
};
426
+
427
+
static struct samsung_gate_clock ccore_gate_clks[] __initdata = {
428
+
GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user",
429
+
ENABLE_PCLK_CCORE, 8, 0, 0),
430
+
};
431
+
432
+
static struct samsung_cmu_info ccore_cmu_info __initdata = {
433
+
.mux_clks = ccore_mux_clks,
434
+
.nr_mux_clks = ARRAY_SIZE(ccore_mux_clks),
435
+
.gate_clks = ccore_gate_clks,
436
+
.nr_gate_clks = ARRAY_SIZE(ccore_gate_clks),
437
+
.nr_clk_ids = CCORE_NR_CLK,
438
+
.clk_regs = ccore_clk_regs,
439
+
.nr_clk_regs = ARRAY_SIZE(ccore_clk_regs),
440
+
};
441
+
442
+
static void __init exynos7_clk_ccore_init(struct device_node *np)
443
+
{
444
+
samsung_cmu_register_one(np, &ccore_cmu_info);
445
+
}
446
+
447
+
CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore",
448
+
exynos7_clk_ccore_init);
449
+
450
+
/* Register Offset definitions for CMU_PERIC0 (0x13610000) */
451
+
#define MUX_SEL_PERIC0 0x0200
452
+
#define ENABLE_PCLK_PERIC0 0x0900
453
+
#define ENABLE_SCLK_PERIC0 0x0A00
454
+
455
+
/* List of parent clocks for Muxes in CMU_PERIC0 */
456
+
PNAME(mout_aclk_peric0_66_p) = { "fin_pll", "dout_aclk_peric0_66" };
457
+
PNAME(mout_sclk_uart0_p) = { "fin_pll", "sclk_uart0" };
458
+
459
+
static unsigned long peric0_clk_regs[] __initdata = {
460
+
MUX_SEL_PERIC0,
461
+
ENABLE_PCLK_PERIC0,
462
+
ENABLE_SCLK_PERIC0,
463
+
};
464
+
465
+
static struct samsung_mux_clock peric0_mux_clks[] __initdata = {
466
+
MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_p,
467
+
MUX_SEL_PERIC0, 0, 1),
468
+
MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_p,
469
+
MUX_SEL_PERIC0, 16, 1),
470
+
};
471
+
472
+
static struct samsung_gate_clock peric0_gate_clks[] __initdata = {
473
+
GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user",
474
+
ENABLE_PCLK_PERIC0, 8, 0, 0),
475
+
GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user",
476
+
ENABLE_PCLK_PERIC0, 9, 0, 0),
477
+
GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user",
478
+
ENABLE_PCLK_PERIC0, 10, 0, 0),
479
+
GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user",
480
+
ENABLE_PCLK_PERIC0, 11, 0, 0),
481
+
GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user",
482
+
ENABLE_PCLK_PERIC0, 12, 0, 0),
483
+
GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user",
484
+
ENABLE_PCLK_PERIC0, 13, 0, 0),
485
+
GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user",
486
+
ENABLE_PCLK_PERIC0, 14, 0, 0),
487
+
GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",
488
+
ENABLE_PCLK_PERIC0, 16, 0, 0),
489
+
GATE(PCLK_ADCIF, "pclk_adcif", "mout_aclk_peric0_66_user",
490
+
ENABLE_PCLK_PERIC0, 20, 0, 0),
491
+
GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user",
492
+
ENABLE_PCLK_PERIC0, 21, 0, 0),
493
+
494
+
GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user",
495
+
ENABLE_SCLK_PERIC0, 16, 0, 0),
496
+
GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0),
497
+
};
498
+
499
+
static struct samsung_cmu_info peric0_cmu_info __initdata = {
500
+
.mux_clks = peric0_mux_clks,
501
+
.nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
502
+
.gate_clks = peric0_gate_clks,
503
+
.nr_gate_clks = ARRAY_SIZE(peric0_gate_clks),
504
+
.nr_clk_ids = PERIC0_NR_CLK,
505
+
.clk_regs = peric0_clk_regs,
506
+
.nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
507
+
};
508
+
509
+
static void __init exynos7_clk_peric0_init(struct device_node *np)
510
+
{
511
+
samsung_cmu_register_one(np, &peric0_cmu_info);
512
+
}
513
+
514
+
/* Register Offset definitions for CMU_PERIC1 (0x14C80000) */
515
+
#define MUX_SEL_PERIC10 0x0200
516
+
#define MUX_SEL_PERIC11 0x0204
517
+
#define ENABLE_PCLK_PERIC1 0x0900
518
+
#define ENABLE_SCLK_PERIC10 0x0A00
519
+
520
+
CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0",
521
+
exynos7_clk_peric0_init);
522
+
523
+
/* List of parent clocks for Muxes in CMU_PERIC1 */
524
+
PNAME(mout_aclk_peric1_66_p) = { "fin_pll", "dout_aclk_peric1_66" };
525
+
PNAME(mout_sclk_uart1_p) = { "fin_pll", "sclk_uart1" };
526
+
PNAME(mout_sclk_uart2_p) = { "fin_pll", "sclk_uart2" };
527
+
PNAME(mout_sclk_uart3_p) = { "fin_pll", "sclk_uart3" };
528
+
529
+
static unsigned long peric1_clk_regs[] __initdata = {
530
+
MUX_SEL_PERIC10,
531
+
MUX_SEL_PERIC11,
532
+
ENABLE_PCLK_PERIC1,
533
+
ENABLE_SCLK_PERIC10,
534
+
};
535
+
536
+
static struct samsung_mux_clock peric1_mux_clks[] __initdata = {
537
+
MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p,
538
+
MUX_SEL_PERIC10, 0, 1),
539
+
540
+
MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p,
541
+
MUX_SEL_PERIC11, 20, 1),
542
+
MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p,
543
+
MUX_SEL_PERIC11, 24, 1),
544
+
MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_p,
545
+
MUX_SEL_PERIC11, 28, 1),
546
+
};
547
+
548
+
static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
549
+
GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user",
550
+
ENABLE_PCLK_PERIC1, 4, 0, 0),
551
+
GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user",
552
+
ENABLE_PCLK_PERIC1, 5, 0, 0),
553
+
GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user",
554
+
ENABLE_PCLK_PERIC1, 6, 0, 0),
555
+
GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user",
556
+
ENABLE_PCLK_PERIC1, 7, 0, 0),
557
+
GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user",
558
+
ENABLE_PCLK_PERIC1, 8, 0, 0),
559
+
GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user",
560
+
ENABLE_PCLK_PERIC1, 9, 0, 0),
561
+
GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user",
562
+
ENABLE_PCLK_PERIC1, 10, 0, 0),
563
+
GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user",
564
+
ENABLE_PCLK_PERIC1, 11, 0, 0),
565
+
566
+
GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user",
567
+
ENABLE_SCLK_PERIC10, 9, 0, 0),
568
+
GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user",
569
+
ENABLE_SCLK_PERIC10, 10, 0, 0),
570
+
GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user",
571
+
ENABLE_SCLK_PERIC10, 11, 0, 0),
572
+
};
573
+
574
+
static struct samsung_cmu_info peric1_cmu_info __initdata = {
575
+
.mux_clks = peric1_mux_clks,
576
+
.nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
577
+
.gate_clks = peric1_gate_clks,
578
+
.nr_gate_clks = ARRAY_SIZE(peric1_gate_clks),
579
+
.nr_clk_ids = PERIC1_NR_CLK,
580
+
.clk_regs = peric1_clk_regs,
581
+
.nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
582
+
};
583
+
584
+
static void __init exynos7_clk_peric1_init(struct device_node *np)
585
+
{
586
+
samsung_cmu_register_one(np, &peric1_cmu_info);
587
+
}
588
+
589
+
CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1",
590
+
exynos7_clk_peric1_init);
591
+
592
+
/* Register Offset definitions for CMU_PERIS (0x10040000) */
593
+
#define MUX_SEL_PERIS 0x0200
594
+
#define ENABLE_PCLK_PERIS 0x0900
595
+
#define ENABLE_PCLK_PERIS_SECURE_CHIPID 0x0910
596
+
#define ENABLE_SCLK_PERIS 0x0A00
597
+
#define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10
598
+
599
+
/* List of parent clocks for Muxes in CMU_PERIS */
600
+
PNAME(mout_aclk_peris_66_p) = { "fin_pll", "dout_aclk_peris_66" };
601
+
602
+
static unsigned long peris_clk_regs[] __initdata = {
603
+
MUX_SEL_PERIS,
604
+
ENABLE_PCLK_PERIS,
605
+
ENABLE_PCLK_PERIS_SECURE_CHIPID,
606
+
ENABLE_SCLK_PERIS,
607
+
ENABLE_SCLK_PERIS_SECURE_CHIPID,
608
+
};
609
+
610
+
static struct samsung_mux_clock peris_mux_clks[] __initdata = {
611
+
MUX(0, "mout_aclk_peris_66_user",
612
+
mout_aclk_peris_66_p, MUX_SEL_PERIS, 0, 1),
613
+
};
614
+
615
+
static struct samsung_gate_clock peris_gate_clks[] __initdata = {
616
+
GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user",
617
+
ENABLE_PCLK_PERIS, 6, 0, 0),
618
+
GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user",
619
+
ENABLE_PCLK_PERIS, 10, 0, 0),
620
+
621
+
GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user",
622
+
ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
623
+
GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll",
624
+
ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
625
+
626
+
GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0),
627
+
};
628
+
629
+
static struct samsung_cmu_info peris_cmu_info __initdata = {
630
+
.mux_clks = peris_mux_clks,
631
+
.nr_mux_clks = ARRAY_SIZE(peris_mux_clks),
632
+
.gate_clks = peris_gate_clks,
633
+
.nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
634
+
.nr_clk_ids = PERIS_NR_CLK,
635
+
.clk_regs = peris_clk_regs,
636
+
.nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
637
+
};
638
+
639
+
static void __init exynos7_clk_peris_init(struct device_node *np)
640
+
{
641
+
samsung_cmu_register_one(np, &peris_cmu_info);
642
+
}
643
+
644
+
CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
645
+
exynos7_clk_peris_init);
646
+
647
+
/* Register Offset definitions for CMU_FSYS0 (0x10E90000) */
648
+
#define MUX_SEL_FSYS00 0x0200
649
+
#define MUX_SEL_FSYS01 0x0204
650
+
#define ENABLE_ACLK_FSYS01 0x0804
651
+
652
+
/*
653
+
* List of parent clocks for Muxes in CMU_FSYS0
654
+
*/
655
+
PNAME(mout_aclk_fsys0_200_p) = { "fin_pll", "dout_aclk_fsys0_200" };
656
+
PNAME(mout_sclk_mmc2_p) = { "fin_pll", "sclk_mmc2" };
657
+
658
+
static unsigned long fsys0_clk_regs[] __initdata = {
659
+
MUX_SEL_FSYS00,
660
+
MUX_SEL_FSYS01,
661
+
ENABLE_ACLK_FSYS01,
662
+
};
663
+
664
+
static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
665
+
MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_p,
666
+
MUX_SEL_FSYS00, 24, 1),
667
+
668
+
MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1),
669
+
};
670
+
671
+
static struct samsung_gate_clock fsys0_gate_clks[] __initdata = {
672
+
GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user",
673
+
ENABLE_ACLK_FSYS01, 31, 0, 0),
674
+
};
675
+
676
+
static struct samsung_cmu_info fsys0_cmu_info __initdata = {
677
+
.mux_clks = fsys0_mux_clks,
678
+
.nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks),
679
+
.gate_clks = fsys0_gate_clks,
680
+
.nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
681
+
.nr_clk_ids = TOP1_NR_CLK,
682
+
.clk_regs = fsys0_clk_regs,
683
+
.nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs),
684
+
};
685
+
686
+
static void __init exynos7_clk_fsys0_init(struct device_node *np)
687
+
{
688
+
samsung_cmu_register_one(np, &fsys0_cmu_info);
689
+
}
690
+
691
+
CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0",
692
+
exynos7_clk_fsys0_init);
693
+
694
+
/* Register Offset definitions for CMU_FSYS1 (0x156E0000) */
695
+
#define MUX_SEL_FSYS10 0x0200
696
+
#define MUX_SEL_FSYS11 0x0204
697
+
#define ENABLE_ACLK_FSYS1 0x0800
698
+
699
+
/*
700
+
* List of parent clocks for Muxes in CMU_FSYS1
701
+
*/
702
+
PNAME(mout_aclk_fsys1_200_p) = { "fin_pll", "dout_aclk_fsys1_200" };
703
+
PNAME(mout_sclk_mmc0_p) = { "fin_pll", "sclk_mmc0" };
704
+
PNAME(mout_sclk_mmc1_p) = { "fin_pll", "sclk_mmc1" };
705
+
706
+
static unsigned long fsys1_clk_regs[] __initdata = {
707
+
MUX_SEL_FSYS10,
708
+
MUX_SEL_FSYS11,
709
+
ENABLE_ACLK_FSYS1,
710
+
};
711
+
712
+
static struct samsung_mux_clock fsys1_mux_clks[] __initdata = {
713
+
MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_p,
714
+
MUX_SEL_FSYS10, 28, 1),
715
+
716
+
MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_p, MUX_SEL_FSYS11, 24, 1),
717
+
MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_p, MUX_SEL_FSYS11, 28, 1),
718
+
};
719
+
720
+
static struct samsung_gate_clock fsys1_gate_clks[] __initdata = {
721
+
GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user",
722
+
ENABLE_ACLK_FSYS1, 29, 0, 0),
723
+
GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user",
724
+
ENABLE_ACLK_FSYS1, 30, 0, 0),
725
+
};
726
+
727
+
static struct samsung_cmu_info fsys1_cmu_info __initdata = {
728
+
.mux_clks = fsys1_mux_clks,
729
+
.nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks),
730
+
.gate_clks = fsys1_gate_clks,
731
+
.nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
732
+
.nr_clk_ids = TOP1_NR_CLK,
733
+
.clk_regs = fsys1_clk_regs,
734
+
.nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
735
+
};
736
+
737
+
static void __init exynos7_clk_fsys1_init(struct device_node *np)
738
+
{
739
+
samsung_cmu_register_one(np, &fsys1_cmu_info);
740
+
}
741
+
742
+
CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1",
743
+
exynos7_clk_fsys1_init);
+20
-5
drivers/clk/samsung/clk-pll.c
+20
-5
drivers/clk/samsung/clk-pll.c
···
482
482
483
483
#define PLL46XX_VSEL_MASK (1)
484
484
#define PLL46XX_MDIV_MASK (0x1FF)
485
+
#define PLL1460X_MDIV_MASK (0x3FF)
486
+
485
487
#define PLL46XX_PDIV_MASK (0x3F)
486
488
#define PLL46XX_SDIV_MASK (0x7)
487
489
#define PLL46XX_VSEL_SHIFT (27)
···
513
511
514
512
pll_con0 = __raw_readl(pll->con_reg);
515
513
pll_con1 = __raw_readl(pll->con_reg + 4);
516
-
mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
514
+
mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ?
515
+
PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK);
517
516
pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
518
517
sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
519
518
kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK :
520
519
pll_con1 & PLL46XX_KDIV_MASK;
521
520
522
-
shift = pll->type == pll_4600 ? 16 : 10;
521
+
shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10;
522
+
523
523
fvco *= (mdiv << shift) + kdiv;
524
524
do_div(fvco, (pdiv << sdiv));
525
525
fvco >>= shift;
···
577
573
lock = 0xffff;
578
574
579
575
/* Set PLL PMS and VSEL values. */
580
-
con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
576
+
if (pll->type == pll_1460x) {
577
+
con0 &= ~((PLL1460X_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
578
+
(PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) |
579
+
(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT));
580
+
} else {
581
+
con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
581
582
(PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) |
582
583
(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT) |
583
584
(PLL46XX_VSEL_MASK << PLL46XX_VSEL_SHIFT));
585
+
con0 |= rate->vsel << PLL46XX_VSEL_SHIFT;
586
+
}
587
+
584
588
con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) |
585
589
(rate->pdiv << PLL46XX_PDIV_SHIFT) |
586
-
(rate->sdiv << PLL46XX_SDIV_SHIFT) |
587
-
(rate->vsel << PLL46XX_VSEL_SHIFT);
590
+
(rate->sdiv << PLL46XX_SDIV_SHIFT);
588
591
589
592
/* Set PLL K, MFR and MRR values. */
590
593
con1 = __raw_readl(pll->con_reg + 0x4);
···
1201
1190
/* clk_ops for 35xx and 2550 are similar */
1202
1191
case pll_35xx:
1203
1192
case pll_2550:
1193
+
case pll_1450x:
1194
+
case pll_1451x:
1195
+
case pll_1452x:
1204
1196
if (!pll->rate_table)
1205
1197
init.ops = &samsung_pll35xx_clk_min_ops;
1206
1198
else
···
1237
1223
case pll_4600:
1238
1224
case pll_4650:
1239
1225
case pll_4650c:
1226
+
case pll_1460x:
1240
1227
if (!pll->rate_table)
1241
1228
init.ops = &samsung_pll46xx_clk_min_ops;
1242
1229
else
+4
drivers/clk/samsung/clk-pll.h
+4
drivers/clk/samsung/clk-pll.h
+100
-2
drivers/clk/samsung/clk.c
+100
-2
drivers/clk/samsung/clk.c
···
11
11
* clock framework for Samsung platforms.
12
12
*/
13
13
14
+
#include <linux/of_address.h>
14
15
#include <linux/syscore_ops.h>
16
+
15
17
#include "clk.h"
18
+
19
+
static LIST_HEAD(clock_reg_cache_list);
16
20
17
21
void samsung_clk_save(void __iomem *base,
18
22
struct samsung_clk_reg_dump *rd,
···
285
281
* obtain the clock speed of all external fixed clock sources from device
286
282
* tree and register it
287
283
*/
288
-
#ifdef CONFIG_OF
289
284
void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx,
290
285
struct samsung_fixed_rate_clock *fixed_rate_clk,
291
286
unsigned int nr_fixed_rate_clk,
···
301
298
}
302
299
samsung_clk_register_fixed_rate(ctx, fixed_rate_clk, nr_fixed_rate_clk);
303
300
}
304
-
#endif
305
301
306
302
/* utility function to get the rate of a specified clock */
307
303
unsigned long _get_rate(const char *clk_name)
···
314
312
}
315
313
316
314
return clk_get_rate(clk);
315
+
}
316
+
317
+
#ifdef CONFIG_PM_SLEEP
318
+
static int samsung_clk_suspend(void)
319
+
{
320
+
struct samsung_clock_reg_cache *reg_cache;
321
+
322
+
list_for_each_entry(reg_cache, &clock_reg_cache_list, node)
323
+
samsung_clk_save(reg_cache->reg_base, reg_cache->rdump,
324
+
reg_cache->rd_num);
325
+
return 0;
326
+
}
327
+
328
+
static void samsung_clk_resume(void)
329
+
{
330
+
struct samsung_clock_reg_cache *reg_cache;
331
+
332
+
list_for_each_entry(reg_cache, &clock_reg_cache_list, node)
333
+
samsung_clk_restore(reg_cache->reg_base, reg_cache->rdump,
334
+
reg_cache->rd_num);
335
+
}
336
+
337
+
static struct syscore_ops samsung_clk_syscore_ops = {
338
+
.suspend = samsung_clk_suspend,
339
+
.resume = samsung_clk_resume,
340
+
};
341
+
342
+
static void samsung_clk_sleep_init(void __iomem *reg_base,
343
+
const unsigned long *rdump,
344
+
unsigned long nr_rdump)
345
+
{
346
+
struct samsung_clock_reg_cache *reg_cache;
347
+
348
+
reg_cache = kzalloc(sizeof(struct samsung_clock_reg_cache),
349
+
GFP_KERNEL);
350
+
if (!reg_cache)
351
+
panic("could not allocate register reg_cache.\n");
352
+
reg_cache->rdump = samsung_clk_alloc_reg_dump(rdump, nr_rdump);
353
+
354
+
if (!reg_cache->rdump)
355
+
panic("could not allocate register dump storage.\n");
356
+
357
+
if (list_empty(&clock_reg_cache_list))
358
+
register_syscore_ops(&samsung_clk_syscore_ops);
359
+
360
+
reg_cache->reg_base = reg_base;
361
+
reg_cache->rd_num = nr_rdump;
362
+
list_add_tail(®_cache->node, &clock_reg_cache_list);
363
+
}
364
+
365
+
#else
366
+
static void samsung_clk_sleep_init(void __iomem *reg_base,
367
+
const unsigned long *rdump,
368
+
unsigned long nr_rdump) {}
369
+
#endif
370
+
371
+
/*
372
+
* Common function which registers plls, muxes, dividers and gates
373
+
* for each CMU. It also add CMU register list to register cache.
374
+
*/
375
+
void __init samsung_cmu_register_one(struct device_node *np,
376
+
struct samsung_cmu_info *cmu)
377
+
{
378
+
void __iomem *reg_base;
379
+
struct samsung_clk_provider *ctx;
380
+
381
+
reg_base = of_iomap(np, 0);
382
+
if (!reg_base)
383
+
panic("%s: failed to map registers\n", __func__);
384
+
385
+
ctx = samsung_clk_init(np, reg_base, cmu->nr_clk_ids);
386
+
if (!ctx)
387
+
panic("%s: unable to alllocate ctx\n", __func__);
388
+
389
+
if (cmu->pll_clks)
390
+
samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks,
391
+
reg_base);
392
+
if (cmu->mux_clks)
393
+
samsung_clk_register_mux(ctx, cmu->mux_clks,
394
+
cmu->nr_mux_clks);
395
+
if (cmu->div_clks)
396
+
samsung_clk_register_div(ctx, cmu->div_clks, cmu->nr_div_clks);
397
+
if (cmu->gate_clks)
398
+
samsung_clk_register_gate(ctx, cmu->gate_clks,
399
+
cmu->nr_gate_clks);
400
+
if (cmu->fixed_clks)
401
+
samsung_clk_register_fixed_rate(ctx, cmu->fixed_clks,
402
+
cmu->nr_fixed_clks);
403
+
if (cmu->fixed_factor_clks)
404
+
samsung_clk_register_fixed_factor(ctx, cmu->fixed_factor_clks,
405
+
cmu->nr_fixed_factor_clks);
406
+
if (cmu->clk_regs)
407
+
samsung_clk_sleep_init(reg_base, cmu->clk_regs,
408
+
cmu->nr_clk_regs);
409
+
410
+
samsung_clk_of_add_provider(np, ctx);
317
411
}
+38
-5
drivers/clk/samsung/clk.h
+38
-5
drivers/clk/samsung/clk.h
···
13
13
#ifndef __SAMSUNG_CLK_H
14
14
#define __SAMSUNG_CLK_H
15
15
16
-
#include <linux/clk.h>
17
16
#include <linux/clkdev.h>
18
-
#include <linux/io.h>
19
17
#include <linux/clk-provider.h>
20
-
#include <linux/of.h>
21
-
#include <linux/of_address.h>
22
18
#include "clk-pll.h"
23
19
24
20
/**
25
21
* struct samsung_clk_provider: information about clock provider
26
22
* @reg_base: virtual address for the register base.
27
23
* @clk_data: holds clock related data like clk* and number of clocks.
28
-
* @lock: maintains exclusion bwtween callbacks for a given clock-provider.
24
+
* @lock: maintains exclusion between callbacks for a given clock-provider.
29
25
*/
30
26
struct samsung_clk_provider {
31
27
void __iomem *reg_base;
···
320
324
__PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE, \
321
325
_lock, _con, _rtable, _alias)
322
326
327
+
struct samsung_clock_reg_cache {
328
+
struct list_head node;
329
+
void __iomem *reg_base;
330
+
struct samsung_clk_reg_dump *rdump;
331
+
unsigned int rd_num;
332
+
};
333
+
334
+
struct samsung_cmu_info {
335
+
/* list of pll clocks and respective count */
336
+
struct samsung_pll_clock *pll_clks;
337
+
unsigned int nr_pll_clks;
338
+
/* list of mux clocks and respective count */
339
+
struct samsung_mux_clock *mux_clks;
340
+
unsigned int nr_mux_clks;
341
+
/* list of div clocks and respective count */
342
+
struct samsung_div_clock *div_clks;
343
+
unsigned int nr_div_clks;
344
+
/* list of gate clocks and respective count */
345
+
struct samsung_gate_clock *gate_clks;
346
+
unsigned int nr_gate_clks;
347
+
/* list of fixed clocks and respective count */
348
+
struct samsung_fixed_rate_clock *fixed_clks;
349
+
unsigned int nr_fixed_clks;
350
+
/* list of fixed factor clocks and respective count */
351
+
struct samsung_fixed_factor_clock *fixed_factor_clks;
352
+
unsigned int nr_fixed_factor_clks;
353
+
/* total number of clocks with IDs assigned*/
354
+
unsigned int nr_clk_ids;
355
+
356
+
/* list and number of clocks registers */
357
+
unsigned long *clk_regs;
358
+
unsigned int nr_clk_regs;
359
+
};
360
+
323
361
extern struct samsung_clk_provider *__init samsung_clk_init(
324
362
struct device_node *np, void __iomem *base,
325
363
unsigned long nr_clks);
···
391
361
extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
392
362
struct samsung_pll_clock *pll_list,
393
363
unsigned int nr_clk, void __iomem *base);
364
+
365
+
extern void __init samsung_cmu_register_one(struct device_node *,
366
+
struct samsung_cmu_info *);
394
367
395
368
extern unsigned long _get_rate(const char *clk_name);
396
369
+101
-12
drivers/clk/shmobile/clk-div6.c
+101
-12
drivers/clk/shmobile/clk-div6.c
···
32
32
struct clk_hw hw;
33
33
void __iomem *reg;
34
34
unsigned int div;
35
+
u32 src_shift;
36
+
u32 src_width;
37
+
u8 *parents;
35
38
};
36
39
37
40
#define to_div6_clock(_hw) container_of(_hw, struct div6_clock, hw)
···
42
39
static int cpg_div6_clock_enable(struct clk_hw *hw)
43
40
{
44
41
struct div6_clock *clock = to_div6_clock(hw);
42
+
u32 val;
45
43
46
-
clk_writel(CPG_DIV6_DIV(clock->div - 1), clock->reg);
44
+
val = (clk_readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP))
45
+
| CPG_DIV6_DIV(clock->div - 1);
46
+
clk_writel(val, clock->reg);
47
47
48
48
return 0;
49
49
}
···
58
52
/* DIV6 clocks require the divisor field to be non-zero when stopping
59
53
* the clock.
60
54
*/
61
-
clk_writel(CPG_DIV6_CKSTP | CPG_DIV6_DIV(CPG_DIV6_DIV_MASK),
55
+
clk_writel(clk_readl(clock->reg) | CPG_DIV6_CKSTP | CPG_DIV6_DIV_MASK,
62
56
clock->reg);
63
57
}
64
58
···
100
94
{
101
95
struct div6_clock *clock = to_div6_clock(hw);
102
96
unsigned int div = cpg_div6_clock_calc_div(rate, parent_rate);
97
+
u32 val;
103
98
104
99
clock->div = div;
105
100
101
+
val = clk_readl(clock->reg) & ~CPG_DIV6_DIV_MASK;
106
102
/* Only program the new divisor if the clock isn't stopped. */
107
-
if (!(clk_readl(clock->reg) & CPG_DIV6_CKSTP))
108
-
clk_writel(CPG_DIV6_DIV(clock->div - 1), clock->reg);
103
+
if (!(val & CPG_DIV6_CKSTP))
104
+
clk_writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg);
105
+
106
+
return 0;
107
+
}
108
+
109
+
static u8 cpg_div6_clock_get_parent(struct clk_hw *hw)
110
+
{
111
+
struct div6_clock *clock = to_div6_clock(hw);
112
+
unsigned int i;
113
+
u8 hw_index;
114
+
115
+
if (clock->src_width == 0)
116
+
return 0;
117
+
118
+
hw_index = (clk_readl(clock->reg) >> clock->src_shift) &
119
+
(BIT(clock->src_width) - 1);
120
+
for (i = 0; i < __clk_get_num_parents(hw->clk); i++) {
121
+
if (clock->parents[i] == hw_index)
122
+
return i;
123
+
}
124
+
125
+
pr_err("%s: %s DIV6 clock set to invalid parent %u\n",
126
+
__func__, __clk_get_name(hw->clk), hw_index);
127
+
return 0;
128
+
}
129
+
130
+
static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index)
131
+
{
132
+
struct div6_clock *clock = to_div6_clock(hw);
133
+
u8 hw_index;
134
+
u32 mask;
135
+
136
+
if (index >= __clk_get_num_parents(hw->clk))
137
+
return -EINVAL;
138
+
139
+
mask = ~((BIT(clock->src_width) - 1) << clock->src_shift);
140
+
hw_index = clock->parents[index];
141
+
142
+
clk_writel((clk_readl(clock->reg) & mask) |
143
+
(hw_index << clock->src_shift), clock->reg);
109
144
110
145
return 0;
111
146
}
···
155
108
.enable = cpg_div6_clock_enable,
156
109
.disable = cpg_div6_clock_disable,
157
110
.is_enabled = cpg_div6_clock_is_enabled,
111
+
.get_parent = cpg_div6_clock_get_parent,
112
+
.set_parent = cpg_div6_clock_set_parent,
158
113
.recalc_rate = cpg_div6_clock_recalc_rate,
159
114
.round_rate = cpg_div6_clock_round_rate,
160
115
.set_rate = cpg_div6_clock_set_rate,
···
164
115
165
116
static void __init cpg_div6_clock_init(struct device_node *np)
166
117
{
118
+
unsigned int num_parents, valid_parents;
119
+
const char **parent_names;
167
120
struct clk_init_data init;
168
121
struct div6_clock *clock;
169
-
const char *parent_name;
170
122
const char *name;
171
123
struct clk *clk;
124
+
unsigned int i;
172
125
int ret;
173
126
174
127
clock = kzalloc(sizeof(*clock), GFP_KERNEL);
175
-
if (!clock) {
176
-
pr_err("%s: failed to allocate %s DIV6 clock\n",
128
+
if (!clock)
129
+
return;
130
+
131
+
num_parents = of_clk_get_parent_count(np);
132
+
if (num_parents < 1) {
133
+
pr_err("%s: no parent found for %s DIV6 clock\n",
177
134
__func__, np->name);
178
135
return;
179
136
}
137
+
138
+
clock->parents = kmalloc_array(num_parents, sizeof(*clock->parents),
139
+
GFP_KERNEL);
140
+
parent_names = kmalloc_array(num_parents, sizeof(*parent_names),
141
+
GFP_KERNEL);
142
+
if (!parent_names)
143
+
return;
180
144
181
145
/* Remap the clock register and read the divisor. Disabling the
182
146
* clock overwrites the divisor, so we need to cache its value for the
···
212
150
goto error;
213
151
}
214
152
215
-
parent_name = of_clk_get_parent_name(np, 0);
216
-
if (parent_name == NULL) {
217
-
pr_err("%s: failed to get %s DIV6 clock parent name\n",
153
+
154
+
for (i = 0, valid_parents = 0; i < num_parents; i++) {
155
+
const char *name = of_clk_get_parent_name(np, i);
156
+
157
+
if (name) {
158
+
parent_names[valid_parents] = name;
159
+
clock->parents[valid_parents] = i;
160
+
valid_parents++;
161
+
}
162
+
}
163
+
164
+
switch (num_parents) {
165
+
case 1:
166
+
/* fixed parent clock */
167
+
clock->src_shift = clock->src_width = 0;
168
+
break;
169
+
case 4:
170
+
/* clock with EXSRC bits 6-7 */
171
+
clock->src_shift = 6;
172
+
clock->src_width = 2;
173
+
break;
174
+
case 8:
175
+
/* VCLK with EXSRC bits 12-14 */
176
+
clock->src_shift = 12;
177
+
clock->src_width = 3;
178
+
break;
179
+
default:
180
+
pr_err("%s: invalid number of parents for DIV6 clock %s\n",
218
181
__func__, np->name);
219
182
goto error;
220
183
}
···
248
161
init.name = name;
249
162
init.ops = &cpg_div6_clock_ops;
250
163
init.flags = CLK_IS_BASIC;
251
-
init.parent_names = &parent_name;
252
-
init.num_parents = 1;
164
+
init.parent_names = parent_names;
165
+
init.num_parents = valid_parents;
253
166
254
167
clock->hw.init = &init;
255
168
···
262
175
263
176
of_clk_add_provider(np, of_clk_src_simple_get, clk);
264
177
178
+
kfree(parent_names);
265
179
return;
266
180
267
181
error:
268
182
if (clock->reg)
269
183
iounmap(clock->reg);
184
+
kfree(parent_names);
270
185
kfree(clock);
271
186
}
272
187
CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init);
+1
drivers/clk/sunxi/Makefile
+1
drivers/clk/sunxi/Makefile
+6
-1
drivers/clk/sunxi/clk-a20-gmac.c
+6
-1
drivers/clk/sunxi/clk-a20-gmac.c
···
53
53
#define SUN7I_A20_GMAC_MASK 0x3
54
54
#define SUN7I_A20_GMAC_PARENTS 2
55
55
56
+
static u32 sun7i_a20_gmac_mux_table[SUN7I_A20_GMAC_PARENTS] = {
57
+
0x00, /* Select mii_phy_tx_clk */
58
+
0x02, /* Select gmac_int_tx_clk */
59
+
};
60
+
56
61
static void __init sun7i_a20_gmac_clk_setup(struct device_node *node)
57
62
{
58
63
struct clk *clk;
···
95
90
gate->lock = &gmac_lock;
96
91
mux->reg = reg;
97
92
mux->mask = SUN7I_A20_GMAC_MASK;
98
-
mux->flags = CLK_MUX_INDEX_BIT;
93
+
mux->table = sun7i_a20_gmac_mux_table;
99
94
mux->lock = &gmac_lock;
100
95
101
96
clk = clk_register_composite(NULL, clk_name,
+3
-3
drivers/clk/sunxi/clk-factors.c
+3
-3
drivers/clk/sunxi/clk-factors.c
···
81
81
82
82
static long clk_factors_determine_rate(struct clk_hw *hw, unsigned long rate,
83
83
unsigned long *best_parent_rate,
84
-
struct clk **best_parent_p)
84
+
struct clk_hw **best_parent_p)
85
85
{
86
86
struct clk *clk = hw->clk, *parent, *best_parent = NULL;
87
87
int i, num_parents;
···
108
108
}
109
109
110
110
if (best_parent)
111
-
*best_parent_p = best_parent;
111
+
*best_parent_p = __clk_get_hw(best_parent);
112
112
*best_parent_rate = best;
113
113
114
114
return best_child_rate;
···
224
224
/* set up gate properties */
225
225
mux->reg = reg;
226
226
mux->shift = data->mux;
227
-
mux->mask = SUNXI_FACTORS_MUX_MASK;
227
+
mux->mask = data->muxmask;
228
228
mux->lock = factors->lock;
229
229
mux_hw = &mux->hw;
230
230
}
+1
-2
drivers/clk/sunxi/clk-factors.h
+1
-2
drivers/clk/sunxi/clk-factors.h
···
7
7
8
8
#define SUNXI_FACTORS_NOT_APPLICABLE (0)
9
9
10
-
#define SUNXI_FACTORS_MUX_MASK 0x3
11
-
12
10
struct clk_factors_config {
13
11
u8 nshift;
14
12
u8 nwidth;
···
22
24
struct factors_data {
23
25
int enable;
24
26
int mux;
27
+
int muxmask;
25
28
struct clk_factors_config *table;
26
29
void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
27
30
const char *name;
+1
drivers/clk/sunxi/clk-mod0.c
+1
drivers/clk/sunxi/clk-mod0.c
+2
-2
drivers/clk/sunxi/clk-sun6i-ar100.c
+2
-2
drivers/clk/sunxi/clk-sun6i-ar100.c
···
46
46
47
47
static long ar100_determine_rate(struct clk_hw *hw, unsigned long rate,
48
48
unsigned long *best_parent_rate,
49
-
struct clk **best_parent_clk)
49
+
struct clk_hw **best_parent_clk)
50
50
{
51
51
int nparents = __clk_get_num_parents(hw->clk);
52
52
long best_rate = -EINVAL;
···
100
100
101
101
tmp_rate = (parent_rate >> shift) / div;
102
102
if (!*best_parent_clk || tmp_rate > best_rate) {
103
-
*best_parent_clk = parent;
103
+
*best_parent_clk = __clk_get_hw(parent);
104
104
*best_parent_rate = parent_rate;
105
105
best_rate = tmp_rate;
106
106
}
+1
drivers/clk/sunxi/clk-sun8i-mbus.c
+1
drivers/clk/sunxi/clk-sun8i-mbus.c
+271
drivers/clk/sunxi/clk-sun9i-core.c
+271
drivers/clk/sunxi/clk-sun9i-core.c
···
1
+
/*
2
+
* Copyright 2014 Chen-Yu Tsai
3
+
*
4
+
* Chen-Yu Tsai <wens@csie.org>
5
+
*
6
+
* This program is free software; you can redistribute it and/or modify
7
+
* it under the terms of the GNU General Public License as published by
8
+
* the Free Software Foundation; either version 2 of the License, or
9
+
* (at your option) any later version.
10
+
*
11
+
* This program is distributed in the hope that it will be useful,
12
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
13
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14
+
* GNU General Public License for more details.
15
+
*/
16
+
17
+
#include <linux/clk-provider.h>
18
+
#include <linux/clkdev.h>
19
+
#include <linux/of.h>
20
+
#include <linux/of_address.h>
21
+
#include <linux/log2.h>
22
+
23
+
#include "clk-factors.h"
24
+
25
+
26
+
/**
27
+
* sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL1
28
+
* PLL4 rate is calculated as follows
29
+
* rate = (parent_rate * n >> p) / (m + 1);
30
+
* parent_rate is always 24Mhz
31
+
*
32
+
* p and m are named div1 and div2 in Allwinner's SDK
33
+
*/
34
+
35
+
static void sun9i_a80_get_pll4_factors(u32 *freq, u32 parent_rate,
36
+
u8 *n, u8 *k, u8 *m, u8 *p)
37
+
{
38
+
int div;
39
+
40
+
/* Normalize value to a 6M multiple */
41
+
div = DIV_ROUND_UP(*freq, 6000000);
42
+
43
+
/* divs above 256 cannot be odd */
44
+
if (div > 256)
45
+
div = round_up(div, 2);
46
+
47
+
/* divs above 512 must be a multiple of 4 */
48
+
if (div > 512)
49
+
div = round_up(div, 4);
50
+
51
+
*freq = 6000000 * div;
52
+
53
+
/* we were called to round the frequency, we can now return */
54
+
if (n == NULL)
55
+
return;
56
+
57
+
/* p will be 1 for divs under 512 */
58
+
if (div < 512)
59
+
*p = 1;
60
+
else
61
+
*p = 0;
62
+
63
+
/* m will be 1 if div is odd */
64
+
if (div & 1)
65
+
*m = 1;
66
+
else
67
+
*m = 0;
68
+
69
+
/* calculate a suitable n based on m and p */
70
+
*n = div / (*p + 1) / (*m + 1);
71
+
}
72
+
73
+
static struct clk_factors_config sun9i_a80_pll4_config = {
74
+
.mshift = 18,
75
+
.mwidth = 1,
76
+
.nshift = 8,
77
+
.nwidth = 8,
78
+
.pshift = 16,
79
+
.pwidth = 1,
80
+
};
81
+
82
+
static const struct factors_data sun9i_a80_pll4_data __initconst = {
83
+
.enable = 31,
84
+
.table = &sun9i_a80_pll4_config,
85
+
.getter = sun9i_a80_get_pll4_factors,
86
+
};
87
+
88
+
static DEFINE_SPINLOCK(sun9i_a80_pll4_lock);
89
+
90
+
static void __init sun9i_a80_pll4_setup(struct device_node *node)
91
+
{
92
+
sunxi_factors_register(node, &sun9i_a80_pll4_data, &sun9i_a80_pll4_lock);
93
+
}
94
+
CLK_OF_DECLARE(sun9i_a80_pll4, "allwinner,sun9i-a80-pll4-clk", sun9i_a80_pll4_setup);
95
+
96
+
97
+
/**
98
+
* sun9i_a80_get_gt_factors() - calculates m factor for GT
99
+
* GT rate is calculated as follows
100
+
* rate = parent_rate / (m + 1);
101
+
*/
102
+
103
+
static void sun9i_a80_get_gt_factors(u32 *freq, u32 parent_rate,
104
+
u8 *n, u8 *k, u8 *m, u8 *p)
105
+
{
106
+
u32 div;
107
+
108
+
if (parent_rate < *freq)
109
+
*freq = parent_rate;
110
+
111
+
div = DIV_ROUND_UP(parent_rate, *freq);
112
+
113
+
/* maximum divider is 4 */
114
+
if (div > 4)
115
+
div = 4;
116
+
117
+
*freq = parent_rate / div;
118
+
119
+
/* we were called to round the frequency, we can now return */
120
+
if (!m)
121
+
return;
122
+
123
+
*m = div;
124
+
}
125
+
126
+
static struct clk_factors_config sun9i_a80_gt_config = {
127
+
.mshift = 0,
128
+
.mwidth = 2,
129
+
};
130
+
131
+
static const struct factors_data sun9i_a80_gt_data __initconst = {
132
+
.mux = 24,
133
+
.muxmask = BIT(1) | BIT(0),
134
+
.table = &sun9i_a80_gt_config,
135
+
.getter = sun9i_a80_get_gt_factors,
136
+
};
137
+
138
+
static DEFINE_SPINLOCK(sun9i_a80_gt_lock);
139
+
140
+
static void __init sun9i_a80_gt_setup(struct device_node *node)
141
+
{
142
+
struct clk *gt = sunxi_factors_register(node, &sun9i_a80_gt_data,
143
+
&sun9i_a80_gt_lock);
144
+
145
+
/* The GT bus clock needs to be always enabled */
146
+
__clk_get(gt);
147
+
clk_prepare_enable(gt);
148
+
}
149
+
CLK_OF_DECLARE(sun9i_a80_gt, "allwinner,sun9i-a80-gt-clk", sun9i_a80_gt_setup);
150
+
151
+
152
+
/**
153
+
* sun9i_a80_get_ahb_factors() - calculates p factor for AHB0/1/2
154
+
* AHB rate is calculated as follows
155
+
* rate = parent_rate >> p;
156
+
*/
157
+
158
+
static void sun9i_a80_get_ahb_factors(u32 *freq, u32 parent_rate,
159
+
u8 *n, u8 *k, u8 *m, u8 *p)
160
+
{
161
+
u32 _p;
162
+
163
+
if (parent_rate < *freq)
164
+
*freq = parent_rate;
165
+
166
+
_p = order_base_2(DIV_ROUND_UP(parent_rate, *freq));
167
+
168
+
/* maximum p is 3 */
169
+
if (_p > 3)
170
+
_p = 3;
171
+
172
+
*freq = parent_rate >> _p;
173
+
174
+
/* we were called to round the frequency, we can now return */
175
+
if (!p)
176
+
return;
177
+
178
+
*p = _p;
179
+
}
180
+
181
+
static struct clk_factors_config sun9i_a80_ahb_config = {
182
+
.pshift = 0,
183
+
.pwidth = 2,
184
+
};
185
+
186
+
static const struct factors_data sun9i_a80_ahb_data __initconst = {
187
+
.mux = 24,
188
+
.muxmask = BIT(1) | BIT(0),
189
+
.table = &sun9i_a80_ahb_config,
190
+
.getter = sun9i_a80_get_ahb_factors,
191
+
};
192
+
193
+
static DEFINE_SPINLOCK(sun9i_a80_ahb_lock);
194
+
195
+
static void __init sun9i_a80_ahb_setup(struct device_node *node)
196
+
{
197
+
sunxi_factors_register(node, &sun9i_a80_ahb_data, &sun9i_a80_ahb_lock);
198
+
}
199
+
CLK_OF_DECLARE(sun9i_a80_ahb, "allwinner,sun9i-a80-ahb-clk", sun9i_a80_ahb_setup);
200
+
201
+
202
+
static const struct factors_data sun9i_a80_apb0_data __initconst = {
203
+
.mux = 24,
204
+
.muxmask = BIT(0),
205
+
.table = &sun9i_a80_ahb_config,
206
+
.getter = sun9i_a80_get_ahb_factors,
207
+
};
208
+
209
+
static DEFINE_SPINLOCK(sun9i_a80_apb0_lock);
210
+
211
+
static void __init sun9i_a80_apb0_setup(struct device_node *node)
212
+
{
213
+
sunxi_factors_register(node, &sun9i_a80_apb0_data, &sun9i_a80_apb0_lock);
214
+
}
215
+
CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-clk", sun9i_a80_apb0_setup);
216
+
217
+
218
+
/**
219
+
* sun9i_a80_get_apb1_factors() - calculates m, p factors for APB1
220
+
* APB1 rate is calculated as follows
221
+
* rate = (parent_rate >> p) / (m + 1);
222
+
*/
223
+
224
+
static void sun9i_a80_get_apb1_factors(u32 *freq, u32 parent_rate,
225
+
u8 *n, u8 *k, u8 *m, u8 *p)
226
+
{
227
+
u32 div;
228
+
u8 calcm, calcp;
229
+
230
+
if (parent_rate < *freq)
231
+
*freq = parent_rate;
232
+
233
+
div = DIV_ROUND_UP(parent_rate, *freq);
234
+
235
+
/* Highest possible divider is 256 (p = 3, m = 31) */
236
+
if (div > 256)
237
+
div = 256;
238
+
239
+
calcp = order_base_2(div);
240
+
calcm = (parent_rate >> calcp) - 1;
241
+
*freq = (parent_rate >> calcp) / (calcm + 1);
242
+
243
+
/* we were called to round the frequency, we can now return */
244
+
if (n == NULL)
245
+
return;
246
+
247
+
*m = calcm;
248
+
*p = calcp;
249
+
}
250
+
251
+
static struct clk_factors_config sun9i_a80_apb1_config = {
252
+
.mshift = 0,
253
+
.mwidth = 5,
254
+
.pshift = 16,
255
+
.pwidth = 2,
256
+
};
257
+
258
+
static const struct factors_data sun9i_a80_apb1_data __initconst = {
259
+
.mux = 24,
260
+
.muxmask = BIT(0),
261
+
.table = &sun9i_a80_apb1_config,
262
+
.getter = sun9i_a80_get_apb1_factors,
263
+
};
264
+
265
+
static DEFINE_SPINLOCK(sun9i_a80_apb1_lock);
266
+
267
+
static void __init sun9i_a80_apb1_setup(struct device_node *node)
268
+
{
269
+
sunxi_factors_register(node, &sun9i_a80_apb1_data, &sun9i_a80_apb1_lock);
270
+
}
271
+
CLK_OF_DECLARE(sun9i_a80_apb1, "allwinner,sun9i-a80-apb1-clk", sun9i_a80_apb1_setup);
+59
-26
drivers/clk/sunxi/clk-sunxi.c
+59
-26
drivers/clk/sunxi/clk-sunxi.c
···
245
245
}
246
246
247
247
/**
248
-
* sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6
249
-
* PLL6 rate is calculated as follows
250
-
* rate = parent_rate * n * (k + 1) / 2
248
+
* sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6x2
249
+
* PLL6x2 rate is calculated as follows
250
+
* rate = parent_rate * (n + 1) * (k + 1)
251
251
* parent_rate is always 24Mhz
252
252
*/
253
253
···
256
256
{
257
257
u8 div;
258
258
259
-
/*
260
-
* We always have 24MHz / 2, so we can just say that our
261
-
* parent clock is 12MHz.
262
-
*/
263
-
parent_rate = parent_rate / 2;
264
-
265
-
/* Normalize value to a parent_rate multiple (24M / 2) */
259
+
/* Normalize value to a parent_rate multiple (24M) */
266
260
div = *freq / parent_rate;
267
261
*freq = parent_rate * div;
268
262
···
268
274
if (*k > 3)
269
275
*k = 3;
270
276
271
-
*n = DIV_ROUND_UP(div, (*k+1));
277
+
*n = DIV_ROUND_UP(div, (*k+1)) - 1;
272
278
}
273
279
274
280
/**
···
439
445
.nwidth = 5,
440
446
.kshift = 4,
441
447
.kwidth = 2,
448
+
.n_start = 1,
442
449
};
443
450
444
451
static struct clk_factors_config sun4i_apb1_config = {
···
499
504
.enable = 31,
500
505
.table = &sun6i_a31_pll6_config,
501
506
.getter = sun6i_a31_get_pll6_factors,
507
+
.name = "pll6x2",
502
508
};
503
509
504
510
static const struct factors_data sun4i_apb1_data __initconst = {
511
+
.mux = 24,
512
+
.muxmask = BIT(1) | BIT(0),
505
513
.table = &sun4i_apb1_config,
506
514
.getter = sun4i_get_apb1_factors,
507
515
};
···
512
514
static const struct factors_data sun7i_a20_out_data __initconst = {
513
515
.enable = 31,
514
516
.mux = 24,
517
+
.muxmask = BIT(1) | BIT(0),
515
518
.table = &sun7i_a20_out_config,
516
519
.getter = sun7i_a20_get_out_factors,
517
520
};
···
541
542
542
543
static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
543
544
.shift = 12,
544
-
};
545
-
546
-
static const struct mux_data sun4i_apb1_mux_data __initconst = {
547
-
.shift = 24,
548
545
};
549
546
550
547
static void __init sunxi_mux_clk_setup(struct device_node *node,
···
626
631
.pow = 1,
627
632
.width = 2,
628
633
.table = sun4i_apb0_table,
629
-
};
630
-
631
-
static const struct div_data sun6i_a31_apb2_div_data __initconst = {
632
-
.shift = 0,
633
-
.pow = 0,
634
-
.width = 4,
635
634
};
636
635
637
636
static void __init sunxi_divider_clk_setup(struct device_node *node,
···
746
757
.mask = {0x25386742, 0x2505111},
747
758
};
748
759
760
+
static const struct gates_data sun9i_a80_ahb0_gates_data __initconst = {
761
+
.mask = {0xF5F12B},
762
+
};
763
+
764
+
static const struct gates_data sun9i_a80_ahb1_gates_data __initconst = {
765
+
.mask = {0x1E20003},
766
+
};
767
+
768
+
static const struct gates_data sun9i_a80_ahb2_gates_data __initconst = {
769
+
.mask = {0x9B7},
770
+
};
771
+
749
772
static const struct gates_data sun4i_apb0_gates_data __initconst = {
750
773
.mask = {0x4EF},
751
774
};
···
772
771
773
772
static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
774
773
.mask = { 0x4ff },
774
+
};
775
+
776
+
static const struct gates_data sun9i_a80_apb0_gates_data __initconst = {
777
+
.mask = {0xEB822},
775
778
};
776
779
777
780
static const struct gates_data sun4i_apb1_gates_data __initconst = {
···
804
799
805
800
static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
806
801
.mask = { 0xff80ff },
802
+
};
803
+
804
+
static const struct gates_data sun9i_a80_apb1_gates_data __initconst = {
805
+
.mask = {0x3F001F},
807
806
};
808
807
809
808
static const struct gates_data sun8i_a23_apb2_gates_data __initconst = {
···
902
893
903
894
struct divs_data {
904
895
const struct factors_data *factors; /* data for the factor clock */
896
+
int ndivs; /* number of children */
905
897
struct {
906
898
u8 fixed; /* is it a fixed divisor? if not... */
907
899
struct clk_div_table *table; /* is it a table based divisor? */
···
922
912
923
913
static const struct divs_data pll5_divs_data __initconst = {
924
914
.factors = &sun4i_pll5_data,
915
+
.ndivs = 2,
925
916
.div = {
926
917
{ .shift = 0, .pow = 0, }, /* M, DDR */
927
918
{ .shift = 16, .pow = 1, }, /* P, other */
···
931
920
932
921
static const struct divs_data pll6_divs_data __initconst = {
933
922
.factors = &sun4i_pll6_data,
923
+
.ndivs = 2,
934
924
.div = {
935
925
{ .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
936
926
{ .fixed = 2 }, /* P, other */
927
+
}
928
+
};
929
+
930
+
static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
931
+
.factors = &sun6i_a31_pll6_data,
932
+
.ndivs = 1,
933
+
.div = {
934
+
{ .fixed = 2 }, /* normal output */
937
935
}
938
936
};
939
937
···
970
950
struct clk_fixed_factor *fix_factor;
971
951
struct clk_divider *divider;
972
952
void __iomem *reg;
973
-
int i = 0;
953
+
int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
974
954
int flags, clkflags;
975
955
976
956
/* Set up factor clock that we will be dividing */
···
993
973
* our RAM clock! */
994
974
clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
995
975
996
-
for (i = 0; i < SUNXI_DIVS_MAX_QTY; i++) {
976
+
/* if number of children known, use it */
977
+
if (data->ndivs)
978
+
ndivs = data->ndivs;
979
+
980
+
for (i = 0; i < ndivs; i++) {
997
981
if (of_property_read_string_index(node, "clock-output-names",
998
982
i, &clk_name) != 0)
999
983
break;
···
1086
1062
{.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
1087
1063
{.compatible = "allwinner,sun8i-a23-pll1-clk", .data = &sun8i_a23_pll1_data,},
1088
1064
{.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
1089
-
{.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,},
1090
1065
{.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
1091
1066
{.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
1092
1067
{}
···
1097
1074
{.compatible = "allwinner,sun8i-a23-axi-clk", .data = &sun8i_a23_axi_data,},
1098
1075
{.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,},
1099
1076
{.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,},
1100
-
{.compatible = "allwinner,sun6i-a31-apb2-div-clk", .data = &sun6i_a31_apb2_div_data,},
1101
1077
{}
1102
1078
};
1103
1079
···
1104
1082
static const struct of_device_id clk_divs_match[] __initconst = {
1105
1083
{.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,},
1106
1084
{.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,},
1085
+
{.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_divs_data,},
1107
1086
{}
1108
1087
};
1109
1088
1110
1089
/* Matches for mux clocks */
1111
1090
static const struct of_device_id clk_mux_match[] __initconst = {
1112
1091
{.compatible = "allwinner,sun4i-a10-cpu-clk", .data = &sun4i_cpu_mux_data,},
1113
-
{.compatible = "allwinner,sun4i-a10-apb1-mux-clk", .data = &sun4i_apb1_mux_data,},
1114
1092
{.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
1115
1093
{}
1116
1094
};
···
1124
1102
{.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
1125
1103
{.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
1126
1104
{.compatible = "allwinner,sun8i-a23-ahb1-gates-clk", .data = &sun8i_a23_ahb1_gates_data,},
1105
+
{.compatible = "allwinner,sun9i-a80-ahb0-gates-clk", .data = &sun9i_a80_ahb0_gates_data,},
1106
+
{.compatible = "allwinner,sun9i-a80-ahb1-gates-clk", .data = &sun9i_a80_ahb1_gates_data,},
1107
+
{.compatible = "allwinner,sun9i-a80-ahb2-gates-clk", .data = &sun9i_a80_ahb2_gates_data,},
1127
1108
{.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
1128
1109
{.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
1129
1110
{.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
1130
1111
{.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
1112
+
{.compatible = "allwinner,sun9i-a80-apb0-gates-clk", .data = &sun9i_a80_apb0_gates_data,},
1131
1113
{.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
1132
1114
{.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
1133
1115
{.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
1134
1116
{.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
1135
1117
{.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
1136
1118
{.compatible = "allwinner,sun8i-a23-apb1-gates-clk", .data = &sun8i_a23_apb1_gates_data,},
1119
+
{.compatible = "allwinner,sun9i-a80-apb1-gates-clk", .data = &sun9i_a80_apb1_gates_data,},
1137
1120
{.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
1138
1121
{.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,},
1139
1122
{.compatible = "allwinner,sun4i-a10-usb-clk", .data = &sun4i_a10_usb_gates_data,},
···
1227
1200
}
1228
1201
CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
1229
1202
CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
1203
+
1204
+
static void __init sun9i_init_clocks(struct device_node *node)
1205
+
{
1206
+
sunxi_init_clocks(NULL, 0);
1207
+
}
1208
+
CLK_OF_DECLARE(sun9i_a80_clk_init, "allwinner,sun9i-a80", sun9i_init_clocks);
+360
include/dt-bindings/clock/exynos4415.h
+360
include/dt-bindings/clock/exynos4415.h
···
1
+
/*
2
+
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
3
+
* Author: Chanwoo Choi <cw00.choi@samsung.com>
4
+
*
5
+
* This program is free software; you can redistribute it and/or modify
6
+
* it under the terms of the GNU General Public License version 2 as
7
+
* published by the Free Software Foundation.
8
+
*
9
+
* Device Tree binding constants for Samsung Exynos4415 clock controllers.
10
+
*/
11
+
12
+
#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H
13
+
#define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H
14
+
15
+
/*
16
+
* Let each exported clock get a unique index, which is used on DT-enabled
17
+
* platforms to lookup the clock from a clock specifier. These indices are
18
+
* therefore considered an ABI and so must not be changed. This implies
19
+
* that new clocks should be added either in free spaces between clock groups
20
+
* or at the end.
21
+
*/
22
+
23
+
/*
24
+
* Main CMU
25
+
*/
26
+
27
+
#define CLK_OSCSEL 1
28
+
#define CLK_FIN_PLL 2
29
+
#define CLK_FOUT_APLL 3
30
+
#define CLK_FOUT_MPLL 4
31
+
#define CLK_FOUT_EPLL 5
32
+
#define CLK_FOUT_G3D_PLL 6
33
+
#define CLK_FOUT_ISP_PLL 7
34
+
#define CLK_FOUT_DISP_PLL 8
35
+
36
+
/* Muxes */
37
+
#define CLK_MOUT_MPLL_USER_L 16
38
+
#define CLK_MOUT_GDL 17
39
+
#define CLK_MOUT_MPLL_USER_R 18
40
+
#define CLK_MOUT_GDR 19
41
+
#define CLK_MOUT_EBI 20
42
+
#define CLK_MOUT_ACLK_200 21
43
+
#define CLK_MOUT_ACLK_160 22
44
+
#define CLK_MOUT_ACLK_100 23
45
+
#define CLK_MOUT_ACLK_266 24
46
+
#define CLK_MOUT_G3D_PLL 25
47
+
#define CLK_MOUT_EPLL 26
48
+
#define CLK_MOUT_EBI_1 27
49
+
#define CLK_MOUT_ISP_PLL 28
50
+
#define CLK_MOUT_DISP_PLL 29
51
+
#define CLK_MOUT_MPLL_USER_T 30
52
+
#define CLK_MOUT_ACLK_400_MCUISP 31
53
+
#define CLK_MOUT_G3D_PLLSRC 32
54
+
#define CLK_MOUT_CSIS1 33
55
+
#define CLK_MOUT_CSIS0 34
56
+
#define CLK_MOUT_CAM1 35
57
+
#define CLK_MOUT_FIMC3_LCLK 36
58
+
#define CLK_MOUT_FIMC2_LCLK 37
59
+
#define CLK_MOUT_FIMC1_LCLK 38
60
+
#define CLK_MOUT_FIMC0_LCLK 39
61
+
#define CLK_MOUT_MFC 40
62
+
#define CLK_MOUT_MFC_1 41
63
+
#define CLK_MOUT_MFC_0 42
64
+
#define CLK_MOUT_G3D 43
65
+
#define CLK_MOUT_G3D_1 44
66
+
#define CLK_MOUT_G3D_0 45
67
+
#define CLK_MOUT_MIPI0 46
68
+
#define CLK_MOUT_FIMD0 47
69
+
#define CLK_MOUT_TSADC_ISP 48
70
+
#define CLK_MOUT_UART_ISP 49
71
+
#define CLK_MOUT_SPI1_ISP 50
72
+
#define CLK_MOUT_SPI0_ISP 51
73
+
#define CLK_MOUT_PWM_ISP 52
74
+
#define CLK_MOUT_AUDIO0 53
75
+
#define CLK_MOUT_TSADC 54
76
+
#define CLK_MOUT_MMC2 55
77
+
#define CLK_MOUT_MMC1 56
78
+
#define CLK_MOUT_MMC0 57
79
+
#define CLK_MOUT_UART3 58
80
+
#define CLK_MOUT_UART2 59
81
+
#define CLK_MOUT_UART1 60
82
+
#define CLK_MOUT_UART0 61
83
+
#define CLK_MOUT_SPI2 62
84
+
#define CLK_MOUT_SPI1 63
85
+
#define CLK_MOUT_SPI0 64
86
+
#define CLK_MOUT_SPDIF 65
87
+
#define CLK_MOUT_AUDIO2 66
88
+
#define CLK_MOUT_AUDIO1 67
89
+
#define CLK_MOUT_MPLL_USER_C 68
90
+
#define CLK_MOUT_HPM 69
91
+
#define CLK_MOUT_CORE 70
92
+
#define CLK_MOUT_APLL 71
93
+
#define CLK_MOUT_PXLASYNC_CSIS1_FIMC 72
94
+
#define CLK_MOUT_PXLASYNC_CSIS0_FIMC 73
95
+
#define CLK_MOUT_JPEG 74
96
+
#define CLK_MOUT_JPEG1 75
97
+
#define CLK_MOUT_JPEG0 76
98
+
#define CLK_MOUT_ACLK_ISP0_300 77
99
+
#define CLK_MOUT_ACLK_ISP0_400 78
100
+
#define CLK_MOUT_ACLK_ISP0_300_USER 79
101
+
#define CLK_MOUT_ACLK_ISP1_300 80
102
+
#define CLK_MOUT_ACLK_ISP1_300_USER 81
103
+
#define CLK_MOUT_HDMI 82
104
+
105
+
/* Dividers */
106
+
#define CLK_DIV_GPL 90
107
+
#define CLK_DIV_GDL 91
108
+
#define CLK_DIV_GPR 92
109
+
#define CLK_DIV_GDR 93
110
+
#define CLK_DIV_ACLK_400_MCUISP 94
111
+
#define CLK_DIV_EBI 95
112
+
#define CLK_DIV_ACLK_200 96
113
+
#define CLK_DIV_ACLK_160 97
114
+
#define CLK_DIV_ACLK_100 98
115
+
#define CLK_DIV_ACLK_266 99
116
+
#define CLK_DIV_CSIS1 100
117
+
#define CLK_DIV_CSIS0 101
118
+
#define CLK_DIV_CAM1 102
119
+
#define CLK_DIV_FIMC3_LCLK 103
120
+
#define CLK_DIV_FIMC2_LCLK 104
121
+
#define CLK_DIV_FIMC1_LCLK 105
122
+
#define CLK_DIV_FIMC0_LCLK 106
123
+
#define CLK_DIV_TV_BLK 107
124
+
#define CLK_DIV_MFC 108
125
+
#define CLK_DIV_G3D 109
126
+
#define CLK_DIV_MIPI0_PRE 110
127
+
#define CLK_DIV_MIPI0 111
128
+
#define CLK_DIV_FIMD0 112
129
+
#define CLK_DIV_UART_ISP 113
130
+
#define CLK_DIV_SPI1_ISP_PRE 114
131
+
#define CLK_DIV_SPI1_ISP 115
132
+
#define CLK_DIV_SPI0_ISP_PRE 116
133
+
#define CLK_DIV_SPI0_ISP 117
134
+
#define CLK_DIV_PWM_ISP 118
135
+
#define CLK_DIV_PCM0 119
136
+
#define CLK_DIV_AUDIO0 120
137
+
#define CLK_DIV_TSADC_PRE 121
138
+
#define CLK_DIV_TSADC 122
139
+
#define CLK_DIV_MMC1_PRE 123
140
+
#define CLK_DIV_MMC1 124
141
+
#define CLK_DIV_MMC0_PRE 125
142
+
#define CLK_DIV_MMC0 126
143
+
#define CLK_DIV_MMC2_PRE 127
144
+
#define CLK_DIV_MMC2 128
145
+
#define CLK_DIV_UART3 129
146
+
#define CLK_DIV_UART2 130
147
+
#define CLK_DIV_UART1 131
148
+
#define CLK_DIV_UART0 132
149
+
#define CLK_DIV_SPI1_PRE 133
150
+
#define CLK_DIV_SPI1 134
151
+
#define CLK_DIV_SPI0_PRE 135
152
+
#define CLK_DIV_SPI0 136
153
+
#define CLK_DIV_SPI2_PRE 137
154
+
#define CLK_DIV_SPI2 138
155
+
#define CLK_DIV_PCM2 139
156
+
#define CLK_DIV_AUDIO2 140
157
+
#define CLK_DIV_PCM1 141
158
+
#define CLK_DIV_AUDIO1 142
159
+
#define CLK_DIV_I2S1 143
160
+
#define CLK_DIV_PXLASYNC_CSIS1_FIMC 144
161
+
#define CLK_DIV_PXLASYNC_CSIS0_FIMC 145
162
+
#define CLK_DIV_JPEG 146
163
+
#define CLK_DIV_CORE2 147
164
+
#define CLK_DIV_APLL 148
165
+
#define CLK_DIV_PCLK_DBG 149
166
+
#define CLK_DIV_ATB 150
167
+
#define CLK_DIV_PERIPH 151
168
+
#define CLK_DIV_COREM1 152
169
+
#define CLK_DIV_COREM0 153
170
+
#define CLK_DIV_CORE 154
171
+
#define CLK_DIV_HPM 155
172
+
#define CLK_DIV_COPY 156
173
+
174
+
/* Gates */
175
+
#define CLK_ASYNC_G3D 180
176
+
#define CLK_ASYNC_MFCL 181
177
+
#define CLK_ASYNC_TVX 182
178
+
#define CLK_PPMULEFT 183
179
+
#define CLK_GPIO_LEFT 184
180
+
#define CLK_PPMUIMAGE 185
181
+
#define CLK_QEMDMA2 186
182
+
#define CLK_QEROTATOR 187
183
+
#define CLK_SMMUMDMA2 188
184
+
#define CLK_SMMUROTATOR 189
185
+
#define CLK_MDMA2 190
186
+
#define CLK_ROTATOR 191
187
+
#define CLK_ASYNC_ISPMX 192
188
+
#define CLK_ASYNC_MAUDIOX 193
189
+
#define CLK_ASYNC_MFCR 194
190
+
#define CLK_ASYNC_FSYSD 195
191
+
#define CLK_ASYNC_LCD0X 196
192
+
#define CLK_ASYNC_CAMX 197
193
+
#define CLK_PPMURIGHT 198
194
+
#define CLK_GPIO_RIGHT 199
195
+
#define CLK_ANTIRBK_APBIF 200
196
+
#define CLK_EFUSE_WRITER_APBIF 201
197
+
#define CLK_MONOCNT 202
198
+
#define CLK_TZPC6 203
199
+
#define CLK_PROVISIONKEY1 204
200
+
#define CLK_PROVISIONKEY0 205
201
+
#define CLK_CMU_ISPPART 206
202
+
#define CLK_TMU_APBIF 207
203
+
#define CLK_KEYIF 208
204
+
#define CLK_RTC 209
205
+
#define CLK_WDT 210
206
+
#define CLK_MCT 211
207
+
#define CLK_SECKEY 212
208
+
#define CLK_HDMI_CEC 213
209
+
#define CLK_TZPC5 214
210
+
#define CLK_TZPC4 215
211
+
#define CLK_TZPC3 216
212
+
#define CLK_TZPC2 217
213
+
#define CLK_TZPC1 218
214
+
#define CLK_TZPC0 219
215
+
#define CLK_CMU_COREPART 220
216
+
#define CLK_CMU_TOPPART 221
217
+
#define CLK_PMU_APBIF 222
218
+
#define CLK_SYSREG 223
219
+
#define CLK_CHIP_ID 224
220
+
#define CLK_SMMUFIMC_LITE2 225
221
+
#define CLK_FIMC_LITE2 226
222
+
#define CLK_PIXELASYNCM1 227
223
+
#define CLK_PIXELASYNCM0 228
224
+
#define CLK_PPMUCAMIF 229
225
+
#define CLK_SMMUJPEG 230
226
+
#define CLK_SMMUFIMC3 231
227
+
#define CLK_SMMUFIMC2 232
228
+
#define CLK_SMMUFIMC1 233
229
+
#define CLK_SMMUFIMC0 234
230
+
#define CLK_JPEG 235
231
+
#define CLK_CSIS1 236
232
+
#define CLK_CSIS0 237
233
+
#define CLK_FIMC3 238
234
+
#define CLK_FIMC2 239
235
+
#define CLK_FIMC1 240
236
+
#define CLK_FIMC0 241
237
+
#define CLK_PPMUTV 242
238
+
#define CLK_SMMUTV 243
239
+
#define CLK_HDMI 244
240
+
#define CLK_MIXER 245
241
+
#define CLK_VP 246
242
+
#define CLK_PPMUMFC_R 247
243
+
#define CLK_PPMUMFC_L 248
244
+
#define CLK_SMMUMFC_R 249
245
+
#define CLK_SMMUMFC_L 250
246
+
#define CLK_MFC 251
247
+
#define CLK_PPMUG3D 252
248
+
#define CLK_G3D 253
249
+
#define CLK_PPMULCD0 254
250
+
#define CLK_SMMUFIMD0 255
251
+
#define CLK_DSIM0 256
252
+
#define CLK_SMIES 257
253
+
#define CLK_MIE0 258
254
+
#define CLK_FIMD0 259
255
+
#define CLK_TSADC 260
256
+
#define CLK_PPMUFILE 261
257
+
#define CLK_NFCON 262
258
+
#define CLK_USBDEVICE 263
259
+
#define CLK_USBHOST 264
260
+
#define CLK_SROMC 265
261
+
#define CLK_SDMMC2 266
262
+
#define CLK_SDMMC1 267
263
+
#define CLK_SDMMC0 268
264
+
#define CLK_PDMA1 269
265
+
#define CLK_PDMA0 270
266
+
#define CLK_SPDIF 271
267
+
#define CLK_PWM 272
268
+
#define CLK_PCM2 273
269
+
#define CLK_PCM1 274
270
+
#define CLK_I2S1 275
271
+
#define CLK_SPI2 276
272
+
#define CLK_SPI1 277
273
+
#define CLK_SPI0 278
274
+
#define CLK_I2CHDMI 279
275
+
#define CLK_I2C7 280
276
+
#define CLK_I2C6 281
277
+
#define CLK_I2C5 282
278
+
#define CLK_I2C4 283
279
+
#define CLK_I2C3 284
280
+
#define CLK_I2C2 285
281
+
#define CLK_I2C1 286
282
+
#define CLK_I2C0 287
283
+
#define CLK_UART3 288
284
+
#define CLK_UART2 289
285
+
#define CLK_UART1 290
286
+
#define CLK_UART0 291
287
+
288
+
/* Special clocks */
289
+
#define CLK_SCLK_PXLAYSNC_CSIS1_FIMC 330
290
+
#define CLK_SCLK_PXLAYSNC_CSIS0_FIMC 331
291
+
#define CLK_SCLK_JPEG 332
292
+
#define CLK_SCLK_CSIS1 333
293
+
#define CLK_SCLK_CSIS0 334
294
+
#define CLK_SCLK_CAM1 335
295
+
#define CLK_SCLK_FIMC3_LCLK 336
296
+
#define CLK_SCLK_FIMC2_LCLK 337
297
+
#define CLK_SCLK_FIMC1_LCLK 338
298
+
#define CLK_SCLK_FIMC0_LCLK 339
299
+
#define CLK_SCLK_PIXEL 340
300
+
#define CLK_SCLK_HDMI 341
301
+
#define CLK_SCLK_MIXER 342
302
+
#define CLK_SCLK_MFC 343
303
+
#define CLK_SCLK_G3D 344
304
+
#define CLK_SCLK_MIPIDPHY4L 345
305
+
#define CLK_SCLK_MIPI0 346
306
+
#define CLK_SCLK_MDNIE0 347
307
+
#define CLK_SCLK_FIMD0 348
308
+
#define CLK_SCLK_PCM0 349
309
+
#define CLK_SCLK_AUDIO0 350
310
+
#define CLK_SCLK_TSADC 351
311
+
#define CLK_SCLK_EBI 352
312
+
#define CLK_SCLK_MMC2 353
313
+
#define CLK_SCLK_MMC1 354
314
+
#define CLK_SCLK_MMC0 355
315
+
#define CLK_SCLK_I2S 356
316
+
#define CLK_SCLK_PCM2 357
317
+
#define CLK_SCLK_PCM1 358
318
+
#define CLK_SCLK_AUDIO2 359
319
+
#define CLK_SCLK_AUDIO1 360
320
+
#define CLK_SCLK_SPDIF 361
321
+
#define CLK_SCLK_SPI2 362
322
+
#define CLK_SCLK_SPI1 363
323
+
#define CLK_SCLK_SPI0 364
324
+
#define CLK_SCLK_UART3 365
325
+
#define CLK_SCLK_UART2 366
326
+
#define CLK_SCLK_UART1 367
327
+
#define CLK_SCLK_UART0 368
328
+
#define CLK_SCLK_HDMIPHY 369
329
+
330
+
/*
331
+
* Total number of clocks of main CMU.
332
+
* NOTE: Must be equal to last clock ID increased by one.
333
+
*/
334
+
#define CLK_NR_CLKS 370
335
+
336
+
/*
337
+
* CMU DMC
338
+
*/
339
+
#define CLK_DMC_FOUT_MPLL 1
340
+
#define CLK_DMC_FOUT_BPLL 2
341
+
342
+
#define CLK_DMC_MOUT_MPLL 3
343
+
#define CLK_DMC_MOUT_BPLL 4
344
+
#define CLK_DMC_MOUT_DPHY 5
345
+
#define CLK_DMC_MOUT_DMC_BUS 6
346
+
347
+
#define CLK_DMC_DIV_DMC 7
348
+
#define CLK_DMC_DIV_DPHY 8
349
+
#define CLK_DMC_DIV_DMC_PRE 9
350
+
#define CLK_DMC_DIV_DMCP 10
351
+
#define CLK_DMC_DIV_DMCD 11
352
+
#define CLK_DMC_DIV_MPLL_PRE 12
353
+
354
+
/*
355
+
* Total number of clocks of CMU_DMC.
356
+
* NOTE: Must be equal to highest clock ID increased by one.
357
+
*/
358
+
#define NR_CLKS_DMC 13
359
+
360
+
#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H */
+92
include/dt-bindings/clock/exynos7-clk.h
+92
include/dt-bindings/clock/exynos7-clk.h
···
1
+
/*
2
+
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
3
+
* Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
4
+
*
5
+
* This program is free software; you can redistribute it and/or modify
6
+
* it under the terms of the GNU General Public License version 2 as
7
+
* published by the Free Software Foundation.
8
+
*/
9
+
10
+
#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
11
+
#define _DT_BINDINGS_CLOCK_EXYNOS7_H
12
+
13
+
/* TOPC */
14
+
#define DOUT_ACLK_PERIS 1
15
+
#define DOUT_SCLK_BUS0_PLL 2
16
+
#define DOUT_SCLK_BUS1_PLL 3
17
+
#define DOUT_SCLK_CC_PLL 4
18
+
#define DOUT_SCLK_MFC_PLL 5
19
+
#define DOUT_ACLK_CCORE_133 6
20
+
#define TOPC_NR_CLK 7
21
+
22
+
/* TOP0 */
23
+
#define DOUT_ACLK_PERIC1 1
24
+
#define DOUT_ACLK_PERIC0 2
25
+
#define CLK_SCLK_UART0 3
26
+
#define CLK_SCLK_UART1 4
27
+
#define CLK_SCLK_UART2 5
28
+
#define CLK_SCLK_UART3 6
29
+
#define TOP0_NR_CLK 7
30
+
31
+
/* TOP1 */
32
+
#define DOUT_ACLK_FSYS1_200 1
33
+
#define DOUT_ACLK_FSYS0_200 2
34
+
#define DOUT_SCLK_MMC2 3
35
+
#define DOUT_SCLK_MMC1 4
36
+
#define DOUT_SCLK_MMC0 5
37
+
#define CLK_SCLK_MMC2 6
38
+
#define CLK_SCLK_MMC1 7
39
+
#define CLK_SCLK_MMC0 8
40
+
#define TOP1_NR_CLK 9
41
+
42
+
/* CCORE */
43
+
#define PCLK_RTC 1
44
+
#define CCORE_NR_CLK 2
45
+
46
+
/* PERIC0 */
47
+
#define PCLK_UART0 1
48
+
#define SCLK_UART0 2
49
+
#define PCLK_HSI2C0 3
50
+
#define PCLK_HSI2C1 4
51
+
#define PCLK_HSI2C4 5
52
+
#define PCLK_HSI2C5 6
53
+
#define PCLK_HSI2C9 7
54
+
#define PCLK_HSI2C10 8
55
+
#define PCLK_HSI2C11 9
56
+
#define PCLK_PWM 10
57
+
#define SCLK_PWM 11
58
+
#define PCLK_ADCIF 12
59
+
#define PERIC0_NR_CLK 13
60
+
61
+
/* PERIC1 */
62
+
#define PCLK_UART1 1
63
+
#define PCLK_UART2 2
64
+
#define PCLK_UART3 3
65
+
#define SCLK_UART1 4
66
+
#define SCLK_UART2 5
67
+
#define SCLK_UART3 6
68
+
#define PCLK_HSI2C2 7
69
+
#define PCLK_HSI2C3 8
70
+
#define PCLK_HSI2C6 9
71
+
#define PCLK_HSI2C7 10
72
+
#define PCLK_HSI2C8 11
73
+
#define PERIC1_NR_CLK 12
74
+
75
+
/* PERIS */
76
+
#define PCLK_CHIPID 1
77
+
#define SCLK_CHIPID 2
78
+
#define PCLK_WDT 3
79
+
#define PCLK_TMU 4
80
+
#define SCLK_TMU 5
81
+
#define PERIS_NR_CLK 6
82
+
83
+
/* FSYS0 */
84
+
#define ACLK_MMC2 1
85
+
#define FSYS0_NR_CLK 2
86
+
87
+
/* FSYS1 */
88
+
#define ACLK_MMC1 1
89
+
#define ACLK_MMC0 2
90
+
#define FSYS1_NR_CLK 3
91
+
92
+
#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
+74
include/dt-bindings/clock/marvell,mmp2.h
+74
include/dt-bindings/clock/marvell,mmp2.h
···
1
+
#ifndef __DTS_MARVELL_MMP2_CLOCK_H
2
+
#define __DTS_MARVELL_MMP2_CLOCK_H
3
+
4
+
/* fixed clocks and plls */
5
+
#define MMP2_CLK_CLK32 1
6
+
#define MMP2_CLK_VCTCXO 2
7
+
#define MMP2_CLK_PLL1 3
8
+
#define MMP2_CLK_PLL1_2 8
9
+
#define MMP2_CLK_PLL1_4 9
10
+
#define MMP2_CLK_PLL1_8 10
11
+
#define MMP2_CLK_PLL1_16 11
12
+
#define MMP2_CLK_PLL1_3 12
13
+
#define MMP2_CLK_PLL1_6 13
14
+
#define MMP2_CLK_PLL1_12 14
15
+
#define MMP2_CLK_PLL1_20 15
16
+
#define MMP2_CLK_PLL2 16
17
+
#define MMP2_CLK_PLL2_2 17
18
+
#define MMP2_CLK_PLL2_4 18
19
+
#define MMP2_CLK_PLL2_8 19
20
+
#define MMP2_CLK_PLL2_16 20
21
+
#define MMP2_CLK_PLL2_3 21
22
+
#define MMP2_CLK_PLL2_6 22
23
+
#define MMP2_CLK_PLL2_12 23
24
+
#define MMP2_CLK_VCTCXO_2 24
25
+
#define MMP2_CLK_VCTCXO_4 25
26
+
#define MMP2_CLK_UART_PLL 26
27
+
#define MMP2_CLK_USB_PLL 27
28
+
29
+
/* apb periphrals */
30
+
#define MMP2_CLK_TWSI0 60
31
+
#define MMP2_CLK_TWSI1 61
32
+
#define MMP2_CLK_TWSI2 62
33
+
#define MMP2_CLK_TWSI3 63
34
+
#define MMP2_CLK_TWSI4 64
35
+
#define MMP2_CLK_TWSI5 65
36
+
#define MMP2_CLK_GPIO 66
37
+
#define MMP2_CLK_KPC 67
38
+
#define MMP2_CLK_RTC 68
39
+
#define MMP2_CLK_PWM0 69
40
+
#define MMP2_CLK_PWM1 70
41
+
#define MMP2_CLK_PWM2 71
42
+
#define MMP2_CLK_PWM3 72
43
+
#define MMP2_CLK_UART0 73
44
+
#define MMP2_CLK_UART1 74
45
+
#define MMP2_CLK_UART2 75
46
+
#define MMP2_CLK_UART3 76
47
+
#define MMP2_CLK_SSP0 77
48
+
#define MMP2_CLK_SSP1 78
49
+
#define MMP2_CLK_SSP2 79
50
+
#define MMP2_CLK_SSP3 80
51
+
52
+
/* axi periphrals */
53
+
#define MMP2_CLK_SDH0 101
54
+
#define MMP2_CLK_SDH1 102
55
+
#define MMP2_CLK_SDH2 103
56
+
#define MMP2_CLK_SDH3 104
57
+
#define MMP2_CLK_USB 105
58
+
#define MMP2_CLK_DISP0 106
59
+
#define MMP2_CLK_DISP0_MUX 107
60
+
#define MMP2_CLK_DISP0_SPHY 108
61
+
#define MMP2_CLK_DISP1 109
62
+
#define MMP2_CLK_DISP1_MUX 110
63
+
#define MMP2_CLK_CCIC_ARBITER 111
64
+
#define MMP2_CLK_CCIC0 112
65
+
#define MMP2_CLK_CCIC0_MIX 113
66
+
#define MMP2_CLK_CCIC0_PHY 114
67
+
#define MMP2_CLK_CCIC0_SPHY 115
68
+
#define MMP2_CLK_CCIC1 116
69
+
#define MMP2_CLK_CCIC1_MIX 117
70
+
#define MMP2_CLK_CCIC1_PHY 118
71
+
#define MMP2_CLK_CCIC1_SPHY 119
72
+
73
+
#define MMP2_NR_CLKS 200
74
+
#endif
+57
include/dt-bindings/clock/marvell,pxa168.h
+57
include/dt-bindings/clock/marvell,pxa168.h
···
1
+
#ifndef __DTS_MARVELL_PXA168_CLOCK_H
2
+
#define __DTS_MARVELL_PXA168_CLOCK_H
3
+
4
+
/* fixed clocks and plls */
5
+
#define PXA168_CLK_CLK32 1
6
+
#define PXA168_CLK_VCTCXO 2
7
+
#define PXA168_CLK_PLL1 3
8
+
#define PXA168_CLK_PLL1_2 8
9
+
#define PXA168_CLK_PLL1_4 9
10
+
#define PXA168_CLK_PLL1_8 10
11
+
#define PXA168_CLK_PLL1_16 11
12
+
#define PXA168_CLK_PLL1_6 12
13
+
#define PXA168_CLK_PLL1_12 13
14
+
#define PXA168_CLK_PLL1_24 14
15
+
#define PXA168_CLK_PLL1_48 15
16
+
#define PXA168_CLK_PLL1_96 16
17
+
#define PXA168_CLK_PLL1_13 17
18
+
#define PXA168_CLK_PLL1_13_1_5 18
19
+
#define PXA168_CLK_PLL1_2_1_5 19
20
+
#define PXA168_CLK_PLL1_3_16 20
21
+
#define PXA168_CLK_UART_PLL 27
22
+
23
+
/* apb periphrals */
24
+
#define PXA168_CLK_TWSI0 60
25
+
#define PXA168_CLK_TWSI1 61
26
+
#define PXA168_CLK_TWSI2 62
27
+
#define PXA168_CLK_TWSI3 63
28
+
#define PXA168_CLK_GPIO 64
29
+
#define PXA168_CLK_KPC 65
30
+
#define PXA168_CLK_RTC 66
31
+
#define PXA168_CLK_PWM0 67
32
+
#define PXA168_CLK_PWM1 68
33
+
#define PXA168_CLK_PWM2 69
34
+
#define PXA168_CLK_PWM3 70
35
+
#define PXA168_CLK_UART0 71
36
+
#define PXA168_CLK_UART1 72
37
+
#define PXA168_CLK_UART2 73
38
+
#define PXA168_CLK_SSP0 74
39
+
#define PXA168_CLK_SSP1 75
40
+
#define PXA168_CLK_SSP2 76
41
+
#define PXA168_CLK_SSP3 77
42
+
#define PXA168_CLK_SSP4 78
43
+
44
+
/* axi periphrals */
45
+
#define PXA168_CLK_DFC 100
46
+
#define PXA168_CLK_SDH0 101
47
+
#define PXA168_CLK_SDH1 102
48
+
#define PXA168_CLK_SDH2 103
49
+
#define PXA168_CLK_USB 104
50
+
#define PXA168_CLK_SPH 105
51
+
#define PXA168_CLK_DISP0 106
52
+
#define PXA168_CLK_CCIC0 107
53
+
#define PXA168_CLK_CCIC0_PHY 108
54
+
#define PXA168_CLK_CCIC0_SPHY 109
55
+
56
+
#define PXA168_NR_CLKS 200
57
+
#endif
+54
include/dt-bindings/clock/marvell,pxa910.h
+54
include/dt-bindings/clock/marvell,pxa910.h
···
1
+
#ifndef __DTS_MARVELL_PXA910_CLOCK_H
2
+
#define __DTS_MARVELL_PXA910_CLOCK_H
3
+
4
+
/* fixed clocks and plls */
5
+
#define PXA910_CLK_CLK32 1
6
+
#define PXA910_CLK_VCTCXO 2
7
+
#define PXA910_CLK_PLL1 3
8
+
#define PXA910_CLK_PLL1_2 8
9
+
#define PXA910_CLK_PLL1_4 9
10
+
#define PXA910_CLK_PLL1_8 10
11
+
#define PXA910_CLK_PLL1_16 11
12
+
#define PXA910_CLK_PLL1_6 12
13
+
#define PXA910_CLK_PLL1_12 13
14
+
#define PXA910_CLK_PLL1_24 14
15
+
#define PXA910_CLK_PLL1_48 15
16
+
#define PXA910_CLK_PLL1_96 16
17
+
#define PXA910_CLK_PLL1_13 17
18
+
#define PXA910_CLK_PLL1_13_1_5 18
19
+
#define PXA910_CLK_PLL1_2_1_5 19
20
+
#define PXA910_CLK_PLL1_3_16 20
21
+
#define PXA910_CLK_UART_PLL 27
22
+
23
+
/* apb periphrals */
24
+
#define PXA910_CLK_TWSI0 60
25
+
#define PXA910_CLK_TWSI1 61
26
+
#define PXA910_CLK_TWSI2 62
27
+
#define PXA910_CLK_TWSI3 63
28
+
#define PXA910_CLK_GPIO 64
29
+
#define PXA910_CLK_KPC 65
30
+
#define PXA910_CLK_RTC 66
31
+
#define PXA910_CLK_PWM0 67
32
+
#define PXA910_CLK_PWM1 68
33
+
#define PXA910_CLK_PWM2 69
34
+
#define PXA910_CLK_PWM3 70
35
+
#define PXA910_CLK_UART0 71
36
+
#define PXA910_CLK_UART1 72
37
+
#define PXA910_CLK_UART2 73
38
+
#define PXA910_CLK_SSP0 74
39
+
#define PXA910_CLK_SSP1 75
40
+
41
+
/* axi periphrals */
42
+
#define PXA910_CLK_DFC 100
43
+
#define PXA910_CLK_SDH0 101
44
+
#define PXA910_CLK_SDH1 102
45
+
#define PXA910_CLK_SDH2 103
46
+
#define PXA910_CLK_USB 104
47
+
#define PXA910_CLK_SPH 105
48
+
#define PXA910_CLK_DISP0 106
49
+
#define PXA910_CLK_CCIC0 107
50
+
#define PXA910_CLK_CCIC0_PHY 108
51
+
#define PXA910_CLK_CCIC0_SPHY 109
52
+
53
+
#define PXA910_NR_CLKS 200
54
+
#endif
+13
include/dt-bindings/clock/rk3288-cru.h
+13
include/dt-bindings/clock/rk3288-cru.h
···
71
71
#define SCLK_HDMI_CEC 110
72
72
#define SCLK_HEVC_CABAC 111
73
73
#define SCLK_HEVC_CORE 112
74
+
#define SCLK_I2S0_OUT 113
75
+
#define SCLK_SDMMC_DRV 114
76
+
#define SCLK_SDIO0_DRV 115
77
+
#define SCLK_SDIO1_DRV 116
78
+
#define SCLK_EMMC_DRV 117
79
+
#define SCLK_SDMMC_SAMPLE 118
80
+
#define SCLK_SDIO0_SAMPLE 119
81
+
#define SCLK_SDIO1_SAMPLE 120
82
+
#define SCLK_EMMC_SAMPLE 121
74
83
75
84
#define DCLK_VOP0 190
76
85
#define DCLK_VOP1 191
···
150
141
#define PCLK_VIO2_H2P 361
151
142
#define PCLK_CPU 362
152
143
#define PCLK_PERI 363
144
+
#define PCLK_DDRUPCTL0 364
145
+
#define PCLK_PUBL0 365
146
+
#define PCLK_DDRUPCTL1 366
147
+
#define PCLK_PUBL1 367
153
148
154
149
/* hclk gates */
155
150
#define HCLK_GPS 448
+3
-5
include/linux/clk-provider.h
+3
-5
include/linux/clk-provider.h
···
176
176
unsigned long *parent_rate);
177
177
long (*determine_rate)(struct clk_hw *hw, unsigned long rate,
178
178
unsigned long *best_parent_rate,
179
-
struct clk **best_parent_clk);
179
+
struct clk_hw **best_parent_hw);
180
180
int (*set_parent)(struct clk_hw *hw, u8 index);
181
181
u8 (*get_parent)(struct clk_hw *hw);
182
182
int (*set_rate)(struct clk_hw *hw, unsigned long rate,
···
544
544
struct clk *__clk_get_parent(struct clk *clk);
545
545
struct clk *clk_get_parent_by_index(struct clk *clk, u8 index);
546
546
unsigned int __clk_get_enable_count(struct clk *clk);
547
-
unsigned int __clk_get_prepare_count(struct clk *clk);
548
547
unsigned long __clk_get_rate(struct clk *clk);
549
-
unsigned long __clk_get_accuracy(struct clk *clk);
550
548
unsigned long __clk_get_flags(struct clk *clk);
551
549
bool __clk_is_prepared(struct clk *clk);
552
550
bool __clk_is_enabled(struct clk *clk);
553
551
struct clk *__clk_lookup(const char *name);
554
552
long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
555
553
unsigned long *best_parent_rate,
556
-
struct clk **best_parent_p);
554
+
struct clk_hw **best_parent_p);
557
555
558
556
/*
559
557
* FIXME clock api without lock protection
···
650
652
#endif /* platform dependent I/O accessors */
651
653
652
654
#ifdef CONFIG_DEBUG_FS
653
-
struct dentry *clk_debugfs_add_file(struct clk *clk, char *name, umode_t mode,
655
+
struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode,
654
656
void *data, const struct file_operations *fops);
655
657
#endif
656
658
+2
-2
include/linux/clk/ti.h
+2
-2
include/linux/clk/ti.h
···
264
264
long omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
265
265
unsigned long rate,
266
266
unsigned long *best_parent_rate,
267
-
struct clk **best_parent_clk);
267
+
struct clk_hw **best_parent_clk);
268
268
unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
269
269
unsigned long parent_rate);
270
270
long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
···
273
273
long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
274
274
unsigned long rate,
275
275
unsigned long *best_parent_rate,
276
-
struct clk **best_parent_clk);
276
+
struct clk_hw **best_parent_clk);
277
277
u8 omap2_init_dpll_parent(struct clk_hw *hw);
278
278
unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
279
279
long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,