Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm:
ARM: 6126/1: ARM mpcore_wdt: fix build failure and other fixes
ARM: 6125/1: ARM TWD: move TWD registers to common header
ARM: 6110/1: Fix Thumb-2 kernel builds when UACCESS_WITH_MEMCPY is enabled
ARM: 6112/1: Use the Inner Shareable I-cache and BTB ops on ARMv7 SMP
ARM: 6111/1: Implement read/write for ownership in the ARMv6 DMA cache ops
ARM: 6106/1: Implement copy_to_user_page() for noMMU
ARM: 6105/1: Fix the __arm_ioremap_caller() definition in nommu.c
+99
-35
+4
arch/arm/include/asm/cacheflush.h
+4
arch/arm/include/asm/cacheflush.h
···
371
371
#ifdef CONFIG_ARM_ERRATA_411920
372
372
extern void v6_icache_inval_all(void);
373
373
v6_icache_inval_all();
374
+
#elif defined(CONFIG_SMP) && __LINUX_ARM_ARCH__ >= 7
375
+
asm("mcr p15, 0, %0, c7, c1, 0 @ invalidate I-cache inner shareable\n"
376
+
:
377
+
: "r" (0));
374
378
#else
375
379
asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n"
376
380
:
+17
arch/arm/include/asm/smp_twd.h
+17
arch/arm/include/asm/smp_twd.h
···
1
1
#ifndef __ASMARM_SMP_TWD_H
2
2
#define __ASMARM_SMP_TWD_H
3
3
4
+
#define TWD_TIMER_LOAD 0x00
5
+
#define TWD_TIMER_COUNTER 0x04
6
+
#define TWD_TIMER_CONTROL 0x08
7
+
#define TWD_TIMER_INTSTAT 0x0C
8
+
9
+
#define TWD_WDOG_LOAD 0x20
10
+
#define TWD_WDOG_COUNTER 0x24
11
+
#define TWD_WDOG_CONTROL 0x28
12
+
#define TWD_WDOG_INTSTAT 0x2C
13
+
#define TWD_WDOG_RESETSTAT 0x30
14
+
#define TWD_WDOG_DISABLE 0x34
15
+
16
+
#define TWD_TIMER_CONTROL_ENABLE (1 << 0)
17
+
#define TWD_TIMER_CONTROL_ONESHOT (0 << 1)
18
+
#define TWD_TIMER_CONTROL_PERIODIC (1 << 1)
19
+
#define TWD_TIMER_CONTROL_IT_ENABLE (1 << 2)
20
+
4
21
struct clock_event_device;
5
22
6
23
extern void __iomem *twd_base;
+28
-1
arch/arm/include/asm/tlbflush.h
+28
-1
arch/arm/include/asm/tlbflush.h
···
46
46
#define TLB_V7_UIS_FULL (1 << 20)
47
47
#define TLB_V7_UIS_ASID (1 << 21)
48
48
49
+
/* Inner Shareable BTB operation (ARMv7 MP extensions) */
50
+
#define TLB_V7_IS_BTB (1 << 22)
51
+
49
52
#define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */
50
53
#define TLB_DCLEAN (1 << 30)
51
54
#define TLB_WB (1 << 31)
···
186
183
#endif
187
184
188
185
#ifdef CONFIG_SMP
189
-
#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
186
+
#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
190
187
TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
191
188
#else
192
189
#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
···
342
339
dsb();
343
340
isb();
344
341
}
342
+
if (tlb_flag(TLB_V7_IS_BTB)) {
343
+
/* flush the branch target cache */
344
+
asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero) : "cc");
345
+
dsb();
346
+
isb();
347
+
}
345
348
}
346
349
347
350
static inline void local_flush_tlb_mm(struct mm_struct *mm)
···
384
375
/* flush the branch target cache */
385
376
asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
386
377
dsb();
378
+
}
379
+
if (tlb_flag(TLB_V7_IS_BTB)) {
380
+
/* flush the branch target cache */
381
+
asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero) : "cc");
382
+
dsb();
383
+
isb();
387
384
}
388
385
}
389
386
···
431
416
asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
432
417
dsb();
433
418
}
419
+
if (tlb_flag(TLB_V7_IS_BTB)) {
420
+
/* flush the branch target cache */
421
+
asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero) : "cc");
422
+
dsb();
423
+
isb();
424
+
}
434
425
}
435
426
436
427
static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
···
472
451
if (tlb_flag(TLB_BTB)) {
473
452
/* flush the branch target cache */
474
453
asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
454
+
dsb();
455
+
isb();
456
+
}
457
+
if (tlb_flag(TLB_V7_IS_BTB)) {
458
+
/* flush the branch target cache */
459
+
asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero) : "cc");
475
460
dsb();
476
461
isb();
477
462
}
-17
arch/arm/kernel/smp_twd.c
-17
arch/arm/kernel/smp_twd.c
···
21
21
#include <asm/smp_twd.h>
22
22
#include <asm/hardware/gic.h>
23
23
24
-
#define TWD_TIMER_LOAD 0x00
25
-
#define TWD_TIMER_COUNTER 0x04
26
-
#define TWD_TIMER_CONTROL 0x08
27
-
#define TWD_TIMER_INTSTAT 0x0C
28
-
29
-
#define TWD_WDOG_LOAD 0x20
30
-
#define TWD_WDOG_COUNTER 0x24
31
-
#define TWD_WDOG_CONTROL 0x28
32
-
#define TWD_WDOG_INTSTAT 0x2C
33
-
#define TWD_WDOG_RESETSTAT 0x30
34
-
#define TWD_WDOG_DISABLE 0x34
35
-
36
-
#define TWD_TIMER_CONTROL_ENABLE (1 << 0)
37
-
#define TWD_TIMER_CONTROL_ONESHOT (0 << 1)
38
-
#define TWD_TIMER_CONTROL_PERIODIC (1 << 1)
39
-
#define TWD_TIMER_CONTROL_IT_ENABLE (1 << 2)
40
-
41
24
/* set up by the platform code */
42
25
void __iomem *twd_base;
43
26
+1
arch/arm/lib/clear_user.S
+1
arch/arm/lib/clear_user.S
+1
arch/arm/lib/copy_to_user.S
+1
arch/arm/lib/copy_to_user.S
+13
-4
arch/arm/mm/cache-v6.S
+13
-4
arch/arm/mm/cache-v6.S
···
211
211
mcrne p15, 0, r1, c7, c15, 1 @ clean & invalidate unified line
212
212
#endif
213
213
1:
214
+
#ifdef CONFIG_SMP
215
+
str r0, [r0] @ write for ownership
216
+
#endif
214
217
#ifdef HARVARD_CACHE
215
218
mcr p15, 0, r0, c7, c6, 1 @ invalidate D line
216
219
#else
···
234
231
v6_dma_clean_range:
235
232
bic r0, r0, #D_CACHE_LINE_SIZE - 1
236
233
1:
234
+
#ifdef CONFIG_SMP
235
+
ldr r2, [r0] @ read for ownership
236
+
#endif
237
237
#ifdef HARVARD_CACHE
238
238
mcr p15, 0, r0, c7, c10, 1 @ clean D line
239
239
#else
···
257
251
ENTRY(v6_dma_flush_range)
258
252
bic r0, r0, #D_CACHE_LINE_SIZE - 1
259
253
1:
254
+
#ifdef CONFIG_SMP
255
+
ldr r2, [r0] @ read for ownership
256
+
str r2, [r0] @ write for ownership
257
+
#endif
260
258
#ifdef HARVARD_CACHE
261
259
mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
262
260
#else
···
283
273
add r1, r1, r0
284
274
teq r2, #DMA_FROM_DEVICE
285
275
beq v6_dma_inv_range
286
-
b v6_dma_clean_range
276
+
teq r2, #DMA_TO_DEVICE
277
+
beq v6_dma_clean_range
278
+
b v6_dma_flush_range
287
279
ENDPROC(v6_dma_map_area)
288
280
289
281
/*
···
295
283
* - dir - DMA direction
296
284
*/
297
285
ENTRY(v6_dma_unmap_area)
298
-
add r1, r1, r0
299
-
teq r2, #DMA_TO_DEVICE
300
-
bne v6_dma_inv_range
301
286
mov pc, lr
302
287
ENDPROC(v6_dma_unmap_area)
303
288
+4
arch/arm/mm/cache-v7.S
+4
arch/arm/mm/cache-v7.S
+11
-2
arch/arm/mm/nommu.c
+11
-2
arch/arm/mm/nommu.c
···
65
65
}
66
66
EXPORT_SYMBOL(flush_dcache_page);
67
67
68
+
void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
69
+
unsigned long uaddr, void *dst, const void *src,
70
+
unsigned long len)
71
+
{
72
+
memcpy(dst, src, len);
73
+
if (vma->vm_flags & VM_EXEC)
74
+
__cpuc_coherent_user_range(uaddr, uaddr + len);
75
+
}
76
+
68
77
void __iomem *__arm_ioremap_pfn(unsigned long pfn, unsigned long offset,
69
78
size_t size, unsigned int mtype)
70
79
{
···
96
87
}
97
88
EXPORT_SYMBOL(__arm_ioremap);
98
89
99
-
void __iomem *__arm_ioremap(unsigned long phys_addr, size_t size,
100
-
unsigned int mtype, void *caller)
90
+
void __iomem *__arm_ioremap_caller(unsigned long phys_addr, size_t size,
91
+
unsigned int mtype, void *caller)
101
92
{
102
93
return __arm_ioremap(phys_addr, size, mtype);
103
94
}
+8
arch/arm/mm/tlb-v7.S
+8
arch/arm/mm/tlb-v7.S
···
50
50
cmp r0, r1
51
51
blo 1b
52
52
mov ip, #0
53
+
#ifdef CONFIG_SMP
54
+
mcr p15, 0, ip, c7, c1, 6 @ flush BTAC/BTB Inner Shareable
55
+
#else
53
56
mcr p15, 0, ip, c7, c5, 6 @ flush BTAC/BTB
57
+
#endif
54
58
dsb
55
59
mov pc, lr
56
60
ENDPROC(v7wbi_flush_user_tlb_range)
···
83
79
cmp r0, r1
84
80
blo 1b
85
81
mov r2, #0
82
+
#ifdef CONFIG_SMP
83
+
mcr p15, 0, r2, c7, c1, 6 @ flush BTAC/BTB Inner Shareable
84
+
#else
86
85
mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
86
+
#endif
87
87
dsb
88
88
isb
89
89
mov pc, lr
+1
-1
drivers/watchdog/Kconfig
+1
-1
drivers/watchdog/Kconfig
+11
-10
drivers/watchdog/mpcore_wdt.c
+11
-10
drivers/watchdog/mpcore_wdt.c
···
31
31
#include <linux/platform_device.h>
32
32
#include <linux/uaccess.h>
33
33
#include <linux/slab.h>
34
+
#include <linux/io.h>
34
35
35
-
#include <asm/hardware/arm_twd.h>
36
+
#include <asm/smp_twd.h>
36
37
37
38
struct mpcore_wdt {
38
39
unsigned long timer_alive;
···
45
44
};
46
45
47
46
static struct platform_device *mpcore_wdt_dev;
48
-
extern unsigned int mpcore_timer_rate;
47
+
static DEFINE_SPINLOCK(wdt_lock);
49
48
50
49
#define TIMER_MARGIN 60
51
50
static int mpcore_margin = TIMER_MARGIN;
···
95
94
*/
96
95
static void mpcore_wdt_keepalive(struct mpcore_wdt *wdt)
97
96
{
98
-
unsigned int count;
97
+
unsigned long count;
99
98
99
+
spin_lock(&wdt_lock);
100
100
/* Assume prescale is set to 256 */
101
-
count = (mpcore_timer_rate / 256) * mpcore_margin;
101
+
count = __raw_readl(wdt->base + TWD_WDOG_COUNTER);
102
+
count = (0xFFFFFFFFU - count) * (HZ / 5);
103
+
count = (count / 256) * mpcore_margin;
102
104
103
105
/* Reload the counter */
104
-
spin_lock(&wdt_lock);
105
106
writel(count + wdt->perturb, wdt->base + TWD_WDOG_LOAD);
106
107
wdt->perturb = wdt->perturb ? 0 : 1;
107
108
spin_unlock(&wdt_lock);
···
122
119
{
123
120
dev_printk(KERN_INFO, wdt->dev, "enabling watchdog.\n");
124
121
125
-
spin_lock(&wdt_lock);
126
122
/* This loads the count register but does NOT start the count yet */
127
123
mpcore_wdt_keepalive(wdt);
128
124
···
132
130
/* Enable watchdog - prescale=256, watchdog mode=1, enable=1 */
133
131
writel(0x0000FF09, wdt->base + TWD_WDOG_CONTROL);
134
132
}
135
-
spin_unlock(&wdt_lock);
136
133
}
137
134
138
135
static int mpcore_wdt_set_heartbeat(int t)
···
361
360
mpcore_wdt_miscdev.parent = &dev->dev;
362
361
ret = misc_register(&mpcore_wdt_miscdev);
363
362
if (ret) {
364
-
dev_printk(KERN_ERR, _dev,
363
+
dev_printk(KERN_ERR, wdt->dev,
365
364
"cannot register miscdev on minor=%d (err=%d)\n",
366
365
WATCHDOG_MINOR, ret);
367
366
goto err_misc;
···
370
369
ret = request_irq(wdt->irq, mpcore_wdt_fire, IRQF_DISABLED,
371
370
"mpcore_wdt", wdt);
372
371
if (ret) {
373
-
dev_printk(KERN_ERR, _dev,
372
+
dev_printk(KERN_ERR, wdt->dev,
374
373
"cannot register IRQ%d for watchdog\n", wdt->irq);
375
374
goto err_irq;
376
375
}
377
376
378
377
mpcore_wdt_stop(wdt);
379
-
platform_set_drvdata(&dev->dev, wdt);
378
+
platform_set_drvdata(dev, wdt);
380
379
mpcore_wdt_dev = dev;
381
380
382
381
return 0;