Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2023-02-03' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie:
"A few more fixes this week, a bit more spread out though.
We have a bunch of nouveau regression and stabilisation fixes, along
with usual amdgpu, and i915. Otherwise just some minor misc ones:
dma-fence:
- fix signaling bit for private fences
panel:
- boe-tv101wum-nl6 disable fix
nouveau:
- gm20b acr regression fix
- tu102 scrub status fix
- tu102 wait for firmware fix
i915:
- Fixes for potential use-after-free and double-free
- GuC locking and refcount fixes
- Display's reference clock value fix
amdgpu:
- GC11 fixes
- DCN 3.1.4 fixes
- NBIO 4.3 fix
- DCN 3.2 fixes
- Properly handle additional cases where DCN is not supported
- SMU13 fixes
vc4:
- fix CEC adapter names
ssd130x:
- fix display init regression"
* tag 'drm-fixes-2023-02-03' of git://anongit.freedesktop.org/drm/drm: (23 commits)
drm/amd/display: Properly handle additional cases where DCN is not supported
drm/amdgpu: Enable vclk dclk node for gc11.0.3
drm/amd: Fix initialization for nbio 4.3.0
drm/amdgpu: enable HDP SD for gfx 11.0.3
drm/amd/pm: drop unneeded dpm features disablement for SMU 13.0.4/11
drm/amd/display: Reset DMUB mailbox SW state after HW reset
drm/amd/display: Unassign does_plane_fit_in_mall function from dcn3.2
drm/amd/display: Adjust downscaling limits for dcn314
drm/amd/display: Add missing brackets in calculation
drm/amdgpu: update wave data type to 3 for gfx11
drm/panel: boe-tv101wum-nl6: Ensure DSI writes succeed during disable
drm/nouveau/acr/gm20b: regression fixes
drm/nouveau/fb/tu102-: fix register used to determine scrub status
drm/nouveau/devinit/tu102-: wait for GFW_BOOT_PROGRESS == COMPLETED
drm/i915/adlp: Fix typo for reference clock
drm/i915: Fix potential bit_17 double-free
drm/i915: Fix up locking around dumping requests lists
drm/i915: Fix request ref counting during error capture & debugfs dump
drm/i915/guc: Fix locking when searching for a hung request
drm/i915: Avoid potential vm use-after-free
...
+297
-123
+1
-1
drivers/dma-buf/dma-fence.c
+1
-1
drivers/dma-buf/dma-fence.c
+2
-2
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+2
-2
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
···
790
790
* zero here */
791
791
WARN_ON(simd != 0);
792
792
793
-
/* type 2 wave data */
794
-
dst[(*no_fields)++] = 2;
793
+
/* type 3 wave data */
794
+
dst[(*no_fields)++] = 3;
795
795
dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
796
796
dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
797
797
dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
+7
-1
drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
+7
-1
drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
···
337
337
338
338
static void nbio_v4_3_init_registers(struct amdgpu_device *adev)
339
339
{
340
-
return;
340
+
if (adev->ip_versions[NBIO_HWIP][0] == IP_VERSION(4, 3, 0)) {
341
+
uint32_t data;
342
+
343
+
data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2);
344
+
data &= ~RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK;
345
+
WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2, data);
346
+
}
341
347
}
342
348
343
349
static u32 nbio_v4_3_get_rom_offset(struct amdgpu_device *adev)
+2
-1
drivers/gpu/drm/amd/amdgpu/soc21.c
+2
-1
drivers/gpu/drm/amd/amdgpu/soc21.c
···
640
640
AMD_CG_SUPPORT_GFX_CGCG |
641
641
AMD_CG_SUPPORT_GFX_CGLS |
642
642
AMD_CG_SUPPORT_REPEATER_FGCG |
643
-
AMD_CG_SUPPORT_GFX_MGCG;
643
+
AMD_CG_SUPPORT_GFX_MGCG |
644
+
AMD_CG_SUPPORT_HDP_SD;
644
645
adev->pg_flags = AMD_PG_SUPPORT_VCN |
645
646
AMD_PG_SUPPORT_VCN_DPG |
646
647
AMD_PG_SUPPORT_JPEG;
+11
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+11
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
4501
4501
static int dm_early_init(void *handle)
4502
4502
{
4503
4503
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4504
+
struct amdgpu_mode_info *mode_info = &adev->mode_info;
4505
+
struct atom_context *ctx = mode_info->atom_context;
4506
+
int index = GetIndexIntoMasterTable(DATA, Object_Header);
4507
+
u16 data_offset;
4508
+
4509
+
/* if there is no object header, skip DM */
4510
+
if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
4511
+
adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
4512
+
dev_info(adev->dev, "No object header, skipping DM\n");
4513
+
return -ENOENT;
4514
+
}
4504
4515
4505
4516
switch (adev->asic_type) {
4506
4517
#if defined(CONFIG_DRM_AMD_DC_SI)
+3
-2
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
+3
-2
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
···
874
874
},
875
875
876
876
// 6:1 downscaling ratio: 1000/6 = 166.666
877
+
// 4:1 downscaling ratio for ARGB888 to prevent underflow during P010 playback: 1000/4 = 250
877
878
.max_downscale_factor = {
878
-
.argb8888 = 167,
879
+
.argb8888 = 250,
879
880
.nv12 = 167,
880
881
.fp16 = 167
881
882
},
···
1764
1763
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1765
1764
pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1766
1765
pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1767
-
dc->caps.max_downscale_ratio = 600;
1766
+
dc->caps.max_downscale_ratio = 400;
1768
1767
dc->caps.i2c_speed_in_khz = 100;
1769
1768
dc->caps.i2c_speed_in_khz_hdcp = 100;
1770
1769
dc->caps.max_cursor_size = 256;
+1
-1
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
+1
-1
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c
···
94
94
.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
95
95
.calc_vupdate_position = dcn10_calc_vupdate_position,
96
96
.apply_idle_power_optimizations = dcn32_apply_idle_power_optimizations,
97
-
.does_plane_fit_in_mall = dcn30_does_plane_fit_in_mall,
97
+
.does_plane_fit_in_mall = NULL,
98
98
.set_backlight_level = dcn21_set_backlight_level,
99
99
.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
100
100
.hardware_release = dcn30_hardware_release,
+1
-1
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
+1
-1
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
···
3183
3183
} else {
3184
3184
v->MIN_DST_Y_NEXT_START[k] = v->VTotal[k] - v->VFrontPorch[k] + v->VTotal[k] - v->VActive[k] - v->VStartup[k];
3185
3185
}
3186
-
v->MIN_DST_Y_NEXT_START[k] += dml_floor(4.0 * v->TSetup[k] / (double)v->HTotal[k] / v->PixelClock[k], 1.0) / 4.0;
3186
+
v->MIN_DST_Y_NEXT_START[k] += dml_floor(4.0 * v->TSetup[k] / ((double)v->HTotal[k] / v->PixelClock[k]), 1.0) / 4.0;
3187
3187
if (((v->VUpdateOffsetPix[k] + v->VUpdateWidthPix[k] + v->VReadyOffsetPix[k]) / v->HTotal[k])
3188
3188
<= (isInterlaceTiming ?
3189
3189
dml_floor((v->VTotal[k] - v->VActive[k] - v->VFrontPorch[k] - v->VStartup[k]) / 2.0, 1.0) :
+12
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+12
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
···
532
532
if (dmub->hw_funcs.reset)
533
533
dmub->hw_funcs.reset(dmub);
534
534
535
+
/* reset the cache of the last wptr as well now that hw is reset */
536
+
dmub->inbox1_last_wptr = 0;
537
+
535
538
cw0.offset.quad_part = inst_fb->gpu_addr;
536
539
cw0.region.base = DMUB_CW0_BASE;
537
540
cw0.region.top = cw0.region.base + inst_fb->size - 1;
···
651
648
652
649
if (dmub->hw_funcs.reset)
653
650
dmub->hw_funcs.reset(dmub);
651
+
652
+
/* mailboxes have been reset in hw, so reset the sw state as well */
653
+
dmub->inbox1_last_wptr = 0;
654
+
dmub->inbox1_rb.wrpt = 0;
655
+
dmub->inbox1_rb.rptr = 0;
656
+
dmub->outbox0_rb.wrpt = 0;
657
+
dmub->outbox0_rb.rptr = 0;
658
+
dmub->outbox1_rb.wrpt = 0;
659
+
dmub->outbox1_rb.rptr = 0;
654
660
655
661
dmub->hw_init = false;
656
662
+4
-2
drivers/gpu/drm/amd/pm/amdgpu_pm.c
+4
-2
drivers/gpu/drm/amd/pm/amdgpu_pm.c
···
2007
2007
gc_ver == IP_VERSION(10, 3, 0) ||
2008
2008
gc_ver == IP_VERSION(10, 1, 2) ||
2009
2009
gc_ver == IP_VERSION(11, 0, 0) ||
2010
-
gc_ver == IP_VERSION(11, 0, 2)))
2010
+
gc_ver == IP_VERSION(11, 0, 2) ||
2011
+
gc_ver == IP_VERSION(11, 0, 3)))
2011
2012
*states = ATTR_STATE_UNSUPPORTED;
2012
2013
} else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
2013
2014
if (!(gc_ver == IP_VERSION(10, 3, 1) ||
2014
2015
gc_ver == IP_VERSION(10, 3, 0) ||
2015
2016
gc_ver == IP_VERSION(10, 1, 2) ||
2016
2017
gc_ver == IP_VERSION(11, 0, 0) ||
2017
-
gc_ver == IP_VERSION(11, 0, 2)))
2018
+
gc_ver == IP_VERSION(11, 0, 2) ||
2019
+
gc_ver == IP_VERSION(11, 0, 3)))
2018
2020
*states = ATTR_STATE_UNSUPPORTED;
2019
2021
} else if (DEVICE_ATTR_IS(pp_power_profile_mode)) {
2020
2022
if (amdgpu_dpm_get_power_profile_mode(adev, NULL) == -EOPNOTSUPP)
+14
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+14
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
···
1500
1500
}
1501
1501
1502
1502
/*
1503
+
* For SMU 13.0.4/11, PMFW will handle the features disablement properly
1504
+
* for gpu reset case. Driver involvement is unnecessary.
1505
+
*/
1506
+
if (amdgpu_in_reset(adev)) {
1507
+
switch (adev->ip_versions[MP1_HWIP][0]) {
1508
+
case IP_VERSION(13, 0, 4):
1509
+
case IP_VERSION(13, 0, 11):
1510
+
return 0;
1511
+
default:
1512
+
break;
1513
+
}
1514
+
}
1515
+
1516
+
/*
1503
1517
* For gpu reset, runpm and hibernation through BACO,
1504
1518
* BACO feature has to be kept enabled.
1505
1519
*/
+1
-1
drivers/gpu/drm/i915/display/intel_cdclk.c
+1
-1
drivers/gpu/drm/i915/display/intel_cdclk.c
···
1319
1319
{ .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
1320
1320
{ .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1321
1321
{ .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1322
-
{ .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
1322
+
{ .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
1323
1323
1324
1324
{ .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
1325
1325
{ .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
+12
-4
drivers/gpu/drm/i915/gem/i915_gem_context.c
+12
-4
drivers/gpu/drm/i915/gem/i915_gem_context.c
···
1861
1861
vm = ctx->vm;
1862
1862
GEM_BUG_ON(!vm);
1863
1863
1864
-
err = xa_alloc(&file_priv->vm_xa, &id, vm, xa_limit_32b, GFP_KERNEL);
1865
-
if (err)
1866
-
return err;
1867
-
1864
+
/*
1865
+
* Get a reference for the allocated handle. Once the handle is
1866
+
* visible in the vm_xa table, userspace could try to close it
1867
+
* from under our feet, so we need to hold the extra reference
1868
+
* first.
1869
+
*/
1868
1870
i915_vm_get(vm);
1871
+
1872
+
err = xa_alloc(&file_priv->vm_xa, &id, vm, xa_limit_32b, GFP_KERNEL);
1873
+
if (err) {
1874
+
i915_vm_put(vm);
1875
+
return err;
1876
+
}
1869
1877
1870
1878
GEM_BUG_ON(id == 0); /* reserved for invalid/unassigned ppgtt */
1871
1879
args->value = id;
+5
-4
drivers/gpu/drm/i915/gem/i915_gem_tiling.c
+5
-4
drivers/gpu/drm/i915/gem/i915_gem_tiling.c
···
305
305
spin_unlock(&obj->vma.lock);
306
306
307
307
obj->tiling_and_stride = tiling | stride;
308
-
i915_gem_object_unlock(obj);
309
-
310
-
/* Force the fence to be reacquired for GTT access */
311
-
i915_gem_object_release_mmap_gtt(obj);
312
308
313
309
/* Try to preallocate memory required to save swizzling on put-pages */
314
310
if (i915_gem_object_needs_bit17_swizzle(obj)) {
···
316
320
bitmap_free(obj->bit_17);
317
321
obj->bit_17 = NULL;
318
322
}
323
+
324
+
i915_gem_object_unlock(obj);
325
+
326
+
/* Force the fence to be reacquired for GTT access */
327
+
i915_gem_object_release_mmap_gtt(obj);
319
328
320
329
return 0;
321
330
}
+3
-1
drivers/gpu/drm/i915/gt/intel_context.c
+3
-1
drivers/gpu/drm/i915/gt/intel_context.c
···
528
528
return rq;
529
529
}
530
530
531
-
struct i915_request *intel_context_find_active_request(struct intel_context *ce)
531
+
struct i915_request *intel_context_get_active_request(struct intel_context *ce)
532
532
{
533
533
struct intel_context *parent = intel_context_to_parent(ce);
534
534
struct i915_request *rq, *active = NULL;
···
552
552
553
553
active = rq;
554
554
}
555
+
if (active)
556
+
active = i915_request_get_rcu(active);
555
557
spin_unlock_irqrestore(&parent->guc_state.lock, flags);
556
558
557
559
return active;
+1
-2
drivers/gpu/drm/i915/gt/intel_context.h
+1
-2
drivers/gpu/drm/i915/gt/intel_context.h
···
268
268
269
269
struct i915_request *intel_context_create_request(struct intel_context *ce);
270
270
271
-
struct i915_request *
272
-
intel_context_find_active_request(struct intel_context *ce);
271
+
struct i915_request *intel_context_get_active_request(struct intel_context *ce);
273
272
274
273
static inline bool intel_context_is_barrier(const struct intel_context *ce)
275
274
{
+2
-2
drivers/gpu/drm/i915/gt/intel_engine.h
+2
-2
drivers/gpu/drm/i915/gt/intel_engine.h
···
248
248
ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine,
249
249
ktime_t *now);
250
250
251
-
struct i915_request *
252
-
intel_engine_execlist_find_hung_request(struct intel_engine_cs *engine);
251
+
void intel_engine_get_hung_entity(struct intel_engine_cs *engine,
252
+
struct intel_context **ce, struct i915_request **rq);
253
253
254
254
u32 intel_engine_context_size(struct intel_gt *gt, u8 class);
255
255
struct intel_context *
+39
-35
drivers/gpu/drm/i915/gt/intel_engine_cs.c
+39
-35
drivers/gpu/drm/i915/gt/intel_engine_cs.c
···
2094
2094
}
2095
2095
}
2096
2096
2097
-
static unsigned long list_count(struct list_head *list)
2098
-
{
2099
-
struct list_head *pos;
2100
-
unsigned long count = 0;
2101
-
2102
-
list_for_each(pos, list)
2103
-
count++;
2104
-
2105
-
return count;
2106
-
}
2107
-
2108
2097
static unsigned long read_ul(void *p, size_t x)
2109
2098
{
2110
2099
return *(unsigned long *)(p + x);
···
2185
2196
}
2186
2197
}
2187
2198
2188
-
static void engine_dump_active_requests(struct intel_engine_cs *engine, struct drm_printer *m)
2199
+
static void engine_dump_active_requests(struct intel_engine_cs *engine,
2200
+
struct drm_printer *m)
2189
2201
{
2202
+
struct intel_context *hung_ce = NULL;
2190
2203
struct i915_request *hung_rq = NULL;
2191
-
struct intel_context *ce;
2192
-
bool guc;
2193
2204
2194
2205
/*
2195
2206
* No need for an engine->irq_seqno_barrier() before the seqno reads.
···
2198
2209
* But the intention here is just to report an instantaneous snapshot
2199
2210
* so that's fine.
2200
2211
*/
2201
-
lockdep_assert_held(&engine->sched_engine->lock);
2212
+
intel_engine_get_hung_entity(engine, &hung_ce, &hung_rq);
2202
2213
2203
2214
drm_printf(m, "\tRequests:\n");
2204
2215
2205
-
guc = intel_uc_uses_guc_submission(&engine->gt->uc);
2206
-
if (guc) {
2207
-
ce = intel_engine_get_hung_context(engine);
2208
-
if (ce)
2209
-
hung_rq = intel_context_find_active_request(ce);
2210
-
} else {
2211
-
hung_rq = intel_engine_execlist_find_hung_request(engine);
2212
-
}
2213
-
2214
2216
if (hung_rq)
2215
2217
engine_dump_request(hung_rq, m, "\t\thung");
2218
+
else if (hung_ce)
2219
+
drm_printf(m, "\t\tGot hung ce but no hung rq!\n");
2216
2220
2217
-
if (guc)
2221
+
if (intel_uc_uses_guc_submission(&engine->gt->uc))
2218
2222
intel_guc_dump_active_requests(engine, hung_rq, m);
2219
2223
else
2220
-
intel_engine_dump_active_requests(&engine->sched_engine->requests,
2221
-
hung_rq, m);
2224
+
intel_execlists_dump_active_requests(engine, hung_rq, m);
2225
+
2226
+
if (hung_rq)
2227
+
i915_request_put(hung_rq);
2222
2228
}
2223
2229
2224
2230
void intel_engine_dump(struct intel_engine_cs *engine,
···
2223
2239
struct i915_gpu_error * const error = &engine->i915->gpu_error;
2224
2240
struct i915_request *rq;
2225
2241
intel_wakeref_t wakeref;
2226
-
unsigned long flags;
2227
2242
ktime_t dummy;
2228
2243
2229
2244
if (header) {
···
2259
2276
i915_reset_count(error));
2260
2277
print_properties(engine, m);
2261
2278
2262
-
spin_lock_irqsave(&engine->sched_engine->lock, flags);
2263
2279
engine_dump_active_requests(engine, m);
2264
-
2265
-
drm_printf(m, "\tOn hold?: %lu\n",
2266
-
list_count(&engine->sched_engine->hold));
2267
-
spin_unlock_irqrestore(&engine->sched_engine->lock, flags);
2268
2280
2269
2281
drm_printf(m, "\tMMIO base: 0x%08x\n", engine->mmio_base);
2270
2282
wakeref = intel_runtime_pm_get_if_in_use(engine->uncore->rpm);
···
2306
2328
return siblings[0]->cops->create_virtual(siblings, count, flags);
2307
2329
}
2308
2330
2309
-
struct i915_request *
2310
-
intel_engine_execlist_find_hung_request(struct intel_engine_cs *engine)
2331
+
static struct i915_request *engine_execlist_find_hung_request(struct intel_engine_cs *engine)
2311
2332
{
2312
2333
struct i915_request *request, *active = NULL;
2313
2334
···
2356
2379
}
2357
2380
2358
2381
return active;
2382
+
}
2383
+
2384
+
void intel_engine_get_hung_entity(struct intel_engine_cs *engine,
2385
+
struct intel_context **ce, struct i915_request **rq)
2386
+
{
2387
+
unsigned long flags;
2388
+
2389
+
*ce = intel_engine_get_hung_context(engine);
2390
+
if (*ce) {
2391
+
intel_engine_clear_hung_context(engine);
2392
+
2393
+
*rq = intel_context_get_active_request(*ce);
2394
+
return;
2395
+
}
2396
+
2397
+
/*
2398
+
* Getting here with GuC enabled means it is a forced error capture
2399
+
* with no actual hang. So, no need to attempt the execlist search.
2400
+
*/
2401
+
if (intel_uc_uses_guc_submission(&engine->gt->uc))
2402
+
return;
2403
+
2404
+
spin_lock_irqsave(&engine->sched_engine->lock, flags);
2405
+
*rq = engine_execlist_find_hung_request(engine);
2406
+
if (*rq)
2407
+
*rq = i915_request_get_rcu(*rq);
2408
+
spin_unlock_irqrestore(&engine->sched_engine->lock, flags);
2359
2409
}
2360
2410
2361
2411
void xehp_enable_ccs_engines(struct intel_engine_cs *engine)
+27
drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+27
drivers/gpu/drm/i915/gt/intel_execlists_submission.c
···
4148
4148
spin_unlock_irqrestore(&sched_engine->lock, flags);
4149
4149
}
4150
4150
4151
+
static unsigned long list_count(struct list_head *list)
4152
+
{
4153
+
struct list_head *pos;
4154
+
unsigned long count = 0;
4155
+
4156
+
list_for_each(pos, list)
4157
+
count++;
4158
+
4159
+
return count;
4160
+
}
4161
+
4162
+
void intel_execlists_dump_active_requests(struct intel_engine_cs *engine,
4163
+
struct i915_request *hung_rq,
4164
+
struct drm_printer *m)
4165
+
{
4166
+
unsigned long flags;
4167
+
4168
+
spin_lock_irqsave(&engine->sched_engine->lock, flags);
4169
+
4170
+
intel_engine_dump_active_requests(&engine->sched_engine->requests, hung_rq, m);
4171
+
4172
+
drm_printf(m, "\tOn hold?: %lu\n",
4173
+
list_count(&engine->sched_engine->hold));
4174
+
4175
+
spin_unlock_irqrestore(&engine->sched_engine->lock, flags);
4176
+
}
4177
+
4151
4178
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
4152
4179
#include "selftest_execlists.c"
4153
4180
#endif
+4
drivers/gpu/drm/i915/gt/intel_execlists_submission.h
+4
drivers/gpu/drm/i915/gt/intel_execlists_submission.h
···
32
32
int indent),
33
33
unsigned int max);
34
34
35
+
void intel_execlists_dump_active_requests(struct intel_engine_cs *engine,
36
+
struct i915_request *hung_rq,
37
+
struct drm_printer *m);
38
+
35
39
bool
36
40
intel_engine_in_execlists_submission_mode(const struct intel_engine_cs *engine);
37
41
+13
-1
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+13
-1
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
···
1702
1702
goto next_context;
1703
1703
1704
1704
guilty = false;
1705
-
rq = intel_context_find_active_request(ce);
1705
+
rq = intel_context_get_active_request(ce);
1706
1706
if (!rq) {
1707
1707
head = ce->ring->tail;
1708
1708
goto out_replay;
···
1715
1715
head = intel_ring_wrap(ce->ring, rq->head);
1716
1716
1717
1717
__i915_request_reset(rq, guilty);
1718
+
i915_request_put(rq);
1718
1719
out_replay:
1719
1720
guc_reset_state(ce, head, guilty);
1720
1721
next_context:
···
4818
4817
4819
4818
xa_lock_irqsave(&guc->context_lookup, flags);
4820
4819
xa_for_each(&guc->context_lookup, index, ce) {
4820
+
bool found;
4821
+
4821
4822
if (!kref_get_unless_zero(&ce->ref))
4822
4823
continue;
4823
4824
···
4836
4833
goto next;
4837
4834
}
4838
4835
4836
+
found = false;
4837
+
spin_lock(&ce->guc_state.lock);
4839
4838
list_for_each_entry(rq, &ce->guc_state.requests, sched.link) {
4840
4839
if (i915_test_request_state(rq) != I915_REQUEST_ACTIVE)
4841
4840
continue;
4842
4841
4842
+
found = true;
4843
+
break;
4844
+
}
4845
+
spin_unlock(&ce->guc_state.lock);
4846
+
4847
+
if (found) {
4843
4848
intel_engine_set_hung_context(engine, ce);
4844
4849
4845
4850
/* Can only cope with one hang at a time... */
···
4855
4844
xa_lock(&guc->context_lookup);
4856
4845
goto done;
4857
4846
}
4847
+
4858
4848
next:
4859
4849
intel_context_put(ce);
4860
4850
xa_lock(&guc->context_lookup);
+6
-27
drivers/gpu/drm/i915/i915_gpu_error.c
+6
-27
drivers/gpu/drm/i915/i915_gpu_error.c
···
1596
1596
{
1597
1597
struct intel_engine_capture_vma *capture = NULL;
1598
1598
struct intel_engine_coredump *ee;
1599
-
struct intel_context *ce;
1599
+
struct intel_context *ce = NULL;
1600
1600
struct i915_request *rq = NULL;
1601
-
unsigned long flags;
1602
1601
1603
1602
ee = intel_engine_coredump_alloc(engine, ALLOW_FAIL, dump_flags);
1604
1603
if (!ee)
1605
1604
return NULL;
1606
1605
1607
-
ce = intel_engine_get_hung_context(engine);
1608
-
if (ce) {
1609
-
intel_engine_clear_hung_context(engine);
1610
-
rq = intel_context_find_active_request(ce);
1611
-
if (!rq || !i915_request_started(rq))
1612
-
goto no_request_capture;
1613
-
} else {
1614
-
/*
1615
-
* Getting here with GuC enabled means it is a forced error capture
1616
-
* with no actual hang. So, no need to attempt the execlist search.
1617
-
*/
1618
-
if (!intel_uc_uses_guc_submission(&engine->gt->uc)) {
1619
-
spin_lock_irqsave(&engine->sched_engine->lock, flags);
1620
-
rq = intel_engine_execlist_find_hung_request(engine);
1621
-
spin_unlock_irqrestore(&engine->sched_engine->lock,
1622
-
flags);
1623
-
}
1624
-
}
1625
-
if (rq)
1626
-
rq = i915_request_get_rcu(rq);
1627
-
1628
-
if (!rq)
1606
+
intel_engine_get_hung_entity(engine, &ce, &rq);
1607
+
if (!rq || !i915_request_started(rq))
1629
1608
goto no_request_capture;
1630
1609
1631
1610
capture = intel_engine_coredump_add_request(ee, rq, ATOMIC_MAYFAIL);
1632
-
if (!capture) {
1633
-
i915_request_put(rq);
1611
+
if (!capture)
1634
1612
goto no_request_capture;
1635
-
}
1636
1613
if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)
1637
1614
intel_guc_capture_get_matching_node(engine->gt, ee, ce);
1638
1615
···
1619
1642
return ee;
1620
1643
1621
1644
no_request_capture:
1645
+
if (rq)
1646
+
i915_request_put(rq);
1622
1647
kfree(ee);
1623
1648
return NULL;
1624
1649
}
+1
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
+1
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
···
97
97
int gp102_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
98
98
int gp10b_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
99
99
int gv100_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
100
+
int tu102_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
100
101
int ga100_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
101
102
int ga102_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
102
103
+3
drivers/gpu/drm/nouveau/nvkm/core/firmware.c
+3
drivers/gpu/drm/nouveau/nvkm/core/firmware.c
+5
-5
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+5
-5
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
···
2405
2405
.bus = { 0x00000001, gf100_bus_new },
2406
2406
.devinit = { 0x00000001, tu102_devinit_new },
2407
2407
.fault = { 0x00000001, tu102_fault_new },
2408
-
.fb = { 0x00000001, gv100_fb_new },
2408
+
.fb = { 0x00000001, tu102_fb_new },
2409
2409
.fuse = { 0x00000001, gm107_fuse_new },
2410
2410
.gpio = { 0x00000001, gk104_gpio_new },
2411
2411
.gsp = { 0x00000001, gv100_gsp_new },
···
2440
2440
.bus = { 0x00000001, gf100_bus_new },
2441
2441
.devinit = { 0x00000001, tu102_devinit_new },
2442
2442
.fault = { 0x00000001, tu102_fault_new },
2443
-
.fb = { 0x00000001, gv100_fb_new },
2443
+
.fb = { 0x00000001, tu102_fb_new },
2444
2444
.fuse = { 0x00000001, gm107_fuse_new },
2445
2445
.gpio = { 0x00000001, gk104_gpio_new },
2446
2446
.gsp = { 0x00000001, gv100_gsp_new },
···
2475
2475
.bus = { 0x00000001, gf100_bus_new },
2476
2476
.devinit = { 0x00000001, tu102_devinit_new },
2477
2477
.fault = { 0x00000001, tu102_fault_new },
2478
-
.fb = { 0x00000001, gv100_fb_new },
2478
+
.fb = { 0x00000001, tu102_fb_new },
2479
2479
.fuse = { 0x00000001, gm107_fuse_new },
2480
2480
.gpio = { 0x00000001, gk104_gpio_new },
2481
2481
.gsp = { 0x00000001, gv100_gsp_new },
···
2510
2510
.bus = { 0x00000001, gf100_bus_new },
2511
2511
.devinit = { 0x00000001, tu102_devinit_new },
2512
2512
.fault = { 0x00000001, tu102_fault_new },
2513
-
.fb = { 0x00000001, gv100_fb_new },
2513
+
.fb = { 0x00000001, tu102_fb_new },
2514
2514
.fuse = { 0x00000001, gm107_fuse_new },
2515
2515
.gpio = { 0x00000001, gk104_gpio_new },
2516
2516
.gsp = { 0x00000001, gv100_gsp_new },
···
2545
2545
.bus = { 0x00000001, gf100_bus_new },
2546
2546
.devinit = { 0x00000001, tu102_devinit_new },
2547
2547
.fault = { 0x00000001, tu102_fault_new },
2548
-
.fb = { 0x00000001, gv100_fb_new },
2548
+
.fb = { 0x00000001, tu102_fb_new },
2549
2549
.fuse = { 0x00000001, gm107_fuse_new },
2550
2550
.gpio = { 0x00000001, gk104_gpio_new },
2551
2551
.gsp = { 0x00000001, gv100_gsp_new },
+13
-1
drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c
+13
-1
drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c
···
48
48
img += 4;
49
49
len -= 4;
50
50
}
51
+
52
+
/* Sigh. Tegra PMU FW's init message... */
53
+
if (len) {
54
+
u32 data = nvkm_falcon_rd32(falcon, 0x1c4 + (port * 8));
55
+
56
+
while (len--) {
57
+
*(u8 *)img++ = data & 0xff;
58
+
data >>= 8;
59
+
}
60
+
}
51
61
}
52
62
53
63
static void
···
74
64
img += 4;
75
65
len -= 4;
76
66
}
67
+
68
+
WARN_ON(len);
77
69
}
78
70
79
71
static void
···
86
74
87
75
const struct nvkm_falcon_func_pio
88
76
gm200_flcn_dmem_pio = {
89
-
.min = 4,
77
+
.min = 1,
90
78
.max = 0x100,
91
79
.wr_init = gm200_flcn_pio_dmem_wr_init,
92
80
.wr = gm200_flcn_pio_dmem_wr,
+23
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/tu102.c
+23
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/tu102.c
···
65
65
return ret;
66
66
}
67
67
68
+
static int
69
+
tu102_devinit_wait(struct nvkm_device *device)
70
+
{
71
+
unsigned timeout = 50 + 2000;
72
+
73
+
do {
74
+
if (nvkm_rd32(device, 0x118128) & 0x00000001) {
75
+
if ((nvkm_rd32(device, 0x118234) & 0x000000ff) == 0xff)
76
+
return 0;
77
+
}
78
+
79
+
usleep_range(1000, 2000);
80
+
} while (timeout--);
81
+
82
+
return -ETIMEDOUT;
83
+
}
84
+
68
85
int
69
86
tu102_devinit_post(struct nvkm_devinit *base, bool post)
70
87
{
71
88
struct nv50_devinit *init = nv50_devinit(base);
89
+
int ret;
90
+
91
+
ret = tu102_devinit_wait(init->base.subdev.device);
92
+
if (ret)
93
+
return ret;
94
+
72
95
gm200_devinit_preos(init, post);
73
96
return 0;
74
97
}
+1
drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild
+1
drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild
+1
-7
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga102.c
+1
-7
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga102.c
···
40
40
return ret;
41
41
}
42
42
43
-
static bool
44
-
ga102_fb_vpr_scrub_required(struct nvkm_fb *fb)
45
-
{
46
-
return (nvkm_rd32(fb->subdev.device, 0x1fa80c) & 0x00000010) != 0;
47
-
}
48
-
49
43
static const struct nvkm_fb_func
50
44
ga102_fb = {
51
45
.dtor = gf100_fb_dtor,
···
50
56
.sysmem.flush_page_init = gf100_fb_sysmem_flush_page_init,
51
57
.ram_new = ga102_ram_new,
52
58
.default_bigpage = 16,
53
-
.vpr.scrub_required = ga102_fb_vpr_scrub_required,
59
+
.vpr.scrub_required = tu102_fb_vpr_scrub_required,
54
60
.vpr.scrub = ga102_fb_vpr_scrub,
55
61
};
56
62
-5
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.c
-5
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.c
···
49
49
}
50
50
51
51
MODULE_FIRMWARE("nvidia/gv100/nvdec/scrubber.bin");
52
-
MODULE_FIRMWARE("nvidia/tu102/nvdec/scrubber.bin");
53
-
MODULE_FIRMWARE("nvidia/tu104/nvdec/scrubber.bin");
54
-
MODULE_FIRMWARE("nvidia/tu106/nvdec/scrubber.bin");
55
-
MODULE_FIRMWARE("nvidia/tu116/nvdec/scrubber.bin");
56
-
MODULE_FIRMWARE("nvidia/tu117/nvdec/scrubber.bin");
+2
drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h
+2
drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h
+55
drivers/gpu/drm/nouveau/nvkm/subdev/fb/tu102.c
+55
drivers/gpu/drm/nouveau/nvkm/subdev/fb/tu102.c
···
1
+
/*
2
+
* Copyright 2018 Red Hat Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*/
22
+
#include "gf100.h"
23
+
#include "ram.h"
24
+
25
+
bool
26
+
tu102_fb_vpr_scrub_required(struct nvkm_fb *fb)
27
+
{
28
+
return (nvkm_rd32(fb->subdev.device, 0x1fa80c) & 0x00000010) != 0;
29
+
}
30
+
31
+
static const struct nvkm_fb_func
32
+
tu102_fb = {
33
+
.dtor = gf100_fb_dtor,
34
+
.oneinit = gf100_fb_oneinit,
35
+
.init = gm200_fb_init,
36
+
.init_page = gv100_fb_init_page,
37
+
.init_unkn = gp100_fb_init_unkn,
38
+
.sysmem.flush_page_init = gf100_fb_sysmem_flush_page_init,
39
+
.vpr.scrub_required = tu102_fb_vpr_scrub_required,
40
+
.vpr.scrub = gp102_fb_vpr_scrub,
41
+
.ram_new = gp100_ram_new,
42
+
.default_bigpage = 16,
43
+
};
44
+
45
+
int
46
+
tu102_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
47
+
{
48
+
return gp102_fb_new_(&tu102_fb, device, type, inst, pfb);
49
+
}
50
+
51
+
MODULE_FIRMWARE("nvidia/tu102/nvdec/scrubber.bin");
52
+
MODULE_FIRMWARE("nvidia/tu104/nvdec/scrubber.bin");
53
+
MODULE_FIRMWARE("nvidia/tu106/nvdec/scrubber.bin");
54
+
MODULE_FIRMWARE("nvidia/tu116/nvdec/scrubber.bin");
55
+
MODULE_FIRMWARE("nvidia/tu117/nvdec/scrubber.bin");
+1
-1
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c
+12
-4
drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
+12
-4
drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
···
1193
1193
return 0;
1194
1194
}
1195
1195
1196
-
static int boe_panel_unprepare(struct drm_panel *panel)
1196
+
static int boe_panel_disable(struct drm_panel *panel)
1197
1197
{
1198
1198
struct boe_panel *boe = to_boe_panel(panel);
1199
1199
int ret;
1200
-
1201
-
if (!boe->prepared)
1202
-
return 0;
1203
1200
1204
1201
ret = boe_panel_enter_sleep_mode(boe);
1205
1202
if (ret < 0) {
···
1205
1208
}
1206
1209
1207
1210
msleep(150);
1211
+
1212
+
return 0;
1213
+
}
1214
+
1215
+
static int boe_panel_unprepare(struct drm_panel *panel)
1216
+
{
1217
+
struct boe_panel *boe = to_boe_panel(panel);
1218
+
1219
+
if (!boe->prepared)
1220
+
return 0;
1208
1221
1209
1222
if (boe->desc->discharge_on_disable) {
1210
1223
regulator_disable(boe->avee);
···
1535
1528
}
1536
1529
1537
1530
static const struct drm_panel_funcs boe_panel_funcs = {
1531
+
.disable = boe_panel_disable,
1538
1532
.unprepare = boe_panel_unprepare,
1539
1533
.prepare = boe_panel_prepare,
1540
1534
.enable = boe_panel_enable,
+7
-11
drivers/gpu/drm/solomon/ssd130x.c
+7
-11
drivers/gpu/drm/solomon/ssd130x.c
···
656
656
.atomic_check = drm_crtc_helper_atomic_check,
657
657
};
658
658
659
-
static void ssd130x_crtc_reset(struct drm_crtc *crtc)
660
-
{
661
-
struct drm_device *drm = crtc->dev;
662
-
struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);
663
-
664
-
ssd130x_init(ssd130x);
665
-
666
-
drm_atomic_helper_crtc_reset(crtc);
667
-
}
668
-
669
659
static const struct drm_crtc_funcs ssd130x_crtc_funcs = {
670
-
.reset = ssd130x_crtc_reset,
660
+
.reset = drm_atomic_helper_crtc_reset,
671
661
.destroy = drm_crtc_cleanup,
672
662
.set_config = drm_atomic_helper_set_config,
673
663
.page_flip = drm_atomic_helper_page_flip,
···
675
685
ret = ssd130x_power_on(ssd130x);
676
686
if (ret)
677
687
return;
688
+
689
+
ret = ssd130x_init(ssd130x);
690
+
if (ret) {
691
+
ssd130x_power_off(ssd130x);
692
+
return;
693
+
}
678
694
679
695
ssd130x_write_cmd(ssd130x, 1, SSD130X_DISPLAY_ON);
680
696
+2
-1
drivers/gpu/drm/vc4/vc4_hdmi.c
+2
-1
drivers/gpu/drm/vc4/vc4_hdmi.c