Merge tag 'amd-drm-next-6.20-2026-01-16' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

+2

drivers/gpu/drm/amd/amdgpu/amdgpu.h

··· 269 269 extern int amdgpu_wbrf; 270 270 extern int amdgpu_user_queue; 271 271 272 + extern uint amdgpu_hdmi_hpd_debounce_delay_ms; 273 + 272 274 #define AMDGPU_VM_MAX_NUM_CTX 4096 273 275 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 274 276 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000

+10 -5

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

··· 248 248 kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry); 249 249 } 250 250 251 + void amdgpu_amdkfd_teardown_processes(struct amdgpu_device *adev) 252 + { 253 + kgd2kfd_teardown_processes(adev); 254 + } 255 + 251 256 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool suspend_proc) 252 257 { 253 258 if (adev->kfd.dev) { ··· 321 316 &adev->kfd.reset_work); 322 317 } 323 318 324 - int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, 325 - void **mem_obj, uint64_t *gpu_addr, 319 + int amdgpu_amdkfd_alloc_kernel_mem(struct amdgpu_device *adev, size_t size, 320 + u32 domain, void **mem_obj, uint64_t *gpu_addr, 326 321 void **cpu_ptr, bool cp_mqd_gfx9) 327 322 { 328 323 struct amdgpu_bo *bo = NULL; ··· 333 328 memset(&bp, 0, sizeof(bp)); 334 329 bp.size = size; 335 330 bp.byte_align = PAGE_SIZE; 336 - bp.domain = AMDGPU_GEM_DOMAIN_GTT; 331 + bp.domain = domain; 337 332 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC; 338 333 bp.type = ttm_bo_type_kernel; 339 334 bp.resv = NULL; ··· 356 351 goto allocate_mem_reserve_bo_failed; 357 352 } 358 353 359 - r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); 354 + r = amdgpu_bo_pin(bo, domain); 360 355 if (r) { 361 356 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r); 362 357 goto allocate_mem_pin_bo_failed; ··· 393 388 return r; 394 389 } 395 390 396 - void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void **mem_obj) 391 + void amdgpu_amdkfd_free_kernel_mem(struct amdgpu_device *adev, void **mem_obj) 397 392 { 398 393 struct amdgpu_bo **bo = (struct amdgpu_bo **) mem_obj; 399 394

+14 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h

··· 158 158 159 159 int amdgpu_amdkfd_init(void); 160 160 void amdgpu_amdkfd_fini(void); 161 + void amdgpu_amdkfd_teardown_processes(struct amdgpu_device *adev); 161 162 162 163 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool suspend_proc); 163 164 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool resume_proc); ··· 241 240 } 242 241 #endif 243 242 /* Shared API */ 244 - int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, 245 - void **mem_obj, uint64_t *gpu_addr, 243 + int amdgpu_amdkfd_alloc_kernel_mem(struct amdgpu_device *adev, size_t size, 244 + u32 domain, void **mem_obj, uint64_t *gpu_addr, 246 245 void **cpu_ptr, bool mqd_gfx9); 247 - void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void **mem_obj); 246 + void amdgpu_amdkfd_free_kernel_mem(struct amdgpu_device *adev, void **mem_obj); 248 247 int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size, 249 248 void **mem_obj); 250 249 void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj); ··· 439 438 bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id); 440 439 bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry, 441 440 bool retry_fault); 441 + void kgd2kfd_lock_kfd(void); 442 + void kgd2kfd_teardown_processes(struct amdgpu_device *adev); 442 443 443 444 #else 444 445 static inline int kgd2kfd_init(void) ··· 551 548 bool retry_fault) 552 549 { 553 550 return false; 551 + } 552 + 553 + static inline void kgd2kfd_lock_kfd(void) 554 + { 555 + } 556 + 557 + static inline void kgd2kfd_teardown_processes(struct amdgpu_device *adev) 558 + { 554 559 } 555 560 556 561 #endif

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

··· 2215 2215 * @bo_gart: Return bo reference 2216 2216 * 2217 2217 * Before return, bo reference count is incremented. To release the reference and unpin/ 2218 - * unmap the BO, call amdgpu_amdkfd_free_gtt_mem. 2218 + * unmap the BO, call amdgpu_amdkfd_free_kernel_mem. 2219 2219 */ 2220 2220 int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_bo *bo, struct amdgpu_bo **bo_gart) 2221 2221 {

+1

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

··· 3509 3509 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); 3510 3510 3511 3511 amdgpu_amdkfd_suspend(adev, true); 3512 + amdgpu_amdkfd_teardown_processes(adev); 3512 3513 amdgpu_userq_suspend(adev); 3513 3514 3514 3515 /* Workaround for ASICs need to disable SMC first */

+4 -7

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

··· 891 891 892 892 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 893 893 { 894 - ssize_t res, at; 894 + ssize_t at; 895 895 int ii; 896 896 897 - for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 897 + for (at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 898 898 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 899 899 */ 900 900 if (at + 12 > PAGE_SIZE) 901 901 break; 902 - res = sysfs_emit_at(buf, at, "0x%08X\n", 902 + at += sysfs_emit_at(buf, at, "0x%08X\n", 903 903 ip_hw_instance->base_addr[ii]); 904 - if (res <= 0) 905 - break; 906 - at += res; 907 904 } 908 905 909 - return res < 0 ? res : at; 906 + return at; 910 907 } 911 908 912 909 static struct ip_hw_instance_attr ip_hw_attr[] = {

+11

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

··· 247 247 int amdgpu_umsch_mm_fwlog; 248 248 int amdgpu_rebar = -1; /* auto */ 249 249 int amdgpu_user_queue = -1; 250 + uint amdgpu_hdmi_hpd_debounce_delay_ms; 250 251 251 252 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 252 253 "DRM_UT_CORE", ··· 1123 1122 */ 1124 1123 MODULE_PARM_DESC(user_queue, "Enable user queues (-1 = auto (default), 0 = disable, 1 = enable, 2 = enable UQs and disable KQs)"); 1125 1124 module_param_named(user_queue, amdgpu_user_queue, int, 0444); 1125 + 1126 + /* 1127 + * DOC: hdmi_hpd_debounce_delay_ms (uint) 1128 + * HDMI HPD disconnect debounce delay in milliseconds. 1129 + * 1130 + * Used to filter short disconnect->reconnect HPD toggles some HDMI sinks 1131 + * generate while entering/leaving power save. Set to 0 to disable by default. 1132 + */ 1133 + MODULE_PARM_DESC(hdmi_hpd_debounce_delay_ms, "HDMI HPD disconnect debounce delay in milliseconds (0 to disable (by default), 1500 is common)"); 1134 + module_param_named(hdmi_hpd_debounce_delay_ms, amdgpu_hdmi_hpd_debounce_delay_ms, uint, 0644); 1126 1135 1127 1136 /* These devices are not supported by amdgpu. 1128 1137 * They are supported by the mach64, r128, radeon drivers

+2 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c

··· 375 375 * @start_page: first page to map in the GART aperture 376 376 * @num_pages: number of pages to be mapped 377 377 * @flags: page table entry flags 378 - * @dst: CPU address of the GART table 378 + * @dst: valid CPU address of GART table, cannot be null 379 379 * 380 380 * Binds a BO that is allocated in VRAM to the GART page table 381 381 * (all ASICs). ··· 396 396 return; 397 397 398 398 for (i = 0; i < num_pages; ++i) { 399 - amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr, 399 + amdgpu_gmc_set_pte_pde(adev, dst, 400 400 start_page + i, pa + AMDGPU_GPU_PAGE_SIZE * i, flags); 401 401 } 402 402

+37 -39

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

··· 417 417 /* always clear VRAM */ 418 418 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED; 419 419 420 - if (args->in.domains & AMDGPU_GEM_DOMAIN_MMIO_REMAP) 421 - return -EINVAL; 422 - 423 420 /* create a gem object to contain this object in */ 424 421 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | 425 422 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { ··· 729 732 struct amdgpu_bo_va *bo_va, 730 733 uint32_t operation) 731 734 { 732 - struct dma_fence *clear_fence = dma_fence_get_stub(); 733 - struct dma_fence *last_update = NULL; 734 - int r; 735 + struct dma_fence *fence; 736 + int r = 0; 737 + 738 + /* Always start from the VM's existing last update fence. */ 739 + fence = dma_fence_get(vm->last_update); 735 740 736 741 if (!amdgpu_vm_ready(vm)) 737 - return clear_fence; 742 + return fence; 738 743 739 - /* First clear freed BOs and get a fence for that work, if any. */ 740 - r = amdgpu_vm_clear_freed(adev, vm, &clear_fence); 744 + /* 745 + * First clean up any freed mappings in the VM. 746 + * 747 + * amdgpu_vm_clear_freed() may replace @fence with a new fence if it 748 + * schedules GPU work. If nothing needs clearing, @fence can remain as 749 + * the original vm->last_update. 750 + */ 751 + r = amdgpu_vm_clear_freed(adev, vm, &fence); 741 752 if (r) 742 753 goto error; 743 754 ··· 763 758 goto error; 764 759 765 760 /* 766 - * Decide which fence represents the "last update" for this VM/BO: 761 + * Decide which fence best represents the last update: 767 762 * 768 - * - For MAP/REPLACE we want the PT update fence, which is tracked as 769 - * either vm->last_update (for always-valid BOs) or bo_va->last_pt_update 770 - * (for per-BO updates). 763 + * MAP/REPLACE: 764 + * - For always-valid mappings, use vm->last_update. 765 + * - Otherwise, export bo_va->last_pt_update. 771 766 * 772 - * - For UNMAP/CLEAR we rely on the fence returned by 773 - * amdgpu_vm_clear_freed(), which already covers the page table work 774 - * for the removed mappings. 767 + * UNMAP/CLEAR: 768 + * Keep the fence returned by amdgpu_vm_clear_freed(). If no work was 769 + * needed, it can remain as vm->last_pt_update. 770 + * 771 + * The VM and BO update fences are always initialized to a valid value. 772 + * vm->last_update and bo_va->last_pt_update always start as valid fences. 773 + * and are never expected to be NULL. 775 774 */ 776 775 switch (operation) { 777 776 case AMDGPU_VA_OP_MAP: 778 777 case AMDGPU_VA_OP_REPLACE: 779 - if (bo_va && bo_va->base.bo) { 780 - if (amdgpu_vm_is_bo_always_valid(vm, bo_va->base.bo)) { 781 - if (vm->last_update) 782 - last_update = dma_fence_get(vm->last_update); 783 - } else { 784 - if (bo_va->last_pt_update) 785 - last_update = dma_fence_get(bo_va->last_pt_update); 786 - } 787 - } 778 + /* 779 + * For MAP/REPLACE, return the page table update fence for the 780 + * mapping we just modified. bo_va is expected to be valid here. 781 + */ 782 + dma_fence_put(fence); 783 + 784 + if (amdgpu_vm_is_bo_always_valid(vm, bo_va->base.bo)) 785 + fence = dma_fence_get(vm->last_update); 786 + else 787 + fence = dma_fence_get(bo_va->last_pt_update); 788 788 break; 789 789 case AMDGPU_VA_OP_UNMAP: 790 790 case AMDGPU_VA_OP_CLEAR: 791 - if (clear_fence) 792 - last_update = dma_fence_get(clear_fence); 793 - break; 794 791 default: 792 + /* keep @fence as returned by amdgpu_vm_clear_freed() */ 795 793 break; 796 794 } 797 795 ··· 802 794 if (r && r != -ERESTARTSYS) 803 795 DRM_ERROR("Couldn't update BO_VA (%d)\n", r); 804 796 805 - /* 806 - * If we managed to pick a more specific last-update fence, prefer it 807 - * over the generic clear_fence and drop the extra reference to the 808 - * latter. 809 - */ 810 - if (last_update) { 811 - dma_fence_put(clear_fence); 812 - return last_update; 813 - } 814 - 815 - return clear_fence; 797 + return fence; 816 798 } 817 799 818 800 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,

+4

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

··· 780 780 return 0; 781 781 782 782 if (!adev->gmc.flush_pasid_uses_kiq || !ring->sched.ready) { 783 + 784 + if (!adev->gmc.gmc_funcs->flush_gpu_tlb_pasid) 785 + return 0; 786 + 783 787 if (adev->gmc.flush_tlb_needs_extra_type_2) 784 788 adev->gmc.gmc_funcs->flush_gpu_tlb_pasid(adev, pasid, 785 789 2, all_hub,

+41 -24

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c

··· 31 31 32 32 #define AMDGPU_MES_MAX_NUM_OF_QUEUES_PER_PROCESS 1024 33 33 #define AMDGPU_ONE_DOORBELL_SIZE 8 34 - #define AMDGPU_MES_RESERVED_QUEUES 2 35 34 36 35 int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev) 37 36 { ··· 88 89 bitmap_free(adev->mes.doorbell_bitmap); 89 90 } 90 91 92 + static inline u32 amdgpu_mes_get_hqd_mask(u32 num_pipe, 93 + u32 num_hqd_per_pipe, 94 + u32 num_reserved_hqd) 95 + { 96 + if (num_pipe == 0) 97 + return 0; 98 + 99 + u32 total_hqd_mask = (u32)((1ULL << num_hqd_per_pipe) - 1); 100 + u32 reserved_hqd_mask = (u32)((1ULL << DIV_ROUND_UP(num_reserved_hqd, num_pipe)) - 1); 101 + 102 + return (total_hqd_mask & ~reserved_hqd_mask); 103 + } 104 + 91 105 int amdgpu_mes_init(struct amdgpu_device *adev) 92 106 { 93 107 int i, r, num_pipes; 94 108 u32 total_vmid_mask, reserved_vmid_mask; 95 - u32 queue_mask, reserved_queue_mask; 96 109 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; 110 + u32 gfx_hqd_mask = amdgpu_mes_get_hqd_mask(adev->gfx.me.num_pipe_per_me, 111 + adev->gfx.me.num_queue_per_pipe, 112 + adev->gfx.disable_kq ? 0 : adev->gfx.num_gfx_rings); 113 + u32 compute_hqd_mask = amdgpu_mes_get_hqd_mask(adev->gfx.mec.num_pipe_per_mec, 114 + adev->gfx.mec.num_queue_per_pipe, 115 + adev->gfx.disable_kq ? 0 : adev->gfx.num_compute_rings); 97 116 98 117 adev->mes.adev = adev; 99 118 ··· 132 115 adev->mes.vmid_mask_mmhub = 0xFF00; 133 116 adev->mes.vmid_mask_gfxhub = total_vmid_mask & ~reserved_vmid_mask; 134 117 135 - queue_mask = (u32)(1UL << adev->gfx.mec.num_queue_per_pipe) - 1; 136 - reserved_queue_mask = (u32)(1UL << AMDGPU_MES_RESERVED_QUEUES) - 1; 137 - 138 118 num_pipes = adev->gfx.me.num_pipe_per_me * adev->gfx.me.num_me; 139 119 if (num_pipes > AMDGPU_MES_MAX_GFX_PIPES) 140 120 dev_warn(adev->dev, "more gfx pipes than supported by MES! (%d vs %d)\n", ··· 140 126 for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++) { 141 127 if (i >= num_pipes) 142 128 break; 143 - if (amdgpu_ip_version(adev, GC_HWIP, 0) >= 144 - IP_VERSION(12, 0, 0)) 145 - /* 146 - * GFX V12 has only one GFX pipe, but 8 queues in it. 147 - * GFX pipe 0 queue 0 is being used by Kernel queue. 148 - * Set GFX pipe 0 queue 1-7 for MES scheduling 149 - * mask = 1111 1110b 150 - */ 151 - adev->mes.gfx_hqd_mask[i] = adev->gfx.disable_kq ? 0xFF : 0xFE; 152 - else 153 - /* 154 - * GFX pipe 0 queue 0 is being used by Kernel queue. 155 - * Set GFX pipe 0 queue 1 for MES scheduling 156 - * mask = 10b 157 - */ 158 - adev->mes.gfx_hqd_mask[i] = adev->gfx.disable_kq ? 0x3 : 0x2; 129 + 130 + adev->mes.gfx_hqd_mask[i] = gfx_hqd_mask; 159 131 } 160 132 161 133 num_pipes = adev->gfx.mec.num_pipe_per_mec * adev->gfx.mec.num_mec; ··· 150 150 num_pipes, AMDGPU_MES_MAX_COMPUTE_PIPES); 151 151 152 152 for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) { 153 - if (i >= num_pipes) 153 + /* 154 + * Currently, only MEC1 is used for both kernel and user compute queue. 155 + * To enable other MEC, we need to redistribute queues per pipe and 156 + * adjust queue resource shared with kfd that needs a separate patch. 157 + * Skip other MEC for now to avoid potential issues. 158 + */ 159 + if (i >= adev->gfx.mec.num_pipe_per_mec) 154 160 break; 155 - adev->mes.compute_hqd_mask[i] = 156 - adev->gfx.disable_kq ? 0xF : (queue_mask & ~reserved_queue_mask); 161 + 162 + adev->mes.compute_hqd_mask[i] = compute_hqd_mask; 157 163 } 158 164 159 165 num_pipes = adev->sdma.num_instances; ··· 172 166 break; 173 167 adev->mes.sdma_hqd_mask[i] = 0xfc; 174 168 } 169 + 170 + dev_info(adev->dev, 171 + "MES: vmid_mask_mmhub 0x%08x, vmid_mask_gfxhub 0x%08x\n", 172 + adev->mes.vmid_mask_mmhub, 173 + adev->mes.vmid_mask_gfxhub); 174 + 175 + dev_info(adev->dev, 176 + "MES: gfx_hqd_mask 0x%08x, compute_hqd_mask 0x%08x, sdma_hqd_mask 0x%08x\n", 177 + adev->mes.gfx_hqd_mask[0], 178 + adev->mes.compute_hqd_mask[0], 179 + adev->mes.sdma_hqd_mask[0]); 175 180 176 181 for (i = 0; i < AMDGPU_MAX_MES_PIPES * num_xcc; i++) { 177 182 r = amdgpu_device_wb_get(adev, &adev->mes.sch_ctx_offs[i]);

+10 -11

drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

··· 153 153 c++; 154 154 } 155 155 156 - if (domain & AMDGPU_GEM_DOMAIN_MMIO_REMAP) { 157 - places[c].fpfn = 0; 158 - places[c].lpfn = 0; 159 - places[c].mem_type = AMDGPU_PL_MMIO_REMAP; 160 - places[c].flags = 0; 161 - c++; 162 - } 163 - 164 156 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 165 157 places[c].fpfn = 0; 166 158 places[c].lpfn = 0; ··· 1538 1546 */ 1539 1547 uint32_t amdgpu_bo_mem_stats_placement(struct amdgpu_bo *bo) 1540 1548 { 1541 - uint32_t domain = bo->preferred_domains & AMDGPU_GEM_DOMAIN_MASK; 1549 + u32 domain; 1542 1550 1551 + /* 1552 + * MMIO_REMAP is internal now, so it no longer maps from a userspace 1553 + * domain bit. Keep fdinfo/mem-stats visibility by checking the actual 1554 + * TTM placement. 1555 + */ 1556 + if (bo->tbo.resource && bo->tbo.resource->mem_type == AMDGPU_PL_MMIO_REMAP) 1557 + return AMDGPU_PL_MMIO_REMAP; 1558 + 1559 + domain = bo->preferred_domains & AMDGPU_GEM_DOMAIN_MASK; 1543 1560 if (!domain) 1544 1561 return TTM_PL_SYSTEM; 1545 1562 ··· 1567 1566 return AMDGPU_PL_OA; 1568 1567 case AMDGPU_GEM_DOMAIN_DOORBELL: 1569 1568 return AMDGPU_PL_DOORBELL; 1570 - case AMDGPU_GEM_DOMAIN_MMIO_REMAP: 1571 - return AMDGPU_PL_MMIO_REMAP; 1572 1569 default: 1573 1570 return TTM_PL_SYSTEM; 1574 1571 }

-2

drivers/gpu/drm/amd/amdgpu/amdgpu_object.h

··· 168 168 return AMDGPU_GEM_DOMAIN_OA; 169 169 case AMDGPU_PL_DOORBELL: 170 170 return AMDGPU_GEM_DOMAIN_DOORBELL; 171 - case AMDGPU_PL_MMIO_REMAP: 172 - return AMDGPU_GEM_DOMAIN_MMIO_REMAP; 173 171 default: 174 172 break; 175 173 }

+49 -28

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

··· 1909 1909 } 1910 1910 1911 1911 /** 1912 - * amdgpu_ttm_mmio_remap_bo_init - Allocate the singleton 4K MMIO_REMAP BO 1912 + * amdgpu_ttm_mmio_remap_bo_init - Allocate the singleton MMIO_REMAP BO 1913 1913 * @adev: amdgpu device 1914 1914 * 1915 - * Allocates a one-page (4K) GEM BO in AMDGPU_GEM_DOMAIN_MMIO_REMAP when the 1915 + * Allocates a global BO with backing AMDGPU_PL_MMIO_REMAP when the 1916 1916 * hardware exposes a remap base (adev->rmmio_remap.bus_addr) and the host 1917 1917 * PAGE_SIZE is <= AMDGPU_GPU_PAGE_SIZE (4K). The BO is created as a regular 1918 1918 * GEM object (amdgpu_bo_create). 1919 - * 1920 - * The BO is created as a normal GEM object via amdgpu_bo_create(), then 1921 - * reserved and pinned at the TTM level (ttm_bo_pin()) so it can never be 1922 - * migrated or evicted. No CPU mapping is established here. 1923 1919 * 1924 1920 * Return: 1925 1921 * * 0 on success or intentional skip (feature not present/unsupported) 1926 1922 * * negative errno on allocation failure 1927 1923 */ 1928 - static int amdgpu_ttm_mmio_remap_bo_init(struct amdgpu_device *adev) 1924 + static int amdgpu_ttm_alloc_mmio_remap_bo(struct amdgpu_device *adev) 1929 1925 { 1926 + struct ttm_operation_ctx ctx = { false, false }; 1927 + struct ttm_placement placement; 1928 + struct ttm_buffer_object *tbo; 1929 + struct ttm_place placements; 1930 1930 struct amdgpu_bo_param bp; 1931 + struct ttm_resource *tmp; 1931 1932 int r; 1932 1933 1933 1934 /* Skip if HW doesn't expose remap, or if PAGE_SIZE > AMDGPU_GPU_PAGE_SIZE (4K). */ 1934 1935 if (!adev->rmmio_remap.bus_addr || PAGE_SIZE > AMDGPU_GPU_PAGE_SIZE) 1935 1936 return 0; 1936 1937 1938 + /* 1939 + * Allocate a BO first and then move it to AMDGPU_PL_MMIO_REMAP. 1940 + * The initial TTM resource assigned by amdgpu_bo_create() is 1941 + * replaced below with a fixed MMIO_REMAP placement. 1942 + */ 1937 1943 memset(&bp, 0, sizeof(bp)); 1938 - 1939 - /* Create exactly one GEM BO in the MMIO_REMAP domain. */ 1940 - bp.type = ttm_bo_type_device; /* userspace-mappable GEM */ 1941 - bp.size = AMDGPU_GPU_PAGE_SIZE; /* 4K */ 1944 + bp.type = ttm_bo_type_device; 1945 + bp.size = AMDGPU_GPU_PAGE_SIZE; 1942 1946 bp.byte_align = AMDGPU_GPU_PAGE_SIZE; 1943 - bp.domain = AMDGPU_GEM_DOMAIN_MMIO_REMAP; 1947 + bp.domain = 0; 1944 1948 bp.flags = 0; 1945 1949 bp.resv = NULL; 1946 1950 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 1947 - 1948 1951 r = amdgpu_bo_create(adev, &bp, &adev->rmmio_remap.bo); 1949 1952 if (r) 1950 1953 return r; ··· 1956 1953 if (r) 1957 1954 goto err_unref; 1958 1955 1956 + tbo = &adev->rmmio_remap.bo->tbo; 1957 + 1959 1958 /* 1960 1959 * MMIO_REMAP is a fixed I/O placement (AMDGPU_PL_MMIO_REMAP). 1961 - * Use TTM-level pin so the BO cannot be evicted/migrated, 1962 - * independent of GEM domains. This 1963 - * enforces the “fixed I/O window” 1964 1960 */ 1965 - ttm_bo_pin(&adev->rmmio_remap.bo->tbo); 1961 + placement.num_placement = 1; 1962 + placement.placement = &placements; 1963 + placements.fpfn = 0; 1964 + placements.lpfn = 0; 1965 + placements.mem_type = AMDGPU_PL_MMIO_REMAP; 1966 + placements.flags = 0; 1967 + /* Force the BO into the fixed MMIO_REMAP placement */ 1968 + r = ttm_bo_mem_space(tbo, &placement, &tmp, &ctx); 1969 + if (unlikely(r)) 1970 + goto err_unlock; 1971 + 1972 + ttm_resource_free(tbo, &tbo->resource); 1973 + ttm_bo_assign_mem(tbo, tmp); 1974 + ttm_bo_pin(tbo); 1966 1975 1967 1976 amdgpu_bo_unreserve(adev->rmmio_remap.bo); 1968 1977 return 0; 1969 1978 1979 + err_unlock: 1980 + amdgpu_bo_unreserve(adev->rmmio_remap.bo); 1981 + 1970 1982 err_unref: 1971 - if (adev->rmmio_remap.bo) 1972 - amdgpu_bo_unref(&adev->rmmio_remap.bo); 1983 + amdgpu_bo_unref(&adev->rmmio_remap.bo); 1973 1984 adev->rmmio_remap.bo = NULL; 1974 1985 return r; 1975 1986 } 1976 1987 1977 1988 /** 1978 - * amdgpu_ttm_mmio_remap_bo_fini - Free the singleton MMIO_REMAP BO 1989 + * amdgpu_ttm_free_mmio_remap_bo - Free the singleton MMIO_REMAP BO 1979 1990 * @adev: amdgpu device 1980 1991 * 1981 1992 * Frees the kernel-owned MMIO_REMAP BO if it was allocated by 1982 1993 * amdgpu_ttm_mmio_remap_bo_init(). 1983 1994 */ 1984 - static void amdgpu_ttm_mmio_remap_bo_fini(struct amdgpu_device *adev) 1995 + static void amdgpu_ttm_free_mmio_remap_bo(struct amdgpu_device *adev) 1985 1996 { 1986 - struct amdgpu_bo *bo = adev->rmmio_remap.bo; 1987 - 1988 - if (!bo) 1989 - return; /* <-- safest early exit */ 1997 + if (!adev->rmmio_remap.bo) 1998 + return; 1990 1999 1991 2000 if (!amdgpu_bo_reserve(adev->rmmio_remap.bo, true)) { 1992 2001 ttm_bo_unpin(&adev->rmmio_remap.bo->tbo); 1993 2002 amdgpu_bo_unreserve(adev->rmmio_remap.bo); 1994 2003 } 2004 + 2005 + /* 2006 + * At this point we rely on normal DRM teardown ordering: 2007 + * no new user ioctls can access the global MMIO_REMAP BO 2008 + * once TTM teardown begins. 2009 + */ 1995 2010 amdgpu_bo_unref(&adev->rmmio_remap.bo); 1996 2011 adev->rmmio_remap.bo = NULL; 1997 2012 } ··· 2193 2172 return r; 2194 2173 } 2195 2174 2196 - /* Allocate the singleton MMIO_REMAP BO (4K) if supported */ 2197 - r = amdgpu_ttm_mmio_remap_bo_init(adev); 2175 + /* Allocate the singleton MMIO_REMAP BO if supported */ 2176 + r = amdgpu_ttm_alloc_mmio_remap_bo(adev); 2198 2177 if (r) 2199 2178 return r; 2200 2179 ··· 2262 2241 amdgpu_bo_free_kernel(&adev->mman.sdma_access_bo, NULL, 2263 2242 &adev->mman.sdma_access_ptr); 2264 2243 2265 - amdgpu_ttm_mmio_remap_bo_fini(adev); 2244 + amdgpu_ttm_free_mmio_remap_bo(adev); 2266 2245 amdgpu_ttm_fw_reserve_vram_fini(adev); 2267 2246 amdgpu_ttm_drv_reserve_vram_fini(adev); 2268 2247

+16

drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c

··· 889 889 return 0; 890 890 } 891 891 892 + bool amdgpu_userq_enabled(struct drm_device *dev) 893 + { 894 + struct amdgpu_device *adev = drm_to_adev(dev); 895 + int i; 896 + 897 + for (i = 0; i < AMDGPU_HW_IP_NUM; i++) { 898 + if (adev->userq_funcs[i]) 899 + return true; 900 + } 901 + 902 + return false; 903 + } 904 + 892 905 int amdgpu_userq_ioctl(struct drm_device *dev, void *data, 893 906 struct drm_file *filp) 894 907 { 895 908 union drm_amdgpu_userq *args = data; 896 909 int r; 910 + 911 + if (!amdgpu_userq_enabled(dev)) 912 + return -ENOTSUPP; 897 913 898 914 if (amdgpu_userq_input_args_validate(dev, args, filp) < 0) 899 915 return -EINVAL;

+1

drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h

··· 135 135 struct drm_file *filp); 136 136 137 137 u32 amdgpu_userq_get_supported_ip_mask(struct amdgpu_device *adev); 138 + bool amdgpu_userq_enabled(struct drm_device *dev); 138 139 139 140 int amdgpu_userq_suspend(struct amdgpu_device *adev); 140 141 int amdgpu_userq_resume(struct amdgpu_device *adev);

+8

drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c

··· 141 141 void 142 142 amdgpu_userq_fence_driver_free(struct amdgpu_usermode_queue *userq) 143 143 { 144 + dma_fence_put(userq->last_fence); 145 + 144 146 amdgpu_userq_walk_and_drop_fence_drv(&userq->fence_drv_xa); 145 147 xa_destroy(&userq->fence_drv_xa); 146 148 /* Drop the fence_drv reference held by user queue */ ··· 476 474 struct drm_exec exec; 477 475 u64 wptr; 478 476 477 + if (!amdgpu_userq_enabled(dev)) 478 + return -ENOTSUPP; 479 + 479 480 num_syncobj_handles = args->num_syncobj_handles; 480 481 syncobj_handles = memdup_user(u64_to_user_ptr(args->syncobj_handles), 481 482 size_mul(sizeof(u32), num_syncobj_handles)); ··· 660 655 u16 num_points, num_fences = 0; 661 656 int r, i, rentry, wentry, cnt; 662 657 struct drm_exec exec; 658 + 659 + if (!amdgpu_userq_enabled(dev)) 660 + return -ENOTSUPP; 663 661 664 662 num_read_bo_handles = wait_info->num_bo_read_handles; 665 663 bo_handles_read = memdup_user(u64_to_user_ptr(wait_info->bo_read_handles),

+1

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

··· 1262 1262 || ucode_id == AMDGPU_UCODE_ID_SDMA5 1263 1263 || ucode_id == AMDGPU_UCODE_ID_SDMA6 1264 1264 || ucode_id == AMDGPU_UCODE_ID_SDMA7 1265 + || ucode_id == AMDGPU_UCODE_ID_SDMA_RS64 1265 1266 || ucode_id == AMDGPU_UCODE_ID_RLC_G 1266 1267 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 1267 1268 || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM

+1 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

··· 1069 1069 } 1070 1070 1071 1071 /* Prepare a TLB flush fence to be attached to PTs */ 1072 - if (!params->unlocked && 1073 - /* SI doesn't support pasid or KIQ/MES */ 1074 - params->adev->family > AMDGPU_FAMILY_SI) { 1072 + if (!params->unlocked) { 1075 1073 amdgpu_vm_tlb_fence_create(params->adev, vm, fence); 1076 1074 1077 1075 /* Makes sure no PD/PT is freed before the flush */

+2 -1

drivers/gpu/drm/amd/amdkfd/kfd_debug.c

··· 357 357 return 0; 358 358 359 359 if (!pdd->proc_ctx_cpu_ptr) { 360 - r = amdgpu_amdkfd_alloc_gtt_mem(adev, 360 + r = amdgpu_amdkfd_alloc_kernel_mem(adev, 361 361 AMDGPU_MES_PROC_CTX_SIZE, 362 + AMDGPU_GEM_DOMAIN_GTT, 362 363 &pdd->proc_ctx_bo, 363 364 &pdd->proc_ctx_gpu_addr, 364 365 &pdd->proc_ctx_cpu_ptr,

+82 -7

drivers/gpu/drm/amd/amdkfd/kfd_device.c

··· 820 820 /* add another 512KB for all other allocations on gart (HPD, fences) */ 821 821 size += 512 * 1024; 822 822 823 - if (amdgpu_amdkfd_alloc_gtt_mem( 824 - kfd->adev, size, &kfd->gtt_mem, 823 + if (amdgpu_amdkfd_alloc_kernel_mem( 824 + kfd->adev, size, AMDGPU_GEM_DOMAIN_GTT, 825 + &kfd->gtt_mem, 825 826 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 826 827 false)) { 827 828 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 828 - goto alloc_gtt_mem_failure; 829 + goto alloc_kernel_mem_failure; 829 830 } 830 831 831 832 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); ··· 952 951 kfd_doorbell_error: 953 952 kfd_gtt_sa_fini(kfd); 954 953 kfd_gtt_sa_init_error: 955 - amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem); 956 - alloc_gtt_mem_failure: 954 + amdgpu_amdkfd_free_kernel_mem(kfd->adev, &kfd->gtt_mem); 955 + alloc_kernel_mem_failure: 957 956 dev_err(kfd_device, 958 957 "device %x:%x NOT added due to errors\n", 959 958 kfd->adev->pdev->vendor, kfd->adev->pdev->device); ··· 970 969 kfd_doorbell_fini(kfd); 971 970 ida_destroy(&kfd->doorbell_ida); 972 971 kfd_gtt_sa_fini(kfd); 973 - amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem); 972 + amdgpu_amdkfd_free_kernel_mem(kfd->adev, &kfd->gtt_mem); 974 973 } 975 974 976 975 kfree(kfd); 976 + 977 + /* after remove a kfd device unlock kfd driver */ 978 + kgd2kfd_unlock_kfd(NULL); 977 979 } 978 980 979 981 int kgd2kfd_pre_reset(struct kfd_dev *kfd, ··· 1561 1557 return r; 1562 1558 } 1563 1559 1560 + /* unlock a kfd dev or kfd driver */ 1564 1561 void kgd2kfd_unlock_kfd(struct kfd_dev *kfd) 1565 1562 { 1566 1563 mutex_lock(&kfd_processes_mutex); 1567 - --kfd->kfd_dev_lock; 1564 + if (kfd) 1565 + --kfd->kfd_dev_lock; 1566 + else 1567 + --kfd_locked; 1568 1568 mutex_unlock(&kfd_processes_mutex); 1569 1569 } 1570 1570 ··· 1735 1727 kfd_unref_process(p); 1736 1728 } 1737 1729 return false; 1730 + } 1731 + 1732 + /* check if there is kfd process still uses adev */ 1733 + static bool kgd2kfd_check_device_idle(struct amdgpu_device *adev) 1734 + { 1735 + struct kfd_process *p; 1736 + struct hlist_node *p_temp; 1737 + unsigned int temp; 1738 + struct kfd_node *dev; 1739 + 1740 + mutex_lock(&kfd_processes_mutex); 1741 + 1742 + if (hash_empty(kfd_processes_table)) { 1743 + mutex_unlock(&kfd_processes_mutex); 1744 + return true; 1745 + } 1746 + 1747 + /* check if there is device still use adev */ 1748 + hash_for_each_safe(kfd_processes_table, temp, p_temp, p, kfd_processes) { 1749 + for (int i = 0; i < p->n_pdds; i++) { 1750 + dev = p->pdds[i]->dev; 1751 + if (dev->adev == adev) { 1752 + mutex_unlock(&kfd_processes_mutex); 1753 + return false; 1754 + } 1755 + } 1756 + } 1757 + 1758 + mutex_unlock(&kfd_processes_mutex); 1759 + 1760 + return true; 1761 + } 1762 + 1763 + /** kgd2kfd_teardown_processes - gracefully tear down existing 1764 + * kfd processes that use adev 1765 + * 1766 + * @adev: amdgpu_device where kfd processes run on and will be 1767 + * teardown 1768 + * 1769 + */ 1770 + void kgd2kfd_teardown_processes(struct amdgpu_device *adev) 1771 + { 1772 + struct hlist_node *p_temp; 1773 + struct kfd_process *p; 1774 + struct kfd_node *dev; 1775 + unsigned int temp; 1776 + 1777 + mutex_lock(&kfd_processes_mutex); 1778 + 1779 + if (hash_empty(kfd_processes_table)) { 1780 + mutex_unlock(&kfd_processes_mutex); 1781 + return; 1782 + } 1783 + 1784 + hash_for_each_safe(kfd_processes_table, temp, p_temp, p, kfd_processes) { 1785 + for (int i = 0; i < p->n_pdds; i++) { 1786 + dev = p->pdds[i]->dev; 1787 + if (dev->adev == adev) 1788 + kfd_signal_process_terminate_event(p); 1789 + } 1790 + } 1791 + 1792 + mutex_unlock(&kfd_processes_mutex); 1793 + 1794 + /* wait all kfd processes use adev terminate */ 1795 + while (!kgd2kfd_check_device_idle(adev)) 1796 + cond_resched(); 1738 1797 } 1739 1798 1740 1799 #if defined(CONFIG_DEBUG_FS)

+15 -21

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c

··· 1211 1211 pr_debug_ratelimited("Evicting process pid %d queues\n", 1212 1212 pdd->process->lead_thread->pid); 1213 1213 1214 - if (dqm->dev->kfd->shared_resources.enable_mes) { 1214 + if (dqm->dev->kfd->shared_resources.enable_mes) 1215 1215 pdd->last_evict_timestamp = get_jiffies_64(); 1216 - retval = suspend_all_queues_mes(dqm); 1217 - if (retval) { 1218 - dev_err(dev, "Suspending all queues failed"); 1219 - goto out; 1220 - } 1221 - } 1222 1216 1223 1217 /* Mark all queues as evicted. Deactivate all active queues on 1224 1218 * the qpd. ··· 1242 1248 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES : 1243 1249 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, 1244 1250 USE_DEFAULT_GRACE_PERIOD); 1245 - } else { 1246 - retval = resume_all_queues_mes(dqm); 1247 - if (retval) 1248 - dev_err(dev, "Resuming all queues failed"); 1249 1251 } 1250 1252 1251 1253 out: ··· 2899 2909 (dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size * 2900 2910 NUM_XCC(dqm->dev->xcc_mask)); 2901 2911 2902 - retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, size, 2903 - &(mem_obj->gtt_mem), &(mem_obj->gpu_addr), 2912 + retval = amdgpu_amdkfd_alloc_kernel_mem(dev->adev, size, 2913 + AMDGPU_GEM_DOMAIN_GTT, 2914 + &(mem_obj->mem), &(mem_obj->gpu_addr), 2904 2915 (void *)&(mem_obj->cpu_ptr), false); 2905 2916 2906 2917 return retval; 2918 + } 2919 + 2920 + static void deallocate_hiq_sdma_mqd(struct kfd_node *dev, 2921 + struct kfd_mem_obj *mqd) 2922 + { 2923 + WARN(!mqd, "No hiq sdma mqd trunk to free"); 2924 + 2925 + amdgpu_amdkfd_free_kernel_mem(dev->adev, &mqd->mem); 2907 2926 } 2908 2927 2909 2928 struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev) ··· 3040 3041 return dqm; 3041 3042 } 3042 3043 3044 + if (!dev->kfd->shared_resources.enable_mes) 3045 + deallocate_hiq_sdma_mqd(dev, &dqm->hiq_sdma_mqd); 3046 + 3043 3047 out_free: 3044 3048 kfree(dqm); 3045 3049 return NULL; 3046 - } 3047 - 3048 - static void deallocate_hiq_sdma_mqd(struct kfd_node *dev, 3049 - struct kfd_mem_obj *mqd) 3050 - { 3051 - WARN(!mqd, "No hiq sdma mqd trunk to free"); 3052 - 3053 - amdgpu_amdkfd_free_gtt_mem(dev->adev, &mqd->gtt_mem); 3054 3050 } 3055 3051 3056 3052 void device_queue_manager_uninit(struct device_queue_manager *dqm)

+29

drivers/gpu/drm/amd/amdkfd/kfd_events.c

··· 1380 1380 1381 1381 kfd_unref_process(p); 1382 1382 } 1383 + 1384 + /* signal KFD_EVENT_TYPE_SIGNAL events from process p 1385 + * send signal SIGBUS to correspondent user space process 1386 + */ 1387 + void kfd_signal_process_terminate_event(struct kfd_process *p) 1388 + { 1389 + struct kfd_event *ev; 1390 + u32 id; 1391 + 1392 + rcu_read_lock(); 1393 + 1394 + /* iterate from id 1 for KFD_EVENT_TYPE_SIGNAL events */ 1395 + id = 1; 1396 + idr_for_each_entry_continue(&p->event_idr, ev, id) 1397 + if (ev->type == KFD_EVENT_TYPE_SIGNAL) { 1398 + spin_lock(&ev->lock); 1399 + set_event(ev); 1400 + spin_unlock(&ev->lock); 1401 + } 1402 + 1403 + /* Send SIGBUS to p->lead_thread */ 1404 + dev_notice(kfd_device, 1405 + "Sending SIGBUS to process %d", 1406 + p->lead_thread->pid); 1407 + 1408 + send_sig(SIGBUS, p->lead_thread, 0); 1409 + 1410 + rcu_read_unlock(); 1411 + }

+2 -2

drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c

··· 342 342 343 343 static void kfd_init_apertures_v9(struct kfd_process_device *pdd, uint8_t id) 344 344 { 345 - if (pdd->dev->adev->vm_manager.root_level == AMDGPU_VM_PDB3) 345 + if (KFD_GC_VERSION(pdd->dev) >= IP_VERSION(12, 1, 0)) 346 346 pdd->lds_base = pdd->dev->adev->gmc.shared_aperture_start; 347 347 else 348 348 pdd->lds_base = MAKE_LDS_APP_BASE_V9(); ··· 352 352 pdd->gpuvm_limit = 353 353 pdd->dev->kfd->shared_resources.gpuvm_size - 1; 354 354 355 - if (pdd->dev->adev->vm_manager.root_level == AMDGPU_VM_PDB3) 355 + if (KFD_GC_VERSION(pdd->dev) >= IP_VERSION(12, 1, 0)) 356 356 pdd->scratch_base = pdd->dev->adev->gmc.private_aperture_start; 357 357 else 358 358 pdd->scratch_base = MAKE_SCRATCH_APP_BASE_V9();

+1 -1

drivers/gpu/drm/amd/amdkfd/kfd_migrate.c

··· 63 63 *gart_addr = adev->gmc.gart_start; 64 64 65 65 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); 66 - num_bytes = npages * 8; 66 + num_bytes = npages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE; 67 67 68 68 r = amdgpu_job_alloc_with_ib(adev, &entity->base, 69 69 AMDGPU_FENCE_OWNER_UNDEFINED,

+7 -7

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c

··· 54 54 if (!mqd_mem_obj) 55 55 return NULL; 56 56 57 - mqd_mem_obj->gtt_mem = dev->dqm->hiq_sdma_mqd.gtt_mem; 57 + mqd_mem_obj->mem = dev->dqm->hiq_sdma_mqd.mem; 58 58 mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr; 59 59 mqd_mem_obj->cpu_ptr = dev->dqm->hiq_sdma_mqd.cpu_ptr; 60 60 ··· 79 79 offset += dev->dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size * 80 80 NUM_XCC(dev->xcc_mask); 81 81 82 - mqd_mem_obj->gtt_mem = (void *)((uint64_t)dev->dqm->hiq_sdma_mqd.gtt_mem 82 + mqd_mem_obj->mem = (void *)((uint64_t)dev->dqm->hiq_sdma_mqd.mem 83 83 + offset); 84 84 mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr + offset; 85 85 mqd_mem_obj->cpu_ptr = (uint32_t *)((uint64_t) ··· 91 91 void free_mqd_hiq_sdma(struct mqd_manager *mm, void *mqd, 92 92 struct kfd_mem_obj *mqd_mem_obj) 93 93 { 94 - WARN_ON(!mqd_mem_obj->gtt_mem); 94 + WARN_ON(!mqd_mem_obj->mem); 95 95 kfree(mqd_mem_obj); 96 96 } 97 97 ··· 224 224 void kfd_free_mqd_cp(struct mqd_manager *mm, void *mqd, 225 225 struct kfd_mem_obj *mqd_mem_obj) 226 226 { 227 - if (mqd_mem_obj->gtt_mem) { 228 - amdgpu_amdkfd_free_gtt_mem(mm->dev->adev, &mqd_mem_obj->gtt_mem); 227 + if (mqd_mem_obj->mem) { 228 + amdgpu_amdkfd_free_kernel_mem(mm->dev->adev, &mqd_mem_obj->mem); 229 229 kfree(mqd_mem_obj); 230 230 } else { 231 231 kfd_gtt_sa_free(mm->dev, mqd_mem_obj); ··· 280 280 281 281 offset = kfd_hiq_mqd_stride(dev) * virtual_xcc_id; 282 282 283 - mqd_mem_obj->gtt_mem = (virtual_xcc_id == 0) ? 284 - dev->dqm->hiq_sdma_mqd.gtt_mem : NULL; 283 + mqd_mem_obj->mem = (virtual_xcc_id == 0) ? 284 + dev->dqm->hiq_sdma_mqd.mem : NULL; 285 285 mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr + offset; 286 286 mqd_mem_obj->cpu_ptr = (uint32_t *)((uintptr_t) 287 287 dev->dqm->hiq_sdma_mqd.cpu_ptr + offset);

+2 -2

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c

··· 454 454 struct kfd_mem_obj *xcc_mqd_mem_obj, 455 455 uint64_t offset) 456 456 { 457 - xcc_mqd_mem_obj->gtt_mem = (offset == 0) ? 458 - mqd_mem_obj->gtt_mem : NULL; 457 + xcc_mqd_mem_obj->mem = (offset == 0) ? 458 + mqd_mem_obj->mem : NULL; 459 459 xcc_mqd_mem_obj->gpu_addr = mqd_mem_obj->gpu_addr + offset; 460 460 xcc_mqd_mem_obj->cpu_ptr = (uint32_t *)((uintptr_t)mqd_mem_obj->cpu_ptr 461 461 + offset);

+5 -4

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c

··· 135 135 mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 136 136 if (!mqd_mem_obj) 137 137 return NULL; 138 - retval = amdgpu_amdkfd_alloc_gtt_mem(node->adev, 138 + retval = amdgpu_amdkfd_alloc_kernel_mem(node->adev, 139 139 (ALIGN(q->ctl_stack_size, PAGE_SIZE) + 140 140 ALIGN(sizeof(struct v9_mqd), PAGE_SIZE)) * 141 141 NUM_XCC(node->xcc_mask), 142 - &(mqd_mem_obj->gtt_mem), 142 + AMDGPU_GEM_DOMAIN_GTT, 143 + &(mqd_mem_obj->mem), 143 144 &(mqd_mem_obj->gpu_addr), 144 145 (void *)&(mqd_mem_obj->cpu_ptr), true); 145 146 ··· 666 665 struct kfd_mem_obj *xcc_mqd_mem_obj, 667 666 uint64_t offset) 668 667 { 669 - xcc_mqd_mem_obj->gtt_mem = (offset == 0) ? 670 - mqd_mem_obj->gtt_mem : NULL; 668 + xcc_mqd_mem_obj->mem = (offset == 0) ? 669 + mqd_mem_obj->mem : NULL; 671 670 xcc_mqd_mem_obj->gpu_addr = mqd_mem_obj->gpu_addr + offset; 672 671 xcc_mqd_mem_obj->cpu_ptr = (uint32_t *)((uintptr_t)mqd_mem_obj->cpu_ptr 673 672 + offset);

+3 -1

drivers/gpu/drm/amd/amdkfd/kfd_priv.h

··· 252 252 uint32_t range_end; 253 253 uint64_t gpu_addr; 254 254 uint32_t *cpu_ptr; 255 - void *gtt_mem; 255 + void *mem; 256 256 }; 257 257 258 258 struct kfd_vmid_info { ··· 1192 1192 } 1193 1193 int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_node **kdev); 1194 1194 int kfd_numa_node_to_apic_id(int numa_node_id); 1195 + uint32_t kfd_gpu_node_num(void); 1195 1196 1196 1197 /* Interrupts */ 1197 1198 #define KFD_IRQ_FENCE_CLIENTID 0xff ··· 1548 1547 void kfd_signal_reset_event(struct kfd_node *dev); 1549 1548 1550 1549 void kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid); 1550 + void kfd_signal_process_terminate_event(struct kfd_process *p); 1551 1551 1552 1552 static inline void kfd_flush_tlb(struct kfd_process_device *pdd, 1553 1553 enum TLB_FLUSH_TYPE type)

+12 -2

drivers/gpu/drm/amd/amdkfd/kfd_process.c

··· 949 949 */ 950 950 mutex_lock(&kfd_processes_mutex); 951 951 952 + if (kfd_gpu_node_num() <= 0) { 953 + pr_warn("no gpu node! Cannot create KFD process"); 954 + process = ERR_PTR(-EINVAL); 955 + goto out; 956 + } 957 + 952 958 if (kfd_is_locked(NULL)) { 953 959 pr_debug("KFD is locked! Cannot create process"); 954 960 process = ERR_PTR(-EINVAL); ··· 1137 1131 1138 1132 if (pdd->dev->kfd->shared_resources.enable_mes && 1139 1133 pdd->proc_ctx_cpu_ptr) 1140 - amdgpu_amdkfd_free_gtt_mem(pdd->dev->adev, 1134 + amdgpu_amdkfd_free_kernel_mem(pdd->dev->adev, 1141 1135 &pdd->proc_ctx_bo); 1142 1136 /* 1143 1137 * before destroying pdd, make sure to report availability ··· 1241 1235 else 1242 1236 ida_destroy(&p->id_table); 1243 1237 1244 - kfd_process_remove_sysfs(p); 1245 1238 kfd_debugfs_remove_process(p); 1246 1239 1247 1240 kfd_process_kunmap_signal_bo(p); ··· 1255 1250 mutex_destroy(&p->mutex); 1256 1251 1257 1252 put_task_struct(p->lead_thread); 1253 + 1254 + /* the last step is removing process entries under /sys 1255 + * to indicate the process has been terminated. 1256 + */ 1257 + kfd_process_remove_sysfs(p); 1258 1258 1259 1259 kfree(p); 1260 1260 }

+7 -5

drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c

··· 210 210 } 211 211 212 212 if (dev->kfd->shared_resources.enable_mes) { 213 - amdgpu_amdkfd_free_gtt_mem(dev->adev, &pqn->q->gang_ctx_bo); 214 - amdgpu_amdkfd_free_gtt_mem(dev->adev, (void **)&pqn->q->wptr_bo_gart); 213 + amdgpu_amdkfd_free_kernel_mem(dev->adev, &pqn->q->gang_ctx_bo); 214 + amdgpu_amdkfd_free_kernel_mem(dev->adev, (void **)&pqn->q->wptr_bo_gart); 215 215 } 216 216 } 217 217 ··· 265 265 (*q)->process = pqm->process; 266 266 267 267 if (dev->kfd->shared_resources.enable_mes) { 268 - retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, 268 + retval = amdgpu_amdkfd_alloc_kernel_mem(dev->adev, 269 269 AMDGPU_MES_GANG_CTX_SIZE, 270 + AMDGPU_GEM_DOMAIN_GTT, 270 271 &(*q)->gang_ctx_bo, 271 272 &(*q)->gang_ctx_gpu_addr, 272 273 &(*q)->gang_ctx_cpu_ptr, ··· 299 298 return 0; 300 299 301 300 free_gang_ctx_bo: 302 - amdgpu_amdkfd_free_gtt_mem(dev->adev, &(*q)->gang_ctx_bo); 301 + amdgpu_amdkfd_free_kernel_mem(dev->adev, &(*q)->gang_ctx_bo); 303 302 cleanup: 304 303 uninit_queue(*q); 305 304 *q = NULL; ··· 369 368 370 369 /* Allocate proc_ctx_bo only if MES is enabled and this is the first queue */ 371 370 if (!pdd->proc_ctx_cpu_ptr && dev->kfd->shared_resources.enable_mes) { 372 - retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, 371 + retval = amdgpu_amdkfd_alloc_kernel_mem(dev->adev, 373 372 AMDGPU_MES_PROC_CTX_SIZE, 373 + AMDGPU_GEM_DOMAIN_GTT, 374 374 &pdd->proc_ctx_bo, 375 375 &pdd->proc_ctx_gpu_addr, 376 376 &pdd->proc_ctx_cpu_ptr,

+3 -3

drivers/gpu/drm/amd/amdkfd/kfd_queue.c

··· 278 278 279 279 /* EOP buffer is not required for all ASICs */ 280 280 if (properties->eop_ring_buffer_address) { 281 - if (properties->eop_ring_buffer_size != topo_dev->node_props.eop_buffer_size) { 282 - pr_debug("queue eop bo size 0x%x not equal to node eop buf size 0x%x\n", 281 + if (properties->eop_ring_buffer_size < topo_dev->node_props.eop_buffer_size) { 282 + pr_debug("queue eop bo size 0x%x is less than node eop buf size 0x%x\n", 283 283 properties->eop_ring_buffer_size, 284 284 topo_dev->node_props.eop_buffer_size); 285 285 err = -EINVAL; ··· 287 287 } 288 288 err = kfd_queue_buffer_get(vm, (void *)properties->eop_ring_buffer_address, 289 289 &properties->eop_buf_bo, 290 - properties->eop_ring_buffer_size); 290 + ALIGN(properties->eop_ring_buffer_size, PAGE_SIZE)); 291 291 if (err) 292 292 goto out_err_unreserve; 293 293 }

+21 -8

drivers/gpu/drm/amd/amdkfd/kfd_svm.c

··· 1355 1355 struct dma_fence **fence) 1356 1356 { 1357 1357 uint64_t init_pte_value = adev->gmc.init_pte_flags; 1358 + uint64_t gpu_start, gpu_end; 1358 1359 1359 - pr_debug("[0x%llx 0x%llx]\n", start, last); 1360 + /* Convert CPU page range to GPU page range */ 1361 + gpu_start = start * AMDGPU_GPU_PAGES_IN_CPU_PAGE; 1362 + gpu_end = (last + 1) * AMDGPU_GPU_PAGES_IN_CPU_PAGE - 1; 1360 1363 1361 - return amdgpu_vm_update_range(adev, vm, false, true, true, false, NULL, start, 1362 - last, init_pte_value, 0, 0, NULL, NULL, 1364 + pr_debug("CPU[0x%llx 0x%llx] -> GPU[0x%llx 0x%llx]\n", start, last, 1365 + gpu_start, gpu_end); 1366 + return amdgpu_vm_update_range(adev, vm, false, true, true, false, NULL, gpu_start, 1367 + gpu_end, init_pte_value, 0, 0, NULL, NULL, 1363 1368 fence); 1364 1369 } 1365 1370 ··· 1444 1439 last_start, last_start + npages - 1, readonly); 1445 1440 1446 1441 for (i = offset; i < offset + npages; i++) { 1442 + uint64_t gpu_start; 1443 + uint64_t gpu_end; 1444 + 1447 1445 last_domain = dma_addr[i] & SVM_RANGE_VRAM_DOMAIN; 1448 1446 dma_addr[i] &= ~SVM_RANGE_VRAM_DOMAIN; 1449 1447 ··· 1464 1456 if (readonly) 1465 1457 pte_flags &= ~AMDGPU_PTE_WRITEABLE; 1466 1458 1467 - pr_debug("svms 0x%p map [0x%lx 0x%llx] vram %d PTE 0x%llx\n", 1468 - prange->svms, last_start, prange->start + i, 1469 - (last_domain == SVM_RANGE_VRAM_DOMAIN) ? 1 : 0, 1470 - pte_flags); 1471 1459 1472 1460 /* For dGPU mode, we use same vm_manager to allocate VRAM for 1473 1461 * different memory partition based on fpfn/lpfn, we should use 1474 1462 * same vm_manager.vram_base_offset regardless memory partition. 1475 1463 */ 1464 + gpu_start = last_start * AMDGPU_GPU_PAGES_IN_CPU_PAGE; 1465 + gpu_end = (prange->start + i + 1) * AMDGPU_GPU_PAGES_IN_CPU_PAGE - 1; 1466 + 1467 + pr_debug("svms 0x%p map CPU[0x%lx 0x%llx] GPU[0x%llx 0x%llx] vram %d PTE 0x%llx\n", 1468 + prange->svms, last_start, prange->start + i, 1469 + gpu_start, gpu_end, 1470 + (last_domain == SVM_RANGE_VRAM_DOMAIN) ? 1 : 0, 1471 + pte_flags); 1472 + 1476 1473 r = amdgpu_vm_update_range(adev, vm, false, false, flush_tlb, true, 1477 - NULL, last_start, prange->start + i, 1474 + NULL, gpu_start, gpu_end, 1478 1475 pte_flags, 1479 1476 (last_start - prange->start) << PAGE_SHIFT, 1480 1477 bo_adev ? bo_adev->vm_manager.vram_base_offset : 0,

+22

drivers/gpu/drm/amd/amdkfd/kfd_topology.c

··· 2357 2357 return kfd_cpumask_to_apic_id(cpumask_of_node(numa_node_id)); 2358 2358 } 2359 2359 2360 + /* kfd_gpu_node_num - Return kfd gpu node number at system */ 2361 + uint32_t kfd_gpu_node_num(void) 2362 + { 2363 + struct kfd_node *dev; 2364 + u8 gpu_num = 0; 2365 + u8 id = 0; 2366 + 2367 + while (kfd_topology_enum_kfd_devices(id, &dev) == 0) { 2368 + if (!dev || kfd_devcgroup_check_permission(dev)) { 2369 + /* Skip non GPU devices and devices to which the 2370 + * current process have no access to 2371 + */ 2372 + id++; 2373 + continue; 2374 + } 2375 + id++; 2376 + gpu_num++; 2377 + } 2378 + 2379 + return gpu_num; 2380 + } 2381 + 2360 2382 #if defined(CONFIG_DEBUG_FS) 2361 2383 2362 2384 int kfd_debugfs_hqds_by_device(struct seq_file *m, void *data)

+59 -32

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

··· 1137 1137 1138 1138 mutex_unlock(&adev->dm.audio_lock); 1139 1139 1140 - DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled); 1140 + drm_dbg_kms(adev_to_drm(adev), "Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled); 1141 1141 1142 1142 return ret; 1143 1143 } ··· 1231 1231 struct drm_audio_component *acomp = adev->dm.audio_component; 1232 1232 1233 1233 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) { 1234 - DRM_DEBUG_KMS("Notify ELD: %d\n", pin); 1234 + drm_dbg_kms(adev_to_drm(adev), "Notify ELD: %d\n", pin); 1235 1235 1236 1236 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, 1237 1237 pin, -1); ··· 2377 2377 } 2378 2378 2379 2379 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2380 - DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); 2380 + drm_dbg_kms(adev_to_drm(adev), "dm: DMCU firmware not supported on direct or SMU loading\n"); 2381 2381 return 0; 2382 2382 } 2383 2383 ··· 2385 2385 "%s", fw_name_dmcu); 2386 2386 if (r == -ENODEV) { 2387 2387 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ 2388 - DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); 2388 + drm_dbg_kms(adev_to_drm(adev), "dm: DMCU firmware not found\n"); 2389 2389 adev->dm.fw_dmcu = NULL; 2390 2390 return 0; 2391 2391 } ··· 2409 2409 2410 2410 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); 2411 2411 2412 - DRM_DEBUG_KMS("PSP loading DMCU firmware\n"); 2412 + drm_dbg_kms(adev_to_drm(adev), "PSP loading DMCU firmware\n"); 2413 2413 2414 2414 return 0; 2415 2415 } ··· 4157 4157 offload_work->adev = adev; 4158 4158 4159 4159 queue_work(offload_wq->wq, &offload_work->work); 4160 - DRM_DEBUG_KMS("queue work to handle hpd_rx offload work"); 4160 + drm_dbg_kms(adev_to_drm(adev), "queue work to handle hpd_rx offload work"); 4161 4161 } 4162 4162 4163 4163 static void handle_hpd_rx_irq(void *param) ··· 4986 4986 caps->min_input_signal < 0 || 4987 4987 spread > AMDGPU_DM_DEFAULT_MAX_BACKLIGHT || 4988 4988 spread < AMDGPU_DM_MIN_SPREAD) { 4989 - DRM_DEBUG_KMS("DM: Invalid backlight caps: min=%d, max=%d\n", 4989 + drm_dbg_kms(adev_to_drm(dm->adev), "DM: Invalid backlight caps: min=%d, max=%d\n", 4990 4990 caps->min_input_signal, caps->max_input_signal); 4991 4991 caps->caps_valid = false; 4992 4992 } ··· 5279 5279 struct amdgpu_dm_backlight_caps *caps; 5280 5280 char bl_name[16]; 5281 5281 int min, max; 5282 + int real_brightness; 5283 + int init_brightness; 5282 5284 5283 5285 if (aconnector->bl_idx == -1) 5284 5286 return; ··· 5305 5303 } else 5306 5304 props.brightness = props.max_brightness = MAX_BACKLIGHT_LEVEL; 5307 5305 5306 + init_brightness = props.brightness; 5307 + 5308 5308 if (caps->data_points && !(amdgpu_dc_debug_mask & DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE)) { 5309 5309 drm_info(drm, "Using custom brightness curve\n"); 5310 5310 props.scale = BACKLIGHT_SCALE_NON_LINEAR; ··· 5325 5321 if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) { 5326 5322 drm_err(drm, "DM: Backlight registration failed!\n"); 5327 5323 dm->backlight_dev[aconnector->bl_idx] = NULL; 5328 - } else 5324 + } else { 5325 + /* 5326 + * dm->brightness[x] can be inconsistent just after startup until 5327 + * ops.get_brightness is called. 5328 + */ 5329 + real_brightness = 5330 + amdgpu_dm_backlight_ops.get_brightness(dm->backlight_dev[aconnector->bl_idx]); 5331 + 5332 + if (real_brightness != init_brightness) { 5333 + dm->actual_brightness[aconnector->bl_idx] = real_brightness; 5334 + dm->brightness[aconnector->bl_idx] = real_brightness; 5335 + } 5329 5336 drm_dbg_driver(drm, "DM: Registered Backlight device: %s\n", bl_name); 5337 + } 5330 5338 } 5331 5339 5332 5340 static int initialize_plane(struct amdgpu_display_manager *dm, ··· 5531 5515 } 5532 5516 break; 5533 5517 default: 5534 - DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n", 5518 + drm_dbg_kms(adev_to_drm(adev), "Unsupported DCN IP version for outbox: 0x%X\n", 5535 5519 amdgpu_ip_version(adev, DCE_HWIP, 0)); 5536 5520 } 5537 5521 ··· 5655 5639 5656 5640 if (psr_feature_enabled) { 5657 5641 amdgpu_dm_set_psr_caps(link); 5658 - drm_info(adev_to_drm(adev), "PSR support %d, DC PSR ver %d, sink PSR ver %d DPCD caps 0x%x su_y_granularity %d\n", 5642 + drm_info(adev_to_drm(adev), "%s: PSR support %d, DC PSR ver %d, sink PSR ver %d DPCD caps 0x%x su_y_granularity %d\n", 5643 + aconnector->base.name, 5659 5644 link->psr_settings.psr_feature_enabled, 5660 5645 link->psr_settings.psr_version, 5661 5646 link->dpcd_caps.psr_info.psr_version, ··· 6434 6417 &flip_addrs->dirty_rect_count, true); 6435 6418 } 6436 6419 6437 - static void update_stream_scaling_settings(const struct drm_display_mode *mode, 6420 + static void update_stream_scaling_settings(struct drm_device *dev, 6421 + const struct drm_display_mode *mode, 6438 6422 const struct dm_connector_state *dm_state, 6439 6423 struct dc_stream_state *stream) 6440 6424 { ··· 6485 6467 stream->src = src; 6486 6468 stream->dst = dst; 6487 6469 6488 - DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n", 6489 - dst.x, dst.y, dst.width, dst.height); 6470 + drm_dbg_kms(dev, "Destination Rectangle x:%d y:%d width:%d height:%d\n", 6471 + dst.x, dst.y, dst.width, dst.height); 6490 6472 6491 6473 } 6492 6474 ··· 7374 7356 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps); 7375 7357 #endif 7376 7358 7377 - update_stream_scaling_settings(&mode, dm_state, stream); 7359 + update_stream_scaling_settings(dev, &mode, dm_state, stream); 7378 7360 7379 7361 fill_audio_info( 7380 7362 &stream->audio_info, ··· 8109 8091 dc_result = dm_validate_stream_and_context(adev->dm.dc, stream); 8110 8092 8111 8093 if (dc_result != DC_OK) { 8112 - DRM_DEBUG_KMS("Pruned mode %d x %d (clk %d) %s %s -- %s\n", 8094 + drm_dbg_kms(connector->dev, "Pruned mode %d x %d (clk %d) %s %s -- %s\n", 8113 8095 drm_mode->hdisplay, 8114 8096 drm_mode->vdisplay, 8115 8097 drm_mode->clock, ··· 8461 8443 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port, 8462 8444 dm_new_connector_state->pbn); 8463 8445 if (dm_new_connector_state->vcpi_slots < 0) { 8464 - DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); 8446 + drm_dbg_atomic(connector->dev, "failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); 8465 8447 return dm_new_connector_state->vcpi_slots; 8466 8448 } 8467 8449 return 0; ··· 8961 8943 mutex_init(&aconnector->hpd_lock); 8962 8944 mutex_init(&aconnector->handle_mst_msg_ready); 8963 8945 8964 - aconnector->hdmi_hpd_debounce_delay_ms = AMDGPU_DM_HDMI_HPD_DEBOUNCE_MS; 8965 - INIT_DELAYED_WORK(&aconnector->hdmi_hpd_debounce_work, hdmi_hpd_debounce_work); 8966 - aconnector->hdmi_prev_sink = NULL; 8946 + /* 8947 + * If HDMI HPD debounce delay is set, use the minimum between selected 8948 + * value and AMDGPU_DM_MAX_HDMI_HPD_DEBOUNCE_MS 8949 + */ 8950 + if (amdgpu_hdmi_hpd_debounce_delay_ms) { 8951 + aconnector->hdmi_hpd_debounce_delay_ms = min(amdgpu_hdmi_hpd_debounce_delay_ms, 8952 + AMDGPU_DM_MAX_HDMI_HPD_DEBOUNCE_MS); 8953 + INIT_DELAYED_WORK(&aconnector->hdmi_hpd_debounce_work, hdmi_hpd_debounce_work); 8954 + aconnector->hdmi_prev_sink = NULL; 8955 + } else { 8956 + aconnector->hdmi_hpd_debounce_delay_ms = 0; 8957 + } 8967 8958 8968 8959 /* 8969 8960 * configure support HPD hot plug connector_>polled default value is 0 ··· 9654 9627 new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params); 9655 9628 9656 9629 if (new_crtc_state->freesync_vrr_info_changed) 9657 - DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d", 9630 + drm_dbg_kms(adev_to_drm(adev), "VRR packet update: crtc=%u enabled=%d state=%d", 9658 9631 new_crtc_state->base.crtc->base.id, 9659 9632 (int)new_crtc_state->base.vrr_enabled, 9660 9633 (int)vrr_params.state); ··· 10920 10893 10921 10894 stream_update.stream = dm_new_crtc_state->stream; 10922 10895 if (scaling_changed) { 10923 - update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, 10896 + update_stream_scaling_settings(dev, &dm_new_con_state->base.crtc->mode, 10924 10897 dm_new_con_state, dm_new_crtc_state->stream); 10925 10898 10926 10899 stream_update.src = dm_new_crtc_state->stream->src; ··· 11600 11573 11601 11574 dc_stream_retain(new_stream); 11602 11575 11603 - DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n", 11576 + drm_dbg_atomic(adev_to_drm(adev), "Enabling DRM crtc: %d\n", 11604 11577 crtc->base.id); 11605 11578 11606 11579 if (dc_state_add_stream( ··· 11639 11612 /* Scaling or underscan settings */ 11640 11613 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) || 11641 11614 drm_atomic_crtc_needs_modeset(new_crtc_state)) 11642 - update_stream_scaling_settings( 11615 + update_stream_scaling_settings(adev_to_drm(adev), 11643 11616 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); 11644 11617 11645 11618 /* ABM settings */ ··· 11830 11803 11831 11804 if (fb->width > new_acrtc->max_cursor_width || 11832 11805 fb->height > new_acrtc->max_cursor_height) { 11833 - DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n", 11806 + drm_dbg_atomic(adev_to_drm(adev), "Bad cursor FB size %dx%d\n", 11834 11807 new_plane_state->fb->width, 11835 11808 new_plane_state->fb->height); 11836 11809 return -EINVAL; 11837 11810 } 11838 11811 if (new_plane_state->src_w != fb->width << 16 || 11839 11812 new_plane_state->src_h != fb->height << 16) { 11840 - DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); 11813 + drm_dbg_atomic(adev_to_drm(adev), "Cropping not supported for cursor plane\n"); 11841 11814 return -EINVAL; 11842 11815 } 11843 11816 ··· 11845 11818 pitch = fb->pitches[0] / fb->format->cpp[0]; 11846 11819 11847 11820 if (fb->width != pitch) { 11848 - DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d", 11821 + drm_dbg_atomic(adev_to_drm(adev), "Cursor FB width %d doesn't match pitch %d", 11849 11822 fb->width, pitch); 11850 11823 return -EINVAL; 11851 11824 } ··· 11857 11830 /* FB pitch is supported by cursor plane */ 11858 11831 break; 11859 11832 default: 11860 - DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch); 11833 + drm_dbg_atomic(adev_to_drm(adev), "Bad cursor FB pitch %d px\n", pitch); 11861 11834 return -EINVAL; 11862 11835 } 11863 11836 ··· 11875 11848 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0; 11876 11849 } 11877 11850 if (!linear) { 11878 - DRM_DEBUG_ATOMIC("Cursor FB not linear"); 11851 + drm_dbg_atomic(adev_to_drm(adev), "Cursor FB not linear"); 11879 11852 return -EINVAL; 11880 11853 } 11881 11854 } ··· 11902 11875 new_acrtc = to_amdgpu_crtc(new_plane_crtc); 11903 11876 11904 11877 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) { 11905 - DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); 11878 + drm_dbg_atomic(new_plane_crtc->dev, "Cropping not supported for cursor plane\n"); 11906 11879 return -EINVAL; 11907 11880 } 11908 11881 ··· 12001 11974 if (!dm_old_crtc_state->stream) 12002 11975 return 0; 12003 11976 12004 - DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", 11977 + drm_dbg_atomic(old_plane_crtc->dev, "Disabling DRM plane: %d on DRM crtc %d\n", 12005 11978 plane->base.id, old_plane_crtc->base.id); 12006 11979 12007 11980 ret = dm_atomic_get_state(state, &dm_state); ··· 12054 12027 goto out; 12055 12028 } 12056 12029 12057 - DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n", 12030 + drm_dbg_atomic(new_plane_crtc->dev, "Enabling DRM plane: %d on DRM crtc %d\n", 12058 12031 plane->base.id, new_plane_crtc->base.id); 12059 12032 12060 12033 ret = fill_dc_plane_attributes( ··· 13146 13119 amd_vsdb->version == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3) { 13147 13120 vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false; 13148 13121 vsdb_info->amd_vsdb_version = HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3; 13149 - DRM_DEBUG_KMS("Panel supports Replay Mode: %d\n", vsdb_info->replay_mode); 13122 + drm_dbg_kms(aconnector->base.dev, "Panel supports Replay Mode: %d\n", vsdb_info->replay_mode); 13150 13123 13151 13124 return true; 13152 13125 }

+5 -1

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

··· 59 59 60 60 #define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL) 61 61 62 - #define AMDGPU_DM_HDMI_HPD_DEBOUNCE_MS 1500 62 + /* 63 + * Maximum HDMI HPD debounce delay in milliseconds 64 + */ 65 + #define AMDGPU_DM_MAX_HDMI_HPD_DEBOUNCE_MS 5000 63 66 /* 64 67 #include "include/amdgpu_dal_power_if.h" 65 68 #include "amdgpu_dm_irq.h" ··· 818 815 819 816 int sr_skip_count; 820 817 bool disallow_edp_enter_psr; 818 + bool disallow_edp_enter_replay; 821 819 822 820 /* Record progress status of mst*/ 823 821 uint8_t mst_status;

+22 -3

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

··· 32 32 #include "dc.h" 33 33 #include "amdgpu_securedisplay.h" 34 34 #include "amdgpu_dm_psr.h" 35 + #include "amdgpu_dm_replay.h" 35 36 36 37 static const char *const pipe_crc_sources[] = { 37 38 "none", ··· 503 502 { 504 503 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 505 504 struct dc_stream_state *stream_state = dm_crtc_state->stream; 505 + struct amdgpu_dm_connector *aconnector = NULL; 506 506 bool enable = amdgpu_dm_is_valid_crc_source(source); 507 507 int ret = 0; 508 508 ··· 511 509 if (!stream_state) 512 510 return -EINVAL; 513 511 512 + /* Get connector from stream */ 513 + aconnector = (struct amdgpu_dm_connector *)stream_state->dm_stream_context; 514 + 514 515 mutex_lock(&adev->dm.dc_lock); 515 516 516 - /* For PSR1, check that the panel has exited PSR */ 517 - if (stream_state->link->psr_settings.psr_version < DC_PSR_VERSION_SU_1) 518 - amdgpu_dm_psr_wait_disable(stream_state); 517 + 518 + if (enable) { 519 + /* For PSR1, check that the panel has exited PSR */ 520 + if (stream_state->link->psr_settings.psr_version < DC_PSR_VERSION_SU_1) 521 + amdgpu_dm_psr_wait_disable(stream_state); 522 + 523 + /* Set flag to disallow enter replay when CRC source is enabled */ 524 + if (aconnector) 525 + aconnector->disallow_edp_enter_replay = true; 526 + amdgpu_dm_replay_disable(stream_state); 527 + } 519 528 520 529 /* Enable or disable CRTC CRC generation */ 521 530 if (dm_is_crc_source_crtc(source) || source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE) { ··· 547 534 DITHER_OPTION_DEFAULT); 548 535 dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state, 549 536 DYN_EXPANSION_AUTO); 537 + } 538 + 539 + if (!enable) { 540 + /* Clear flag to allow enter replay when CRC source is disabled */ 541 + if (aconnector) 542 + aconnector->disallow_edp_enter_replay = false; 550 543 } 551 544 552 545 unlock:

+8 -1

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

··· 154 154 { 155 155 bool replay_active = true; 156 156 struct dc_link *link = NULL; 157 + struct amdgpu_dm_connector *aconnector = NULL; 157 158 158 159 if (stream == NULL) 159 160 return false; 160 161 162 + /* Check if replay is disabled by connector flag */ 163 + aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; 164 + if (!aconnector || aconnector->disallow_edp_enter_replay) { 165 + return false; 166 + } 167 + 161 168 link = stream->link; 162 169 163 170 if (link) { 164 - link->dc->link_srv->edp_setup_replay(link, stream); 171 + link->dc->link_srv->dp_setup_replay(link, stream); 165 172 link->dc->link_srv->edp_set_coasting_vtotal(link, stream->timing.v_total, 0); 166 173 DRM_DEBUG_DRIVER("Enabling replay...\n"); 167 174 link->dc->link_srv->edp_set_replay_allow_active(link, &replay_active, wait, false, NULL);

+33 -16

drivers/gpu/drm/amd/display/dc/core/dc.c

··· 7246 7246 ); 7247 7247 } 7248 7248 7249 + static void transition_countdown_init(struct dc *dc) 7250 + { 7251 + dc->check_config.transition_countdown_to_steady_state = 7252 + dc->debug.num_fast_flips_to_steady_state_override ? 7253 + dc->debug.num_fast_flips_to_steady_state_override : 7254 + NUM_FAST_FLIPS_TO_STEADY_STATE; 7255 + } 7256 + 7249 7257 static bool update_planes_and_stream_prepare_v3( 7250 7258 struct dc_update_scratch_space *scratch 7251 7259 ) ··· 7313 7305 ); 7314 7306 if (seamless) { 7315 7307 scratch->flow = UPDATE_V3_FLOW_NEW_CONTEXT_SEAMLESS; 7308 + if (scratch->dc->check_config.deferred_transition_state) 7309 + /* reset countdown as steady state not reached */ 7310 + transition_countdown_init(scratch->dc); 7316 7311 return true; 7312 + } 7313 + 7314 + if (!scratch->dc->debug.disable_deferred_minimal_transitions) { 7315 + scratch->dc->check_config.deferred_transition_state = true; 7316 + transition_countdown_init(scratch->dc); 7317 7317 } 7318 7318 7319 7319 scratch->intermediate_context = create_minimal_transition_state( ··· 7367 7351 static void update_planes_and_stream_execute_v3_commit( 7368 7352 const struct dc_update_scratch_space *scratch, 7369 7353 bool intermediate_update, 7370 - bool intermediate_context 7354 + bool intermediate_context, 7355 + bool use_stream_update 7371 7356 ) 7372 7357 { 7373 7358 commit_planes_for_stream( ··· 7376 7359 intermediate_update ? scratch->intermediate_updates : scratch->surface_updates, 7377 7360 intermediate_update ? scratch->intermediate_count : scratch->surface_count, 7378 7361 scratch->stream, 7379 - intermediate_context ? NULL : scratch->stream_update, 7362 + use_stream_update ? scratch->stream_update : NULL, 7380 7363 intermediate_context ? UPDATE_TYPE_FULL : scratch->update_type, 7381 7364 // `dc->current_state` only used in `NO_NEW_CONTEXT`, where it is equal to `new_context` 7382 7365 intermediate_context ? scratch->intermediate_context : scratch->new_context ··· 7402 7385 7403 7386 case UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FULL: 7404 7387 case UPDATE_V3_FLOW_NEW_CONTEXT_SEAMLESS: 7405 - update_planes_and_stream_execute_v3_commit(scratch, false, false); 7388 + update_planes_and_stream_execute_v3_commit(scratch, false, false, true); 7406 7389 break; 7407 7390 7408 7391 case UPDATE_V3_FLOW_NEW_CONTEXT_MINIMAL_NEW: 7409 - update_planes_and_stream_execute_v3_commit(scratch, false, true); 7392 + update_planes_and_stream_execute_v3_commit(scratch, false, true, 7393 + scratch->dc->check_config.deferred_transition_state); 7410 7394 break; 7411 7395 7412 7396 case UPDATE_V3_FLOW_NEW_CONTEXT_MINIMAL_CURRENT: 7413 - update_planes_and_stream_execute_v3_commit(scratch, true, true); 7397 + update_planes_and_stream_execute_v3_commit(scratch, true, true, false); 7414 7398 break; 7415 7399 7416 7400 case UPDATE_V3_FLOW_INVALID: 7417 7401 default: 7418 7402 ASSERT(false); 7419 7403 } 7420 - } 7421 - 7422 - static void update_planes_and_stream_cleanup_v3_new_context( 7423 - struct dc_update_scratch_space *scratch 7424 - ) 7425 - { 7426 - swap_and_release_current_context(scratch->dc, scratch->new_context, scratch->stream); 7427 7404 } 7428 7405 7429 7406 static void update_planes_and_stream_cleanup_v3_release_minimal( ··· 7450 7439 switch (scratch->flow) { 7451 7440 case UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FAST: 7452 7441 case UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FULL: 7453 - // No cleanup required 7442 + if (scratch->dc->check_config.transition_countdown_to_steady_state) 7443 + scratch->dc->check_config.transition_countdown_to_steady_state--; 7454 7444 break; 7455 7445 7456 7446 case UPDATE_V3_FLOW_NEW_CONTEXT_SEAMLESS: 7457 - update_planes_and_stream_cleanup_v3_new_context(scratch); 7447 + swap_and_release_current_context(scratch->dc, scratch->new_context, scratch->stream); 7458 7448 break; 7459 7449 7460 7450 case UPDATE_V3_FLOW_NEW_CONTEXT_MINIMAL_NEW: 7461 7451 update_planes_and_stream_cleanup_v3_intermediate(scratch, false); 7462 - scratch->flow = UPDATE_V3_FLOW_NEW_CONTEXT_SEAMLESS; 7463 - return true; 7452 + if (scratch->dc->check_config.deferred_transition_state) { 7453 + dc_state_release(scratch->new_context); 7454 + } else { 7455 + scratch->flow = UPDATE_V3_FLOW_NEW_CONTEXT_SEAMLESS; 7456 + return true; 7457 + } 7458 + break; 7464 7459 7465 7460 case UPDATE_V3_FLOW_NEW_CONTEXT_MINIMAL_CURRENT: 7466 7461 update_planes_and_stream_cleanup_v3_intermediate(scratch, true);

+4 -5

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

··· 493 493 494 494 bool dc_link_set_pr_enable(struct dc_link *link, bool enable) 495 495 { 496 - return link->dc->link_srv->edp_pr_enable(link, enable); 496 + return link->dc->link_srv->dp_pr_enable(link, enable); 497 497 } 498 498 499 499 bool dc_link_update_pr_state(struct dc_link *link, 500 500 struct dmub_cmd_pr_update_state_data *update_state_data) 501 501 { 502 - return link->dc->link_srv->edp_pr_update_state(link, update_state_data); 502 + return link->dc->link_srv->dp_pr_update_state(link, update_state_data); 503 503 } 504 504 505 505 bool dc_link_set_pr_general_cmd(struct dc_link *link, 506 506 struct dmub_cmd_pr_general_cmd_data *general_cmd_data) 507 507 { 508 - return link->dc->link_srv->edp_pr_set_general_cmd(link, general_cmd_data); 508 + return link->dc->link_srv->dp_pr_set_general_cmd(link, general_cmd_data); 509 509 } 510 510 511 511 bool dc_link_get_pr_state(const struct dc_link *link, uint64_t *state) 512 512 { 513 - return link->dc->link_srv->edp_pr_get_state(link, state); 513 + return link->dc->link_srv->dp_pr_get_state(link, state); 514 514 } 515 515 516 516 bool dc_link_wait_for_t12(struct dc_link *link) ··· 549 549 { 550 550 link->dc->link_srv->edp_get_alpm_support(link, auxless_support, auxwake_support); 551 551 } 552 -

+1 -1

drivers/gpu/drm/amd/display/dc/dc.h

··· 63 63 struct dcn_optc_reg_state; 64 64 struct dcn_dccg_reg_state; 65 65 66 - #define DC_VER "3.2.364" 66 + #define DC_VER "3.2.365" 67 67 68 68 /** 69 69 * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC

+1

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

··· 999 999 DC_LOG_DEBUG(" is_traceport_en : %d", dc_dmub_srv->dmub->debug.is_traceport_en); 1000 1000 DC_LOG_DEBUG(" is_cw0_en : %d", dc_dmub_srv->dmub->debug.is_cw0_enabled); 1001 1001 DC_LOG_DEBUG(" is_cw6_en : %d", dc_dmub_srv->dmub->debug.is_cw6_enabled); 1002 + DC_LOG_DEBUG(" is_pwait : %d", dc_dmub_srv->dmub->debug.is_pwait); 1002 1003 } 1003 1004 1004 1005 static bool dc_dmub_should_update_cursor_data(struct pipe_ctx *pipe_ctx)

+33 -1

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

··· 1167 1167 unsigned char raw; 1168 1168 }; 1169 1169 1170 + union dpcd_panel_replay_capability { 1171 + struct { 1172 + unsigned char RESERVED :2; 1173 + unsigned char DSC_DECODE_NOT_SUPPORTED :1; 1174 + unsigned char ASYNC_VIDEO_TIMING_NOT_SUPPORTED :1; 1175 + unsigned char DSC_CRC_OF_MULTI_SU_SUPPORTED :1; 1176 + unsigned char PR_SU_GRANULARITY_NEEDED :1; 1177 + unsigned char SU_Y_GRANULARITY_EXT_CAP_SUPPORTED :1; 1178 + unsigned char LINK_OFF_SUPPORTED_IN_PR_ACTIVE :1; 1179 + } bits; 1180 + unsigned char raw; 1181 + }; 1182 + 1183 + struct dpcd_panel_replay_selective_update_info { 1184 + uint16_t pr_su_x_granularity; 1185 + uint8_t pr_su_y_granularity; 1186 + uint16_t pr_su_y_granularity_extended_caps; 1187 + }; 1188 + 1170 1189 enum dpcd_downstream_port_max_bpc { 1171 1190 DOWN_STREAM_MAX_8BPC = 0, 1172 1191 DOWN_STREAM_MAX_10BPC, ··· 1309 1290 struct edp_psr_info psr_info; 1310 1291 1311 1292 struct replay_info pr_info; 1312 - union dpcd_panel_replay_capability_supported pr_caps_supported; 1293 + union dpcd_panel_replay_capability_supported vesa_replay_caps_supported; 1294 + union dpcd_panel_replay_capability vesa_replay_caps; 1295 + struct dpcd_panel_replay_selective_update_info vesa_replay_su_info; 1313 1296 uint16_t edp_oled_emission_rate; 1314 1297 union dp_receive_port0_cap receive_port0_cap; 1315 1298 /* Indicates the number of SST links supported by MSO (Multi-Stream Output) */ ··· 1419 1398 struct { 1420 1399 unsigned char ENABLE : 1; 1421 1400 unsigned char RESERVED : 7; 1401 + } bits; 1402 + unsigned char raw; 1403 + }; 1404 + 1405 + union pr_error_status { 1406 + struct { 1407 + unsigned char LINK_CRC_ERROR :1; 1408 + unsigned char RFB_STORAGE_ERROR :1; 1409 + unsigned char VSC_SDP_ERROR :1; 1410 + unsigned char ASSDP_MISSING_ERROR :1; 1411 + unsigned char RESERVED :4; 1422 1412 } bits; 1423 1413 unsigned char raw; 1424 1414 };

+1 -1

drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h

··· 41 41 /* kHZ*/ 42 42 #define DP_ADAPTOR_DVI_MAX_TMDS_CLK 165000 43 43 /* kHZ*/ 44 - #define DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK 165000 44 + #define DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK 340000 45 45 46 46 struct dp_hdmi_dongle_signature_data { 47 47 int8_t id[15];/* "DP-HDMI ADAPTOR"*/

+6

drivers/gpu/drm/amd/display/dc/dc_hw_types.h

··· 491 491 * for each plane. 492 492 */ 493 493 bool translate_by_source; 494 + 495 + /** 496 + * @use_viewport_for_clip: Use viewport position for clip_x calculation 497 + * instead of clip_rect. Required to protect against clip being overwritten 498 + */ 499 + bool use_viewport_for_clip; 494 500 }; 495 501 496 502 struct dc_cursor_mi_param {

+2 -1

drivers/gpu/drm/amd/display/dc/dc_types.h

··· 1101 1101 Replay_Set_Residency_Frameupdate_Timer, 1102 1102 Replay_Set_Pseudo_VTotal, 1103 1103 Replay_Disabled_Adaptive_Sync_SDP, 1104 - Replay_Set_Version, 1105 1104 Replay_Set_General_Cmd, 1106 1105 }; 1107 1106 ··· 1223 1224 uint32_t replay_desync_error_fail_count; 1224 1225 /* The frame skip number dal send to DMUB */ 1225 1226 uint16_t frame_skip_number; 1227 + /* Current Panel Replay event */ 1228 + uint32_t replay_events; 1226 1229 }; 1227 1230 1228 1231 /* To split out "global" and "per-panel" config settings.

+1 -1

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

··· 69 69 if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) 70 70 return true; 71 71 72 - if (link->replay_settings.replay_feature_enabled) 72 + if (link->replay_settings.replay_feature_enabled && dc_is_embedded_signal(link->connector_signal)) 73 73 return true; 74 74 75 75 if (link->psr_settings.psr_version == DC_PSR_VERSION_1) {

-13

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

··· 387 387 cmd.replay_disabled_adaptive_sync_sdp.data.force_disabled = 388 388 cmd_element->disabled_adaptive_sync_sdp_data.force_disabled; 389 389 break; 390 - case Replay_Set_Version: 391 - //Header 392 - cmd.replay_set_version.header.sub_type = 393 - DMUB_CMD__REPLAY_SET_VERSION; 394 - cmd.replay_set_version.header.payload_bytes = 395 - sizeof(struct dmub_rb_cmd_replay_set_version) - 396 - sizeof(struct dmub_cmd_header); 397 - //Cmd Body 398 - cmd.replay_set_version.replay_set_version_data.panel_inst = 399 - cmd_element->version_data.panel_inst; 400 - cmd.replay_set_version.replay_set_version_data.version = 401 - cmd_element->version_data.version; 402 - break; 403 390 case Replay_Set_General_Cmd: 404 391 //Header 405 392 cmd.replay_set_general_cmd.header.sub_type =

+5 -1

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

··· 3666 3666 int y_plane = pipe_ctx->plane_state->dst_rect.y; 3667 3667 int x_pos = pos_cpy.x; 3668 3668 int y_pos = pos_cpy.y; 3669 - int clip_x = pipe_ctx->plane_state->clip_rect.x; 3669 + bool is_primary_plane = (pipe_ctx->plane_state->layer_index == 0); 3670 + 3671 + int clip_x = (pos_cpy.use_viewport_for_clip && is_primary_plane && 3672 + !odm_combine_on && !pipe_split_on && param.viewport.x != 0) 3673 + ? param.viewport.x : pipe_ctx->plane_state->clip_rect.x; 3670 3674 int clip_width = pipe_ctx->plane_state->clip_rect.width; 3671 3675 3672 3676 if ((pipe_ctx->top_pipe != NULL) || (pipe_ctx->bottom_pipe != NULL)) {

+52

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

··· 1727 1727 { 1728 1728 dc_dmub_srv_program_cursor_now(dc, pipe); 1729 1729 } 1730 + 1731 + static void disable_link_output_symclk_on_tx_off(struct dc_link *link, enum dp_link_encoding link_encoding) 1732 + { 1733 + struct dc *dc = link->ctx->dc; 1734 + struct pipe_ctx *pipe_ctx = NULL; 1735 + uint8_t i; 1736 + 1737 + for (i = 0; i < MAX_PIPES; i++) { 1738 + pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 1739 + if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) { 1740 + pipe_ctx->clock_source->funcs->program_pix_clk( 1741 + pipe_ctx->clock_source, 1742 + &pipe_ctx->stream_res.pix_clk_params, 1743 + link_encoding, 1744 + &pipe_ctx->pll_settings); 1745 + break; 1746 + } 1747 + } 1748 + } 1749 + 1750 + void dcn35_disable_link_output(struct dc_link *link, 1751 + const struct link_resource *link_res, 1752 + enum signal_type signal) 1753 + { 1754 + struct dc *dc = link->ctx->dc; 1755 + const struct link_hwss *link_hwss = get_link_hwss(link, link_res); 1756 + struct dmcu *dmcu = dc->res_pool->dmcu; 1757 + 1758 + if (signal == SIGNAL_TYPE_EDP && 1759 + link->dc->hwss.edp_backlight_control && 1760 + !link->skip_implict_edp_power_control) 1761 + link->dc->hwss.edp_backlight_control(link, false); 1762 + else if (dmcu != NULL && dmcu->funcs->lock_phy) 1763 + dmcu->funcs->lock_phy(dmcu); 1764 + 1765 + if (dc_is_tmds_signal(signal) && link->phy_state.symclk_ref_cnts.otg > 0) { 1766 + disable_link_output_symclk_on_tx_off(link, DP_UNKNOWN_ENCODING); 1767 + link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; 1768 + } else { 1769 + link_hwss->disable_link_output(link, link_res, signal); 1770 + link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; 1771 + } 1772 + /* 1773 + * Add the logic to extract BOTH power up and power down sequences 1774 + * from enable/disable link output and only call edp panel control 1775 + * in enable_link_dp and disable_link_dp once. 1776 + */ 1777 + if (dmcu != NULL && dmcu->funcs->unlock_phy) 1778 + dmcu->funcs->unlock_phy(dmcu); 1779 + 1780 + dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY); 1781 + }

+3

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

··· 108 108 void dcn35_notify_cursor_offload_drr_update(struct dc *dc, struct dc_state *context, 109 109 const struct dc_stream_state *stream); 110 110 void dcn35_program_cursor_offload_now(struct dc *dc, const struct pipe_ctx *pipe); 111 + void dcn35_disable_link_output(struct dc_link *link, 112 + const struct link_resource *link_res, 113 + enum signal_type signal); 111 114 112 115 #endif /* __DC_HWSS_DCN35_H__ */

+1 -1

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c

··· 113 113 .enable_lvds_link_output = dce110_enable_lvds_link_output, 114 114 .enable_tmds_link_output = dce110_enable_tmds_link_output, 115 115 .enable_dp_link_output = dce110_enable_dp_link_output, 116 - .disable_link_output = dcn32_disable_link_output, 116 + .disable_link_output = dcn35_disable_link_output, 117 117 .z10_restore = dcn35_z10_restore, 118 118 .z10_save_init = dcn31_z10_save_init, 119 119 .set_disp_pattern_generator = dcn30_set_disp_pattern_generator,

+2

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

··· 287 287 for (i = 0; i < dc->link_count; i++) { 288 288 struct dc_link *link = dc->links[i]; 289 289 290 + if (link->ep_type != DISPLAY_ENDPOINT_PHY) 291 + continue; 290 292 if (link->link_enc->funcs->is_dig_enabled && 291 293 link->link_enc->funcs->is_dig_enabled(link->link_enc) && 292 294 hws->funcs.power_down) {

+1

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

··· 333 333 void (*set_ref_dscclk)(struct dccg *dccg, uint32_t dsc_inst); 334 334 void (*dccg_root_gate_disable_control)(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating); 335 335 void (*dccg_read_reg_state)(struct dccg *dccg, struct dcn_dccg_reg_state *dccg_reg_state); 336 + void (*dccg_enable_global_fgcg)(struct dccg *dccg, bool enable); 336 337 }; 337 338 338 339 #endif //__DAL_DCCG_H__

+6 -6

drivers/gpu/drm/amd/display/dc/inc/link_service.h

··· 283 283 bool (*edp_set_replay_allow_active)(struct dc_link *dc_link, 284 284 const bool *enable, bool wait, bool force_static, 285 285 const unsigned int *power_opts); 286 - bool (*edp_setup_replay)(struct dc_link *link, 287 - const struct dc_stream_state *stream); 288 286 bool (*edp_send_replay_cmd)(struct dc_link *link, 289 287 enum replay_FW_Message_type msg, 290 288 union dmub_replay_cmd_set *cmd_data); ··· 302 304 bool (*edp_receiver_ready_T9)(struct dc_link *link); 303 305 bool (*edp_receiver_ready_T7)(struct dc_link *link); 304 306 bool (*edp_power_alpm_dpcd_enable)(struct dc_link *link, bool enable); 305 - bool (*edp_pr_enable)(struct dc_link *link, bool enable); 306 - bool (*edp_pr_update_state)(struct dc_link *link, struct dmub_cmd_pr_update_state_data *update_state_data); 307 - bool (*edp_pr_set_general_cmd)(struct dc_link *link, struct dmub_cmd_pr_general_cmd_data *general_cmd_data); 308 - bool (*edp_pr_get_state)(const struct dc_link *link, uint64_t *state); 307 + bool (*dp_setup_replay)(struct dc_link *link, const struct dc_stream_state *stream); 308 + bool (*dp_pr_get_panel_inst)(const struct dc *dc, const struct dc_link *link, unsigned int *inst_out); 309 + bool (*dp_pr_enable)(struct dc_link *link, bool enable); 310 + bool (*dp_pr_update_state)(struct dc_link *link, struct dmub_cmd_pr_update_state_data *update_state_data); 311 + bool (*dp_pr_set_general_cmd)(struct dc_link *link, struct dmub_cmd_pr_general_cmd_data *general_cmd_data); 312 + bool (*dp_pr_get_state)(const struct dc_link *link, uint64_t *state); 309 313 void (*edp_set_panel_power)(struct dc_link *link, bool powerOn); 310 314 311 315

+1 -1

drivers/gpu/drm/amd/display/dc/link/Makefile

··· 56 56 link_dp_training.o link_dp_training_8b_10b.o link_dp_training_128b_132b.o \ 57 57 link_dp_training_dpia.o link_dp_training_auxless.o \ 58 58 link_dp_training_fixed_vs_pe_retimer.o link_dp_phy.o link_dp_capability.o \ 59 - link_edp_panel_control.o link_dp_irq_handler.o link_dp_dpia_bw.o 59 + link_edp_panel_control.o link_dp_panel_replay.o link_dp_irq_handler.o link_dp_dpia_bw.o 60 60 61 61 AMD_DAL_LINK_PROTOCOLS = $(addprefix $(AMDDALPATH)/dc/link/protocols/, \ 62 62 $(LINK_PROTOCOLS))

+6 -1

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

··· 70 70 struct dc_state *state = link->dc->current_state; 71 71 struct dc_stream_update stream_update = { 0 }; 72 72 bool dpms_off = false; 73 + bool needs_divider_update = false; 73 74 bool was_hpo_acquired = resource_is_hpo_acquired(link->dc->current_state); 74 75 bool is_hpo_acquired; 75 76 uint8_t count; ··· 79 78 struct dc_stream_state *streams_on_link[MAX_PIPES]; 80 79 int num_streams_on_link = 0; 81 80 struct dc *dc = (struct dc *)link->dc; 81 + 82 + needs_divider_update = (link->dc->link_srv->dp_get_encoding_format(link_setting) != 83 + link->dc->link_srv->dp_get_encoding_format((const struct dc_link_settings *) &link->cur_link_settings)) 84 + || link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA; 82 85 83 86 udelay(100); 84 87 ··· 100 95 pipes[i]->stream_res.tg->funcs->disable_crtc(pipes[i]->stream_res.tg); 101 96 } 102 97 103 - if (link->dc->res_pool->funcs->update_dc_state_for_encoder_switch) { 98 + if (needs_divider_update && link->dc->res_pool->funcs->update_dc_state_for_encoder_switch) { 104 99 link->dc->res_pool->funcs->update_dc_state_for_encoder_switch(link, 105 100 link_setting, count, 106 101 *pipes, &audio_output[0]);

+4 -2

drivers/gpu/drm/amd/display/dc/link/link_detection.c

··· 335 335 336 336 /* Assume we have no valid DP passive dongle connected */ 337 337 *dongle = DISPLAY_DONGLE_NONE; 338 - sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK; 338 + sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK; 339 339 340 340 /* Read DP-HDMI dongle I2c (no response interpreted as DP-DVI dongle)*/ 341 341 if (!i2c_read( ··· 391 391 392 392 } 393 393 } 394 + if (is_valid_hdmi_signature) 395 + sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK; 394 396 395 397 if (is_type2_dongle) { 396 398 uint32_t max_tmds_clk = ··· 995 993 (link->dpcd_sink_ext_caps.bits.oled == 1)) { 996 994 dpcd_set_source_specific_data(link); 997 995 msleep(post_oui_delay); 998 - set_default_brightness(link); 996 + set_default_brightness_aux(link); 999 997 } 1000 998 1001 999 return true;

+6 -2

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

··· 46 46 #include "protocols/link_dp_capability.h" 47 47 #include "protocols/link_dp_training.h" 48 48 #include "protocols/link_edp_panel_control.h" 49 + #include "protocols/link_dp_panel_replay.h" 49 50 #include "protocols/link_dp_dpia_bw.h" 50 51 51 52 #include "dm_helpers.h" ··· 2062 2061 skip_video_pattern = false; 2063 2062 2064 2063 if (stream->sink_patches.oled_optimize_display_on) 2065 - set_default_brightness(link); 2064 + set_default_brightness_aux(link); 2066 2065 2067 2066 if (perform_link_training_with_retries(link_settings, 2068 2067 skip_video_pattern, ··· 2088 2087 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 || 2089 2088 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) { 2090 2089 if (!stream->sink_patches.oled_optimize_display_on) { 2091 - set_default_brightness(link); 2090 + set_default_brightness_aux(link); 2092 2091 if (link->dpcd_sink_ext_caps.bits.oled == 1) 2093 2092 msleep(bl_oled_enable_delay); 2094 2093 edp_backlight_enable_aux(link, true); ··· 2529 2528 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2530 2529 link_set_dsc_enable(pipe_ctx, true); 2531 2530 } 2531 + 2532 + if (link->replay_settings.config.replay_supported && !dc_is_embedded_signal(link->connector_signal)) 2533 + dp_setup_replay(link, stream); 2532 2534 2533 2535 status = enable_link(state, pipe_ctx); 2534 2536

+14 -5

drivers/gpu/drm/amd/display/dc/link/link_factory.c

··· 41 41 #include "protocols/link_dp_phy.h" 42 42 #include "protocols/link_dp_training.h" 43 43 #include "protocols/link_edp_panel_control.h" 44 + #include "protocols/link_dp_panel_replay.h" 44 45 #include "protocols/link_hpd.h" 45 46 #include "gpio_service_interface.h" 46 47 #include "atomfirmware.h" ··· 215 214 216 215 link_srv->edp_get_replay_state = edp_get_replay_state; 217 216 link_srv->edp_set_replay_allow_active = edp_set_replay_allow_active; 218 - link_srv->edp_setup_replay = edp_setup_replay; 219 217 link_srv->edp_send_replay_cmd = edp_send_replay_cmd; 220 218 link_srv->edp_set_coasting_vtotal = edp_set_coasting_vtotal; 221 219 link_srv->edp_replay_residency = edp_replay_residency; ··· 228 228 link_srv->edp_receiver_ready_T9 = edp_receiver_ready_T9; 229 229 link_srv->edp_receiver_ready_T7 = edp_receiver_ready_T7; 230 230 link_srv->edp_power_alpm_dpcd_enable = edp_power_alpm_dpcd_enable; 231 - link_srv->edp_pr_enable = edp_pr_enable; 232 - link_srv->edp_pr_update_state = edp_pr_update_state; 233 - link_srv->edp_pr_set_general_cmd = edp_pr_set_general_cmd; 234 - link_srv->edp_pr_get_state = edp_pr_get_state; 235 231 link_srv->edp_set_panel_power = edp_set_panel_power; 232 + } 233 + 234 + /* link dp panel replay implements DP panel replay functionality. 235 + */ 236 + static void construct_link_service_dp_panel_replay(struct link_service *link_srv) 237 + { 238 + link_srv->dp_setup_replay = dp_setup_replay; 239 + link_srv->dp_pr_get_panel_inst = dp_pr_get_panel_inst; 240 + link_srv->dp_pr_enable = dp_pr_enable; 241 + link_srv->dp_pr_update_state = dp_pr_update_state; 242 + link_srv->dp_pr_set_general_cmd = dp_pr_set_general_cmd; 243 + link_srv->dp_pr_get_state = dp_pr_get_state; 236 244 } 237 245 238 246 /* link dp cts implements dp compliance test automation protocols and manual ··· 295 287 construct_link_service_dp_phy_or_dpia(link_srv); 296 288 construct_link_service_dp_irq_handler(link_srv); 297 289 construct_link_service_edp_panel_control(link_srv); 290 + construct_link_service_dp_panel_replay(link_srv); 298 291 construct_link_service_dp_cts(link_srv); 299 292 construct_link_service_dp_trace(link_srv); 300 293 }

+46 -3

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

··· 1593 1593 return true; 1594 1594 } 1595 1595 1596 + static void retrieve_vesa_replay_su_info(struct dc_link *link) 1597 + { 1598 + uint8_t dpcd_data = 0; 1599 + 1600 + core_link_read_dpcd(link, 1601 + DP_PR_SU_X_GRANULARITY_LOW, 1602 + &dpcd_data, 1603 + sizeof(dpcd_data)); 1604 + link->dpcd_caps.vesa_replay_su_info.pr_su_x_granularity = dpcd_data; 1605 + 1606 + core_link_read_dpcd(link, 1607 + DP_PR_SU_X_GRANULARITY_HIGH, 1608 + &dpcd_data, 1609 + sizeof(dpcd_data)); 1610 + link->dpcd_caps.vesa_replay_su_info.pr_su_x_granularity |= (dpcd_data << 8); 1611 + 1612 + core_link_read_dpcd(link, 1613 + DP_PR_SU_Y_GRANULARITY, 1614 + &dpcd_data, 1615 + sizeof(dpcd_data)); 1616 + link->dpcd_caps.vesa_replay_su_info.pr_su_y_granularity = dpcd_data; 1617 + 1618 + core_link_read_dpcd(link, 1619 + DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_LOW, 1620 + &dpcd_data, 1621 + sizeof(dpcd_data)); 1622 + link->dpcd_caps.vesa_replay_su_info.pr_su_y_granularity_extended_caps = dpcd_data; 1623 + 1624 + core_link_read_dpcd(link, 1625 + DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_HIGH, 1626 + &dpcd_data, 1627 + sizeof(dpcd_data)); 1628 + link->dpcd_caps.vesa_replay_su_info.pr_su_y_granularity_extended_caps |= (dpcd_data << 8); 1629 + } 1630 + 1596 1631 enum dc_status dp_retrieve_lttpr_cap(struct dc_link *link) 1597 1632 { 1598 1633 uint8_t lttpr_dpcd_data[10] = {0}; ··· 2129 2094 2130 2095 core_link_read_dpcd(link, 2131 2096 DP_PANEL_REPLAY_CAPABILITY_SUPPORT, 2132 - &link->dpcd_caps.pr_caps_supported.raw, 2133 - sizeof(link->dpcd_caps.pr_caps_supported.raw)); 2097 + &link->dpcd_caps.vesa_replay_caps_supported.raw, 2098 + sizeof(link->dpcd_caps.vesa_replay_caps_supported.raw)); 2099 + 2100 + core_link_read_dpcd(link, 2101 + DP_PANEL_REPLAY_CAPABILITY, 2102 + &link->dpcd_caps.vesa_replay_caps.raw, 2103 + sizeof(link->dpcd_caps.vesa_replay_caps.raw)); 2104 + 2105 + /* Read VESA Panel Replay Selective Update caps */ 2106 + retrieve_vesa_replay_su_info(link); 2134 2107 2135 2108 /* Read DP tunneling information. */ 2136 2109 status = dpcd_get_tunneling_device_data(link); ··· 2210 2167 link->dpcd_caps.set_power_state_capable_edp = 2211 2168 (general_edp_cap & DP_EDP_SET_POWER_CAP) ? true : false; 2212 2169 2213 - set_default_brightness(link); 2170 + set_default_brightness_aux(link); 2214 2171 2215 2172 core_link_read_dpcd(link, DP_EDP_DPCD_REV, 2216 2173 &link->dpcd_caps.edp_rev,

+43

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

··· 34 34 #include "link_dp_training.h" 35 35 #include "link_dp_capability.h" 36 36 #include "link_edp_panel_control.h" 37 + #include "link_dp_panel_replay.h" 37 38 #include "link/accessories/link_dp_trace.h" 38 39 #include "link/link_dpms.h" 39 40 #include "dm_helpers.h" 40 41 #include "link_dp_dpia_bw.h" 42 + #include "link_dp_panel_replay.h" 41 43 42 44 #define DC_LOGGER \ 43 45 link->ctx->logger ··· 187 185 return false; 188 186 } 189 187 188 + static void handle_hpd_irq_vesa_replay_sink(struct dc_link *link) 189 + { 190 + union pr_error_status pr_error_status = {0}; 191 + 192 + if (!link->replay_settings.replay_feature_enabled || 193 + link->replay_settings.config.replay_version != DC_VESA_PANEL_REPLAY) 194 + return; 195 + 196 + dm_helpers_dp_read_dpcd( 197 + link->ctx, 198 + link, 199 + DP_PR_ERROR_STATUS, 200 + &pr_error_status.raw, 201 + sizeof(pr_error_status.raw)); 202 + 203 + if (pr_error_status.bits.LINK_CRC_ERROR || 204 + pr_error_status.bits.RFB_STORAGE_ERROR || 205 + pr_error_status.bits.VSC_SDP_ERROR || 206 + pr_error_status.bits.ASSDP_MISSING_ERROR) { 207 + 208 + /* Acknowledge and clear error bits */ 209 + dm_helpers_dp_write_dpcd( 210 + link->ctx, 211 + link, 212 + DP_PR_ERROR_STATUS, /*DpcdAddress_PR_Error_Status*/ 213 + &pr_error_status.raw, 214 + sizeof(pr_error_status.raw)); 215 + 216 + /* Replay error, disable and re-enable Replay */ 217 + if (link->replay_settings.replay_allow_active) { 218 + dp_pr_enable(link, false); 219 + dp_pr_enable(link, true); 220 + } 221 + } 222 + } 223 + 190 224 static void handle_hpd_irq_replay_sink(struct dc_link *link) 191 225 { 192 226 union dpcd_replay_configuration replay_configuration = {0}; ··· 233 195 234 196 if (!link->replay_settings.replay_feature_enabled) 235 197 return; 198 + 199 + if (link->replay_settings.config.replay_version != DC_FREESYNC_REPLAY) { 200 + handle_hpd_irq_vesa_replay_sink(link); 201 + return; 202 + } 236 203 237 204 while (retries < 10) { 238 205 ret = dm_helpers_dp_read_dpcd(

+343

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

··· 1 + /* 2 + * Copyright 2025 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included in 12 + * all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 + * 22 + * Authors: AMD 23 + * 24 + */ 25 + 26 + #include "link_dp_panel_replay.h" 27 + #include "link_edp_panel_control.h" 28 + #include "link_dpcd.h" 29 + #include "dm_helpers.h" 30 + #include "dc/dc_dmub_srv.h" 31 + #include "dce/dmub_replay.h" 32 + 33 + #define DC_LOGGER \ 34 + link->ctx->logger 35 + 36 + #define DP_SINK_PR_ENABLE_AND_CONFIGURATION 0x37B 37 + 38 + static bool dp_setup_panel_replay(struct dc_link *link, const struct dc_stream_state *stream) 39 + { 40 + /* To-do: Setup Replay */ 41 + struct dc *dc; 42 + struct dmub_replay *replay; 43 + int i; 44 + unsigned int panel_inst; 45 + struct replay_context replay_context = { 0 }; 46 + unsigned int lineTimeInNs = 0; 47 + 48 + union panel_replay_enable_and_configuration_1 pr_config_1 = { 0 }; 49 + union panel_replay_enable_and_configuration_2 pr_config_2 = { 0 }; 50 + 51 + union dpcd_alpm_configuration alpm_config; 52 + 53 + replay_context.controllerId = CONTROLLER_ID_UNDEFINED; 54 + 55 + if (!link) 56 + return false; 57 + 58 + //Clear Panel Replay enable & config 59 + dm_helpers_dp_write_dpcd(link->ctx, link, 60 + DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1, 61 + (uint8_t *)&(pr_config_1.raw), sizeof(uint8_t)); 62 + 63 + dm_helpers_dp_write_dpcd(link->ctx, link, 64 + DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2, 65 + (uint8_t *)&(pr_config_2.raw), sizeof(uint8_t)); 66 + 67 + if (!(link->replay_settings.config.replay_supported)) 68 + return false; 69 + 70 + dc = link->ctx->dc; 71 + 72 + //not sure should keep or not 73 + replay = dc->res_pool->replay; 74 + 75 + if (!replay) 76 + return false; 77 + 78 + if (!dp_pr_get_panel_inst(dc, link, &panel_inst)) 79 + return false; 80 + 81 + replay_context.aux_inst = link->ddc->ddc_pin->hw_info.ddc_channel; 82 + replay_context.digbe_inst = link->link_enc->transmitter; 83 + replay_context.digfe_inst = link->link_enc->preferred_engine; 84 + 85 + for (i = 0; i < MAX_PIPES; i++) { 86 + if (dc->current_state->res_ctx.pipe_ctx[i].stream 87 + == stream) { 88 + /* dmcu -1 for all controller id values, 89 + * therefore +1 here 90 + */ 91 + replay_context.controllerId = 92 + dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst + 1; 93 + break; 94 + } 95 + } 96 + 97 + lineTimeInNs = 98 + ((stream->timing.h_total * 1000000) / 99 + (stream->timing.pix_clk_100hz / 10)) + 1; 100 + 101 + replay_context.line_time_in_ns = lineTimeInNs; 102 + 103 + link->replay_settings.replay_feature_enabled = dp_pr_copy_settings(link, &replay_context); 104 + 105 + if (link->replay_settings.replay_feature_enabled) { 106 + if (dc_is_embedded_signal(link->connector_signal)) { 107 + pr_config_1.bits.PANEL_REPLAY_ENABLE = 1; 108 + pr_config_1.bits.PANEL_REPLAY_CRC_ENABLE = 1; 109 + pr_config_1.bits.IRQ_HPD_ASSDP_MISSING = 1; 110 + pr_config_1.bits.IRQ_HPD_VSCSDP_UNCORRECTABLE_ERROR = 1; 111 + pr_config_1.bits.IRQ_HPD_RFB_ERROR = 1; 112 + pr_config_1.bits.IRQ_HPD_ACTIVE_FRAME_CRC_ERROR = 1; 113 + pr_config_1.bits.PANEL_REPLAY_SELECTIVE_UPDATE_ENABLE = 1; 114 + pr_config_1.bits.PANEL_REPLAY_EARLY_TRANSPORT_ENABLE = 1; 115 + } else { 116 + pr_config_1.bits.PANEL_REPLAY_ENABLE = 1; 117 + } 118 + 119 + pr_config_2.bits.SINK_REFRESH_RATE_UNLOCK_GRANTED = 0; 120 + 121 + if (link->dpcd_caps.vesa_replay_caps.bits.SU_Y_GRANULARITY_EXT_CAP_SUPPORTED) 122 + pr_config_2.bits.SU_Y_GRANULARITY_EXT_VALUE_ENABLED = 1; 123 + 124 + pr_config_2.bits.SU_REGION_SCAN_LINE_CAPTURE_INDICATION = 0; 125 + 126 + dm_helpers_dp_write_dpcd(link->ctx, link, 127 + DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1, 128 + (uint8_t *)&(pr_config_1.raw), sizeof(uint8_t)); 129 + 130 + dm_helpers_dp_write_dpcd(link->ctx, link, 131 + DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2, 132 + (uint8_t *)&(pr_config_2.raw), sizeof(uint8_t)); 133 + 134 + //ALPM Setup 135 + memset(&alpm_config, 0, sizeof(alpm_config)); 136 + alpm_config.bits.ENABLE = link->replay_settings.config.alpm_mode != DC_ALPM_UNSUPPORTED ? 1 : 0; 137 + 138 + if (link->replay_settings.config.alpm_mode == DC_ALPM_AUXLESS) { 139 + alpm_config.bits.ALPM_MODE_SEL = 1; 140 + alpm_config.bits.ACDS_PERIOD_DURATION = 1; 141 + } 142 + 143 + dm_helpers_dp_write_dpcd( 144 + link->ctx, 145 + link, 146 + DP_RECEIVER_ALPM_CONFIG, 147 + &alpm_config.raw, 148 + sizeof(alpm_config.raw)); 149 + } 150 + 151 + return true; 152 + } 153 + 154 + 155 + bool dp_pr_get_panel_inst(const struct dc *dc, 156 + const struct dc_link *link, 157 + unsigned int *inst_out) 158 + { 159 + if (dc_is_embedded_signal(link->connector_signal)) { 160 + /* TODO: just get edp link panel inst for now, fix it */ 161 + return dc_get_edp_link_panel_inst(dc, link, inst_out); 162 + } else if (dc_is_dp_sst_signal(link->connector_signal)) { 163 + /* TODO: just set to 1 for now, fix it */ 164 + *inst_out = 1; 165 + return true; 166 + } 167 + 168 + return false; 169 + } 170 + 171 + bool dp_setup_replay(struct dc_link *link, const struct dc_stream_state *stream) 172 + { 173 + if (!link) 174 + return false; 175 + if (link->replay_settings.config.replay_version == DC_VESA_PANEL_REPLAY) 176 + return dp_setup_panel_replay(link, stream); 177 + else if (link->replay_settings.config.replay_version == DC_FREESYNC_REPLAY) 178 + return edp_setup_freesync_replay(link, stream); 179 + else 180 + return false; 181 + } 182 + 183 + bool dp_pr_enable(struct dc_link *link, bool enable) 184 + { 185 + struct dc *dc = link->ctx->dc; 186 + unsigned int panel_inst = 0; 187 + union dmub_rb_cmd cmd; 188 + 189 + if (!dp_pr_get_panel_inst(dc, link, &panel_inst)) 190 + return false; 191 + 192 + if (link->replay_settings.replay_allow_active != enable) { 193 + //for sending PR enable commands to DMUB 194 + memset(&cmd, 0, sizeof(cmd)); 195 + 196 + cmd.pr_enable.header.type = DMUB_CMD__PR; 197 + cmd.pr_enable.header.sub_type = DMUB_CMD__PR_ENABLE; 198 + cmd.pr_enable.header.payload_bytes = sizeof(struct dmub_cmd_pr_enable_data); 199 + cmd.pr_enable.data.panel_inst = panel_inst; 200 + cmd.pr_enable.data.enable = enable ? 1 : 0; 201 + 202 + dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 203 + 204 + link->replay_settings.replay_allow_active = enable; 205 + } 206 + return true; 207 + } 208 + 209 + bool dp_pr_copy_settings(struct dc_link *link, struct replay_context *replay_context) 210 + { 211 + struct dc *dc = link->ctx->dc; 212 + unsigned int panel_inst = 0; 213 + union dmub_rb_cmd cmd; 214 + struct pipe_ctx *pipe_ctx = NULL; 215 + 216 + if (!dp_pr_get_panel_inst(dc, link, &panel_inst)) 217 + return false; 218 + 219 + for (unsigned int i = 0; i < MAX_PIPES; i++) { 220 + if (dc->current_state->res_ctx.pipe_ctx[i].stream && 221 + dc->current_state->res_ctx.pipe_ctx[i].stream->link && 222 + dc->current_state->res_ctx.pipe_ctx[i].stream->link == link && 223 + dc_is_dp_sst_signal(dc->current_state->res_ctx.pipe_ctx[i].stream->link->connector_signal)) { 224 + pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 225 + /* todo: need update for MST */ 226 + break; 227 + } 228 + } 229 + 230 + if (!pipe_ctx) 231 + return false; 232 + 233 + memset(&cmd, 0, sizeof(cmd)); 234 + cmd.pr_copy_settings.header.type = DMUB_CMD__PR; 235 + cmd.pr_copy_settings.header.sub_type = DMUB_CMD__PR_COPY_SETTINGS; 236 + cmd.pr_copy_settings.header.payload_bytes = sizeof(struct dmub_cmd_pr_copy_settings_data); 237 + cmd.pr_copy_settings.data.panel_inst = panel_inst; 238 + // HW inst 239 + cmd.pr_copy_settings.data.aux_inst = replay_context->aux_inst; 240 + cmd.pr_copy_settings.data.digbe_inst = replay_context->digbe_inst; 241 + cmd.pr_copy_settings.data.digfe_inst = replay_context->digfe_inst; 242 + if (pipe_ctx->plane_res.dpp) 243 + cmd.pr_copy_settings.data.dpp_inst = pipe_ctx->plane_res.dpp->inst; 244 + else 245 + cmd.pr_copy_settings.data.dpp_inst = 0; 246 + if (pipe_ctx->stream_res.tg) 247 + cmd.pr_copy_settings.data.otg_inst = pipe_ctx->stream_res.tg->inst; 248 + else 249 + cmd.pr_copy_settings.data.otg_inst = 0; 250 + 251 + cmd.pr_copy_settings.data.dpphy_inst = link->link_enc->transmitter; 252 + 253 + cmd.pr_copy_settings.data.line_time_in_ns = replay_context->line_time_in_ns; 254 + cmd.pr_copy_settings.data.flags.bitfields.fec_enable_status = (link->fec_state == dc_link_fec_enabled); 255 + cmd.pr_copy_settings.data.flags.bitfields.dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1); 256 + cmd.pr_copy_settings.data.debug.u32All = link->replay_settings.config.debug_flags; 257 + 258 + cmd.pr_copy_settings.data.su_granularity_needed = link->dpcd_caps.vesa_replay_caps.bits.PR_SU_GRANULARITY_NEEDED; 259 + cmd.pr_copy_settings.data.su_x_granularity = link->dpcd_caps.vesa_replay_su_info.pr_su_x_granularity; 260 + cmd.pr_copy_settings.data.su_y_granularity = link->dpcd_caps.vesa_replay_su_info.pr_su_y_granularity; 261 + cmd.pr_copy_settings.data.su_y_granularity_extended_caps = 262 + link->dpcd_caps.vesa_replay_su_info.pr_su_y_granularity_extended_caps; 263 + 264 + if (pipe_ctx->stream->timing.dsc_cfg.num_slices_v > 0) 265 + cmd.pr_copy_settings.data.dsc_slice_height = (pipe_ctx->stream->timing.v_addressable + 266 + pipe_ctx->stream->timing.v_border_top + pipe_ctx->stream->timing.v_border_bottom) / 267 + pipe_ctx->stream->timing.dsc_cfg.num_slices_v; 268 + 269 + dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 270 + return true; 271 + } 272 + 273 + bool dp_pr_update_state(struct dc_link *link, struct dmub_cmd_pr_update_state_data *update_state_data) 274 + { 275 + struct dc *dc = link->ctx->dc; 276 + unsigned int panel_inst = 0; 277 + union dmub_rb_cmd cmd; 278 + 279 + if (!dp_pr_get_panel_inst(dc, link, &panel_inst)) 280 + return false; 281 + 282 + memset(&cmd, 0, sizeof(cmd)); 283 + cmd.pr_update_state.header.type = DMUB_CMD__PR; 284 + cmd.pr_update_state.header.sub_type = DMUB_CMD__PR_UPDATE_STATE; 285 + cmd.pr_update_state.header.payload_bytes = sizeof(struct dmub_cmd_pr_update_state_data); 286 + cmd.pr_update_state.data.panel_inst = panel_inst; 287 + 288 + memcpy(&cmd.pr_update_state.data, update_state_data, sizeof(struct dmub_cmd_pr_update_state_data)); 289 + 290 + dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 291 + return true; 292 + } 293 + 294 + bool dp_pr_set_general_cmd(struct dc_link *link, struct dmub_cmd_pr_general_cmd_data *general_cmd_data) 295 + { 296 + struct dc *dc = link->ctx->dc; 297 + unsigned int panel_inst = 0; 298 + union dmub_rb_cmd cmd; 299 + 300 + if (!dp_pr_get_panel_inst(dc, link, &panel_inst)) 301 + return false; 302 + 303 + memset(&cmd, 0, sizeof(cmd)); 304 + cmd.pr_general_cmd.header.type = DMUB_CMD__PR; 305 + cmd.pr_general_cmd.header.sub_type = DMUB_CMD__PR_GENERAL_CMD; 306 + cmd.pr_general_cmd.header.payload_bytes = sizeof(struct dmub_cmd_pr_general_cmd_data); 307 + cmd.pr_general_cmd.data.panel_inst = panel_inst; 308 + 309 + memcpy(&cmd.pr_general_cmd.data, general_cmd_data, sizeof(struct dmub_cmd_pr_general_cmd_data)); 310 + 311 + dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 312 + return true; 313 + } 314 + 315 + bool dp_pr_get_state(const struct dc_link *link, uint64_t *state) 316 + { 317 + const struct dc *dc = link->ctx->dc; 318 + unsigned int panel_inst = 0; 319 + uint32_t retry_count = 0; 320 + uint32_t replay_state = 0; 321 + 322 + if (!dp_pr_get_panel_inst(dc, link, &panel_inst)) 323 + return false; 324 + 325 + do { 326 + // Send gpint command and wait for ack 327 + if (!dc_wake_and_execute_gpint(dc->ctx, DMUB_GPINT__GET_REPLAY_STATE, panel_inst, 328 + &replay_state, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) { 329 + // Return invalid state when GPINT times out 330 + replay_state = PR_STATE_INVALID; 331 + } 332 + /* Copy 32-bit result into 64-bit output */ 333 + *state = replay_state; 334 + } while (++retry_count <= 1000 && *state == PR_STATE_INVALID); 335 + 336 + // Assert if max retry hit 337 + if (retry_count >= 1000 && *state == PR_STATE_INVALID) { 338 + ASSERT(0); 339 + /* To-do: Add retry fail log */ 340 + } 341 + 342 + return true; 343 + }

+38

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.h

··· 1 + /* 2 + * Copyright 2025 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included in 12 + * all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 + * 22 + * Authors: AMD 23 + * 24 + */ 25 + #ifndef __DC_LINK_DP_PANEL_REPLAY_H__ 26 + #define __DC_LINK_DP_PANEL_REPLAY_H__ 27 + 28 + #include "link_service.h" 29 + 30 + bool dp_setup_replay(struct dc_link *link, const struct dc_stream_state *stream); 31 + bool dp_pr_get_panel_inst(const struct dc *dc, const struct dc_link *link, unsigned int *inst_out); 32 + bool dp_pr_enable(struct dc_link *link, bool enable); 33 + bool dp_pr_copy_settings(struct dc_link *link, struct replay_context *replay_context); 34 + bool dp_pr_update_state(struct dc_link *link, struct dmub_cmd_pr_update_state_data *update_state_data); 35 + bool dp_pr_set_general_cmd(struct dc_link *link, struct dmub_cmd_pr_general_cmd_data *general_cmd_data); 36 + bool dp_pr_get_state(const struct dc_link *link, uint64_t *state); 37 + 38 + #endif /* __DC_LINK_DP_PANEL_REPLAY_H__ */

+4 -293

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

··· 50 50 /* Nutmeg */ 51 51 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA"; 52 52 53 - static const unsigned int pwr_default_min_brightness_millinits = 1000; 54 - static const unsigned int pwr_default_sdr_brightness_millinits = 270000; 55 - static const unsigned int pwr_default_min_backlight_pwm = 0xC0C; 56 - static const unsigned int pwr_default_max_backlight_pwm = 0xFFFF; 57 - 58 53 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode) 59 54 { 60 55 union dpcd_edp_config edp_config_set; ··· 308 313 return true; 309 314 } 310 315 311 - bool set_default_brightness(struct dc_link *link) 316 + bool set_default_brightness_aux(struct dc_link *link) 312 317 { 313 318 uint32_t default_backlight; 314 319 ··· 319 324 if (default_backlight < 1000 || default_backlight > 5000000) 320 325 default_backlight = 150000; 321 326 322 - if (link->backlight_control_type == BACKLIGHT_CONTROL_VESA_AUX && 323 - link->dc->caps.dmub_caps.aux_backlight_support) { 324 - struct set_backlight_level_params backlight_level_params = { 0 }; 325 - 326 - backlight_level_params.aux_inst = link->ddc->ddc_pin->hw_info.ddc_channel; 327 - backlight_level_params.control_type = BACKLIGHT_CONTROL_VESA_AUX; 328 - backlight_level_params.backlight_pwm_u16_16 = default_backlight; 329 - backlight_level_params.transition_time_in_ms = 0; 330 - // filled in the driver BL default values 331 - backlight_level_params.min_luminance = pwr_default_min_brightness_millinits; 332 - backlight_level_params.max_luminance = pwr_default_sdr_brightness_millinits; 333 - backlight_level_params.min_backlight_pwm = pwr_default_min_backlight_pwm; 334 - backlight_level_params.max_backlight_pwm = pwr_default_max_backlight_pwm; 335 - return edp_set_backlight_level(link, &backlight_level_params); 336 - } else 337 - return edp_set_backlight_level_nits(link, true, 338 - default_backlight, 0); 327 + return edp_set_backlight_level_nits(link, true, 328 + default_backlight, 0); 339 329 } 340 330 return false; 341 331 } ··· 983 1003 return true; 984 1004 } 985 1005 986 - static bool edp_setup_panel_replay(struct dc_link *link, const struct dc_stream_state *stream) 987 - { 988 - /* To-do: Setup Replay */ 989 - struct dc *dc; 990 - struct dmub_replay *replay; 991 - int i; 992 - unsigned int panel_inst; 993 - struct replay_context replay_context = { 0 }; 994 - unsigned int lineTimeInNs = 0; 995 1006 996 - union panel_replay_enable_and_configuration_1 pr_config_1 = { 0 }; 997 - union panel_replay_enable_and_configuration_2 pr_config_2 = { 0 }; 998 - 999 - union dpcd_alpm_configuration alpm_config; 1000 - 1001 - replay_context.controllerId = CONTROLLER_ID_UNDEFINED; 1002 - 1003 - if (!link) 1004 - return false; 1005 - 1006 - //Clear Panel Replay enable & config 1007 - dm_helpers_dp_write_dpcd(link->ctx, link, 1008 - DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1, 1009 - (uint8_t *)&(pr_config_1.raw), sizeof(uint8_t)); 1010 - 1011 - dm_helpers_dp_write_dpcd(link->ctx, link, 1012 - DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2, 1013 - (uint8_t *)&(pr_config_2.raw), sizeof(uint8_t)); 1014 - 1015 - if (!(link->replay_settings.config.replay_supported)) 1016 - return false; 1017 - 1018 - dc = link->ctx->dc; 1019 - 1020 - //not sure should keep or not 1021 - replay = dc->res_pool->replay; 1022 - 1023 - if (!replay) 1024 - return false; 1025 - 1026 - if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst)) 1027 - return false; 1028 - 1029 - replay_context.aux_inst = link->ddc->ddc_pin->hw_info.ddc_channel; 1030 - replay_context.digbe_inst = link->link_enc->transmitter; 1031 - replay_context.digfe_inst = link->link_enc->preferred_engine; 1032 - 1033 - for (i = 0; i < MAX_PIPES; i++) { 1034 - if (dc->current_state->res_ctx.pipe_ctx[i].stream 1035 - == stream) { 1036 - /* dmcu -1 for all controller id values, 1037 - * therefore +1 here 1038 - */ 1039 - replay_context.controllerId = 1040 - dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst + 1; 1041 - break; 1042 - } 1043 - } 1044 - 1045 - lineTimeInNs = 1046 - ((stream->timing.h_total * 1000000) / 1047 - (stream->timing.pix_clk_100hz / 10)) + 1; 1048 - 1049 - replay_context.line_time_in_ns = lineTimeInNs; 1050 - 1051 - link->replay_settings.replay_feature_enabled = edp_pr_copy_settings(link, &replay_context); 1052 - 1053 - if (link->replay_settings.replay_feature_enabled) { 1054 - pr_config_1.bits.PANEL_REPLAY_ENABLE = 1; 1055 - pr_config_1.bits.PANEL_REPLAY_CRC_ENABLE = 1; 1056 - pr_config_1.bits.IRQ_HPD_ASSDP_MISSING = 1; 1057 - pr_config_1.bits.IRQ_HPD_VSCSDP_UNCORRECTABLE_ERROR = 1; 1058 - pr_config_1.bits.IRQ_HPD_RFB_ERROR = 1; 1059 - pr_config_1.bits.IRQ_HPD_ACTIVE_FRAME_CRC_ERROR = 1; 1060 - pr_config_1.bits.PANEL_REPLAY_SELECTIVE_UPDATE_ENABLE = 1; 1061 - pr_config_1.bits.PANEL_REPLAY_EARLY_TRANSPORT_ENABLE = 1; 1062 - 1063 - pr_config_2.bits.SINK_REFRESH_RATE_UNLOCK_GRANTED = 0; 1064 - pr_config_2.bits.SU_Y_GRANULARITY_EXT_VALUE_ENABLED = 0; 1065 - pr_config_2.bits.SU_REGION_SCAN_LINE_CAPTURE_INDICATION = 0; 1066 - 1067 - dm_helpers_dp_write_dpcd(link->ctx, link, 1068 - DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1, 1069 - (uint8_t *)&(pr_config_1.raw), sizeof(uint8_t)); 1070 - 1071 - dm_helpers_dp_write_dpcd(link->ctx, link, 1072 - DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2, 1073 - (uint8_t *)&(pr_config_2.raw), sizeof(uint8_t)); 1074 - 1075 - //ALPM Setup 1076 - memset(&alpm_config, 0, sizeof(alpm_config)); 1077 - alpm_config.bits.ENABLE = link->replay_settings.config.alpm_mode != DC_ALPM_UNSUPPORTED ? 1 : 0; 1078 - 1079 - if (link->replay_settings.config.alpm_mode == DC_ALPM_AUXLESS) { 1080 - alpm_config.bits.ALPM_MODE_SEL = 1; 1081 - alpm_config.bits.ACDS_PERIOD_DURATION = 1; 1082 - } 1083 - 1084 - dm_helpers_dp_write_dpcd( 1085 - link->ctx, 1086 - link, 1087 - DP_RECEIVER_ALPM_CONFIG, 1088 - &alpm_config.raw, 1089 - sizeof(alpm_config.raw)); 1090 - } 1091 - 1092 - return true; 1093 - } 1094 - 1095 - static bool edp_setup_freesync_replay(struct dc_link *link, const struct dc_stream_state *stream) 1007 + bool edp_setup_freesync_replay(struct dc_link *link, const struct dc_stream_state *stream) 1096 1008 { 1097 1009 /* To-do: Setup Replay */ 1098 1010 struct dc *dc; ··· 1080 1208 return true; 1081 1209 } 1082 1210 1083 - bool edp_setup_replay(struct dc_link *link, const struct dc_stream_state *stream) 1084 - { 1085 - if (!link) 1086 - return false; 1087 - if (link->replay_settings.config.replay_version == DC_VESA_PANEL_REPLAY) 1088 - return edp_setup_panel_replay(link, stream); 1089 - else if (link->replay_settings.config.replay_version == DC_FREESYNC_REPLAY) 1090 - return edp_setup_freesync_replay(link, stream); 1091 - else 1092 - return false; 1093 - } 1094 1211 1095 1212 /* 1096 1213 * This is general Interface for Replay to set an 32 bit variable to dmub ··· 1184 1323 return true; 1185 1324 } 1186 1325 1187 - bool edp_pr_enable(struct dc_link *link, bool enable) 1188 - { 1189 - struct dc *dc = link->ctx->dc; 1190 - unsigned int panel_inst = 0; 1191 - union dmub_rb_cmd cmd; 1192 - 1193 - if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst)) 1194 - return false; 1195 - 1196 - if (link->replay_settings.replay_allow_active != enable) { 1197 - //for sending PR enable commands to DMUB 1198 - memset(&cmd, 0, sizeof(cmd)); 1199 - 1200 - cmd.pr_enable.header.type = DMUB_CMD__PR; 1201 - cmd.pr_enable.header.sub_type = DMUB_CMD__PR_ENABLE; 1202 - cmd.pr_enable.header.payload_bytes = sizeof(struct dmub_cmd_pr_enable_data); 1203 - cmd.pr_enable.data.panel_inst = panel_inst; 1204 - cmd.pr_enable.data.enable = enable ? 1 : 0; 1205 - 1206 - dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 1207 - 1208 - link->replay_settings.replay_allow_active = enable; 1209 - } 1210 - return true; 1211 - } 1212 - 1213 - bool edp_pr_copy_settings(struct dc_link *link, struct replay_context *replay_context) 1214 - { 1215 - struct dc *dc = link->ctx->dc; 1216 - unsigned int panel_inst = 0; 1217 - union dmub_rb_cmd cmd; 1218 - struct pipe_ctx *pipe_ctx = NULL; 1219 - 1220 - if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst)) 1221 - return false; 1222 - 1223 - for (unsigned int i = 0; i < MAX_PIPES; i++) { 1224 - if (dc->current_state->res_ctx.pipe_ctx[i].stream && 1225 - dc->current_state->res_ctx.pipe_ctx[i].stream->link && 1226 - dc->current_state->res_ctx.pipe_ctx[i].stream->link == link && 1227 - dc->current_state->res_ctx.pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) { 1228 - pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 1229 - //TODO: refactor for multi edp support 1230 - break; 1231 - } 1232 - } 1233 - 1234 - if (!pipe_ctx) 1235 - return false; 1236 - 1237 - memset(&cmd, 0, sizeof(cmd)); 1238 - cmd.pr_copy_settings.header.type = DMUB_CMD__PR; 1239 - cmd.pr_copy_settings.header.sub_type = DMUB_CMD__PR_COPY_SETTINGS; 1240 - cmd.pr_copy_settings.header.payload_bytes = sizeof(struct dmub_cmd_pr_copy_settings_data); 1241 - cmd.pr_copy_settings.data.panel_inst = panel_inst; 1242 - // HW inst 1243 - cmd.pr_copy_settings.data.aux_inst = replay_context->aux_inst; 1244 - cmd.pr_copy_settings.data.digbe_inst = replay_context->digbe_inst; 1245 - cmd.pr_copy_settings.data.digfe_inst = replay_context->digfe_inst; 1246 - if (pipe_ctx->plane_res.dpp) 1247 - cmd.pr_copy_settings.data.dpp_inst = pipe_ctx->plane_res.dpp->inst; 1248 - else 1249 - cmd.pr_copy_settings.data.dpp_inst = 0; 1250 - if (pipe_ctx->stream_res.tg) 1251 - cmd.pr_copy_settings.data.otg_inst = pipe_ctx->stream_res.tg->inst; 1252 - else 1253 - cmd.pr_copy_settings.data.otg_inst = 0; 1254 - 1255 - cmd.pr_copy_settings.data.dpphy_inst = link->link_enc->transmitter; 1256 - 1257 - cmd.pr_copy_settings.data.line_time_in_ns = replay_context->line_time_in_ns; 1258 - cmd.pr_copy_settings.data.flags.bitfields.fec_enable_status = (link->fec_state == dc_link_fec_enabled); 1259 - cmd.pr_copy_settings.data.flags.bitfields.dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1); 1260 - cmd.pr_copy_settings.data.debug.u32All = link->replay_settings.config.debug_flags; 1261 - 1262 - dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 1263 - return true; 1264 - } 1265 - 1266 - bool edp_pr_update_state(struct dc_link *link, struct dmub_cmd_pr_update_state_data *update_state_data) 1267 - { 1268 - struct dc *dc = link->ctx->dc; 1269 - unsigned int panel_inst = 0; 1270 - union dmub_rb_cmd cmd; 1271 - 1272 - if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst)) 1273 - return false; 1274 - 1275 - memset(&cmd, 0, sizeof(cmd)); 1276 - cmd.pr_update_state.header.type = DMUB_CMD__PR; 1277 - cmd.pr_update_state.header.sub_type = DMUB_CMD__PR_UPDATE_STATE; 1278 - cmd.pr_update_state.header.payload_bytes = sizeof(struct dmub_cmd_pr_update_state_data); 1279 - cmd.pr_update_state.data.panel_inst = panel_inst; 1280 - 1281 - memcpy(&cmd.pr_update_state.data, update_state_data, sizeof(struct dmub_cmd_pr_update_state_data)); 1282 - 1283 - dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 1284 - return true; 1285 - } 1286 - 1287 - bool edp_pr_set_general_cmd(struct dc_link *link, struct dmub_cmd_pr_general_cmd_data *general_cmd_data) 1288 - { 1289 - struct dc *dc = link->ctx->dc; 1290 - unsigned int panel_inst = 0; 1291 - union dmub_rb_cmd cmd; 1292 - 1293 - if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst)) 1294 - return false; 1295 - 1296 - memset(&cmd, 0, sizeof(cmd)); 1297 - cmd.pr_general_cmd.header.type = DMUB_CMD__PR; 1298 - cmd.pr_general_cmd.header.sub_type = DMUB_CMD__PR_GENERAL_CMD; 1299 - cmd.pr_general_cmd.header.payload_bytes = sizeof(struct dmub_cmd_pr_general_cmd_data); 1300 - cmd.pr_general_cmd.data.panel_inst = panel_inst; 1301 - 1302 - memcpy(&cmd.pr_general_cmd.data, general_cmd_data, sizeof(struct dmub_cmd_pr_general_cmd_data)); 1303 - 1304 - dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 1305 - return true; 1306 - } 1307 - 1308 - bool edp_pr_get_state(const struct dc_link *link, uint64_t *state) 1309 - { 1310 - const struct dc *dc = link->ctx->dc; 1311 - unsigned int panel_inst = 0; 1312 - uint32_t retry_count = 0; 1313 - uint32_t replay_state = 0; 1314 - 1315 - if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst)) 1316 - return false; 1317 - 1318 - do { 1319 - // Send gpint command and wait for ack 1320 - if (!dc_wake_and_execute_gpint(dc->ctx, DMUB_GPINT__GET_REPLAY_STATE, panel_inst, 1321 - &replay_state, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) { 1322 - // Return invalid state when GPINT times out 1323 - replay_state = PR_STATE_INVALID; 1324 - } 1325 - /* Copy 32-bit result into 64-bit output */ 1326 - *state = replay_state; 1327 - } while (++retry_count <= 1000 && *state == PR_STATE_INVALID); 1328 - 1329 - // Assert if max retry hit 1330 - if (retry_count >= 1000 && *state == PR_STATE_INVALID) { 1331 - ASSERT(0); 1332 - /* To-do: Add retry fail log */ 1333 - } 1334 - 1335 - return true; 1336 - } 1337 1326 1338 1327 static struct abm *get_abm_from_stream_res(const struct dc_link *link) 1339 1328 {

+2 -8

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h

··· 29 29 30 30 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link); 31 31 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode); 32 - bool set_default_brightness(struct dc_link *link); 32 + bool set_default_brightness_aux(struct dc_link *link); 33 33 bool is_smartmux_suported(struct dc_link *link); 34 34 void edp_panel_backlight_power_on(struct dc_link *link, bool wait_for_hpd); 35 35 int edp_get_backlight_level(const struct dc_link *link); ··· 54 54 void edp_get_psr_residency(const struct dc_link *link, uint32_t *residency, enum psr_residency_mode mode); 55 55 bool edp_set_replay_allow_active(struct dc_link *dc_link, const bool *enable, 56 56 bool wait, bool force_static, const unsigned int *power_opts); 57 - bool edp_setup_replay(struct dc_link *link, 58 - const struct dc_stream_state *stream); 59 57 bool edp_send_replay_cmd(struct dc_link *link, 60 58 enum replay_FW_Message_type msg, 61 59 union dmub_replay_cmd_set *cmd_data); ··· 73 75 bool edp_receiver_ready_T9(struct dc_link *link); 74 76 bool edp_receiver_ready_T7(struct dc_link *link); 75 77 bool edp_power_alpm_dpcd_enable(struct dc_link *link, bool enable); 76 - bool edp_pr_enable(struct dc_link *link, bool enable); 77 - bool edp_pr_copy_settings(struct dc_link *link, struct replay_context *replay_context); 78 - bool edp_pr_update_state(struct dc_link *link, struct dmub_cmd_pr_update_state_data *update_state_data); 79 - bool edp_pr_set_general_cmd(struct dc_link *link, struct dmub_cmd_pr_general_cmd_data *general_cmd_data); 80 - bool edp_pr_get_state(const struct dc_link *link, uint64_t *state); 78 + bool edp_setup_freesync_replay(struct dc_link *link, const struct dc_stream_state *stream); 81 79 void edp_set_panel_power(struct dc_link *link, bool powerOn); 82 80 void edp_set_panel_assr(struct dc_link *link, struct pipe_ctx *pipe_ctx, 83 81 enum dp_panel_mode *panel_mode, bool enable);

+7 -4

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

··· 2250 2250 int i; 2251 2251 2252 2252 #if defined(CONFIG_DRM_AMD_DC_FP) 2253 - for (i = 0; i < state->stream_count; i++) 2254 - if (state->streams[i] && state->streams[i]->link && state->streams[i]->link == link) 2255 - link->dc->hwss.calculate_pix_rate_divider((struct dc *)link->dc, state, state->streams[i]); 2253 + if (link->dc->hwss.calculate_pix_rate_divider) { 2254 + for (i = 0; i < state->stream_count; i++) 2255 + if (state->streams[i] && state->streams[i]->link && state->streams[i]->link == link) 2256 + link->dc->hwss.calculate_pix_rate_divider((struct dc *)link->dc, state, state->streams[i]); 2257 + } 2256 2258 2257 2259 for (i = 0; i < pipe_count; i++) { 2258 - link->dc->res_pool->funcs->build_pipe_pix_clk_params(&pipes[i]); 2260 + if (link->dc->res_pool->funcs->build_pipe_pix_clk_params) 2261 + link->dc->res_pool->funcs->build_pipe_pix_clk_params(&pipes[i]); 2259 2262 2260 2263 // Setup audio 2261 2264 if (pipes[i].stream_res.audio != NULL)

+6 -48

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

··· 1091 1091 uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */ 1092 1092 uint32_t override_hbr3_pll_vco: 1; /**< 1 to override the hbr3 pll vco to 0 */ 1093 1093 uint32_t disable_dpia_bw_allocation: 1; /**< 1 to disable the USB4 DPIA BW allocation */ 1094 - uint32_t reserved : 4; /**< reserved */ 1094 + uint32_t bootcrc_en_at_preos: 1; /**< 1 to run the boot time crc during warm/cold boot*/ 1095 + uint32_t bootcrc_en_at_S0i3: 1; /**< 1 to run the boot time crc during S0i3 boot*/ 1096 + uint32_t bootcrc_boot_mode: 1; /**< 1 for S0i3 resume and 0 for Warm/cold boot*/ 1097 + uint32_t reserved : 1; /**< reserved */ 1095 1098 } bits; /**< boot bits */ 1096 1099 uint32_t all; /**< 32-bit access to bits */ 1097 1100 }; ··· 2641 2638 uint32_t enable_visual_confirm: 1; 2642 2639 uint32_t allow_delay_check_mode: 2; 2643 2640 uint32_t legacy_method_no_fams2 : 1; 2644 - uint32_t reserved: 23; 2641 + uint32_t reserved : 23; 2645 2642 } bits; 2646 2643 uint32_t all; 2647 2644 }; ··· 4338 4335 */ 4339 4336 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8, 4340 4337 /** 4341 - * Set version 4342 - */ 4343 - DMUB_CMD__REPLAY_SET_VERSION = 9, 4344 - /** 4345 4338 * Set Replay General command. 4346 4339 */ 4347 4340 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16, ··· 4378 4379 REPLAY_GENERAL_CMD_UPDATE_ERROR_STATUS, 4379 4380 REPLAY_GENERAL_CMD_SET_LOW_RR_ACTIVATE, 4380 4381 REPLAY_GENERAL_CMD_VIDEO_CONFERENCING, 4382 + REPLAY_GENERAL_CMD_SET_CONTINUOUSLY_RESYNC, 4381 4383 }; 4382 4384 4383 4385 struct dmub_alpm_auxless_data { ··· 4503 4503 * Replay not supported. 4504 4504 */ 4505 4505 REPLAY_VERSION_UNSUPPORTED = 0xFF, 4506 - }; 4507 - 4508 - /** 4509 - * Data passed from driver to FW in a DMUB_CMD___SET_REPLAY_VERSION command. 4510 - */ 4511 - struct dmub_cmd_replay_set_version_data { 4512 - /** 4513 - * Panel Instance. 4514 - * Panel instance to identify which psr_state to use 4515 - * Currently the support is only for 0 or 1 4516 - */ 4517 - uint8_t panel_inst; 4518 - /** 4519 - * Replay version that FW should implement. 4520 - */ 4521 - enum replay_version version; 4522 - /** 4523 - * Explicit padding to 4 byte boundary. 4524 - */ 4525 - uint8_t pad[3]; 4526 - }; 4527 - 4528 - /** 4529 - * Definition of a DMUB_CMD__REPLAY_SET_VERSION command. 4530 - */ 4531 - struct dmub_rb_cmd_replay_set_version { 4532 - /** 4533 - * Command header. 4534 - */ 4535 - struct dmub_cmd_header header; 4536 - /** 4537 - * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_VERSION command. 4538 - */ 4539 - struct dmub_cmd_replay_set_version_data replay_set_version_data; 4540 4506 }; 4541 4507 4542 4508 /** ··· 4895 4929 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data. 4896 4930 */ 4897 4931 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data; 4898 - /** 4899 - * Definition of DMUB_CMD__REPLAY_SET_VERSION command data. 4900 - */ 4901 - struct dmub_cmd_replay_set_version_data version_data; 4902 4932 /** 4903 4933 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data. 4904 4934 */ ··· 6982 7020 * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 6983 7021 */ 6984 7022 struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state; 6985 - /** 6986 - * Definition of a DMUB_CMD__REPLAY_SET_VERSION command. 6987 - */ 6988 - struct dmub_rb_cmd_replay_set_version replay_set_version; 6989 7023 /* 6990 7024 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 6991 7025 */

+30

drivers/gpu/drm/amd/display/include/dpcd_defs.h

··· 37 37 #ifndef DP_PANEL_REPLAY_CAPABILITY // can remove this once the define gets into linux drm_dp_helper.h 38 38 #define DP_PANEL_REPLAY_CAPABILITY 0x0b1 39 39 #endif /* DP_PANEL_REPLAY_CAPABILITY */ 40 + #ifndef DP_PR_SU_X_GRANULARITY_LOW // can remove this once the define gets into linux drm_dp_helper.h 41 + #define DP_PR_SU_X_GRANULARITY_LOW 0x0b2 42 + #endif /* DP_PR_SU_X_GRANULARITY_LOW */ 43 + #ifndef DP_PR_SU_X_GRANULARITY_HIGH // can remove this once the define gets into linux drm_dp_helper.h 44 + #define DP_PR_SU_X_GRANULARITY_HIGH 0x0b3 45 + #endif /* DP_PR_SU_X_GRANULARITY_HIGH */ 46 + #ifndef DP_PR_SU_Y_GRANULARITY // can remove this once the define gets into linux drm_dp_helper.h 47 + #define DP_PR_SU_Y_GRANULARITY 0x0b4 48 + #endif /* DP_PR_SU_Y_GRANULARITY */ 49 + #ifndef DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_LOW // can remove this once the define gets into linux drm_dp_helper.h 50 + #define DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_LOW 0x0b5 51 + #endif /* DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_LOW */ 52 + #ifndef DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_HIGH // can remove this once the define gets into linux drm_dp_helper.h 53 + #define DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_HIGH 0x0b6 54 + #endif /* DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_HIGH */ 40 55 #ifndef DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1 // can remove this once the define gets into linux drm_dp_helper.h 41 56 #define DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1 0x1b0 42 57 #endif /* DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1 */ ··· 61 46 #ifndef DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2 // can remove this once the define gets into linux drm_dp_helper.h 62 47 #define DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2 0x1b1 63 48 #endif /* DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2 */ 49 + #ifndef DP_PR_ERROR_STATUS // can remove this once the define gets into linux drm_dp_helper.h 50 + #define DP_PR_ERROR_STATUS 0x2020 /* DP 2.0 */ 51 + #endif /* DP_PR_ERROR_STATUS */ 52 + #ifndef DP_PR_LINK_CRC_ERROR // can remove this once the define gets into linux drm_dp_helper.h 53 + #define DP_PR_LINK_CRC_ERROR (1 << 0) 54 + #endif /* DP_PR_LINK_CRC_ERROR */ 55 + #ifndef DP_PR_RFB_STORAGE_ERROR // can remove this once the define gets into linux drm_dp_helper.h 56 + #define DP_PR_RFB_STORAGE_ERROR (1 << 1) 57 + #endif /* DP_PR_RFB_STORAGE_ERROR */ 58 + #ifndef DP_PR_VSC_SDP_UNCORRECTABLE_ERROR // can remove this once the define gets into linux drm_dp_helper.h 59 + #define DP_PR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */ 60 + #endif /* DP_PR_VSC_SDP_UNCORRECTABLE_ERROR */ 61 + #ifndef DP_PR_ASSDP_MISSING_ERROR // can remove this once the define gets into linux drm_dp_helper.h 62 + #define DP_PR_ASSDP_MISSING_ERROR (1 << 3) /* eDP 1.5 */ 63 + #endif /* DP_PR_ASSDP_MISSING_ERROR */ 64 64 65 65 enum dpcd_revision { 66 66 DPCD_REV_10 = 0x10,

-2

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

··· 826 826 smu->user_dpm_profile.fan_mode = -1; 827 827 smu->power_profile_mode = PP_SMC_POWER_PROFILE_UNKNOWN; 828 828 829 - mutex_init(&smu->message_lock); 830 - 831 829 adev->powerplay.pp_handle = smu; 832 830 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 833 831

+83 -37

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

··· 551 551 int map_to; 552 552 }; 553 553 554 + #define SMU_MSG_MAX_ARGS 4 555 + 556 + /* Message flags for smu_msg_args */ 557 + #define SMU_MSG_FLAG_ASYNC BIT(0) /* Async send - skip post-poll */ 558 + #define SMU_MSG_FLAG_LOCK_HELD BIT(1) /* Caller holds ctl->lock */ 559 + 560 + /* smu_msg_ctl flags */ 561 + #define SMU_MSG_CTL_DEBUG_MAILBOX BIT(0) /* Debug mailbox supported */ 562 + 563 + struct smu_msg_ctl; 564 + /** 565 + * struct smu_msg_config - IP-level register configuration 566 + * @msg_reg: Message register offset 567 + * @resp_reg: Response register offset 568 + * @arg_regs: Argument register offsets (up to SMU_MSG_MAX_ARGS) 569 + * @num_arg_regs: Number of argument registers available 570 + * @debug_msg_reg: Debug message register offset 571 + * @debug_resp_reg: Debug response register offset 572 + * @debug_param_reg: Debug parameter register offset 573 + */ 574 + struct smu_msg_config { 575 + u32 msg_reg; 576 + u32 resp_reg; 577 + u32 arg_regs[SMU_MSG_MAX_ARGS]; 578 + int num_arg_regs; 579 + u32 debug_msg_reg; 580 + u32 debug_resp_reg; 581 + u32 debug_param_reg; 582 + }; 583 + 584 + /** 585 + * struct smu_msg_args - Per-call message arguments 586 + * @msg: Common message type (enum smu_message_type) 587 + * @args: Input arguments 588 + * @num_args: Number of input arguments 589 + * @out_args: Output arguments (filled after successful send) 590 + * @num_out_args: Number of output arguments to read 591 + * @flags: Message flags (SMU_MSG_FLAG_*) 592 + * @timeout: Per-message timeout in us (0 = use default) 593 + */ 594 + struct smu_msg_args { 595 + enum smu_message_type msg; 596 + u32 args[SMU_MSG_MAX_ARGS]; 597 + int num_args; 598 + u32 out_args[SMU_MSG_MAX_ARGS]; 599 + int num_out_args; 600 + u32 flags; 601 + u32 timeout; 602 + }; 603 + 604 + /** 605 + * struct smu_msg_ops - IP-level protocol operations 606 + * @send_msg: send message protocol 607 + * @wait_response: wait for response (for split send/wait cases) 608 + * @decode_response: Convert response register value to errno 609 + * @send_debug_msg: send debug message 610 + */ 611 + struct smu_msg_ops { 612 + int (*send_msg)(struct smu_msg_ctl *ctl, struct smu_msg_args *args); 613 + int (*wait_response)(struct smu_msg_ctl *ctl, u32 timeout_us); 614 + int (*decode_response)(u32 resp); 615 + int (*send_debug_msg)(struct smu_msg_ctl *ctl, u32 msg, u32 param); 616 + }; 617 + 618 + /** 619 + * struct smu_msg_ctl - Per-device message control block 620 + * This is a standalone control block that encapsulates everything 621 + * needed for SMU messaging. The ops->send_msg implements the complete 622 + * protocol including all filtering and error handling. 623 + */ 624 + struct smu_msg_ctl { 625 + struct smu_context *smu; 626 + struct mutex lock; 627 + struct smu_msg_config config; 628 + const struct smu_msg_ops *ops; 629 + const struct cmn2asic_msg_mapping *message_map; 630 + u32 default_timeout; 631 + u32 flags; 632 + }; 633 + 554 634 struct stb_context { 555 635 uint32_t stb_buf_size; 556 636 bool enabled; ··· 667 587 struct amdgpu_irq_src irq_source; 668 588 669 589 const struct pptable_funcs *ppt_funcs; 670 - const struct cmn2asic_msg_mapping *message_map; 671 590 const struct cmn2asic_mapping *clock_map; 672 591 const struct cmn2asic_mapping *feature_map; 673 592 const struct cmn2asic_mapping *table_map; 674 593 const struct cmn2asic_mapping *pwr_src_map; 675 594 const struct cmn2asic_mapping *workload_map; 676 - struct mutex message_lock; 677 595 uint64_t pool_size; 678 596 679 597 struct smu_table_context smu_table; ··· 755 677 756 678 struct firmware pptable_firmware; 757 679 758 - u32 param_reg; 759 - u32 msg_reg; 760 - u32 resp_reg; 761 - 762 - u32 debug_param_reg; 763 - u32 debug_msg_reg; 764 - u32 debug_resp_reg; 765 - 766 680 struct delayed_work swctf_delayed_work; 767 681 768 682 /* data structures for wbrf feature support */ 769 683 bool wbrf_supported; 770 684 struct notifier_block wbrf_notifier; 771 685 struct delayed_work wbrf_delayed_work; 686 + 687 + /* SMU message control block */ 688 + struct smu_msg_ctl msg_ctl; 772 689 }; 773 690 774 691 struct i2c_adapter; ··· 828 755 * defaults. 829 756 */ 830 757 int (*populate_umd_state_clk)(struct smu_context *smu); 831 - 832 - /** 833 - * @print_clk_levels: Print DPM clock levels for a clock domain 834 - * to buffer. Star current level. 835 - * 836 - * Used for sysfs interfaces. 837 - * Return: Number of characters written to the buffer 838 - */ 839 - int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf); 840 758 841 759 /** 842 760 * @emit_clk_levels: Print DPM clock levels for a clock domain ··· 1185 1121 * @system_features_control: Enable/disable all SMU features. 1186 1122 */ 1187 1123 int (*system_features_control)(struct smu_context *smu, bool en); 1188 - 1189 - /** 1190 - * @send_smc_msg_with_param: Send a message with a parameter to the SMU. 1191 - * &msg: Type of message. 1192 - * &param: Message parameter. 1193 - * &read_arg: SMU response (optional). 1194 - */ 1195 - int (*send_smc_msg_with_param)(struct smu_context *smu, 1196 - enum smu_message_type msg, uint32_t param, uint32_t *read_arg); 1197 - 1198 - /** 1199 - * @send_smc_msg: Send a message to the SMU. 1200 - * &msg: Type of message. 1201 - * &read_arg: SMU response (optional). 1202 - */ 1203 - int (*send_smc_msg)(struct smu_context *smu, 1204 - enum smu_message_type msg, 1205 - uint32_t *read_arg); 1206 1124 1207 1125 /** 1208 1126 * @init_display_count: Notify the SMU of the number of display

+2 -1

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h

··· 282 282 283 283 int smu_v11_0_restore_user_od_settings(struct smu_context *smu); 284 284 285 - void smu_v11_0_set_smu_mailbox_registers(struct smu_context *smu); 285 + void smu_v11_0_init_msg_ctl(struct smu_context *smu, 286 + const struct cmn2asic_msg_mapping *message_map); 286 287 287 288 #endif 288 289 #endif

+3

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v12_0.h

··· 62 62 63 63 int smu_v12_0_get_vbios_bootup_values(struct smu_context *smu); 64 64 65 + void smu_v12_0_init_msg_ctl(struct smu_context *smu, 66 + const struct cmn2asic_msg_mapping *message_map); 67 + 65 68 #endif 66 69 #endif

+2 -1

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h

··· 251 251 252 252 int smu_v13_0_set_default_dpm_tables(struct smu_context *smu); 253 253 254 - void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu); 254 + void smu_v13_0_init_msg_ctl(struct smu_context *smu, 255 + const struct cmn2asic_msg_mapping *message_map); 255 256 256 257 int smu_v13_0_mode1_reset(struct smu_context *smu); 257 258

+2 -4

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h

··· 215 215 uint32_t pptable_id); 216 216 217 217 int smu_v14_0_od_edit_dpm_table(struct smu_context *smu, 218 - enum PP_OD_DPM_TABLE_COMMAND type, 219 - long input[], uint32_t size); 220 - 221 - void smu_v14_0_set_smu_mailbox_registers(struct smu_context *smu); 218 + enum PP_OD_DPM_TABLE_COMMAND type, 219 + long input[], uint32_t size); 222 220 223 221 int smu_v14_0_enable_thermal_alert(struct smu_context *smu); 224 222

-2

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h

··· 237 237 enum PP_OD_DPM_TABLE_COMMAND type, 238 238 long input[], uint32_t size); 239 239 240 - void smu_v15_0_set_smu_mailbox_registers(struct smu_context *smu); 241 - 242 240 int smu_v15_0_enable_thermal_alert(struct smu_context *smu); 243 241 244 242 int smu_v15_0_disable_thermal_alert(struct smu_context *smu);

+1 -4

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

··· 1915 1915 .set_tool_table_location = smu_v11_0_set_tool_table_location, 1916 1916 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 1917 1917 .system_features_control = smu_v11_0_system_features_control, 1918 - .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 1919 - .send_smc_msg = smu_cmn_send_smc_msg, 1920 1918 .init_display_count = NULL, 1921 1919 .set_allowed_mask = smu_v11_0_set_allowed_mask, 1922 1920 .get_enabled_mask = smu_cmn_get_enabled_mask, ··· 1957 1959 void arcturus_set_ppt_funcs(struct smu_context *smu) 1958 1960 { 1959 1961 smu->ppt_funcs = &arcturus_ppt_funcs; 1960 - smu->message_map = arcturus_message_map; 1961 1962 smu->clock_map = arcturus_clk_map; 1962 1963 smu->feature_map = arcturus_feature_mask_map; 1963 1964 smu->table_map = arcturus_table_map; 1964 1965 smu->pwr_src_map = arcturus_pwr_src_map; 1965 1966 smu->workload_map = arcturus_workload_map; 1966 - smu_v11_0_set_smu_mailbox_registers(smu); 1967 + smu_v11_0_init_msg_ctl(smu, arcturus_message_map); 1967 1968 }

+1 -4

drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

··· 592 592 .get_dpm_ultimate_freq = cyan_skillfish_get_dpm_ultimate_freq, 593 593 .register_irq_handler = smu_v11_0_register_irq_handler, 594 594 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 595 - .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 596 - .send_smc_msg = smu_cmn_send_smc_msg, 597 595 .set_driver_table_location = smu_v11_0_set_driver_table_location, 598 596 .interrupt_work = smu_v11_0_interrupt_work, 599 597 }; ··· 599 601 void cyan_skillfish_set_ppt_funcs(struct smu_context *smu) 600 602 { 601 603 smu->ppt_funcs = &cyan_skillfish_ppt_funcs; 602 - smu->message_map = cyan_skillfish_message_map; 603 604 smu->table_map = cyan_skillfish_table_map; 604 605 smu->is_apu = true; 605 - smu_v11_0_set_smu_mailbox_registers(smu); 606 + smu_v11_0_init_msg_ctl(smu, cyan_skillfish_message_map); 606 607 }

+1 -4

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

··· 3319 3319 .set_tool_table_location = smu_v11_0_set_tool_table_location, 3320 3320 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 3321 3321 .system_features_control = smu_v11_0_system_features_control, 3322 - .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 3323 - .send_smc_msg = smu_cmn_send_smc_msg, 3324 3322 .init_display_count = smu_v11_0_init_display_count, 3325 3323 .set_allowed_mask = smu_v11_0_set_allowed_mask, 3326 3324 .get_enabled_mask = smu_cmn_get_enabled_mask, ··· 3367 3369 void navi10_set_ppt_funcs(struct smu_context *smu) 3368 3370 { 3369 3371 smu->ppt_funcs = &navi10_ppt_funcs; 3370 - smu->message_map = navi10_message_map; 3371 3372 smu->clock_map = navi10_clk_map; 3372 3373 smu->feature_map = navi10_feature_mask_map; 3373 3374 smu->table_map = navi10_table_map; 3374 3375 smu->pwr_src_map = navi10_pwr_src_map; 3375 3376 smu->workload_map = navi10_workload_map; 3376 - smu_v11_0_set_smu_mailbox_registers(smu); 3377 + smu_v11_0_init_msg_ctl(smu, navi10_message_map); 3377 3378 }

+12 -15

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

··· 3043 3043 3044 3044 static int sienna_cichlid_mode2_reset(struct smu_context *smu) 3045 3045 { 3046 - int ret = 0, index; 3046 + struct smu_msg_ctl *ctl = &smu->msg_ctl; 3047 3047 struct amdgpu_device *adev = smu->adev; 3048 + int ret = 0; 3048 3049 int timeout = 100; 3049 3050 3050 - index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 3051 - SMU_MSG_DriverMode2Reset); 3051 + mutex_lock(&ctl->lock); 3052 3052 3053 - mutex_lock(&smu->message_lock); 3053 + ret = smu_msg_send_async_locked(ctl, SMU_MSG_DriverMode2Reset, 3054 + SMU_RESET_MODE_2); 3055 + if (ret) 3056 + goto out; 3054 3057 3055 - ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, 3056 - SMU_RESET_MODE_2); 3057 - 3058 - ret = smu_cmn_wait_for_response(smu); 3058 + ret = smu_msg_wait_response(ctl, 0); 3059 3059 while (ret != 0 && timeout) { 3060 - ret = smu_cmn_wait_for_response(smu); 3060 + ret = smu_msg_wait_response(ctl, 0); 3061 3061 /* Wait a bit more time for getting ACK */ 3062 3062 if (ret != 0) { 3063 3063 --timeout; ··· 3075 3075 goto out; 3076 3076 } 3077 3077 3078 - dev_info(smu->adev->dev, "restore config space...\n"); 3078 + dev_info(adev->dev, "restore config space...\n"); 3079 3079 /* Restore the config space saved during init */ 3080 3080 amdgpu_device_load_pci_state(adev->pdev); 3081 3081 out: 3082 - mutex_unlock(&smu->message_lock); 3082 + mutex_unlock(&ctl->lock); 3083 3083 3084 3084 return ret; 3085 3085 } ··· 3126 3126 .set_tool_table_location = smu_v11_0_set_tool_table_location, 3127 3127 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 3128 3128 .system_features_control = sienna_cichlid_system_features_control, 3129 - .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 3130 - .send_smc_msg = smu_cmn_send_smc_msg, 3131 3129 .init_display_count = NULL, 3132 3130 .set_allowed_mask = smu_v11_0_set_allowed_mask, 3133 3131 .get_enabled_mask = smu_cmn_get_enabled_mask, ··· 3180 3182 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu) 3181 3183 { 3182 3184 smu->ppt_funcs = &sienna_cichlid_ppt_funcs; 3183 - smu->message_map = sienna_cichlid_message_map; 3184 3185 smu->clock_map = sienna_cichlid_clk_map; 3185 3186 smu->feature_map = sienna_cichlid_feature_mask_map; 3186 3187 smu->table_map = sienna_cichlid_table_map; 3187 3188 smu->pwr_src_map = sienna_cichlid_pwr_src_map; 3188 3189 smu->workload_map = sienna_cichlid_workload_map; 3189 - smu_v11_0_set_smu_mailbox_registers(smu); 3190 + smu_v11_0_init_msg_ctl(smu, sienna_cichlid_message_map); 3190 3191 }

+12 -4

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

··· 2168 2168 return ret; 2169 2169 } 2170 2170 2171 - void smu_v11_0_set_smu_mailbox_registers(struct smu_context *smu) 2171 + void smu_v11_0_init_msg_ctl(struct smu_context *smu, 2172 + const struct cmn2asic_msg_mapping *message_map) 2172 2173 { 2173 2174 struct amdgpu_device *adev = smu->adev; 2175 + struct smu_msg_ctl *ctl = &smu->msg_ctl; 2174 2176 2175 - smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); 2176 - smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); 2177 - smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); 2177 + ctl->smu = smu; 2178 + mutex_init(&ctl->lock); 2179 + ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); 2180 + ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); 2181 + ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); 2182 + ctl->config.num_arg_regs = 1; 2183 + ctl->ops = &smu_msg_v1_ops; 2184 + ctl->default_timeout = adev->usec_timeout * 20; 2185 + ctl->message_map = message_map; 2178 2186 }

+6 -15

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

··· 2272 2272 2273 2273 static int vangogh_mode_reset(struct smu_context *smu, int type) 2274 2274 { 2275 - int ret = 0, index = 0; 2275 + struct smu_msg_ctl *ctl = &smu->msg_ctl; 2276 + int ret; 2276 2277 2277 - index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 2278 - SMU_MSG_GfxDeviceDriverReset); 2279 - if (index < 0) 2280 - return index == -EACCES ? 0 : index; 2281 - 2282 - mutex_lock(&smu->message_lock); 2283 - 2284 - ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type); 2285 - 2286 - mutex_unlock(&smu->message_lock); 2278 + mutex_lock(&ctl->lock); 2279 + ret = smu_msg_send_async_locked(ctl, SMU_MSG_GfxDeviceDriverReset, type); 2280 + mutex_unlock(&ctl->lock); 2287 2281 2288 2282 mdelay(10); 2289 2283 ··· 2516 2522 .fini_power = smu_v11_0_fini_power, 2517 2523 .register_irq_handler = smu_v11_0_register_irq_handler, 2518 2524 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 2519 - .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 2520 - .send_smc_msg = smu_cmn_send_smc_msg, 2521 2525 .dpm_set_vcn_enable = vangogh_dpm_set_vcn_enable, 2522 2526 .dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable, 2523 2527 .is_dpm_running = vangogh_is_dpm_running, ··· 2555 2563 void vangogh_set_ppt_funcs(struct smu_context *smu) 2556 2564 { 2557 2565 smu->ppt_funcs = &vangogh_ppt_funcs; 2558 - smu->message_map = vangogh_message_map; 2559 2566 smu->feature_map = vangogh_feature_mask_map; 2560 2567 smu->table_map = vangogh_table_map; 2561 2568 smu->workload_map = vangogh_workload_map; 2562 2569 smu->is_apu = true; 2563 - smu_v11_0_set_smu_mailbox_registers(smu); 2570 + smu_v11_0_init_msg_ctl(smu, vangogh_message_map); 2564 2571 }

+1 -17

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

··· 41 41 #undef pr_info 42 42 #undef pr_debug 43 43 44 - #define mmMP1_SMN_C2PMSG_66 0x0282 45 - #define mmMP1_SMN_C2PMSG_66_BASE_IDX 0 46 - 47 - #define mmMP1_SMN_C2PMSG_82 0x0292 48 - #define mmMP1_SMN_C2PMSG_82_BASE_IDX 0 49 - 50 - #define mmMP1_SMN_C2PMSG_90 0x029a 51 - #define mmMP1_SMN_C2PMSG_90_BASE_IDX 0 52 - 53 44 static struct cmn2asic_msg_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = { 54 45 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 55 46 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), ··· 1459 1468 .check_fw_status = smu_v12_0_check_fw_status, 1460 1469 .check_fw_version = smu_v12_0_check_fw_version, 1461 1470 .powergate_sdma = smu_v12_0_powergate_sdma, 1462 - .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 1463 - .send_smc_msg = smu_cmn_send_smc_msg, 1464 1471 .set_gfx_cgpg = smu_v12_0_set_gfx_cgpg, 1465 1472 .gfx_off_control = smu_v12_0_gfx_off_control, 1466 1473 .get_gfx_off_status = smu_v12_0_get_gfxoff_status, ··· 1484 1495 1485 1496 void renoir_set_ppt_funcs(struct smu_context *smu) 1486 1497 { 1487 - struct amdgpu_device *adev = smu->adev; 1488 - 1489 1498 smu->ppt_funcs = &renoir_ppt_funcs; 1490 - smu->message_map = renoir_message_map; 1491 1499 smu->clock_map = renoir_clk_map; 1492 1500 smu->table_map = renoir_table_map; 1493 1501 smu->workload_map = renoir_workload_map; 1494 1502 smu->smc_driver_if_version = SMU12_DRIVER_IF_VERSION; 1495 1503 smu->is_apu = true; 1496 - smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); 1497 - smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); 1498 - smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); 1504 + smu_v12_0_init_msg_ctl(smu, renoir_message_map); 1499 1505 }

+17

drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c

··· 405 405 406 406 return 0; 407 407 } 408 + 409 + void smu_v12_0_init_msg_ctl(struct smu_context *smu, 410 + const struct cmn2asic_msg_mapping *message_map) 411 + { 412 + struct amdgpu_device *adev = smu->adev; 413 + struct smu_msg_ctl *ctl = &smu->msg_ctl; 414 + 415 + ctl->smu = smu; 416 + mutex_init(&ctl->lock); 417 + ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); 418 + ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); 419 + ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); 420 + ctl->config.num_arg_regs = 1; 421 + ctl->ops = &smu_msg_v1_ops; 422 + ctl->default_timeout = adev->usec_timeout * 20; 423 + ctl->message_map = message_map; 424 + }

+14 -15

drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

··· 1828 1828 1829 1829 static int aldebaran_mode2_reset(struct smu_context *smu) 1830 1830 { 1831 - int ret = 0, index; 1831 + struct smu_msg_ctl *ctl = &smu->msg_ctl; 1832 1832 struct amdgpu_device *adev = smu->adev; 1833 + int ret = 0; 1833 1834 int timeout = 10; 1834 1835 1835 - index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 1836 - SMU_MSG_GfxDeviceDriverReset); 1837 - if (index < 0 ) 1838 - return -EINVAL; 1839 - mutex_lock(&smu->message_lock); 1836 + mutex_lock(&ctl->lock); 1837 + 1840 1838 if (smu->smc_fw_version >= 0x00441400) { 1841 - ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, SMU_RESET_MODE_2); 1839 + ret = smu_msg_send_async_locked(ctl, SMU_MSG_GfxDeviceDriverReset, 1840 + SMU_RESET_MODE_2); 1841 + if (ret) 1842 + goto out; 1843 + 1842 1844 /* This is similar to FLR, wait till max FLR timeout */ 1843 1845 msleep(100); 1844 - dev_dbg(smu->adev->dev, "restore config space...\n"); 1846 + dev_dbg(adev->dev, "restore config space...\n"); 1845 1847 /* Restore the config space saved during init */ 1846 1848 amdgpu_device_load_pci_state(adev->pdev); 1847 1849 1848 - dev_dbg(smu->adev->dev, "wait for reset ack\n"); 1850 + dev_dbg(adev->dev, "wait for reset ack\n"); 1849 1851 while (ret == -ETIME && timeout) { 1850 - ret = smu_cmn_wait_for_response(smu); 1852 + ret = smu_msg_wait_response(ctl, 0); 1851 1853 /* Wait a bit more time for getting ACK */ 1852 1854 if (ret == -ETIME) { 1853 1855 --timeout; ··· 1872 1870 if (ret == 1) 1873 1871 ret = 0; 1874 1872 out: 1875 - mutex_unlock(&smu->message_lock); 1873 + mutex_unlock(&ctl->lock); 1876 1874 1877 1875 return ret; 1878 1876 } ··· 1996 1994 .set_tool_table_location = smu_v13_0_set_tool_table_location, 1997 1995 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location, 1998 1996 .system_features_control = aldebaran_system_features_control, 1999 - .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 2000 - .send_smc_msg = smu_cmn_send_smc_msg, 2001 1997 .get_enabled_mask = smu_cmn_get_enabled_mask, 2002 1998 .feature_is_enabled = smu_cmn_feature_is_enabled, 2003 1999 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, ··· 2032 2032 void aldebaran_set_ppt_funcs(struct smu_context *smu) 2033 2033 { 2034 2034 smu->ppt_funcs = &aldebaran_ppt_funcs; 2035 - smu->message_map = aldebaran_message_map; 2036 2035 smu->clock_map = aldebaran_clk_map; 2037 2036 smu->feature_map = aldebaran_feature_mask_map; 2038 2037 smu->table_map = aldebaran_table_map; 2039 2038 smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE; 2040 - smu_v13_0_set_smu_mailbox_registers(smu); 2039 + smu_v13_0_init_msg_ctl(smu, aldebaran_message_map); 2041 2040 }

+21 -9

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

··· 2244 2244 2245 2245 int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu) 2246 2246 { 2247 - uint16_t index; 2247 + struct smu_msg_ctl *ctl = &smu->msg_ctl; 2248 2248 struct amdgpu_device *adev = smu->adev; 2249 + int ret; 2249 2250 2250 2251 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2251 2252 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableGfxImu, 2252 2253 ENABLE_IMU_ARG_GFXOFF_ENABLE, NULL); 2253 2254 } 2254 2255 2255 - index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 2256 - SMU_MSG_EnableGfxImu); 2257 - return smu_cmn_send_msg_without_waiting(smu, index, 2258 - ENABLE_IMU_ARG_GFXOFF_ENABLE); 2256 + mutex_lock(&ctl->lock); 2257 + ret = smu_msg_send_async_locked(ctl, SMU_MSG_EnableGfxImu, 2258 + ENABLE_IMU_ARG_GFXOFF_ENABLE); 2259 + mutex_unlock(&ctl->lock); 2260 + 2261 + return ret; 2259 2262 } 2260 2263 2261 2264 int smu_v13_0_od_edit_dpm_table(struct smu_context *smu, ··· 2351 2348 smu_table->clocks_table, false); 2352 2349 } 2353 2350 2354 - void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu) 2351 + void smu_v13_0_init_msg_ctl(struct smu_context *smu, 2352 + const struct cmn2asic_msg_mapping *message_map) 2355 2353 { 2356 2354 struct amdgpu_device *adev = smu->adev; 2355 + struct smu_msg_ctl *ctl = &smu->msg_ctl; 2357 2356 2358 - smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); 2359 - smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); 2360 - smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); 2357 + ctl->smu = smu; 2358 + mutex_init(&ctl->lock); 2359 + ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); 2360 + ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); 2361 + ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); 2362 + ctl->config.num_arg_regs = 1; 2363 + ctl->ops = &smu_msg_v1_ops; 2364 + ctl->default_timeout = adev->usec_timeout * 20; 2365 + ctl->message_map = message_map; 2366 + ctl->flags = 0; 2361 2367 } 2362 2368 2363 2369 int smu_v13_0_mode1_reset(struct smu_context *smu)

+9 -18

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

··· 70 70 71 71 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000 72 72 73 - #define mmMP1_SMN_C2PMSG_66 0x0282 74 - #define mmMP1_SMN_C2PMSG_66_BASE_IDX 0 75 - 76 - #define mmMP1_SMN_C2PMSG_82 0x0292 77 - #define mmMP1_SMN_C2PMSG_82_BASE_IDX 0 78 - 79 - #define mmMP1_SMN_C2PMSG_90 0x029a 80 - #define mmMP1_SMN_C2PMSG_90_BASE_IDX 0 81 - 82 73 #define mmMP1_SMN_C2PMSG_75 0x028b 83 74 #define mmMP1_SMN_C2PMSG_75_BASE_IDX 0 84 75 ··· 2882 2891 return -EOPNOTSUPP; 2883 2892 } 2884 2893 2885 - static void smu_v13_0_0_set_smu_mailbox_registers(struct smu_context *smu) 2894 + static void smu_v13_0_0_init_msg_ctl(struct smu_context *smu) 2886 2895 { 2887 2896 struct amdgpu_device *adev = smu->adev; 2897 + struct smu_msg_ctl *ctl = &smu->msg_ctl; 2888 2898 2889 - smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); 2890 - smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); 2891 - smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); 2899 + smu_v13_0_init_msg_ctl(smu, smu_v13_0_0_message_map); 2892 2900 2893 - smu->debug_param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_53); 2894 - smu->debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_75); 2895 - smu->debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_54); 2901 + /* Set up debug mailbox registers */ 2902 + ctl->config.debug_param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_53); 2903 + ctl->config.debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_75); 2904 + ctl->config.debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_54); 2905 + ctl->flags |= SMU_MSG_CTL_DEBUG_MAILBOX; 2896 2906 } 2897 2907 2898 2908 static int smu_v13_0_0_smu_send_bad_mem_page_num(struct smu_context *smu, ··· 3215 3223 void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu) 3216 3224 { 3217 3225 smu->ppt_funcs = &smu_v13_0_0_ppt_funcs; 3218 - smu->message_map = smu_v13_0_0_message_map; 3219 3226 smu->clock_map = smu_v13_0_0_clk_map; 3220 3227 smu->feature_map = smu_v13_0_0_feature_mask_map; 3221 3228 smu->table_map = smu_v13_0_0_table_map; 3222 3229 smu->pwr_src_map = smu_v13_0_0_pwr_src_map; 3223 3230 smu->workload_map = smu_v13_0_0_workload_map; 3224 3231 smu->smc_driver_if_version = SMU13_0_0_DRIVER_IF_VERSION; 3225 - smu_v13_0_0_set_smu_mailbox_registers(smu); 3232 + smu_v13_0_0_init_msg_ctl(smu); 3226 3233 3227 3234 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == 3228 3235 IP_VERSION(13, 0, 10) &&

+13 -9

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

··· 1101 1101 .fini_smc_tables = smu_v13_0_4_fini_smc_tables, 1102 1102 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, 1103 1103 .system_features_control = smu_v13_0_4_system_features_control, 1104 - .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 1105 - .send_smc_msg = smu_cmn_send_smc_msg, 1106 1104 .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable, 1107 1105 .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable, 1108 1106 .set_default_dpm_table = smu_v13_0_set_default_dpm_tables, ··· 1122 1124 .set_gfx_power_up_by_imu = smu_v13_0_set_gfx_power_up_by_imu, 1123 1125 }; 1124 1126 1125 - static void smu_v13_0_4_set_smu_mailbox_registers(struct smu_context *smu) 1127 + static void smu_v13_0_4_init_msg_ctl(struct smu_context *smu) 1126 1128 { 1127 1129 struct amdgpu_device *adev = smu->adev; 1130 + struct smu_msg_ctl *ctl = &smu->msg_ctl; 1128 1131 1129 - smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); 1130 - smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); 1131 - smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); 1132 + ctl->smu = smu; 1133 + mutex_init(&ctl->lock); 1134 + ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); 1135 + ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); 1136 + ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); 1137 + ctl->config.num_arg_regs = 1; 1138 + ctl->ops = &smu_msg_v1_ops; 1139 + ctl->default_timeout = adev->usec_timeout * 20; 1140 + ctl->message_map = smu_v13_0_4_message_map; 1132 1141 } 1133 1142 1134 1143 void smu_v13_0_4_set_ppt_funcs(struct smu_context *smu) ··· 1143 1138 struct amdgpu_device *adev = smu->adev; 1144 1139 1145 1140 smu->ppt_funcs = &smu_v13_0_4_ppt_funcs; 1146 - smu->message_map = smu_v13_0_4_message_map; 1147 1141 smu->feature_map = smu_v13_0_4_feature_mask_map; 1148 1142 smu->table_map = smu_v13_0_4_table_map; 1149 1143 smu->smc_driver_if_version = SMU13_0_4_DRIVER_IF_VERSION; 1150 1144 smu->is_apu = true; 1151 1145 1152 1146 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 4)) 1153 - smu_v13_0_4_set_smu_mailbox_registers(smu); 1147 + smu_v13_0_4_init_msg_ctl(smu); 1154 1148 else 1155 - smu_v13_0_set_smu_mailbox_registers(smu); 1149 + smu_v13_0_init_msg_ctl(smu, smu_v13_0_4_message_map); 1156 1150 }

+16 -7

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

··· 1104 1104 .fini_smc_tables = smu_v13_0_5_fini_smc_tables, 1105 1105 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, 1106 1106 .system_features_control = smu_v13_0_5_system_features_control, 1107 - .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 1108 - .send_smc_msg = smu_cmn_send_smc_msg, 1109 1107 .dpm_set_vcn_enable = smu_v13_0_5_dpm_set_vcn_enable, 1110 1108 .dpm_set_jpeg_enable = smu_v13_0_5_dpm_set_jpeg_enable, 1111 1109 .set_default_dpm_table = smu_v13_0_5_set_default_dpm_tables, ··· 1124 1126 .set_fine_grain_gfx_freq_parameters = smu_v13_0_5_set_fine_grain_gfx_freq_parameters, 1125 1127 }; 1126 1128 1127 - void smu_v13_0_5_set_ppt_funcs(struct smu_context *smu) 1129 + static void smu_v13_0_5_init_msg_ctl(struct smu_context *smu) 1128 1130 { 1129 1131 struct amdgpu_device *adev = smu->adev; 1132 + struct smu_msg_ctl *ctl = &smu->msg_ctl; 1130 1133 1134 + ctl->smu = smu; 1135 + mutex_init(&ctl->lock); 1136 + ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_2); 1137 + ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_33); 1138 + ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_34); 1139 + ctl->config.num_arg_regs = 1; 1140 + ctl->ops = &smu_msg_v1_ops; 1141 + ctl->default_timeout = adev->usec_timeout * 20; 1142 + ctl->message_map = smu_v13_0_5_message_map; 1143 + } 1144 + 1145 + void smu_v13_0_5_set_ppt_funcs(struct smu_context *smu) 1146 + { 1131 1147 smu->ppt_funcs = &smu_v13_0_5_ppt_funcs; 1132 - smu->message_map = smu_v13_0_5_message_map; 1133 1148 smu->feature_map = smu_v13_0_5_feature_mask_map; 1134 1149 smu->table_map = smu_v13_0_5_table_map; 1135 1150 smu->is_apu = true; 1136 1151 smu->smc_driver_if_version = SMU13_0_5_DRIVER_IF_VERSION; 1137 - smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_34); 1138 - smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_2); 1139 - smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_33); 1152 + smu_v13_0_5_init_msg_ctl(smu); 1140 1153 }

+15 -17

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

··· 2897 2897 2898 2898 static int smu_v13_0_6_mode2_reset(struct smu_context *smu) 2899 2899 { 2900 - int ret = 0, index; 2900 + struct smu_msg_ctl *ctl = &smu->msg_ctl; 2901 2901 struct amdgpu_device *adev = smu->adev; 2902 + int ret = 0; 2902 2903 int timeout = 10; 2903 2904 2904 - index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 2905 - SMU_MSG_GfxDeviceDriverReset); 2906 - if (index < 0) 2907 - return index; 2905 + mutex_lock(&ctl->lock); 2908 2906 2909 - mutex_lock(&smu->message_lock); 2910 - 2911 - ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, 2912 - SMU_RESET_MODE_2); 2907 + ret = smu_msg_send_async_locked(ctl, SMU_MSG_GfxDeviceDriverReset, 2908 + SMU_RESET_MODE_2); 2909 + if (ret) 2910 + goto out; 2913 2911 2914 2912 /* Reset takes a bit longer, wait for 200ms. */ 2915 2913 msleep(200); 2916 2914 2917 - dev_dbg(smu->adev->dev, "restore config space...\n"); 2915 + dev_dbg(adev->dev, "restore config space...\n"); 2918 2916 /* Restore the config space saved during init */ 2919 2917 amdgpu_device_load_pci_state(adev->pdev); 2920 2918 ··· 2930 2932 if (!(adev->flags & AMD_IS_APU)) 2931 2933 smu_v13_0_6_restore_pci_config(smu); 2932 2934 2933 - dev_dbg(smu->adev->dev, "wait for reset ack\n"); 2935 + dev_dbg(adev->dev, "wait for reset ack\n"); 2934 2936 do { 2935 - ret = smu_cmn_wait_for_response(smu); 2937 + ret = smu_msg_wait_response(ctl, 0); 2936 2938 /* Wait a bit more time for getting ACK */ 2937 2939 if (ret == -ETIME) { 2938 2940 --timeout; ··· 2946 2948 } while (ret == -ETIME && timeout); 2947 2949 2948 2950 out: 2949 - mutex_unlock(&smu->message_lock); 2951 + mutex_unlock(&ctl->lock); 2950 2952 2951 2953 if (ret) 2952 2954 dev_err(adev->dev, "failed to send mode2 reset, error code %d", ··· 3860 3862 .set_tool_table_location = smu_v13_0_set_tool_table_location, 3861 3863 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location, 3862 3864 .system_features_control = smu_v13_0_6_system_features_control, 3863 - .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 3864 - .send_smc_msg = smu_cmn_send_smc_msg, 3865 3865 .get_enabled_mask = smu_v13_0_6_get_enabled_mask, 3866 3866 .feature_is_enabled = smu_cmn_feature_is_enabled, 3867 3867 .set_power_limit = smu_v13_0_6_set_power_limit, ··· 3897 3901 3898 3902 void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu) 3899 3903 { 3904 + const struct cmn2asic_msg_mapping *message_map; 3905 + 3900 3906 smu->ppt_funcs = &smu_v13_0_6_ppt_funcs; 3901 - smu->message_map = (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) ? 3907 + message_map = (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) ? 3902 3908 smu_v13_0_12_message_map : smu_v13_0_6_message_map; 3903 3909 smu->clock_map = smu_v13_0_6_clk_map; 3904 3910 smu->feature_map = (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) ? ··· 3908 3910 smu->table_map = smu_v13_0_6_table_map; 3909 3911 smu->smc_driver_if_version = SMU_IGNORE_IF_VERSION; 3910 3912 smu->smc_fw_caps |= SMU_FW_CAP_RAS_PRI; 3911 - smu_v13_0_set_smu_mailbox_registers(smu); 3913 + smu_v13_0_init_msg_ctl(smu, message_map); 3912 3914 smu_v13_0_6_set_temp_funcs(smu); 3913 3915 amdgpu_mca_smu_init_funcs(smu->adev, &smu_v13_0_6_mca_smu_funcs); 3914 3916 amdgpu_aca_set_smu_funcs(smu->adev, &smu_v13_0_6_aca_smu_funcs);

+1 -2

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

··· 2809 2809 void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu) 2810 2810 { 2811 2811 smu->ppt_funcs = &smu_v13_0_7_ppt_funcs; 2812 - smu->message_map = smu_v13_0_7_message_map; 2813 2812 smu->clock_map = smu_v13_0_7_clk_map; 2814 2813 smu->feature_map = smu_v13_0_7_feature_mask_map; 2815 2814 smu->table_map = smu_v13_0_7_table_map; 2816 2815 smu->pwr_src_map = smu_v13_0_7_pwr_src_map; 2817 2816 smu->workload_map = smu_v13_0_7_workload_map; 2818 2817 smu->smc_driver_if_version = SMU13_0_7_DRIVER_IF_VERSION; 2819 - smu_v13_0_set_smu_mailbox_registers(smu); 2818 + smu_v13_0_init_msg_ctl(smu, smu_v13_0_7_message_map); 2820 2819 }

+1 -4

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

··· 1333 1333 .fini_smc_tables = yellow_carp_fini_smc_tables, 1334 1334 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, 1335 1335 .system_features_control = yellow_carp_system_features_control, 1336 - .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 1337 - .send_smc_msg = smu_cmn_send_smc_msg, 1338 1336 .dpm_set_vcn_enable = yellow_carp_dpm_set_vcn_enable, 1339 1337 .dpm_set_jpeg_enable = yellow_carp_dpm_set_jpeg_enable, 1340 1338 .set_default_dpm_table = yellow_carp_set_default_dpm_tables, ··· 1358 1360 void yellow_carp_set_ppt_funcs(struct smu_context *smu) 1359 1361 { 1360 1362 smu->ppt_funcs = &yellow_carp_ppt_funcs; 1361 - smu->message_map = yellow_carp_message_map; 1362 1363 smu->feature_map = yellow_carp_feature_mask_map; 1363 1364 smu->table_map = yellow_carp_table_map; 1364 1365 smu->is_apu = true; 1365 1366 smu->smc_driver_if_version = SMU13_YELLOW_CARP_DRIVER_IF_VERSION; 1366 - smu_v13_0_set_smu_mailbox_registers(smu); 1367 + smu_v13_0_init_msg_ctl(smu, yellow_carp_message_map); 1367 1368 }

+8 -4

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

··· 1834 1834 1835 1835 int smu_v14_0_set_gfx_power_up_by_imu(struct smu_context *smu) 1836 1836 { 1837 - uint16_t index; 1837 + struct smu_msg_ctl *ctl = &smu->msg_ctl; 1838 1838 struct amdgpu_device *adev = smu->adev; 1839 + int ret; 1839 1840 1840 1841 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1841 1842 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableGfxImu, 1842 1843 ENABLE_IMU_ARG_GFXOFF_ENABLE, NULL); 1843 1844 } 1844 1845 1845 - index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 1846 - SMU_MSG_EnableGfxImu); 1847 - return smu_cmn_send_msg_without_waiting(smu, index, ENABLE_IMU_ARG_GFXOFF_ENABLE); 1846 + mutex_lock(&ctl->lock); 1847 + ret = smu_msg_send_async_locked(ctl, SMU_MSG_EnableGfxImu, 1848 + ENABLE_IMU_ARG_GFXOFF_ENABLE); 1849 + mutex_unlock(&ctl->lock); 1850 + 1851 + return ret; 1848 1852 } 1849 1853 1850 1854 int smu_v14_0_set_default_dpm_tables(struct smu_context *smu)

+12 -9

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

··· 1701 1701 .fini_smc_tables = smu_v14_0_0_fini_smc_tables, 1702 1702 .get_vbios_bootup_values = smu_v14_0_get_vbios_bootup_values, 1703 1703 .system_features_control = smu_v14_0_0_system_features_control, 1704 - .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 1705 - .send_smc_msg = smu_cmn_send_smc_msg, 1706 1704 .dpm_set_vcn_enable = smu_v14_0_set_vcn_enable, 1707 1705 .dpm_set_jpeg_enable = smu_v14_0_set_jpeg_enable, 1708 1706 .set_default_dpm_table = smu_v14_0_set_default_dpm_tables, ··· 1729 1731 .set_mall_enable = smu_v14_0_common_set_mall_enable, 1730 1732 }; 1731 1733 1732 - static void smu_v14_0_0_set_smu_mailbox_registers(struct smu_context *smu) 1734 + static void smu_v14_0_0_init_msg_ctl(struct smu_context *smu) 1733 1735 { 1734 1736 struct amdgpu_device *adev = smu->adev; 1737 + struct smu_msg_ctl *ctl = &smu->msg_ctl; 1735 1738 1736 - smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); 1737 - smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); 1738 - smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); 1739 + ctl->smu = smu; 1740 + mutex_init(&ctl->lock); 1741 + ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); 1742 + ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); 1743 + ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); 1744 + ctl->config.num_arg_regs = 1; 1745 + ctl->ops = &smu_msg_v1_ops; 1746 + ctl->default_timeout = adev->usec_timeout * 20; 1747 + ctl->message_map = smu_v14_0_0_message_map; 1739 1748 } 1740 1749 1741 1750 void smu_v14_0_0_set_ppt_funcs(struct smu_context *smu) 1742 1751 { 1743 - 1744 1752 smu->ppt_funcs = &smu_v14_0_0_ppt_funcs; 1745 - smu->message_map = smu_v14_0_0_message_map; 1746 1753 smu->feature_map = smu_v14_0_0_feature_mask_map; 1747 1754 smu->table_map = smu_v14_0_0_table_map; 1748 1755 smu->is_apu = true; 1749 1756 1750 - smu_v14_0_0_set_smu_mailbox_registers(smu); 1757 + smu_v14_0_0_init_msg_ctl(smu); 1751 1758 }

+20 -10

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

··· 1632 1632 table_context->power_play_table; 1633 1633 PPTable_t *pptable = table_context->driver_pptable; 1634 1634 CustomSkuTable_t *skutable = &pptable->CustomSkuTable; 1635 - uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0; 1635 + int16_t od_percent_upper = 0, od_percent_lower = 0; 1636 1636 uint32_t msg_limit = pptable->SkuTable.MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC]; 1637 + uint32_t power_limit; 1637 1638 1638 1639 if (smu_v14_0_get_current_power_limit(smu, &power_limit)) 1639 1640 power_limit = smu->adev->pm.ac_power ? ··· 2108 2107 return -EOPNOTSUPP; 2109 2108 } 2110 2109 2111 - static void smu_v14_0_2_set_smu_mailbox_registers(struct smu_context *smu) 2110 + static void smu_v14_0_2_init_msg_ctl(struct smu_context *smu) 2112 2111 { 2113 2112 struct amdgpu_device *adev = smu->adev; 2113 + struct smu_msg_ctl *ctl = &smu->msg_ctl; 2114 2114 2115 - smu->param_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_82); 2116 - smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_66); 2117 - smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_90); 2115 + ctl->smu = smu; 2116 + mutex_init(&ctl->lock); 2117 + ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_66); 2118 + ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_90); 2119 + ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_82); 2120 + ctl->config.num_arg_regs = 1; 2121 + ctl->ops = &smu_msg_v1_ops; 2122 + ctl->default_timeout = adev->usec_timeout * 20; 2123 + ctl->message_map = smu_v14_0_2_message_map; 2124 + ctl->flags = 0; 2118 2125 2119 - smu->debug_param_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_53); 2120 - smu->debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_75); 2121 - smu->debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_54); 2126 + /* Set up debug mailbox registers */ 2127 + ctl->config.debug_param_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_53); 2128 + ctl->config.debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_75); 2129 + ctl->config.debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_54); 2130 + ctl->flags |= SMU_MSG_CTL_DEBUG_MAILBOX; 2122 2131 } 2123 2132 2124 2133 static ssize_t smu_v14_0_2_get_gpu_metrics(struct smu_context *smu, ··· 2870 2859 void smu_v14_0_2_set_ppt_funcs(struct smu_context *smu) 2871 2860 { 2872 2861 smu->ppt_funcs = &smu_v14_0_2_ppt_funcs; 2873 - smu->message_map = smu_v14_0_2_message_map; 2874 2862 smu->clock_map = smu_v14_0_2_clk_map; 2875 2863 smu->feature_map = smu_v14_0_2_feature_mask_map; 2876 2864 smu->table_map = smu_v14_0_2_table_map; 2877 2865 smu->pwr_src_map = smu_v14_0_2_pwr_src_map; 2878 2866 smu->workload_map = smu_v14_0_2_workload_map; 2879 - smu_v14_0_2_set_smu_mailbox_registers(smu); 2867 + smu_v14_0_2_init_msg_ctl(smu); 2880 2868 }

+8 -4

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

··· 1709 1709 1710 1710 int smu_v15_0_set_gfx_power_up_by_imu(struct smu_context *smu) 1711 1711 { 1712 - uint16_t index; 1712 + struct smu_msg_ctl *ctl = &smu->msg_ctl; 1713 1713 struct amdgpu_device *adev = smu->adev; 1714 + int ret; 1714 1715 1715 1716 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1716 1717 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableGfxImu, 1717 1718 ENABLE_IMU_ARG_GFXOFF_ENABLE, NULL); 1718 1719 } 1719 1720 1720 - index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, 1721 - SMU_MSG_EnableGfxImu); 1722 - return smu_cmn_send_msg_without_waiting(smu, index, ENABLE_IMU_ARG_GFXOFF_ENABLE); 1721 + mutex_lock(&ctl->lock); 1722 + ret = smu_msg_send_async_locked(ctl, SMU_MSG_EnableGfxImu, 1723 + ENABLE_IMU_ARG_GFXOFF_ENABLE); 1724 + mutex_unlock(&ctl->lock); 1725 + 1726 + return ret; 1723 1727 } 1724 1728 1725 1729 int smu_v15_0_set_default_dpm_tables(struct smu_context *smu)

+30 -24

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c

··· 883 883 return 0; 884 884 } 885 885 886 - static int smu_v15_0_0_print_clk_levels(struct smu_context *smu, 887 - enum smu_clk_type clk_type, char *buf) 886 + static int smu_v15_0_0_emit_clk_levels(struct smu_context *smu, 887 + enum smu_clk_type clk_type, char *buf, 888 + int *offset) 888 889 { 889 - int i, idx, ret = 0, size = 0; 890 + int i, idx, ret = 0, size = *offset; 890 891 uint32_t cur_value = 0, value = 0, count = 0; 891 892 uint32_t min, max; 892 - 893 - smu_cmn_get_sysfs_buf(&buf, &size); 894 893 895 894 switch (clk_type) { 896 895 case SMU_OD_SCLK: ··· 914 915 case SMU_FCLK: 915 916 ret = smu_v15_0_0_get_current_clk_freq(smu, clk_type, &cur_value); 916 917 if (ret) 917 - break; 918 + return ret; 918 919 919 920 ret = smu_v15_0_common_get_dpm_level_count(smu, clk_type, &count); 920 921 if (ret) 921 - break; 922 + return ret; 922 923 923 924 for (i = 0; i < count; i++) { 924 925 idx = (clk_type == SMU_MCLK) ? (count - i - 1) : i; 925 926 ret = smu_v15_0_common_get_dpm_freq_by_index(smu, clk_type, idx, &value); 926 927 if (ret) 927 - break; 928 + return ret; 928 929 929 - size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 930 + size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, 931 + value, 930 932 cur_value == value ? "*" : ""); 931 933 } 932 934 break; ··· 935 935 case SMU_SCLK: 936 936 ret = smu_v15_0_0_get_current_clk_freq(smu, clk_type, &cur_value); 937 937 if (ret) 938 - break; 938 + return ret; 939 939 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq; 940 940 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq; 941 941 if (cur_value == max) ··· 946 946 i = 1; 947 947 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min, 948 948 i == 0 ? "*" : ""); 949 - size += sysfs_emit_at(buf, size, "1: %uMhz %s\n", 950 - i == 1 ? cur_value : 1100, /* UMD PSTATE GFXCLK 1100 */ 951 - i == 1 ? "*" : ""); 949 + size += sysfs_emit_at( 950 + buf, size, "1: %uMhz %s\n", 951 + i == 1 ? cur_value : 1100, /* UMD PSTATE GFXCLK 1100 */ 952 + i == 1 ? "*" : ""); 952 953 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max, 953 954 i == 2 ? "*" : ""); 954 955 break; ··· 957 956 break; 958 957 } 959 958 960 - return size; 959 + *offset = size; 960 + 961 + return 0; 961 962 } 962 963 963 964 static int smu_v15_0_0_set_soft_freq_limited_range(struct smu_context *smu, ··· 1310 1307 .fini_smc_tables = smu_v15_0_0_fini_smc_tables, 1311 1308 .get_vbios_bootup_values = smu_v15_0_get_vbios_bootup_values, 1312 1309 .system_features_control = smu_v15_0_0_system_features_control, 1313 - .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 1314 - .send_smc_msg = smu_cmn_send_smc_msg, 1315 1310 .dpm_set_vcn_enable = smu_v15_0_set_vcn_enable, 1316 1311 .dpm_set_jpeg_enable = smu_v15_0_set_jpeg_enable, 1317 1312 .set_default_dpm_table = smu_v15_0_set_default_dpm_tables, ··· 1324 1323 .mode2_reset = smu_v15_0_0_mode2_reset, 1325 1324 .get_dpm_ultimate_freq = smu_v15_0_common_get_dpm_ultimate_freq, 1326 1325 .od_edit_dpm_table = smu_v15_0_od_edit_dpm_table, 1327 - .print_clk_levels = smu_v15_0_0_print_clk_levels, 1326 + .emit_clk_levels = smu_v15_0_0_emit_clk_levels, 1328 1327 .force_clk_levels = smu_v15_0_0_force_clk_levels, 1329 1328 .set_performance_level = smu_v15_0_common_set_performance_level, 1330 1329 .set_fine_grain_gfx_freq_parameters = smu_v15_0_common_set_fine_grain_gfx_freq_parameters, ··· 1334 1333 .get_dpm_clock_table = smu_v15_0_common_get_dpm_table, 1335 1334 }; 1336 1335 1337 - static void smu_v15_0_0_set_smu_mailbox_registers(struct smu_context *smu) 1336 + static void smu_v15_0_0_init_msg_ctl(struct smu_context *smu) 1338 1337 { 1339 1338 struct amdgpu_device *adev = smu->adev; 1339 + struct smu_msg_ctl *ctl = &smu->msg_ctl; 1340 1340 1341 - smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_32); 1342 - smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_30); 1343 - smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_31); 1341 + ctl->smu = smu; 1342 + mutex_init(&ctl->lock); 1343 + ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_30); 1344 + ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_31); 1345 + ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_32); 1346 + ctl->config.num_arg_regs = 1; 1347 + ctl->ops = &smu_msg_v1_ops; 1348 + ctl->default_timeout = adev->usec_timeout * 20; 1349 + ctl->message_map = smu_v15_0_0_message_map; 1344 1350 } 1345 1351 1346 1352 void smu_v15_0_0_set_ppt_funcs(struct smu_context *smu) 1347 1353 { 1348 - 1349 1354 smu->ppt_funcs = &smu_v15_0_0_ppt_funcs; 1350 - smu->message_map = smu_v15_0_0_message_map; 1351 1355 smu->feature_map = smu_v15_0_0_feature_mask_map; 1352 1356 smu->table_map = smu_v15_0_0_table_map; 1353 1357 smu->is_apu = true; 1354 1358 1355 - smu_v15_0_0_set_smu_mailbox_registers(smu); 1359 + smu_v15_0_0_init_msg_ctl(smu); 1356 1360 }

+423 -346

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c

··· 53 53 -ENOTSUPP) : \ 54 54 -EINVAL) 55 55 56 + #define SMU_MSG_V1_DEFAULT_RATELIMIT_INTERVAL (5 * HZ) 57 + #define SMU_MSG_V1_DEFAULT_RATELIMIT_BURST 10 58 + 56 59 static const char *smu_get_message_name(struct smu_context *smu, 57 60 enum smu_message_type type) 58 61 { ··· 63 60 return "unknown smu message"; 64 61 65 62 return __smu_message_names[type]; 66 - } 67 - 68 - static void smu_cmn_read_arg(struct smu_context *smu, 69 - uint32_t *arg) 70 - { 71 - struct amdgpu_device *adev = smu->adev; 72 - 73 - *arg = RREG32(smu->param_reg); 74 63 } 75 64 76 65 /* Redefine the SMU error codes here. ··· 82 87 #define SMU_RESP_DEBUG_END 0xFB 83 88 84 89 #define SMU_RESP_UNEXP (~0U) 90 + 91 + static int smu_msg_v1_send_debug_msg(struct smu_msg_ctl *ctl, u32 msg, u32 param) 92 + { 93 + struct amdgpu_device *adev = ctl->smu->adev; 94 + struct smu_msg_config *cfg = &ctl->config; 95 + 96 + if (!(ctl->flags & SMU_MSG_CTL_DEBUG_MAILBOX)) 97 + return -EOPNOTSUPP; 98 + 99 + mutex_lock(&ctl->lock); 100 + 101 + WREG32(cfg->debug_param_reg, param); 102 + WREG32(cfg->debug_msg_reg, msg); 103 + WREG32(cfg->debug_resp_reg, 0); 104 + 105 + mutex_unlock(&ctl->lock); 106 + 107 + return 0; 108 + } 109 + 110 + static int __smu_cmn_send_debug_msg(struct smu_msg_ctl *ctl, 111 + u32 msg, 112 + u32 param) 113 + { 114 + if (!ctl->ops || !ctl->ops->send_debug_msg) 115 + return -EOPNOTSUPP; 116 + 117 + return ctl->ops->send_debug_msg(ctl, msg, param); 118 + } 119 + 85 120 /** 86 - * __smu_cmn_poll_stat -- poll for a status from the SMU 87 - * @smu: a pointer to SMU context 121 + * smu_cmn_wait_for_response -- wait for response from the SMU 122 + * @smu: pointer to an SMU context 88 123 * 89 - * Returns the status of the SMU, which could be, 90 - * 0, the SMU is busy with your command; 91 - * 1, execution status: success, execution result: success; 92 - * 0xFF, execution status: success, execution result: failure; 93 - * 0xFE, unknown command; 94 - * 0xFD, valid command, but bad (command) prerequisites; 95 - * 0xFC, the command was rejected as the SMU is busy; 96 - * 0xFB, "SMC_Result_DebugDataDumpEnd". 124 + * Wait for status from the SMU. 97 125 * 98 - * The values here are not defined by macros, because I'd rather we 99 - * include a single header file which defines them, which is 100 - * maintained by the SMU FW team, so that we're impervious to firmware 101 - * changes. At the moment those values are defined in various header 102 - * files, one for each ASIC, yet here we're a single ASIC-agnostic 103 - * interface. Such a change can be followed-up by a subsequent patch. 126 + * Return 0 on success, -errno on error, indicating the execution 127 + * status and result of the message being waited for. See 128 + * smu_msg_v1_decode_response() for details of the -errno. 104 129 */ 105 - static u32 __smu_cmn_poll_stat(struct smu_context *smu) 130 + int smu_cmn_wait_for_response(struct smu_context *smu) 106 131 { 107 - struct amdgpu_device *adev = smu->adev; 108 - int timeout = adev->usec_timeout * 20; 109 - u32 reg; 110 - 111 - for ( ; timeout > 0; timeout--) { 112 - reg = RREG32(smu->resp_reg); 113 - if ((reg & MP1_C2PMSG_90__CONTENT_MASK) != 0) 114 - break; 115 - 116 - udelay(1); 117 - } 118 - 119 - return reg; 132 + return smu_msg_wait_response(&smu->msg_ctl, 0); 120 133 } 121 134 122 - static void __smu_cmn_reg_print_error(struct smu_context *smu, 123 - u32 reg_c2pmsg_90, 124 - int msg_index, 125 - u32 param, 126 - enum smu_message_type msg) 135 + /** 136 + * smu_cmn_send_smc_msg_with_param -- send a message with parameter 137 + * @smu: pointer to an SMU context 138 + * @msg: message to send 139 + * @param: parameter to send to the SMU 140 + * @read_arg: pointer to u32 to return a value from the SMU back 141 + * to the caller 142 + * 143 + * Send the message @msg with parameter @param to the SMU, wait for 144 + * completion of the command, and return back a value from the SMU in 145 + * @read_arg pointer. 146 + * 147 + * Return 0 on success, -errno when a problem is encountered sending 148 + * message or receiving reply. If there is a PCI bus recovery or 149 + * the destination is a virtual GPU which does not allow this message 150 + * type, the message is simply dropped and success is also returned. 151 + * See smu_msg_v1_decode_response() for details of the -errno. 152 + * 153 + * If we weren't able to send the message to the SMU, we also print 154 + * the error to the standard log. 155 + * 156 + * Command completion status is printed only if the -errno is 157 + * -EREMOTEIO, indicating that the SMU returned back an 158 + * undefined/unknown/unspecified result. All other cases are 159 + * well-defined, not printed, but instead given back to the client to 160 + * decide what further to do. 161 + * 162 + * The return value, @read_arg is read back regardless, to give back 163 + * more information to the client, which on error would most likely be 164 + * @param, but we can't assume that. This also eliminates more 165 + * conditionals. 166 + */ 167 + int smu_cmn_send_smc_msg_with_param(struct smu_context *smu, 168 + enum smu_message_type msg, 169 + uint32_t param, 170 + uint32_t *read_arg) 127 171 { 128 - struct amdgpu_device *adev = smu->adev; 129 - const char *message = smu_get_message_name(smu, msg); 130 - u32 msg_idx, prm; 172 + struct smu_msg_ctl *ctl = &smu->msg_ctl; 173 + struct smu_msg_args args = { 174 + .msg = msg, 175 + .args[0] = param, 176 + .num_args = 1, 177 + .num_out_args = read_arg ? 1 : 0, 178 + .flags = 0, 179 + .timeout = 0, 180 + }; 181 + int ret; 131 182 132 - switch (reg_c2pmsg_90) { 133 - case SMU_RESP_NONE: { 134 - msg_idx = RREG32(smu->msg_reg); 135 - prm = RREG32(smu->param_reg); 136 - dev_err_ratelimited(adev->dev, 137 - "SMU: I'm not done with your previous command: SMN_C2PMSG_66:0x%08X SMN_C2PMSG_82:0x%08X", 138 - msg_idx, prm); 139 - } 140 - break; 141 - case SMU_RESP_OK: 142 - /* The SMU executed the command. It completed with a 143 - * successful result. 144 - */ 145 - break; 146 - case SMU_RESP_CMD_FAIL: 147 - /* The SMU executed the command. It completed with an 148 - * unsuccessful result. 149 - */ 150 - break; 151 - case SMU_RESP_CMD_UNKNOWN: 152 - dev_err_ratelimited(adev->dev, 153 - "SMU: unknown command: index:%d param:0x%08X message:%s", 154 - msg_index, param, message); 155 - break; 156 - case SMU_RESP_CMD_BAD_PREREQ: 157 - dev_err_ratelimited(adev->dev, 158 - "SMU: valid command, bad prerequisites: index:%d param:0x%08X message:%s", 159 - msg_index, param, message); 160 - break; 161 - case SMU_RESP_BUSY_OTHER: 162 - /* It is normal for SMU_MSG_GetBadPageCount to return busy 163 - * so don't print error at this case. 164 - */ 165 - if (msg != SMU_MSG_GetBadPageCount) 166 - dev_err_ratelimited(adev->dev, 167 - "SMU: I'm very busy for your command: index:%d param:0x%08X message:%s", 168 - msg_index, param, message); 169 - break; 170 - case SMU_RESP_DEBUG_END: 171 - dev_err_ratelimited(adev->dev, 172 - "SMU: I'm debugging!"); 173 - break; 174 - case SMU_RESP_UNEXP: 175 - if (amdgpu_device_bus_status_check(smu->adev)) { 176 - /* print error immediately if device is off the bus */ 177 - dev_err(adev->dev, 178 - "SMU: response:0x%08X for index:%d param:0x%08X message:%s?", 179 - reg_c2pmsg_90, msg_index, param, message); 180 - break; 181 - } 182 - fallthrough; 183 - default: 184 - dev_err_ratelimited(adev->dev, 185 - "SMU: response:0x%08X for index:%d param:0x%08X message:%s?", 186 - reg_c2pmsg_90, msg_index, param, message); 187 - break; 188 - } 183 + ret = ctl->ops->send_msg(ctl, &args); 184 + 185 + if (read_arg) 186 + *read_arg = args.out_args[0]; 187 + 188 + return ret; 189 189 } 190 190 191 - static int __smu_cmn_reg2errno(struct smu_context *smu, u32 reg_c2pmsg_90) 191 + int smu_cmn_send_smc_msg(struct smu_context *smu, 192 + enum smu_message_type msg, 193 + uint32_t *read_arg) 194 + { 195 + return smu_cmn_send_smc_msg_with_param(smu, 196 + msg, 197 + 0, 198 + read_arg); 199 + } 200 + 201 + int smu_cmn_send_debug_smc_msg(struct smu_context *smu, 202 + uint32_t msg) 203 + { 204 + return __smu_cmn_send_debug_msg(&smu->msg_ctl, msg, 0); 205 + } 206 + 207 + int smu_cmn_send_debug_smc_msg_with_param(struct smu_context *smu, 208 + uint32_t msg, uint32_t param) 209 + { 210 + return __smu_cmn_send_debug_msg(&smu->msg_ctl, msg, param); 211 + } 212 + 213 + static int smu_msg_v1_decode_response(u32 resp) 192 214 { 193 215 int res; 194 216 195 - switch (reg_c2pmsg_90) { 217 + switch (resp) { 196 218 case SMU_RESP_NONE: 197 219 /* The SMU is busy--still executing your command. 198 220 */ ··· 250 238 return res; 251 239 } 252 240 253 - static void __smu_cmn_send_msg(struct smu_context *smu, 254 - u16 msg, 255 - u32 param) 241 + static u32 __smu_msg_v1_poll_stat(struct smu_msg_ctl *ctl, u32 timeout_us) 256 242 { 257 - struct amdgpu_device *adev = smu->adev; 243 + struct amdgpu_device *adev = ctl->smu->adev; 244 + struct smu_msg_config *cfg = &ctl->config; 245 + u32 timeout = timeout_us ? timeout_us : ctl->default_timeout; 246 + u32 reg; 258 247 259 - WREG32(smu->resp_reg, 0); 260 - WREG32(smu->param_reg, param); 261 - WREG32(smu->msg_reg, msg); 262 - } 263 - 264 - static inline uint32_t __smu_cmn_get_msg_flags(struct smu_context *smu, 265 - enum smu_message_type msg) 266 - { 267 - return smu->message_map[msg].flags; 268 - } 269 - 270 - static int __smu_cmn_ras_filter_msg(struct smu_context *smu, 271 - enum smu_message_type msg, bool *poll) 272 - { 273 - struct amdgpu_device *adev = smu->adev; 274 - uint32_t flags, resp; 275 - bool fed_status, pri; 276 - 277 - flags = __smu_cmn_get_msg_flags(smu, msg); 278 - *poll = true; 279 - 280 - pri = !!(flags & SMU_MSG_NO_PRECHECK); 281 - /* When there is RAS fatal error, FW won't process non-RAS priority 282 - * messages. Don't allow any messages other than RAS priority messages. 283 - */ 284 - fed_status = amdgpu_ras_get_fed_status(adev); 285 - if (fed_status) { 286 - if (!(flags & SMU_MSG_RAS_PRI)) { 287 - dev_dbg(adev->dev, 288 - "RAS error detected, skip sending %s", 289 - smu_get_message_name(smu, msg)); 290 - return -EACCES; 291 - } 248 + for (; timeout > 0; timeout--) { 249 + reg = RREG32(cfg->resp_reg); 250 + if ((reg & MP1_C2PMSG_90__CONTENT_MASK) != 0) 251 + break; 252 + udelay(1); 292 253 } 293 254 294 - if (pri || fed_status) { 295 - /* FW will ignore non-priority messages when a RAS fatal error 296 - * or reset condition is detected. Hence it is possible that a 297 - * previous message wouldn't have got response. Allow to 298 - * continue without polling for response status for priority 299 - * messages. 300 - */ 301 - resp = RREG32(smu->resp_reg); 255 + return reg; 256 + } 257 + 258 + static void __smu_msg_v1_send(struct smu_msg_ctl *ctl, u16 index, 259 + struct smu_msg_args *args) 260 + { 261 + struct amdgpu_device *adev = ctl->smu->adev; 262 + struct smu_msg_config *cfg = &ctl->config; 263 + int i; 264 + 265 + WREG32(cfg->resp_reg, 0); 266 + for (i = 0; i < args->num_args; i++) 267 + WREG32(cfg->arg_regs[i], args->args[i]); 268 + WREG32(cfg->msg_reg, index); 269 + } 270 + 271 + static void __smu_msg_v1_read_out_args(struct smu_msg_ctl *ctl, 272 + struct smu_msg_args *args) 273 + { 274 + struct amdgpu_device *adev = ctl->smu->adev; 275 + int i; 276 + 277 + for (i = 0; i < args->num_out_args; i++) 278 + args->out_args[i] = RREG32(ctl->config.arg_regs[i]); 279 + } 280 + 281 + static void __smu_msg_v1_print_err_limited(struct smu_msg_ctl *ctl, 282 + struct smu_msg_args *args, 283 + char *err_msg) 284 + { 285 + static DEFINE_RATELIMIT_STATE(_rs, 286 + SMU_MSG_V1_DEFAULT_RATELIMIT_INTERVAL, 287 + SMU_MSG_V1_DEFAULT_RATELIMIT_BURST); 288 + struct smu_context *smu = ctl->smu; 289 + struct amdgpu_device *adev = smu->adev; 290 + 291 + if (__ratelimit(&_rs)) { 292 + u32 in[SMU_MSG_MAX_ARGS]; 293 + int i; 294 + 295 + dev_err(adev->dev, "%s msg_reg: %x resp_reg: %x", err_msg, 296 + RREG32(ctl->config.msg_reg), 297 + RREG32(ctl->config.resp_reg)); 298 + if (args->num_args > 0) { 299 + for (i = 0; i < args->num_args; i++) 300 + in[i] = RREG32(ctl->config.arg_regs[i]); 301 + print_hex_dump(KERN_ERR, "in params:", DUMP_PREFIX_NONE, 302 + 16, 4, in, args->num_args * sizeof(u32), 303 + false); 304 + } 305 + } 306 + } 307 + 308 + static void __smu_msg_v1_print_error(struct smu_msg_ctl *ctl, 309 + u32 resp, 310 + struct smu_msg_args *args) 311 + { 312 + struct smu_context *smu = ctl->smu; 313 + struct amdgpu_device *adev = smu->adev; 314 + int index = ctl->message_map[args->msg].map_to; 315 + 316 + switch (resp) { 317 + case SMU_RESP_NONE: 318 + __smu_msg_v1_print_err_limited(ctl, args, "SMU: No response"); 319 + break; 320 + case SMU_RESP_OK: 321 + break; 322 + case SMU_RESP_CMD_FAIL: 323 + break; 324 + case SMU_RESP_CMD_UNKNOWN: 325 + __smu_msg_v1_print_err_limited(ctl, args, 326 + "SMU: unknown command"); 327 + break; 328 + case SMU_RESP_CMD_BAD_PREREQ: 329 + __smu_msg_v1_print_err_limited( 330 + ctl, args, "SMU: valid command, bad prerequisites"); 331 + break; 332 + case SMU_RESP_BUSY_OTHER: 333 + if (args->msg != SMU_MSG_GetBadPageCount) 334 + __smu_msg_v1_print_err_limited(ctl, args, 335 + "SMU: I'm very busy"); 336 + break; 337 + case SMU_RESP_DEBUG_END: 338 + __smu_msg_v1_print_err_limited(ctl, args, "SMU: Debug Err"); 339 + break; 340 + case SMU_RESP_UNEXP: 341 + if (amdgpu_device_bus_status_check(adev)) { 342 + dev_err(adev->dev, 343 + "SMU: bus error for message: %s(%d) response:0x%08X ", 344 + smu_get_message_name(smu, args->msg), index, 345 + resp); 346 + if (args->num_args > 0) 347 + print_hex_dump(KERN_ERR, 348 + "in params:", DUMP_PREFIX_NONE, 349 + 16, 4, args->args, 350 + args->num_args * sizeof(u32), 351 + false); 352 + } 353 + break; 354 + default: 355 + __smu_msg_v1_print_err_limited(ctl, args, 356 + "SMU: unknown response"); 357 + break; 358 + } 359 + } 360 + 361 + static int __smu_msg_v1_ras_filter(struct smu_msg_ctl *ctl, 362 + enum smu_message_type msg, u32 msg_flags, 363 + bool *skip_pre_poll) 364 + { 365 + struct smu_context *smu = ctl->smu; 366 + struct amdgpu_device *adev = smu->adev; 367 + bool fed_status; 368 + u32 reg; 369 + 370 + if (!(smu->smc_fw_caps & SMU_FW_CAP_RAS_PRI)) 371 + return 0; 372 + 373 + fed_status = amdgpu_ras_get_fed_status(adev); 374 + 375 + /* Block non-RAS-priority messages during RAS error */ 376 + if (fed_status && !(msg_flags & SMU_MSG_RAS_PRI)) { 377 + dev_dbg(adev->dev, "RAS error detected, skip sending %s", 378 + smu_get_message_name(smu, msg)); 379 + return -EACCES; 380 + } 381 + 382 + /* Skip pre-poll for priority messages or during RAS error */ 383 + if ((msg_flags & SMU_MSG_NO_PRECHECK) || fed_status) { 384 + reg = RREG32(ctl->config.resp_reg); 302 385 dev_dbg(adev->dev, 303 386 "Sending priority message %s response status: %x", 304 - smu_get_message_name(smu, msg), resp); 305 - if (resp == 0) 306 - *poll = false; 387 + smu_get_message_name(smu, msg), reg); 388 + if (reg == 0) 389 + *skip_pre_poll = true; 307 390 } 308 391 309 392 return 0; 310 393 } 311 394 312 - static int __smu_cmn_send_debug_msg(struct smu_context *smu, 313 - u32 msg, 314 - u32 param) 315 - { 316 - struct amdgpu_device *adev = smu->adev; 317 - 318 - WREG32(smu->debug_param_reg, param); 319 - WREG32(smu->debug_msg_reg, msg); 320 - WREG32(smu->debug_resp_reg, 0); 321 - 322 - return 0; 323 - } 324 395 /** 325 - * smu_cmn_send_msg_without_waiting -- send the message; don't wait for status 326 - * @smu: pointer to an SMU context 327 - * @msg_index: message index 328 - * @param: message parameter to send to the SMU 396 + * smu_msg_proto_v1_send_msg - Complete V1 protocol with all filtering 397 + * @ctl: Message control block 398 + * @args: Message arguments 329 399 * 330 - * Send a message to the SMU with the parameter passed. Do not wait 331 - * for status/result of the message, thus the "without_waiting". 332 - * 333 - * Return 0 on success, -errno on error if we weren't able to _send_ 334 - * the message for some reason. See __smu_cmn_reg2errno() for details 335 - * of the -errno. 400 + * Return: 0 on success, negative errno on failure 336 401 */ 337 - int smu_cmn_send_msg_without_waiting(struct smu_context *smu, 338 - uint16_t msg_index, 339 - uint32_t param) 402 + static int smu_msg_v1_send_msg(struct smu_msg_ctl *ctl, 403 + struct smu_msg_args *args) 340 404 { 405 + struct smu_context *smu = ctl->smu; 341 406 struct amdgpu_device *adev = smu->adev; 342 - u32 reg; 343 - int res; 407 + const struct cmn2asic_msg_mapping *mapping; 408 + u32 reg, msg_flags; 409 + int ret, index; 410 + bool skip_pre_poll = false; 411 + bool lock_held = args->flags & SMU_MSG_FLAG_LOCK_HELD; 344 412 413 + /* Early exit if no HW access */ 345 414 if (adev->no_hw_access) 346 415 return 0; 347 416 348 - if (smu->smc_fw_state == SMU_FW_HANG) { 349 - dev_err(adev->dev, "SMU is in hanged state, failed to send smu message!\n"); 350 - res = -EREMOTEIO; 351 - goto Out; 352 - } 417 + /* Message index translation */ 418 + if (args->msg >= SMU_MSG_MAX_COUNT || !ctl->message_map) 419 + return -EINVAL; 353 420 354 - if (smu->smc_fw_state == SMU_FW_INIT) { 355 - smu->smc_fw_state = SMU_FW_RUNTIME; 356 - } else { 357 - reg = __smu_cmn_poll_stat(smu); 358 - res = __smu_cmn_reg2errno(smu, reg); 359 - if (reg == SMU_RESP_NONE || res == -EREMOTEIO) 360 - goto Out; 361 - } 421 + if (args->num_args > ctl->config.num_arg_regs || 422 + args->num_out_args > ctl->config.num_arg_regs) 423 + return -EINVAL; 362 424 363 - __smu_cmn_send_msg(smu, msg_index, param); 364 - res = 0; 365 - Out: 366 - if (unlikely(adev->pm.smu_debug_mask & SMU_DEBUG_HALT_ON_ERROR) && 367 - res && (res != -ETIME)) { 368 - amdgpu_device_halt(adev); 369 - WARN_ON(1); 370 - } 425 + mapping = &ctl->message_map[args->msg]; 426 + if (!mapping->valid_mapping) 427 + return -EINVAL; 371 428 372 - return res; 373 - } 429 + msg_flags = mapping->flags; 430 + index = mapping->map_to; 374 431 375 - /** 376 - * smu_cmn_wait_for_response -- wait for response from the SMU 377 - * @smu: pointer to an SMU context 378 - * 379 - * Wait for status from the SMU. 380 - * 381 - * Return 0 on success, -errno on error, indicating the execution 382 - * status and result of the message being waited for. See 383 - * __smu_cmn_reg2errno() for details of the -errno. 384 - */ 385 - int smu_cmn_wait_for_response(struct smu_context *smu) 386 - { 387 - u32 reg; 388 - int res; 389 - 390 - reg = __smu_cmn_poll_stat(smu); 391 - res = __smu_cmn_reg2errno(smu, reg); 392 - 393 - if (res == -EREMOTEIO) 394 - smu->smc_fw_state = SMU_FW_HANG; 395 - 396 - if (unlikely(smu->adev->pm.smu_debug_mask & SMU_DEBUG_HALT_ON_ERROR) && 397 - res && (res != -ETIME)) { 398 - amdgpu_device_halt(smu->adev); 399 - WARN_ON(1); 400 - } 401 - 402 - return res; 403 - } 404 - 405 - /** 406 - * smu_cmn_send_smc_msg_with_param -- send a message with parameter 407 - * @smu: pointer to an SMU context 408 - * @msg: message to send 409 - * @param: parameter to send to the SMU 410 - * @read_arg: pointer to u32 to return a value from the SMU back 411 - * to the caller 412 - * 413 - * Send the message @msg with parameter @param to the SMU, wait for 414 - * completion of the command, and return back a value from the SMU in 415 - * @read_arg pointer. 416 - * 417 - * Return 0 on success, -errno when a problem is encountered sending 418 - * message or receiving reply. If there is a PCI bus recovery or 419 - * the destination is a virtual GPU which does not allow this message 420 - * type, the message is simply dropped and success is also returned. 421 - * See __smu_cmn_reg2errno() for details of the -errno. 422 - * 423 - * If we weren't able to send the message to the SMU, we also print 424 - * the error to the standard log. 425 - * 426 - * Command completion status is printed only if the -errno is 427 - * -EREMOTEIO, indicating that the SMU returned back an 428 - * undefined/unknown/unspecified result. All other cases are 429 - * well-defined, not printed, but instead given back to the client to 430 - * decide what further to do. 431 - * 432 - * The return value, @read_arg is read back regardless, to give back 433 - * more information to the client, which on error would most likely be 434 - * @param, but we can't assume that. This also eliminates more 435 - * conditionals. 436 - */ 437 - int smu_cmn_send_smc_msg_with_param(struct smu_context *smu, 438 - enum smu_message_type msg, 439 - uint32_t param, 440 - uint32_t *read_arg) 441 - { 442 - struct amdgpu_device *adev = smu->adev; 443 - int res, index; 444 - bool poll = true; 445 - u32 reg; 446 - 447 - if (adev->no_hw_access) 432 + /* VF filter - skip messages not valid for VF */ 433 + if (amdgpu_sriov_vf(adev) && !(msg_flags & SMU_MSG_VF_FLAG)) 448 434 return 0; 449 435 450 - index = smu_cmn_to_asic_specific_index(smu, 451 - CMN2ASIC_MAPPING_MSG, 452 - msg); 453 - if (index < 0) 454 - return index == -EACCES ? 0 : index; 436 + if (!lock_held) 437 + mutex_lock(&ctl->lock); 455 438 456 - mutex_lock(&smu->message_lock); 439 + /* RAS priority filter */ 440 + ret = __smu_msg_v1_ras_filter(ctl, args->msg, msg_flags, 441 + &skip_pre_poll); 442 + if (ret) 443 + goto out; 457 444 458 - if (smu->smc_fw_caps & SMU_FW_CAP_RAS_PRI) { 459 - res = __smu_cmn_ras_filter_msg(smu, msg, &poll); 460 - if (res) 461 - goto Out; 462 - } 463 - 445 + /* FW state checks */ 464 446 if (smu->smc_fw_state == SMU_FW_HANG) { 465 - dev_err(adev->dev, "SMU is in hanged state, failed to send smu message!\n"); 466 - res = -EREMOTEIO; 467 - goto Out; 447 + dev_err(adev->dev, 448 + "SMU is in hanged state, failed to send smu message!\n"); 449 + ret = -EREMOTEIO; 450 + goto out; 468 451 } else if (smu->smc_fw_state == SMU_FW_INIT) { 469 - /* Ignore initial smu response register value */ 470 - poll = false; 452 + skip_pre_poll = true; 471 453 smu->smc_fw_state = SMU_FW_RUNTIME; 472 454 } 473 455 474 - if (poll) { 475 - reg = __smu_cmn_poll_stat(smu); 476 - res = __smu_cmn_reg2errno(smu, reg); 477 - if (reg == SMU_RESP_NONE || res == -EREMOTEIO) { 478 - __smu_cmn_reg_print_error(smu, reg, index, param, msg); 479 - goto Out; 456 + /* Pre-poll: ensure previous message completed */ 457 + if (!skip_pre_poll) { 458 + reg = __smu_msg_v1_poll_stat(ctl, args->timeout); 459 + ret = smu_msg_v1_decode_response(reg); 460 + if (reg == SMU_RESP_NONE || ret == -EREMOTEIO) { 461 + __smu_msg_v1_print_error(ctl, reg, args); 462 + goto out; 480 463 } 481 464 } 482 - __smu_cmn_send_msg(smu, (uint16_t) index, param); 483 - reg = __smu_cmn_poll_stat(smu); 484 - res = __smu_cmn_reg2errno(smu, reg); 485 - if (res != 0) { 486 - if (res == -EREMOTEIO) 487 - smu->smc_fw_state = SMU_FW_HANG; 488 - __smu_cmn_reg_print_error(smu, reg, index, param, msg); 465 + 466 + /* Send message */ 467 + __smu_msg_v1_send(ctl, (u16)index, args); 468 + 469 + /* Post-poll (skip if ASYNC) */ 470 + if (args->flags & SMU_MSG_FLAG_ASYNC) { 471 + ret = 0; 472 + goto out; 489 473 } 490 - if (read_arg) { 491 - smu_cmn_read_arg(smu, read_arg); 492 - dev_dbg(adev->dev, "smu send message: %s(%d) param: 0x%08x, resp: 0x%08x, readval: 0x%08x\n", 493 - smu_get_message_name(smu, msg), index, param, reg, *read_arg); 474 + 475 + reg = __smu_msg_v1_poll_stat(ctl, args->timeout); 476 + ret = smu_msg_v1_decode_response(reg); 477 + 478 + /* FW state update on fatal error */ 479 + if (ret == -EREMOTEIO) { 480 + smu->smc_fw_state = SMU_FW_HANG; 481 + __smu_msg_v1_print_error(ctl, reg, args); 482 + } else if (ret != 0) { 483 + __smu_msg_v1_print_error(ctl, reg, args); 484 + } 485 + 486 + /* Read output args */ 487 + if (ret == 0 && args->num_out_args > 0) { 488 + __smu_msg_v1_read_out_args(ctl, args); 489 + dev_dbg(adev->dev, "smu send message: %s(%d) resp : 0x%08x", 490 + smu_get_message_name(smu, args->msg), index, reg); 491 + if (args->num_args > 0) 492 + print_hex_dump_debug("in params:", DUMP_PREFIX_NONE, 16, 493 + 4, args->args, 494 + args->num_args * sizeof(u32), 495 + false); 496 + print_hex_dump_debug("out params:", DUMP_PREFIX_NONE, 16, 4, 497 + args->out_args, 498 + args->num_out_args * sizeof(u32), false); 494 499 } else { 495 - dev_dbg(adev->dev, "smu send message: %s(%d) param: 0x%08x, resp: 0x%08x\n", 496 - smu_get_message_name(smu, msg), index, param, reg); 500 + dev_dbg(adev->dev, "smu send message: %s(%d), resp: 0x%08x\n", 501 + smu_get_message_name(smu, args->msg), index, reg); 502 + if (args->num_args > 0) 503 + print_hex_dump_debug("in params:", DUMP_PREFIX_NONE, 16, 504 + 4, args->args, 505 + args->num_args * sizeof(u32), 506 + false); 497 507 } 498 - Out: 499 - if (unlikely(adev->pm.smu_debug_mask & SMU_DEBUG_HALT_ON_ERROR) && res) { 508 + 509 + out: 510 + /* Debug halt on error */ 511 + if (unlikely(adev->pm.smu_debug_mask & SMU_DEBUG_HALT_ON_ERROR) && 512 + ret) { 500 513 amdgpu_device_halt(adev); 501 514 WARN_ON(1); 502 515 } 503 516 504 - mutex_unlock(&smu->message_lock); 505 - return res; 517 + if (!lock_held) 518 + mutex_unlock(&ctl->lock); 519 + return ret; 506 520 } 507 521 508 - int smu_cmn_send_smc_msg(struct smu_context *smu, 509 - enum smu_message_type msg, 510 - uint32_t *read_arg) 522 + static int smu_msg_v1_wait_response(struct smu_msg_ctl *ctl, u32 timeout_us) 511 523 { 512 - return smu_cmn_send_smc_msg_with_param(smu, 513 - msg, 514 - 0, 515 - read_arg); 524 + struct smu_context *smu = ctl->smu; 525 + struct amdgpu_device *adev = smu->adev; 526 + u32 reg; 527 + int ret; 528 + 529 + reg = __smu_msg_v1_poll_stat(ctl, timeout_us); 530 + ret = smu_msg_v1_decode_response(reg); 531 + 532 + if (ret == -EREMOTEIO) 533 + smu->smc_fw_state = SMU_FW_HANG; 534 + 535 + if (unlikely(adev->pm.smu_debug_mask & SMU_DEBUG_HALT_ON_ERROR) && 536 + ret && (ret != -ETIME)) { 537 + amdgpu_device_halt(adev); 538 + WARN_ON(1); 539 + } 540 + 541 + return ret; 516 542 } 517 543 518 - int smu_cmn_send_debug_smc_msg(struct smu_context *smu, 519 - uint32_t msg) 544 + const struct smu_msg_ops smu_msg_v1_ops = { 545 + .send_msg = smu_msg_v1_send_msg, 546 + .wait_response = smu_msg_v1_wait_response, 547 + .decode_response = smu_msg_v1_decode_response, 548 + .send_debug_msg = smu_msg_v1_send_debug_msg, 549 + }; 550 + 551 + int smu_msg_wait_response(struct smu_msg_ctl *ctl, u32 timeout_us) 520 552 { 521 - return __smu_cmn_send_debug_msg(smu, msg, 0); 553 + return ctl->ops->wait_response(ctl, timeout_us); 522 554 } 523 555 524 - int smu_cmn_send_debug_smc_msg_with_param(struct smu_context *smu, 525 - uint32_t msg, uint32_t param) 556 + /** 557 + * smu_msg_send_async_locked - Send message asynchronously, caller holds lock 558 + * @ctl: Message control block 559 + * @msg: Message type 560 + * @param: Message parameter 561 + * 562 + * Send an SMU message without waiting for response. Caller must hold ctl->lock 563 + * and call smu_msg_wait_response() later to get the result. 564 + * 565 + * Return: 0 on success, negative errno on failure 566 + */ 567 + int smu_msg_send_async_locked(struct smu_msg_ctl *ctl, 568 + enum smu_message_type msg, u32 param) 526 569 { 527 - return __smu_cmn_send_debug_msg(smu, msg, param); 570 + struct smu_msg_args args = { 571 + .msg = msg, 572 + .args[0] = param, 573 + .num_args = 1, 574 + .num_out_args = 0, 575 + .flags = SMU_MSG_FLAG_ASYNC | SMU_MSG_FLAG_LOCK_HELD, 576 + .timeout = 0, 577 + }; 578 + 579 + return ctl->ops->send_msg(ctl, &args); 528 580 } 529 581 530 582 int smu_cmn_to_asic_specific_index(struct smu_context *smu, ··· 601 525 switch (type) { 602 526 case CMN2ASIC_MAPPING_MSG: 603 527 if (index >= SMU_MSG_MAX_COUNT || 604 - !smu->message_map) 528 + !smu->msg_ctl.message_map) 605 529 return -EINVAL; 606 530 607 - msg_mapping = smu->message_map[index]; 531 + msg_mapping = smu->msg_ctl.message_map[index]; 608 532 if (!msg_mapping.valid_mapping) 609 533 return -EINVAL; 610 534 ··· 1286 1210 struct smu_dpm_table *dpm_table, 1287 1211 uint32_t cur_clk, char *buf, int *offset) 1288 1212 { 1289 - uint32_t min_clk, level_index, count; 1290 - uint32_t freq_values[3] = { 0 }; 1213 + uint32_t min_clk, max_clk, level_index, count; 1214 + uint32_t freq_values[3]; 1215 + int size, lvl, i; 1291 1216 bool is_fine_grained; 1292 1217 bool is_deep_sleep; 1293 - int size, lvl, i; 1294 1218 bool freq_match; 1295 1219 1296 1220 if (!dpm_table || !buf) ··· 1301 1225 count = dpm_table->count; 1302 1226 is_fine_grained = dpm_table->flags & SMU_DPM_TABLE_FINE_GRAINED; 1303 1227 min_clk = SMU_DPM_TABLE_MIN(dpm_table); 1228 + max_clk = SMU_DPM_TABLE_MAX(dpm_table); 1304 1229 1305 1230 /* Deep sleep - current clock < min_clock/2, TBD: cur_clk = 0 as GFXOFF */ 1306 1231 is_deep_sleep = cur_clk < min_clk / 2; ··· 1322 1245 freq_match ? "*" : ""); 1323 1246 } 1324 1247 } else { 1248 + count = 2; 1325 1249 freq_values[0] = min_clk; 1326 - freq_values[2] = SMU_DPM_TABLE_MAX(dpm_table); 1327 - freq_values[1] = cur_clk; 1250 + freq_values[1] = max_clk; 1328 1251 1329 - lvl = -1; 1330 1252 if (!is_deep_sleep) { 1331 - lvl = 1; 1332 - if (smu_cmn_freqs_match(cur_clk, freq_values[0])) 1253 + if (smu_cmn_freqs_match(cur_clk, min_clk)) { 1333 1254 lvl = 0; 1334 - else if (smu_cmn_freqs_match(cur_clk, freq_values[2])) 1335 - lvl = 2; 1336 - } 1337 - count = 3; 1338 - if (lvl != 1) { 1339 - count = 2; 1340 - freq_values[1] = freq_values[2]; 1255 + } else if (smu_cmn_freqs_match(cur_clk, max_clk)) { 1256 + lvl = 1; 1257 + } else { 1258 + /* NOTE: use index '1' to show current clock value */ 1259 + lvl = 1; 1260 + count = 3; 1261 + freq_values[1] = cur_clk; 1262 + freq_values[2] = max_clk; 1263 + } 1341 1264 } 1342 1265 1343 1266 for (i = 0; i < count; i++) {

+6 -16

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h

··· 25 25 26 26 #include "amdgpu_smu.h" 27 27 28 + extern const struct smu_msg_ops smu_msg_v1_ops; 29 + 30 + int smu_msg_wait_response(struct smu_msg_ctl *ctl, u32 timeout_us); 31 + int smu_msg_send_async_locked(struct smu_msg_ctl *ctl, 32 + enum smu_message_type msg, u32 param); 33 + 28 34 #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) || defined(SWSMU_CODE_LAYER_L4) 29 35 30 36 #define FDO_PWM_MODE_STATIC 1 ··· 110 104 return ((gen == 0) ? link_speed[0] : link_speed[gen - 1]); 111 105 } 112 106 113 - int smu_cmn_send_msg_without_waiting(struct smu_context *smu, 114 - uint16_t msg_index, 115 - uint32_t param); 116 107 int smu_cmn_send_smc_msg_with_param(struct smu_context *smu, 117 108 enum smu_message_type msg, 118 109 uint32_t param, ··· 186 183 187 184 int smu_cmn_set_mp1_state(struct smu_context *smu, 188 185 enum pp_mp1_state mp1_state); 189 - 190 - /* 191 - * Helper function to make sysfs_emit_at() happy. Align buf to 192 - * the current page boundary and record the offset. 193 - */ 194 - static inline void smu_cmn_get_sysfs_buf(char **buf, int *offset) 195 - { 196 - if (!*buf || !offset) 197 - return; 198 - 199 - *offset = offset_in_page(*buf); 200 - *buf -= *offset; 201 - } 202 186 203 187 bool smu_cmn_is_audio_func_enabled(struct amdgpu_device *adev); 204 188 void smu_cmn_generic_soc_policy_desc(struct smu_dpm_policy *policy);

-2

drivers/gpu/drm/amd/pm/swsmu/smu_internal.h

··· 54 54 #define smu_system_features_control(smu, en) smu_ppt_funcs(system_features_control, 0, smu, en) 55 55 #define smu_init_max_sustainable_clocks(smu) smu_ppt_funcs(init_max_sustainable_clocks, 0, smu) 56 56 #define smu_set_default_od_settings(smu) smu_ppt_funcs(set_default_od_settings, 0, smu) 57 - #define smu_send_smc_msg_with_param(smu, msg, param, read_arg) smu_ppt_funcs(send_smc_msg_with_param, 0, smu, msg, param, read_arg) 58 - #define smu_send_smc_msg(smu, msg, read_arg) smu_ppt_funcs(send_smc_msg, 0, smu, msg, read_arg) 59 57 #define smu_init_display_count(smu, count) smu_ppt_funcs(init_display_count, 0, smu, count) 60 58 #define smu_feature_set_allowed_mask(smu) smu_ppt_funcs(set_allowed_mask, 0, smu) 61 59 #define smu_feature_get_enabled_mask(smu, mask) smu_ppt_funcs(get_enabled_mask, -EOPNOTSUPP, smu, mask)

+1 -5

include/uapi/drm/amdgpu_drm.h

··· 105 105 * 106 106 * %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for 107 107 * signalling user mode queues. 108 - * 109 - * %AMDGPU_GEM_DOMAIN_MMIO_REMAP MMIO remap page (special mapping for HDP flushing). 110 108 */ 111 109 #define AMDGPU_GEM_DOMAIN_CPU 0x1 112 110 #define AMDGPU_GEM_DOMAIN_GTT 0x2 ··· 113 115 #define AMDGPU_GEM_DOMAIN_GWS 0x10 114 116 #define AMDGPU_GEM_DOMAIN_OA 0x20 115 117 #define AMDGPU_GEM_DOMAIN_DOORBELL 0x40 116 - #define AMDGPU_GEM_DOMAIN_MMIO_REMAP 0x80 117 118 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 118 119 AMDGPU_GEM_DOMAIN_GTT | \ 119 120 AMDGPU_GEM_DOMAIN_VRAM | \ 120 121 AMDGPU_GEM_DOMAIN_GDS | \ 121 122 AMDGPU_GEM_DOMAIN_GWS | \ 122 123 AMDGPU_GEM_DOMAIN_OA | \ 123 - AMDGPU_GEM_DOMAIN_DOORBELL | \ 124 - AMDGPU_GEM_DOMAIN_MMIO_REMAP) 124 + AMDGPU_GEM_DOMAIN_DOORBELL) 125 125 126 126 /* Flag that CPU access will be required for the case of VRAM domain */ 127 127 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)

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