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clk: qcom: gcc-msm8994: Add proper msm8992 support

MSM8992 is a cut-down version of MSM8994, featuring
largely the same hardware.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210923162645.23257-8-konrad.dybcio@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Konrad Dybcio and committed by
Stephen Boyd
c09b8023 a888dc4c

+70 -1
+70 -1
drivers/clk/qcom/gcc-msm8994.c
··· 8 8 #include <linux/ctype.h> 9 9 #include <linux/io.h> 10 10 #include <linux/of.h> 11 + #include <linux/of_device.h> 11 12 #include <linux/platform_device.h> 12 13 #include <linux/module.h> 13 14 #include <linux/regmap.h> ··· 215 214 F(24000000, P_GPLL0, 12.5, 1, 2), 216 215 F(25000000, P_GPLL0, 12, 1, 2), 217 216 F(48000000, P_GPLL0, 12.5, 0, 0), 217 + F(50000000, P_GPLL0, 12, 0, 0), 218 + { } 219 + }; 220 + 221 + static struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src_8992[] = { 222 + F(960000, P_XO, 10, 1, 2), 223 + F(4800000, P_XO, 4, 0, 0), 224 + F(9600000, P_XO, 2, 0, 0), 225 + F(15000000, P_GPLL0, 10, 1, 4), 226 + F(19200000, P_XO, 1, 0, 0), 227 + F(25000000, P_GPLL0, 12, 1, 2), 218 228 F(50000000, P_GPLL0, 12, 0, 0), 219 229 { } 220 230 }; ··· 983 971 F(100000000, P_GPLL0, 6, 0, 0), 984 972 F(192000000, P_GPLL4, 2, 0, 0), 985 973 F(384000000, P_GPLL4, 1, 0, 0), 974 + { } 975 + }; 976 + 977 + static struct freq_tbl ftbl_sdcc1_apps_clk_src_8992[] = { 978 + F(144000, P_XO, 16, 3, 25), 979 + F(400000, P_XO, 12, 1, 4), 980 + F(20000000, P_GPLL0, 15, 1, 2), 981 + F(25000000, P_GPLL0, 12, 1, 2), 982 + F(50000000, P_GPLL0, 12, 0, 0), 983 + F(100000000, P_GPLL0, 6, 0, 0), 984 + F(172000000, P_GPLL4, 2, 0, 0), 985 + F(344000000, P_GPLL4, 1, 0, 0), 986 986 { } 987 987 }; 988 988 ··· 2734 2710 }; 2735 2711 2736 2712 static const struct of_device_id gcc_msm8994_match_table[] = { 2737 - { .compatible = "qcom,gcc-msm8994" }, 2713 + { .compatible = "qcom,gcc-msm8992" }, 2714 + { .compatible = "qcom,gcc-msm8994" }, /* V2 and V2.1 */ 2738 2715 {} 2739 2716 }; 2740 2717 MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table); 2741 2718 2742 2719 static int gcc_msm8994_probe(struct platform_device *pdev) 2743 2720 { 2721 + if (of_device_is_compatible(pdev->dev.of_node, "qcom,gcc-msm8992")) { 2722 + /* MSM8992 features less clocks and some have different freq tables */ 2723 + gcc_msm8994_desc.clks[UFS_AXI_CLK_SRC] = NULL; 2724 + gcc_msm8994_desc.clks[GCC_LPASS_Q6_AXI_CLK] = NULL; 2725 + gcc_msm8994_desc.clks[UFS_PHY_LDO] = NULL; 2726 + gcc_msm8994_desc.clks[GCC_UFS_AHB_CLK] = NULL; 2727 + gcc_msm8994_desc.clks[GCC_UFS_AXI_CLK] = NULL; 2728 + gcc_msm8994_desc.clks[GCC_UFS_RX_CFG_CLK] = NULL; 2729 + gcc_msm8994_desc.clks[GCC_UFS_RX_SYMBOL_0_CLK] = NULL; 2730 + gcc_msm8994_desc.clks[GCC_UFS_RX_SYMBOL_1_CLK] = NULL; 2731 + gcc_msm8994_desc.clks[GCC_UFS_TX_CFG_CLK] = NULL; 2732 + gcc_msm8994_desc.clks[GCC_UFS_TX_SYMBOL_0_CLK] = NULL; 2733 + gcc_msm8994_desc.clks[GCC_UFS_TX_SYMBOL_1_CLK] = NULL; 2734 + 2735 + sdcc1_apps_clk_src.freq_tbl = ftbl_sdcc1_apps_clk_src_8992; 2736 + blsp1_qup1_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2737 + blsp1_qup2_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2738 + blsp1_qup3_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2739 + blsp1_qup4_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2740 + blsp1_qup5_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2741 + blsp1_qup6_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2742 + blsp2_qup1_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2743 + blsp2_qup2_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2744 + blsp2_qup3_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2745 + blsp2_qup4_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2746 + blsp2_qup5_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2747 + blsp2_qup6_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992; 2748 + 2749 + /* 2750 + * Some 8992 boards might *possibly* use 2751 + * PCIe1 clocks and controller, but it's not 2752 + * standard and they should be disabled otherwise. 2753 + */ 2754 + gcc_msm8994_desc.clks[PCIE_1_AUX_CLK_SRC] = NULL; 2755 + gcc_msm8994_desc.clks[PCIE_1_PIPE_CLK_SRC] = NULL; 2756 + gcc_msm8994_desc.clks[PCIE_1_PHY_LDO] = NULL; 2757 + gcc_msm8994_desc.clks[GCC_PCIE_1_AUX_CLK] = NULL; 2758 + gcc_msm8994_desc.clks[GCC_PCIE_1_CFG_AHB_CLK] = NULL; 2759 + gcc_msm8994_desc.clks[GCC_PCIE_1_MSTR_AXI_CLK] = NULL; 2760 + gcc_msm8994_desc.clks[GCC_PCIE_1_PIPE_CLK] = NULL; 2761 + gcc_msm8994_desc.clks[GCC_PCIE_1_SLV_AXI_CLK] = NULL; 2762 + gcc_msm8994_desc.clks[GCC_SYS_NOC_UFS_AXI_CLK] = NULL; 2763 + } 2764 + 2744 2765 return qcom_cc_probe(pdev, &gcc_msm8994_desc); 2745 2766 } 2746 2767